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From: frank.chang@sifive.com
To: qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org
Subject: [PATCH v5 8/8] target/riscv: zfh: add Zfhmin cpu property
Date: Fri, 22 Oct 2021 00:29:54 +0800	[thread overview]
Message-ID: <20211021162956.2772656-9-frank.chang@sifive.com> (raw)
In-Reply-To: <20211021162956.2772656-1-frank.chang@sifive.com>

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b3a7784b06..e6e3ef183ae 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -618,6 +618,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
+    DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com
To: qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Bin Meng <bin.meng@windriver.com>,
	qemu-devel@nongnu.org
Subject: [PATCH v5 8/8] target/riscv: zfh: add Zfhmin cpu property
Date: Fri, 22 Oct 2021 00:29:54 +0800	[thread overview]
Message-ID: <20211021162956.2772656-9-frank.chang@sifive.com> (raw)
In-Reply-To: <20211021162956.2772656-1-frank.chang@sifive.com>

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b3a7784b06..e6e3ef183ae 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -618,6 +618,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
+    DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 
-- 
2.25.1



  parent reply	other threads:[~2021-10-21 16:36 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-21 16:29 [PATCH v5 0/8] target/riscv: support Zfh, Zfhmin extension v0.1 frank.chang
2021-10-21 16:29 ` [PATCH v5 1/8] target/riscv: zfh: half-precision load and store frank.chang
2021-10-21 16:29   ` frank.chang
2021-10-21 22:01   ` Alistair Francis
2021-10-21 22:31   ` Alistair Francis
2021-10-21 23:28     ` Richard Henderson
2021-10-22  3:25       ` Frank Chang
2021-10-22  3:25         ` Frank Chang
2021-10-21 16:29 ` [PATCH v5 2/8] target/riscv: zfh: half-precision computational frank.chang
2021-10-21 16:29   ` frank.chang
2021-10-21 16:29 ` [PATCH v5 3/8] target/riscv: zfh: half-precision convert and move frank.chang
2021-10-21 16:29   ` frank.chang
2021-10-21 16:29 ` [PATCH v5 4/8] target/riscv: zfh: half-precision floating-point compare frank.chang
2021-10-21 16:29   ` frank.chang
2021-10-21 16:29 ` [PATCH v5 5/8] target/riscv: zfh: half-precision floating-point classify frank.chang
2021-10-21 16:29   ` frank.chang
2021-10-21 16:29 ` [PATCH v5 6/8] target/riscv: zfh: add Zfh cpu property frank.chang
2021-10-21 16:29   ` frank.chang
2021-10-21 16:29 ` [PATCH v5 7/8] target/riscv: zfh: implement zfhmin extension frank.chang
2021-10-21 16:29   ` frank.chang
2021-10-21 16:29 ` frank.chang [this message]
2021-10-21 16:29   ` [PATCH v5 8/8] target/riscv: zfh: add Zfhmin cpu property frank.chang
2021-11-02 14:07 ` [PATCH v5 0/8] target/riscv: support Zfh, Zfhmin extension v0.1 Frank Chang

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