[igt-dev] [PATCH i-g-t 0/4] CCS engine and engine resets test

[igt-dev] [PATCH i-g-t 0/4] CCS engine and engine resets test

[priyanka.dandamudi]

From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>

Add CCS engine support and engine reset tests.

John Harrison (1):
  tests/gem_ctx_persistence: Update saturated_hostile for dependent
    engine resets

Priyanka Dandamudi (1):
  lib/i915/i915_drm_local: Add COMPUTE class engine

Tvrtko Ursulin (1):
  i915/gem_engine_topology: Add compute class

Vinay Belgaumkar (1):
  lib/igt_gt: Add compute engine

 lib/i915/gem_engine_topology.c   |  1 +
 lib/i915/i915_drm_local.h        |  1 +
 lib/igt_gt.c                     |  4 +++
 tests/i915/gem_ctx_persistence.c | 55 ++++++++++++++++++++++++++++----
 4 files changed, 54 insertions(+), 7 deletions(-)

-- 
2.25.1

[igt-dev] [PATCH i-g-t 1/4] i915/gem_engine_topology: Add compute class

[priyanka.dandamudi]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Add compute class to engine base names.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
---
 lib/i915/gem_engine_topology.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 4e497a5c..729f42b0 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -130,6 +130,7 @@ static const char *class_names[] = {
 	[I915_ENGINE_CLASS_COPY]	  = "bcs",
 	[I915_ENGINE_CLASS_VIDEO]	  = "vcs",
 	[I915_ENGINE_CLASS_VIDEO_ENHANCE] = "vecs",
+	[I915_ENGINE_CLASS_COMPUTE]       = "ccs",
 };
 
 static void init_engine(struct intel_execution_engine2 *e2,
-- 
2.25.1

[igt-dev] [PATCH i-g-t 2/4] tests/gem_ctx_persistence: Update saturated_hostile for dependent engine resets

[priyanka.dandamudi]

From: John Harrison <John.C.Harrison@Intel.com>

The gem_ctx_persistence test in general has support for twiddling the
scheduling parameters via sysfs to tune timeouts. For some reason,
this was not being applied to the saturated_hostile test. The test was
also broken for platforms with dependent engine resets.

The test submits requests to all engines, kills one and expects the
rest to survive. However, the other engine requests were all marked as
not pre-emptible. On recent platforms, there is a reset dependency
across RCS and CCS engines. That is, if one of those engines is reset
then all engines must be reset. If a context executing on one of those
engines does not pre-empt first then it will be killed.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
---
 tests/i915/gem_ctx_persistence.c | 55 ++++++++++++++++++++++++++++----
 1 file changed, 48 insertions(+), 7 deletions(-)

diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
index fafd8bb2..d7b2488c 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -875,11 +875,14 @@ static void test_process_mixed(int pfd, const intel_ctx_cfg_t *cfg,
 	gem_quiescent_gpu(pfd);
 }
 
+#define SATURATED_NOPREMPT	(1 << 0)
+
 static void
-test_saturated_hostile(int i915, const intel_ctx_t *base_ctx,
-		       const struct intel_execution_engine2 *engine)
+test_saturated_hostile_all(int i915, const intel_ctx_t *base_ctx,
+			   unsigned int engine_flags, unsigned int test_flags)
 {
 	const struct intel_execution_engine2 *other;
+	unsigned int other_flags = 0;
 	igt_spin_t *spin;
 	const intel_ctx_t *ctx;
 	uint64_t ahnd = get_reloc_ahnd(i915, base_ctx->id);
@@ -887,6 +890,20 @@ test_saturated_hostile(int i915, const intel_ctx_t *base_ctx,
 
 	cleanup(i915);
 
+	if (test_flags & SATURATED_NOPREMPT) {
+		/*
+		 * Render and compute engines have a reset dependency. If one is
+		 * reset then all must be reset. Thus, if a hanging batch causes
+		 * a reset, any non-preemptible batches on the other engines
+		 * will be killed. So don't bother testing for the survival of
+		 * non-preemptible batches when compute engines are present.
+		 */
+		for_each_ctx_engine(i915, base_ctx, other)
+			igt_require(other->class != I915_ENGINE_CLASS_COMPUTE);
+
+		other_flags |= IGT_SPIN_NO_PREEMPTION;
+	}
+
 	/*
 	 * Check that if we have to remove a hostile request from a
 	 * non-persistent context, we do so without harming any other
@@ -900,13 +917,12 @@ test_saturated_hostile(int i915, const intel_ctx_t *base_ctx,
 	 */
 
 	for_each_ctx_engine(i915, base_ctx, other) {
-		if (other->flags == engine->flags)
+		if (other->flags == engine_flags)
 			continue;
 
 		spin = igt_spin_new(i915, .ahnd = ahnd, .ctx = base_ctx,
 				   .engine = other->flags,
-				   .flags = (IGT_SPIN_NO_PREEMPTION |
-					     IGT_SPIN_FENCE_OUT));
+				   .flags = other_flags | IGT_SPIN_FENCE_OUT);
 
 		if (fence < 0) {
 			fence = spin->out_fence;
@@ -927,7 +943,7 @@ test_saturated_hostile(int i915, const intel_ctx_t *base_ctx,
 	ctx = ctx_create_persistence(i915, &base_ctx->cfg, false);
 	ahnd = get_reloc_ahnd(i915, ctx->id);
 	spin = igt_spin_new(i915, .ahnd = ahnd, .ctx = ctx,
-			    .engine = engine->flags,
+			    .engine = engine_flags,
 			    .flags = (IGT_SPIN_NO_PREEMPTION |
 				      IGT_SPIN_POLL_RUN |
 				      IGT_SPIN_FENCE_OUT));
@@ -944,6 +960,24 @@ test_saturated_hostile(int i915, const intel_ctx_t *base_ctx,
 	put_ahnd(ahnd);
 }
 
+static void
+test_saturated_hostile_nopreempt(int i915, const intel_ctx_cfg_t *cfg,
+				 unsigned int engine_flags)
+{
+	const intel_ctx_t *ctx = intel_ctx_create(i915, cfg);
+	test_saturated_hostile_all(i915, ctx, engine_flags, SATURATED_NOPREMPT);
+	intel_ctx_destroy(i915, ctx);
+}
+
+static void
+test_saturated_hostile(int i915, const intel_ctx_cfg_t *cfg,
+		       unsigned int engine_flags)
+{
+	const intel_ctx_t *ctx = intel_ctx_create(i915, cfg);
+	test_saturated_hostile_all(i915, ctx, engine_flags, 0);
+	intel_ctx_destroy(i915, ctx);
+}
+
 static void test_processes(int i915)
 {
 	struct {
@@ -1310,7 +1344,14 @@ igt_main
 		igt_subtest_with_dynamic_f("saturated-hostile") {
 			for_each_ctx_engine(i915, ctx, e) {
 				igt_dynamic_f("%s", e->name)
-					test_saturated_hostile(i915, ctx, e);
+					do_test(test_saturated_hostile, i915, &ctx->cfg, e->flags, e->name);
+			}
+		}
+
+		igt_subtest_with_dynamic_f("saturated-hostile-nopreempt") {
+			for_each_ctx_engine(i915, ctx, e) {
+				igt_dynamic_f("%s", e->name)
+					do_test(test_saturated_hostile_nopreempt, i915, &ctx->cfg, e->flags, e->name);
 			}
 		}
 
-- 
2.25.1

[igt-dev] [PATCH i-g-t 3/4] lib/igt_gt: Add compute engine

[priyanka.dandamudi]

From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

Add compute (CCS) engine. Add this to the IGT
structure to allow gem tests to execute.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
---
 lib/igt_gt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index a0ba04cc..80fb65ca 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -604,6 +604,10 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
 	{ "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD | I915_EXEC_BSD_RING2 },
 	{ "vcs2", I915_ENGINE_CLASS_VIDEO, 2, -1 },
 	{ "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, I915_EXEC_VEBOX },
+	{ "ccs0", I915_ENGINE_CLASS_COMPUTE, 0 , -1},
+	{ "ccs1", I915_ENGINE_CLASS_COMPUTE, 1 , -1},
+	{ "ccs2", I915_ENGINE_CLASS_COMPUTE, 2 , -1},
+	{ "ccs3", I915_ENGINE_CLASS_COMPUTE, 3 , -1},
 	{ }
 };
 
-- 
2.25.1

[igt-dev] [PATCH i-g-t 4/4] lib/i915/i915_drm_local: Add COMPUTE class engine

[priyanka.dandamudi]

From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>

Add I915_ENGINE_CLASS_COMPUTE define value.

Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
---
 lib/i915/i915_drm_local.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index a6afdd28..74b85c85 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -19,6 +19,7 @@ extern "C" {
  * or local_ prefix and without any #ifndef's. Attempt should be made to
  * clean these up when kernel uapi headers are sync'd.
  */
+#define I915_ENGINE_CLASS_COMPUTE 4
 
 /* Needed for PXP */
 #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT  1
-- 
2.25.1

[igt-dev] ✓ Fi.CI.BAT: success for CCS engine and engine resets test

[Patchwork]

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== Series Details ==

Series: CCS engine and engine resets test
URL   : https://patchwork.freedesktop.org/series/96095/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10767 -> IGTPW_6339
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/index.html

Known issues
------------

  Here are the changes found in IGTPW_6339 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-snb-2600:        NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-1115g4:      [PASS][2] -> [FAIL][3] ([i915#1888])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cml-u2:          [PASS][4] -> [DMESG-WARN][5] ([i915#4269])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [INCOMPLETE][6] ([i915#3921]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@kms_flip@basic-plain-flip@c-dp1:
    - fi-cfl-8109u:       [FAIL][8] ([i915#4165]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
    - fi-cfl-8109u:       [DMESG-WARN][10] ([i915#295]) -> [PASS][11] +14 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269


Participating hosts (41 -> 36)
------------------------------

  Missing    (5): fi-kbl-soraka bat-dg1-6 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6258 -> IGTPW_6339

  CI-20190529: 20190529
  CI_DRM_10767: 4d947bb057406e5c30081736db70da3f5726e0cd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6339: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/index.html
  IGT_6258: 4c80c71d7dec29b6376846ae96bd04dc0b6e34d9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@gem_ctx_persistence@saturated-hostile-nopreempt
+igt@gem_ctx_switch@ccs0
+igt@gem_ctx_switch@ccs0-forked
+igt@gem_ctx_switch@ccs0-forked-heavy
+igt@gem_ctx_switch@ccs0-forked-heavy-interruptible
+igt@gem_ctx_switch@ccs0-forked-heavy-queue
+igt@gem_ctx_switch@ccs0-forked-heavy-queue-interruptible
+igt@gem_ctx_switch@ccs0-forked-interruptible
+igt@gem_ctx_switch@ccs0-forked-queue
+igt@gem_ctx_switch@ccs0-forked-queue-interruptible
+igt@gem_ctx_switch@ccs0-heavy
+igt@gem_ctx_switch@ccs0-heavy-interruptible
+igt@gem_ctx_switch@ccs0-heavy-queue
+igt@gem_ctx_switch@ccs0-heavy-queue-interruptible
+igt@gem_ctx_switch@ccs0-interruptible
+igt@gem_ctx_switch@ccs0-queue
+igt@gem_ctx_switch@ccs0-queue-interruptible
+igt@gem_ctx_switch@ccs1
+igt@gem_ctx_switch@ccs1-forked
+igt@gem_ctx_switch@ccs1-forked-heavy
+igt@gem_ctx_switch@ccs1-forked-heavy-interruptible
+igt@gem_ctx_switch@ccs1-forked-heavy-queue
+igt@gem_ctx_switch@ccs1-forked-heavy-queue-interruptible
+igt@gem_ctx_switch@ccs1-forked-interruptible
+igt@gem_ctx_switch@ccs1-forked-queue
+igt@gem_ctx_switch@ccs1-forked-queue-interruptible
+igt@gem_ctx_switch@ccs1-heavy
+igt@gem_ctx_switch@ccs1-heavy-interruptible
+igt@gem_ctx_switch@ccs1-heavy-queue
+igt@gem_ctx_switch@ccs1-heavy-queue-interruptible
+igt@gem_ctx_switch@ccs1-interruptible
+igt@gem_ctx_switch@ccs1-queue
+igt@gem_ctx_switch@ccs1-queue-interruptible
+igt@gem_ctx_switch@ccs2
+igt@gem_ctx_switch@ccs2-forked
+igt@gem_ctx_switch@ccs2-forked-heavy
+igt@gem_ctx_switch@ccs2-forked-heavy-interruptible
+igt@gem_ctx_switch@ccs2-forked-heavy-queue
+igt@gem_ctx_switch@ccs2-forked-heavy-queue-interruptible
+igt@gem_ctx_switch@ccs2-forked-interruptible
+igt@gem_ctx_switch@ccs2-forked-queue
+igt@gem_ctx_switch@ccs2-forked-queue-interruptible
+igt@gem_ctx_switch@ccs2-heavy
+igt@gem_ctx_switch@ccs2-heavy-interruptible
+igt@gem_ctx_switch@ccs2-heavy-queue
+igt@gem_ctx_switch@ccs2-heavy-queue-interruptible
+igt@gem_ctx_switch@ccs2-interruptible
+igt@gem_ctx_switch@ccs2-queue
+igt@gem_ctx_switch@ccs2-queue-interruptible
+igt@gem_ctx_switch@ccs3
+igt@gem_ctx_switch@ccs3-forked
+igt@gem_ctx_switch@ccs3-forked-heavy
+igt@gem_ctx_switch@ccs3-forked-heavy-interruptible
+igt@gem_ctx_switch@ccs3-forked-heavy-queue
+igt@gem_ctx_switch@ccs3-forked-heavy-queue-interruptible
+igt@gem_ctx_switch@ccs3-forked-interruptible
+igt@gem_ctx_switch@ccs3-forked-queue
+igt@gem_ctx_switch@ccs3-forked-queue-interruptible
+igt@gem_ctx_switch@ccs3-heavy
+igt@gem_ctx_switch@ccs3-heavy-interruptible
+igt@gem_ctx_switch@ccs3-heavy-queue
+igt@gem_ctx_switch@ccs3-heavy-queue-interruptible
+igt@gem_ctx_switch@ccs3-interruptible
+igt@gem_ctx_switch@ccs3-queue
+igt@gem_ctx_switch@ccs3-queue-interruptible

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/index.html

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Re: [igt-dev] [PATCH i-g-t 4/4] lib/i915/i915_drm_local: Add COMPUTE class engine

[Zbigniew Kempczyński]

On Thu, Oct 21, 2021 at 10:05:08AM +0530, priyanka.dandamudi@intel.com wrote:
> From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> 
> Add I915_ENGINE_CLASS_COMPUTE define value.
> 
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> ---
>  lib/i915/i915_drm_local.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
> index a6afdd28..74b85c85 100644
> --- a/lib/i915/i915_drm_local.h
> +++ b/lib/i915/i915_drm_local.h
> @@ -19,6 +19,7 @@ extern "C" {
>   * or local_ prefix and without any #ifndef's. Attempt should be made to
>   * clean these up when kernel uapi headers are sync'd.
>   */
> +#define I915_ENGINE_CLASS_COMPUTE 4
>  
>  /* Needed for PXP */
>  #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT  1
> -- 
> 2.25.1
> 

This patch should be first, otherwise we got compile error on former
three patches due to lack of definition. Please reorder.

--
Zbigniew

Re: [igt-dev] [PATCH i-g-t 1/4] i915/gem_engine_topology: Add compute class

[Zbigniew Kempczyński]

On Thu, Oct 21, 2021 at 10:05:05AM +0530, priyanka.dandamudi@intel.com wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Add compute class to engine base names.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> ---
>  lib/i915/gem_engine_topology.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> index 4e497a5c..729f42b0 100644
> --- a/lib/i915/gem_engine_topology.c
> +++ b/lib/i915/gem_engine_topology.c
> @@ -130,6 +130,7 @@ static const char *class_names[] = {
>  	[I915_ENGINE_CLASS_COPY]	  = "bcs",
>  	[I915_ENGINE_CLASS_VIDEO]	  = "vcs",
>  	[I915_ENGINE_CLASS_VIDEO_ENHANCE] = "vecs",
> +	[I915_ENGINE_CLASS_COMPUTE]       = "ccs",
>  };
>  
>  static void init_engine(struct intel_execution_engine2 *e2,
> -- 
> 2.25.1
>

Ok, 

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew 

Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_gt: Add compute engine

[Zbigniew Kempczyński]

On Thu, Oct 21, 2021 at 10:05:07AM +0530, priyanka.dandamudi@intel.com wrote:
> From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> 
> Add compute (CCS) engine. Add this to the IGT
> structure to allow gem tests to execute.
> 
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> ---
>  lib/igt_gt.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> index a0ba04cc..80fb65ca 100644
> --- a/lib/igt_gt.c
> +++ b/lib/igt_gt.c
> @@ -604,6 +604,10 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
>  	{ "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD | I915_EXEC_BSD_RING2 },
>  	{ "vcs2", I915_ENGINE_CLASS_VIDEO, 2, -1 },
>  	{ "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, I915_EXEC_VEBOX },
> +	{ "ccs0", I915_ENGINE_CLASS_COMPUTE, 0 , -1},
> +	{ "ccs1", I915_ENGINE_CLASS_COMPUTE, 1 , -1},
> +	{ "ccs2", I915_ENGINE_CLASS_COMPUTE, 2 , -1},
> +	{ "ccs3", I915_ENGINE_CLASS_COMPUTE, 3 , -1},
>  	{ }
>  };
>  
> -- 
> 2.25.1
> 

LGTM, 

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

[igt-dev] ✗ Fi.CI.IGT: failure for CCS engine and engine resets test

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30249 bytes --]

== Series Details ==

Series: CCS engine and engine resets test
URL   : https://patchwork.freedesktop.org/series/96095/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10767_full -> IGTPW_6339_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_6339_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_6339_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6339_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-kbl:          [PASS][1] -> [TIMEOUT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl2/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
    - shard-apl:          [PASS][3] -> [TIMEOUT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-apl8/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl2/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  
New tests
---------

  New tests have been introduced between CI_DRM_10767_full and IGTPW_6339_full:

### New IGT tests (6) ###

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt:
    - Statuses :
    - Exec time: [None] s

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.04, 0.05] s

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.04, 0.06] s

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.03, 0.05] s

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [0.04, 0.05] s

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.03, 0.06] s

  

Known issues
------------

  Here are the changes found in IGTPW_6339_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][5] ([i915#3002]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl4/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@process:
    - shard-snb:          NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +4 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-snb2/igt@gem_ctx_persistence@process.html

  * igt@gem_eio@in-flight-suspend:
    - shard-apl:          NOTRUN -> [DMESG-WARN][7] ([i915#180])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl3/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][8] -> [FAIL][9] ([i915#2846])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-glk9/igt@gem_exec_fair@basic-deadline.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-glk6/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-tglb:         [PASS][10] -> [FAIL][11] ([i915#2842]) +4 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-tglb6/igt@gem_exec_fair@basic-pace@bcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][12] ([i915#2842]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][13] ([i915#2842])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb2/igt@gem_exec_fair@basic-throttle@rcs0.html
    - shard-iclb:         [PASS][14] -> [FAIL][15] ([i915#2849])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - shard-snb:          NOTRUN -> [SKIP][16] ([fdo#109271]) +488 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-snb2/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
    - shard-iclb:         NOTRUN -> [SKIP][17] ([fdo#109313])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb6/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
    - shard-tglb:         NOTRUN -> [SKIP][18] ([fdo#109313])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb2/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_exec_params@no-bsd:
    - shard-tglb:         NOTRUN -> [SKIP][19] ([fdo#109283])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb8/igt@gem_exec_params@no-bsd.html
    - shard-iclb:         NOTRUN -> [SKIP][20] ([fdo#109283])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb8/igt@gem_exec_params@no-bsd.html

  * igt@gem_exec_whisper@basic-queues-all:
    - shard-glk:          [PASS][21] -> [DMESG-WARN][22] ([i915#118]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-glk5/igt@gem_exec_whisper@basic-queues-all.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-glk8/igt@gem_exec_whisper@basic-queues-all.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [PASS][23] -> [FAIL][24] ([i915#644])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_pxp@create-protected-buffer:
    - shard-iclb:         NOTRUN -> [SKIP][25] ([i915#4270])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb7/igt@gem_pxp@create-protected-buffer.html
    - shard-tglb:         NOTRUN -> [SKIP][26] ([i915#4270])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb2/igt@gem_pxp@create-protected-buffer.html

  * igt@gem_userptr_blits@input-checking:
    - shard-apl:          NOTRUN -> [DMESG-WARN][27] ([i915#3002]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl7/igt@gem_userptr_blits@input-checking.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][28] ([i915#3297])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb2/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-apl:          NOTRUN -> [FAIL][29] ([i915#3318])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl1/igt@gem_userptr_blits@vma-merge.html

  * igt@gen9_exec_parse@basic-rejected:
    - shard-iclb:         NOTRUN -> [SKIP][30] ([i915#2856]) +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb6/igt@gen9_exec_parse@basic-rejected.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-tglb:         NOTRUN -> [SKIP][31] ([i915#2856]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb2/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][32] -> [FAIL][33] ([i915#454])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb4/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#111644] / [i915#1397] / [i915#2411])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb2/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - shard-apl:          NOTRUN -> [SKIP][35] ([fdo#109271]) +201 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl7/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#110725] / [fdo#111614])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb8/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
    - shard-tglb:         NOTRUN -> [SKIP][37] ([fdo#111614])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb8/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3777])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-iclb:         NOTRUN -> [SKIP][39] ([fdo#110723])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#3886]) +4 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-glk7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
    - shard-iclb:         NOTRUN -> [SKIP][41] ([fdo#109278] / [i915#3886]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb5/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
    - shard-tglb:         NOTRUN -> [SKIP][42] ([i915#3689] / [i915#3886])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb6/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3886]) +6 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-random-ccs-data-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][44] ([i915#3689]) +1 similar issue
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb5/igt@kms_ccs@pipe-b-random-ccs-data-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +9 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl7/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][46] ([fdo#109278]) +4 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb1/igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@hdmi-mode-timings:
    - shard-iclb:         NOTRUN -> [SKIP][47] ([fdo#109284] / [fdo#111827])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb5/igt@kms_chamelium@hdmi-mode-timings.html

  * igt@kms_chamelium@vga-hpd-after-suspend:
    - shard-glk:          NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-glk8/igt@kms_chamelium@vga-hpd-after-suspend.html

  * igt@kms_color_chamelium@pipe-a-ctm-0-25:
    - shard-snb:          NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +26 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-snb7/igt@kms_color_chamelium@pipe-a-ctm-0-25.html

  * igt@kms_color_chamelium@pipe-b-ctm-0-75:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb3/igt@kms_color_chamelium@pipe-b-ctm-0-75.html

  * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
    - shard-apl:          NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +11 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl1/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html

  * igt@kms_color_chamelium@pipe-c-ctm-0-25:
    - shard-kbl:          NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +13 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl1/igt@kms_color_chamelium@pipe-c-ctm-0-25.html

  * igt@kms_content_protection@uevent:
    - shard-apl:          NOTRUN -> [FAIL][53] ([i915#2105])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl8/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x170-random:
    - shard-tglb:         NOTRUN -> [SKIP][54] ([fdo#109279] / [i915#3359])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-512x170-random.html
    - shard-iclb:         NOTRUN -> [SKIP][55] ([fdo#109278] / [fdo#109279])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-512x170-random.html

  * igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][56] ([i915#3359]) +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][57] -> [DMESG-WARN][58] ([i915#180]) +2 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-iclb:         NOTRUN -> [SKIP][59] ([fdo#109274] / [fdo#109278]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [PASS][60] -> [INCOMPLETE][61] ([i915#180] / [i915#1982])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
    - shard-glk:          [PASS][62] -> [FAIL][63] ([i915#2122])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][64] -> [DMESG-WARN][65] ([i915#180]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-apl:          NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2672])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
    - shard-kbl:          NOTRUN -> [SKIP][67] ([fdo#109271]) +198 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-iclb:         NOTRUN -> [SKIP][68] ([fdo#109280]) +8 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
    - shard-tglb:         NOTRUN -> [SKIP][69] ([fdo#111825]) +10 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-snb:          [PASS][70] -> [DMESG-WARN][71] ([i915#3305])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-snb5/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-snb2/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-glk:          NOTRUN -> [SKIP][72] ([fdo#109271]) +33 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-glk1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][73] ([i915#180])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#533]) +3 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-kbl:          NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#533]) +2 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-kbl:          NOTRUN -> [FAIL][76] ([fdo#108145] / [i915#265])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-apl:          NOTRUN -> [FAIL][77] ([fdo#108145] / [i915#265])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         NOTRUN -> [SKIP][78] ([i915#3536])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-y.html
    - shard-tglb:         NOTRUN -> [SKIP][79] ([i915#3536])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb2/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-kbl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2733])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
    - shard-apl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#658]) +6 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
    - shard-kbl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#658]) +4 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl1/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
    - shard-tglb:         NOTRUN -> [SKIP][83] ([i915#2920])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html

  * igt@kms_setmode@basic:
    - shard-snb:          NOTRUN -> [FAIL][84] ([i915#31])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-snb2/igt@kms_setmode@basic.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#2437])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl6/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-kbl:          NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#2437])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl1/igt@kms_writeback@writeback-pixel-formats.html

  * igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame:
    - shard-tglb:         NOTRUN -> [SKIP][87] ([i915#2530])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb1/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html

  * igt@perf@polling-parameterized:
    - shard-glk:          [PASS][88] -> [FAIL][89] ([i915#1542])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-glk7/igt@perf@polling-parameterized.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-glk5/igt@perf@polling-parameterized.html

  * igt@prime_nv_test@i915_import_cpu_mmap:
    - shard-iclb:         NOTRUN -> [SKIP][90] ([fdo#109291])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb6/igt@prime_nv_test@i915_import_cpu_mmap.html
    - shard-tglb:         NOTRUN -> [SKIP][91] ([fdo#109291])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-tglb6/igt@prime_nv_test@i915_import_cpu_mmap.html

  * igt@sysfs_clients@fair-0:
    - shard-apl:          NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#2994]) +1 similar issue
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl1/igt@sysfs_clients@fair-0.html
    - shard-kbl:          NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2994])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl2/igt@sysfs_clients@fair-0.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-kbl:          [FAIL][94] ([i915#2842]) -> [PASS][95] +2 similar issues
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html
    - shard-iclb:         [FAIL][96] ([i915#2842]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-iclb6/igt@gem_exec_fair@basic-pace@rcs0.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb1/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [SKIP][98] ([fdo#109271]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [FAIL][100] ([i915#2842]) -> [PASS][101] +4 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-glk2/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
    - shard-glk:          [DMESG-WARN][102] ([i915#118]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-glk6/igt@kms_big_fb@linear-32bpp-rotate-180.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-180.html

  * igt@kms_flip@modeset-vs-vblank-race-interruptible@c-hdmi-a1:
    - shard-glk:          [FAIL][104] ([i915#407]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-glk6/igt@kms_flip@modeset-vs-vblank-race-interruptible@c-hdmi-a1.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-glk1/igt@kms_flip@modeset-vs-vblank-race-interruptible@c-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [DMESG-WARN][106] ([i915#180]) -> [PASS][107] +7 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][108] ([i915#180] / [i915#295]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][110] ([i915#1804] / [i915#2684]) -> [WARN][111] ([i915#2684]) +1 similar issue
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3363] / [i915#4312] / [i915#602] / [i915#92]) -> ([FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#4312] / [i915#92])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl6/igt@runner@aborted.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl3/igt@runner@aborted.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl6/igt@runner@aborted.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl3/igt@runner@aborted.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl6/igt@runner@aborted.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl3/igt@runner@aborted.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl3/igt@runner@aborted.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl6/igt@runner@aborted.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-kbl6/igt@runner@aborted.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl6/igt@runner@aborted.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl3/igt@runner@aborted.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl6/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl6/igt@runner@aborted.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl4/igt@runner@aborted.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl6/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-kbl4/igt@runner@aborted.html
    - shard-apl:          [FAIL][128] ([i915#180] / [i915#3363] / [i915#4312]) -> ([FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134]) ([i915#1610] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#4312])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10767/shard-apl6/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl3/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl2/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl7/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl8/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl7/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/shard-apl1/igt@runner@aborted.html

  
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6339/index.html

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Re: [igt-dev] [PATCH i-g-t 2/4] tests/gem_ctx_persistence: Update saturated_hostile for dependent engine resets

[Matthew Brost]

On Thu, Oct 21, 2021 at 10:05:06AM +0530, priyanka.dandamudi@intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> The gem_ctx_persistence test in general has support for twiddling the
> scheduling parameters via sysfs to tune timeouts. For some reason,
> this was not being applied to the saturated_hostile test. The test was
> also broken for platforms with dependent engine resets.
> 
> The test submits requests to all engines, kills one and expects the
> rest to survive. However, the other engine requests were all marked as
> not pre-emptible. On recent platforms, there is a reset dependency
> across RCS and CCS engines. That is, if one of those engines is reset
> then all engines must be reset. If a context executing on one of those
> engines does not pre-empt first then it will be killed.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>

Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> ---
>  tests/i915/gem_ctx_persistence.c | 55 ++++++++++++++++++++++++++++----
>  1 file changed, 48 insertions(+), 7 deletions(-)
> 
> diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
> index fafd8bb2..d7b2488c 100644
> --- a/tests/i915/gem_ctx_persistence.c
> +++ b/tests/i915/gem_ctx_persistence.c
> @@ -875,11 +875,14 @@ static void test_process_mixed(int pfd, const intel_ctx_cfg_t *cfg,
>  	gem_quiescent_gpu(pfd);
>  }
>  
> +#define SATURATED_NOPREMPT	(1 << 0)
> +
>  static void
> -test_saturated_hostile(int i915, const intel_ctx_t *base_ctx,
> -		       const struct intel_execution_engine2 *engine)
> +test_saturated_hostile_all(int i915, const intel_ctx_t *base_ctx,
> +			   unsigned int engine_flags, unsigned int test_flags)
>  {
>  	const struct intel_execution_engine2 *other;
> +	unsigned int other_flags = 0;
>  	igt_spin_t *spin;
>  	const intel_ctx_t *ctx;
>  	uint64_t ahnd = get_reloc_ahnd(i915, base_ctx->id);
> @@ -887,6 +890,20 @@ test_saturated_hostile(int i915, const intel_ctx_t *base_ctx,
>  
>  	cleanup(i915);
>  
> +	if (test_flags & SATURATED_NOPREMPT) {
> +		/*
> +		 * Render and compute engines have a reset dependency. If one is
> +		 * reset then all must be reset. Thus, if a hanging batch causes
> +		 * a reset, any non-preemptible batches on the other engines
> +		 * will be killed. So don't bother testing for the survival of
> +		 * non-preemptible batches when compute engines are present.
> +		 */
> +		for_each_ctx_engine(i915, base_ctx, other)
> +			igt_require(other->class != I915_ENGINE_CLASS_COMPUTE);
> +
> +		other_flags |= IGT_SPIN_NO_PREEMPTION;
> +	}
> +
>  	/*
>  	 * Check that if we have to remove a hostile request from a
>  	 * non-persistent context, we do so without harming any other
> @@ -900,13 +917,12 @@ test_saturated_hostile(int i915, const intel_ctx_t *base_ctx,
>  	 */
>  
>  	for_each_ctx_engine(i915, base_ctx, other) {
> -		if (other->flags == engine->flags)
> +		if (other->flags == engine_flags)
>  			continue;
>  
>  		spin = igt_spin_new(i915, .ahnd = ahnd, .ctx = base_ctx,
>  				   .engine = other->flags,
> -				   .flags = (IGT_SPIN_NO_PREEMPTION |
> -					     IGT_SPIN_FENCE_OUT));
> +				   .flags = other_flags | IGT_SPIN_FENCE_OUT);
>  
>  		if (fence < 0) {
>  			fence = spin->out_fence;
> @@ -927,7 +943,7 @@ test_saturated_hostile(int i915, const intel_ctx_t *base_ctx,
>  	ctx = ctx_create_persistence(i915, &base_ctx->cfg, false);
>  	ahnd = get_reloc_ahnd(i915, ctx->id);
>  	spin = igt_spin_new(i915, .ahnd = ahnd, .ctx = ctx,
> -			    .engine = engine->flags,
> +			    .engine = engine_flags,
>  			    .flags = (IGT_SPIN_NO_PREEMPTION |
>  				      IGT_SPIN_POLL_RUN |
>  				      IGT_SPIN_FENCE_OUT));
> @@ -944,6 +960,24 @@ test_saturated_hostile(int i915, const intel_ctx_t *base_ctx,
>  	put_ahnd(ahnd);
>  }
>  
> +static void
> +test_saturated_hostile_nopreempt(int i915, const intel_ctx_cfg_t *cfg,
> +				 unsigned int engine_flags)
> +{
> +	const intel_ctx_t *ctx = intel_ctx_create(i915, cfg);
> +	test_saturated_hostile_all(i915, ctx, engine_flags, SATURATED_NOPREMPT);
> +	intel_ctx_destroy(i915, ctx);
> +}
> +
> +static void
> +test_saturated_hostile(int i915, const intel_ctx_cfg_t *cfg,
> +		       unsigned int engine_flags)
> +{
> +	const intel_ctx_t *ctx = intel_ctx_create(i915, cfg);
> +	test_saturated_hostile_all(i915, ctx, engine_flags, 0);
> +	intel_ctx_destroy(i915, ctx);
> +}
> +
>  static void test_processes(int i915)
>  {
>  	struct {
> @@ -1310,7 +1344,14 @@ igt_main
>  		igt_subtest_with_dynamic_f("saturated-hostile") {
>  			for_each_ctx_engine(i915, ctx, e) {
>  				igt_dynamic_f("%s", e->name)
> -					test_saturated_hostile(i915, ctx, e);
> +					do_test(test_saturated_hostile, i915, &ctx->cfg, e->flags, e->name);
> +			}
> +		}
> +
> +		igt_subtest_with_dynamic_f("saturated-hostile-nopreempt") {
> +			for_each_ctx_engine(i915, ctx, e) {
> +				igt_dynamic_f("%s", e->name)
> +					do_test(test_saturated_hostile_nopreempt, i915, &ctx->cfg, e->flags, e->name);
>  			}
>  		}
>  
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_gt: Add compute engine

[Dixit, Ashutosh]

On Thu, 21 Oct 2021 00:33:21 -0700, Zbigniew Kempczyński wrote:
>
> On Thu, Oct 21, 2021 at 10:05:07AM +0530, priyanka.dandamudi@intel.com wrote:
> > From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> >
> > Add compute (CCS) engine. Add this to the IGT
> > structure to allow gem tests to execute.
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> > ---
> >  lib/igt_gt.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> > index a0ba04cc..80fb65ca 100644
> > --- a/lib/igt_gt.c
> > +++ b/lib/igt_gt.c
> > @@ -604,6 +604,10 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
> >	{ "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD | I915_EXEC_BSD_RING2 },
> >	{ "vcs2", I915_ENGINE_CLASS_VIDEO, 2, -1 },
> >	{ "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, I915_EXEC_VEBOX },
> > +	{ "ccs0", I915_ENGINE_CLASS_COMPUTE, 0 , -1},
> > +	{ "ccs1", I915_ENGINE_CLASS_COMPUTE, 1 , -1},
> > +	{ "ccs2", I915_ENGINE_CLASS_COMPUTE, 2 , -1},
> > +	{ "ccs3", I915_ENGINE_CLASS_COMPUTE, 3 , -1},
>
> LGTM,
>
> Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Is this correct? Isn't intel_execution_engines2 a list of just the legacy
engines? I don't think compute engines (which may vary in number) can be
added to the list of legacy engines. Isn't it true that compute engines can
only be accessed by querying the present engines dynamically (using
something like intel_ctx_create_all_physical())?

For example see:

/**
 * __for_each_static_engine:
 * @e__: struct intel_execution_engine2 iterator
 *
 * Iterates over each of the statically defined (legacy) engines.
 */
#define __for_each_static_engine(e__) \
        for ((e__) = intel_execution_engines2; (e__)->name[0]; (e__)++)

Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_gt: Add compute engine

[Dixit, Ashutosh]

On Thu, 21 Oct 2021 17:12:26 -0700, Dixit, Ashutosh wrote:
>
> On Thu, 21 Oct 2021 00:33:21 -0700, Zbigniew Kempczyński wrote:
> >
> > On Thu, Oct 21, 2021 at 10:05:07AM +0530, priyanka.dandamudi@intel.com wrote:
> > > From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > >
> > > Add compute (CCS) engine. Add this to the IGT
> > > structure to allow gem tests to execute.
> > >
> > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > > Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> > > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> > > ---
> > >  lib/igt_gt.c | 4 ++++
> > >  1 file changed, 4 insertions(+)
> > >
> > > diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> > > index a0ba04cc..80fb65ca 100644
> > > --- a/lib/igt_gt.c
> > > +++ b/lib/igt_gt.c
> > > @@ -604,6 +604,10 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
> > >	{ "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD | I915_EXEC_BSD_RING2 },
> > >	{ "vcs2", I915_ENGINE_CLASS_VIDEO, 2, -1 },
> > >	{ "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, I915_EXEC_VEBOX },
> > > +	{ "ccs0", I915_ENGINE_CLASS_COMPUTE, 0 , -1},
> > > +	{ "ccs1", I915_ENGINE_CLASS_COMPUTE, 1 , -1},
> > > +	{ "ccs2", I915_ENGINE_CLASS_COMPUTE, 2 , -1},
> > > +	{ "ccs3", I915_ENGINE_CLASS_COMPUTE, 3 , -1},
>
> Is this correct? Isn't intel_execution_engines2 a list of just the legacy
> engines? I don't think compute engines (which may vary in number) can be
> added to the list of legacy engines. Isn't it true that compute engines can
> only be accessed by querying the present engines dynamically (using
> something like intel_ctx_create_all_physical())?

I've copied Tvrtko (the boss :), but I am pretty sure what I said is
correct. Legacy engines are what context 0 is created with (without adding
any more engines onto context 0). So unless we can confirm that these
engines are present for context 0 in the kernel we can't add them in IGT.

Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_gt: Add compute engine

[Zbigniew Kempczyński]

On Thu, Oct 21, 2021 at 05:29:50PM -0700, Dixit, Ashutosh wrote:
> On Thu, 21 Oct 2021 17:12:26 -0700, Dixit, Ashutosh wrote:
> >
> > On Thu, 21 Oct 2021 00:33:21 -0700, Zbigniew Kempczyński wrote:
> > >
> > > On Thu, Oct 21, 2021 at 10:05:07AM +0530, priyanka.dandamudi@intel.com wrote:
> > > > From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > > >
> > > > Add compute (CCS) engine. Add this to the IGT
> > > > structure to allow gem tests to execute.
> > > >
> > > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > > Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > > > Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> > > > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > > Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> > > > ---
> > > >  lib/igt_gt.c | 4 ++++
> > > >  1 file changed, 4 insertions(+)
> > > >
> > > > diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> > > > index a0ba04cc..80fb65ca 100644
> > > > --- a/lib/igt_gt.c
> > > > +++ b/lib/igt_gt.c
> > > > @@ -604,6 +604,10 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
> > > >	{ "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD | I915_EXEC_BSD_RING2 },
> > > >	{ "vcs2", I915_ENGINE_CLASS_VIDEO, 2, -1 },
> > > >	{ "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, I915_EXEC_VEBOX },
> > > > +	{ "ccs0", I915_ENGINE_CLASS_COMPUTE, 0 , -1},
> > > > +	{ "ccs1", I915_ENGINE_CLASS_COMPUTE, 1 , -1},
> > > > +	{ "ccs2", I915_ENGINE_CLASS_COMPUTE, 2 , -1},
> > > > +	{ "ccs3", I915_ENGINE_CLASS_COMPUTE, 3 , -1},
> >
> > Is this correct? Isn't intel_execution_engines2 a list of just the legacy
> > engines? I don't think compute engines (which may vary in number) can be
> > added to the list of legacy engines. Isn't it true that compute engines can
> > only be accessed by querying the present engines dynamically (using
> > something like intel_ctx_create_all_physical())?
> 
> I've copied Tvrtko (the boss :), but I am pretty sure what I said is
> correct. Legacy engines are what context 0 is created with (without adding
> any more engines onto context 0). So unless we can confirm that these
> engines are present for context 0 in the kernel we can't add them in IGT.

I'm sorry, you're right. I wasn't aware legacy engines are "frozen", so
context 0 won't get an access to ccs. My r-b is incorrect then and patch
shouldn't land.  Another problem you've just realized me is with above
patch I would still need to detect ccs somehow on context 0 depending
on gen to allow iterator to go over existing engines.

--
Zbigniew

Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_gt: Add compute engine

[Tvrtko Ursulin]

On 22/10/2021 05:40, Zbigniew Kempczyński wrote:
> On Thu, Oct 21, 2021 at 05:29:50PM -0700, Dixit, Ashutosh wrote:
>> On Thu, 21 Oct 2021 17:12:26 -0700, Dixit, Ashutosh wrote:
>>>
>>> On Thu, 21 Oct 2021 00:33:21 -0700, Zbigniew Kempczyński wrote:
>>>>
>>>> On Thu, Oct 21, 2021 at 10:05:07AM +0530, priyanka.dandamudi@intel.com wrote:
>>>>> From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>>>>>
>>>>> Add compute (CCS) engine. Add this to the IGT
>>>>> structure to allow gem tests to execute.
>>>>>
>>>>> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>>>>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>>>>> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>>>>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>>>>> Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
>>>>> ---
>>>>>   lib/igt_gt.c | 4 ++++
>>>>>   1 file changed, 4 insertions(+)
>>>>>
>>>>> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
>>>>> index a0ba04cc..80fb65ca 100644
>>>>> --- a/lib/igt_gt.c
>>>>> +++ b/lib/igt_gt.c
>>>>> @@ -604,6 +604,10 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
>>>>> 	{ "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD | I915_EXEC_BSD_RING2 },
>>>>> 	{ "vcs2", I915_ENGINE_CLASS_VIDEO, 2, -1 },
>>>>> 	{ "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, I915_EXEC_VEBOX },
>>>>> +	{ "ccs0", I915_ENGINE_CLASS_COMPUTE, 0 , -1},
>>>>> +	{ "ccs1", I915_ENGINE_CLASS_COMPUTE, 1 , -1},
>>>>> +	{ "ccs2", I915_ENGINE_CLASS_COMPUTE, 2 , -1},
>>>>> +	{ "ccs3", I915_ENGINE_CLASS_COMPUTE, 3 , -1},
>>>
>>> Is this correct? Isn't intel_execution_engines2 a list of just the legacy
>>> engines? I don't think compute engines (which may vary in number) can be
>>> added to the list of legacy engines. Isn't it true that compute engines can
>>> only be accessed by querying the present engines dynamically (using
>>> something like intel_ctx_create_all_physical())?
>>
>> I've copied Tvrtko (the boss :), but I am pretty sure what I said is
>> correct. Legacy engines are what context 0 is created with (without adding
>> any more engines onto context 0). So unless we can confirm that these
>> engines are present for context 0 in the kernel we can't add them in IGT.
> 
> I'm sorry, you're right. I wasn't aware legacy engines are "frozen", so
> context 0 won't get an access to ccs. My r-b is incorrect then and patch
> shouldn't land.  Another problem you've just realized me is with above
> patch I would still need to detect ccs somehow on context 0 depending
> on gen to allow iterator to go over existing engines.

Don't know any longer guys - in the past "static engines" iterator was 
supposed to be used to enumerate all possible engines _without_ querying 
the device (like when enumerating subtests it isn't allowed to open the 
device).

As such CCS would go to intel_execution_engines2 with "-1" for flags, as 
above patch had it. In other words in the past it was supposed to 
contain all engines i915 engine query could possibly return. The array 
would then also be used from elsewhere in the code to map class and 
instance to name and similar.

Whether or not all this changed in the intel_ctx_t rewrite I have no 
idea. I see the "legacy" comment was added in:

commit 9b32262bfadffffcde33c18ffb7c5292fbf4901e
Author: Jason Ekstrand <jason@jlekstrand.net>
Date:   Thu Apr 15 12:42:53 2021 -0500

     docs: Add gem_engine_topology.h to the docs

So perhaps ask Jason what was the plan there.

Regards,

Tvrtko

Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_gt: Add compute engine

[Dixit, Ashutosh]

+Jason for this thoughts.

On Fri, 22 Oct 2021 05:07:41 -0700, Tvrtko Ursulin wrote:
> On 22/10/2021 05:40, Zbigniew Kempczyński wrote:
> > On Thu, Oct 21, 2021 at 05:29:50PM -0700, Dixit, Ashutosh wrote:
> >> On Thu, 21 Oct 2021 17:12:26 -0700, Dixit, Ashutosh wrote:
> >>>
> >>> On Thu, 21 Oct 2021 00:33:21 -0700, Zbigniew Kempczyński wrote:
> >>>>
> >>>> On Thu, Oct 21, 2021 at 10:05:07AM +0530, priyanka.dandamudi@intel.com wrote:
> >>>>> From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> >>>>>
> >>>>> Add compute (CCS) engine. Add this to the IGT
> >>>>> structure to allow gem tests to execute.
> >>>>>
> >>>>> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> >>>>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> >>>>> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> >>>>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> >>>>> Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> >>>>> ---
> >>>>>   lib/igt_gt.c | 4 ++++
> >>>>>   1 file changed, 4 insertions(+)
> >>>>>
> >>>>> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> >>>>> index a0ba04cc..80fb65ca 100644
> >>>>> --- a/lib/igt_gt.c
> >>>>> +++ b/lib/igt_gt.c
> >>>>> @@ -604,6 +604,10 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
> >>>>>		{ "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD | I915_EXEC_BSD_RING2 },
> >>>>>		{ "vcs2", I915_ENGINE_CLASS_VIDEO, 2, -1 },
> >>>>>		{ "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, I915_EXEC_VEBOX },
> >>>>> +	{ "ccs0", I915_ENGINE_CLASS_COMPUTE, 0 , -1},
> >>>>> +	{ "ccs1", I915_ENGINE_CLASS_COMPUTE, 1 , -1},
> >>>>> +	{ "ccs2", I915_ENGINE_CLASS_COMPUTE, 2 , -1},
> >>>>> +	{ "ccs3", I915_ENGINE_CLASS_COMPUTE, 3 , -1},
> >>>
> >>> Is this correct? Isn't intel_execution_engines2 a list of just the legacy
> >>> engines? I don't think compute engines (which may vary in number) can be
> >>> added to the list of legacy engines. Isn't it true that compute engines can
> >>> only be accessed by querying the present engines dynamically (using
> >>> something like intel_ctx_create_all_physical())?
> >>
> >> I've copied Tvrtko (the boss :), but I am pretty sure what I said is
> >> correct. Legacy engines are what context 0 is created with (without adding
> >> any more engines onto context 0). So unless we can confirm that these
> >> engines are present for context 0 in the kernel we can't add them in IGT.
> >
> > I'm sorry, you're right. I wasn't aware legacy engines are "frozen", so
> > context 0 won't get an access to ccs. My r-b is incorrect then and patch
> > shouldn't land.  Another problem you've just realized me is with above
> > patch I would still need to detect ccs somehow on context 0 depending
> > on gen to allow iterator to go over existing engines.
>
> Don't know any longer guys - in the past "static engines" iterator was
> supposed to be used to enumerate all possible engines _without_ querying
> the device (like when enumerating subtests it isn't allowed to open the
> device).
>
> As such CCS would go to intel_execution_engines2 with "-1" for flags, as
> above patch had it. In other words in the past it was supposed to contain
> all engines i915 engine query could possibly return. The array would then
> also be used from elsewhere in the code to map class and instance to name
> and similar.
>
> Whether or not all this changed in the intel_ctx_t rewrite I have no
> idea. I see the "legacy" comment was added in:
>
> commit 9b32262bfadffffcde33c18ffb7c5292fbf4901e
> Author: Jason Ekstrand <jason@jlekstrand.net>
> Date:   Thu Apr 15 12:42:53 2021 -0500
>
>     docs: Add gem_engine_topology.h to the docs
>
> So perhaps ask Jason what was the plan there.
>
> Regards,
>
> Tvrtko

Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_gt: Add compute engine

[Dixit, Ashutosh]

On Fri, 22 Oct 2021 05:07:41 -0700, Tvrtko Ursulin wrote:
> On 22/10/2021 05:40, Zbigniew Kempczyński wrote:
> > On Thu, Oct 21, 2021 at 05:29:50PM -0700, Dixit, Ashutosh wrote:
> >> On Thu, 21 Oct 2021 17:12:26 -0700, Dixit, Ashutosh wrote:
> >>>
> >>> On Thu, 21 Oct 2021 00:33:21 -0700, Zbigniew Kempczyński wrote:
> >>>>
> >>>> On Thu, Oct 21, 2021 at 10:05:07AM +0530, priyanka.dandamudi@intel.com wrote:
> >>>>> From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> >>>>>
> >>>>> Add compute (CCS) engine. Add this to the IGT
> >>>>> structure to allow gem tests to execute.
> >>>>>
> >>>>> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> >>>>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> >>>>> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> >>>>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> >>>>> Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> >>>>> ---
> >>>>>   lib/igt_gt.c | 4 ++++
> >>>>>   1 file changed, 4 insertions(+)
> >>>>>
> >>>>> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> >>>>> index a0ba04cc..80fb65ca 100644
> >>>>> --- a/lib/igt_gt.c
> >>>>> +++ b/lib/igt_gt.c
> >>>>> @@ -604,6 +604,10 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
> >>>>>		{ "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD | I915_EXEC_BSD_RING2 },
> >>>>>		{ "vcs2", I915_ENGINE_CLASS_VIDEO, 2, -1 },
> >>>>>		{ "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, I915_EXEC_VEBOX },
> >>>>> +	{ "ccs0", I915_ENGINE_CLASS_COMPUTE, 0 , -1},
> >>>>> +	{ "ccs1", I915_ENGINE_CLASS_COMPUTE, 1 , -1},
> >>>>> +	{ "ccs2", I915_ENGINE_CLASS_COMPUTE, 2 , -1},
> >>>>> +	{ "ccs3", I915_ENGINE_CLASS_COMPUTE, 3 , -1},
> >>>
> >>> Is this correct? Isn't intel_execution_engines2 a list of just the legacy
> >>> engines? I don't think compute engines (which may vary in number) can be
> >>> added to the list of legacy engines. Isn't it true that compute engines can
> >>> only be accessed by querying the present engines dynamically (using
> >>> something like intel_ctx_create_all_physical())?
> >>
> >> I've copied Tvrtko (the boss :), but I am pretty sure what I said is
> >> correct. Legacy engines are what context 0 is created with (without adding
> >> any more engines onto context 0). So unless we can confirm that these
> >> engines are present for context 0 in the kernel we can't add them in IGT.
> >
> > I'm sorry, you're right. I wasn't aware legacy engines are "frozen", so
> > context 0 won't get an access to ccs. My r-b is incorrect then and patch
> > shouldn't land.  Another problem you've just realized me is with above
> > patch I would still need to detect ccs somehow on context 0 depending
> > on gen to allow iterator to go over existing engines.
>
> Don't know any longer guys - in the past "static engines" iterator was
> supposed to be used to enumerate all possible engines _without_ querying
> the device (like when enumerating subtests it isn't allowed to open the
> device).
>
> As such CCS would go to intel_execution_engines2 with "-1" for flags, as
> above patch had it. In other words in the past it was supposed to contain
> all engines i915 engine query could possibly return.

Thanks Tvrtko, still looking at it but considering that future products may
have different number of engines of different classes there are two options
here (a) list every possible engine of every possible class of every
possible product here, or (b) list only a minimum set of engines which
every product is guaranteed to have (if some engines of this minimum set
are missing in a product this list may even have to be pruned).

I believe Jason's assumption during the i915 context mutation changes was
that context 0 is created with only this minimum (or legacy) set of
engines. But is that context 0 engine-set also what
intel_execution_engines2 is referring to? This is what my assumption is as
I was saying above. Hoping Jason responds with his thoughts.

> The array would then also be used from elsewhere in the code to map class
> and instance to name and similar.

Engine names are dynamically generated (from class name and engine
instance) in init_engine() since:

commit 6fa36c0233afb2cf98ed41c2b2255ab484e79add
Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date:   Wed Jan 22 15:23:48 2020 +0000

    i915/gem_engine_topology: Generate engine names based on class

> Whether or not all this changed in the intel_ctx_t rewrite I have no
> idea. I see the "legacy" comment was added in:
>
> commit 9b32262bfadffffcde33c18ffb7c5292fbf4901e
> Author: Jason Ekstrand <jason@jlekstrand.net>
> Date:   Thu Apr 15 12:42:53 2021 -0500
>
>     docs: Add gem_engine_topology.h to the docs
>
> So perhaps ask Jason what was the plan there.
>
> Regards,
>
> Tvrtko

Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_gt: Add compute engine

[Zbigniew Kempczyński]

On Fri, Oct 22, 2021 at 01:07:41PM +0100, Tvrtko Ursulin wrote:
<cut>

> > > > > > --- a/lib/igt_gt.c
> > > > > > +++ b/lib/igt_gt.c
> > > > > > @@ -604,6 +604,10 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
> > > > > > 	{ "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD | I915_EXEC_BSD_RING2 },
> > > > > > 	{ "vcs2", I915_ENGINE_CLASS_VIDEO, 2, -1 },
> > > > > > 	{ "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, I915_EXEC_VEBOX },
> > > > > > +	{ "ccs0", I915_ENGINE_CLASS_COMPUTE, 0 , -1},
> > > > > > +	{ "ccs1", I915_ENGINE_CLASS_COMPUTE, 1 , -1},
> > > > > > +	{ "ccs2", I915_ENGINE_CLASS_COMPUTE, 2 , -1},
> > > > > > +	{ "ccs3", I915_ENGINE_CLASS_COMPUTE, 3 , -1},
> > > > 
> > > > Is this correct? Isn't intel_execution_engines2 a list of just the legacy
> > > > engines? I don't think compute engines (which may vary in number) can be
> > > > added to the list of legacy engines. Isn't it true that compute engines can
> > > > only be accessed by querying the present engines dynamically (using
> > > > something like intel_ctx_create_all_physical())?
> > > 
> > > I've copied Tvrtko (the boss :), but I am pretty sure what I said is
> > > correct. Legacy engines are what context 0 is created with (without adding
> > > any more engines onto context 0). So unless we can confirm that these
> > > engines are present for context 0 in the kernel we can't add them in IGT.
> > 
> > I'm sorry, you're right. I wasn't aware legacy engines are "frozen", so
> > context 0 won't get an access to ccs. My r-b is incorrect then and patch
> > shouldn't land.  Another problem you've just realized me is with above
> > patch I would still need to detect ccs somehow on context 0 depending
> > on gen to allow iterator to go over existing engines.
> 
> Don't know any longer guys - in the past "static engines" iterator was
> supposed to be used to enumerate all possible engines _without_ querying the
> device (like when enumerating subtests it isn't allowed to open the device).
> 
> As such CCS would go to intel_execution_engines2 with "-1" for flags, as
> above patch had it. In other words in the past it was supposed to contain
> all engines i915 engine query could possibly return. The array would then
> also be used from elsewhere in the code to map class and instance to name
> and similar.

Ok, now everything is clear to me. Adding CCS to intel_execution_engines2[]
doesn't make sense because we won't have legacy ID which we could use 
in context 0 (in __for_each_static_engine()). Context 0 itself is legacy,
frozen and already converted from proto->full context during opening i915,
so no changes will occur in the engine set.

> 
> Whether or not all this changed in the intel_ctx_t rewrite I have no idea. I
> see the "legacy" comment was added in:
> 
> commit 9b32262bfadffffcde33c18ffb7c5292fbf4901e
> Author: Jason Ekstrand <jason@jlekstrand.net>
> Date:   Thu Apr 15 12:42:53 2021 -0500
> 
>     docs: Add gem_engine_topology.h to the docs
> 
> So perhaps ask Jason what was the plan there.

I don't think we should bother him - only allowed interface we got now 
in setting with using engines from I915_QUERY(engines) and all legacy 
engines walkthrough just gone for contexts > 0. So adding this to 
above array is useless.

Thanks for explanation.

--
Zbigniew

> 
> Regards,
> 
> Tvrtko

Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_gt: Add compute engine

[Dixit, Ashutosh]

On Fri, 22 Oct 2021 17:15:24 -0700, Dixit, Ashutosh wrote:
> On Fri, 22 Oct 2021 05:07:41 -0700, Tvrtko Ursulin wrote:
> > On 22/10/2021 05:40, Zbigniew Kempczyński wrote:
> > > On Thu, Oct 21, 2021 at 05:29:50PM -0700, Dixit, Ashutosh wrote:
> > >> On Thu, 21 Oct 2021 17:12:26 -0700, Dixit, Ashutosh wrote:
> > >>>
> > >>> On Thu, 21 Oct 2021 00:33:21 -0700, Zbigniew Kempczyński wrote:
> > >>>>
> > >>>> On Thu, Oct 21, 2021 at 10:05:07AM +0530, priyanka.dandamudi@intel.com wrote:
> > >>>>> From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > >>>>>
> > >>>>> Add compute (CCS) engine. Add this to the IGT
> > >>>>> structure to allow gem tests to execute.
> > >>>>>
> > >>>>> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > >>>>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > >>>>> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> > >>>>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > >>>>> Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> > >>>>> ---
> > >>>>>   lib/igt_gt.c | 4 ++++
> > >>>>>   1 file changed, 4 insertions(+)
> > >>>>>
> > >>>>> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> > >>>>> index a0ba04cc..80fb65ca 100644
> > >>>>> --- a/lib/igt_gt.c
> > >>>>> +++ b/lib/igt_gt.c
> > >>>>> @@ -604,6 +604,10 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
> > >>>>>		{ "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD | I915_EXEC_BSD_RING2 },
> > >>>>>		{ "vcs2", I915_ENGINE_CLASS_VIDEO, 2, -1 },
> > >>>>>		{ "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, I915_EXEC_VEBOX },
> > >>>>> +	{ "ccs0", I915_ENGINE_CLASS_COMPUTE, 0 , -1},
> > >>>>> +	{ "ccs1", I915_ENGINE_CLASS_COMPUTE, 1 , -1},
> > >>>>> +	{ "ccs2", I915_ENGINE_CLASS_COMPUTE, 2 , -1},
> > >>>>> +	{ "ccs3", I915_ENGINE_CLASS_COMPUTE, 3 , -1},
> > >>>
> > >>> Is this correct? Isn't intel_execution_engines2 a list of just the legacy
> > >>> engines? I don't think compute engines (which may vary in number) can be
> > >>> added to the list of legacy engines. Isn't it true that compute engines can
> > >>> only be accessed by querying the present engines dynamically (using
> > >>> something like intel_ctx_create_all_physical())?
> > >>
> > >> I've copied Tvrtko (the boss :), but I am pretty sure what I said is
> > >> correct. Legacy engines are what context 0 is created with (without adding
> > >> any more engines onto context 0). So unless we can confirm that these
> > >> engines are present for context 0 in the kernel we can't add them in IGT.
> > >
> > > I'm sorry, you're right. I wasn't aware legacy engines are "frozen", so
> > > context 0 won't get an access to ccs. My r-b is incorrect then and patch
> > > shouldn't land.  Another problem you've just realized me is with above
> > > patch I would still need to detect ccs somehow on context 0 depending
> > > on gen to allow iterator to go over existing engines.
> >
> > Don't know any longer guys - in the past "static engines" iterator was
> > supposed to be used to enumerate all possible engines _without_ querying
> > the device (like when enumerating subtests it isn't allowed to open the
> > device).
> >
> > As such CCS would go to intel_execution_engines2 with "-1" for flags, as
> > above patch had it. In other words in the past it was supposed to contain
> > all engines i915 engine query could possibly return.
>
> Thanks Tvrtko, still looking at it but considering that future products may
> have different number of engines of different classes there are two options
> here (a) list every possible engine of every possible class of every
> possible product here, or (b) list only a minimum set of engines which
> every product is guaranteed to have (if some engines of this minimum set
> are missing in a product this list may even have to be pruned).
>
> I believe Jason's assumption during the i915 context mutation changes was
> that context 0 is created with only this minimum (or legacy) set of
> engines. But is that context 0 engine-set also what
> intel_execution_engines2 is referring to? This is what my assumption is as
> I was saying above. Hoping Jason responds with his thoughts.

Also by intel_ctx_0 I really mean any "legacy context" (any context created
with an all zero intel_ctx_cfg_t). At least one on which
I915_CONTEXT_PARAM_ENGINES has not been executed.

Also (I really should have asked this when reviewing Jason's patches) why
do we have this complication of a "legacy context" which only has "legacy
engines" (see legacy_ring_idx() in i915)? Why can't the default engines for
any context be all physical engines present on a platform (so that
I915_CONTEXT_PARAM_ENGINES is used only to restrict the number of engines
when needed, not to expand the number of engines as we do now). This would
have saved a lot of this intel_ctx_0 complication in IGT. Thanks.

> > The array would then also be used from elsewhere in the code to map class
> > and instance to name and similar.
>
> Engine names are dynamically generated (from class name and engine
> instance) in init_engine() since:
>
> commit 6fa36c0233afb2cf98ed41c2b2255ab484e79add
> Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Date:   Wed Jan 22 15:23:48 2020 +0000
>
>     i915/gem_engine_topology: Generate engine names based on class
>
> > Whether or not all this changed in the intel_ctx_t rewrite I have no
> > idea. I see the "legacy" comment was added in:
> >
> > commit 9b32262bfadffffcde33c18ffb7c5292fbf4901e
> > Author: Jason Ekstrand <jason@jlekstrand.net>
> > Date:   Thu Apr 15 12:42:53 2021 -0500
> >
> >     docs: Add gem_engine_topology.h to the docs
> >
> > So perhaps ask Jason what was the plan there.
> >
> > Regards,
> >
> > Tvrtko