* [PATCH v3 0/2] riscv: switch to relative extable
@ 2021-10-21 16:19 ` Jisheng Zhang
0 siblings, 0 replies; 8+ messages in thread
From: Jisheng Zhang @ 2021-10-21 16:19 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Masahiro Yamada,
Michal Marek, Nick Desaulniers
Cc: Kefeng Wang, linux-riscv, linux-kernel, linux-kbuild
From: Jisheng Zhang <jszhang@kernel.org>
Similar as other architectures such as arm64, x86 and so on, use
offsets relative to the exception table entry values rather than
absolute addresses for both the exception locationand the fixup.
patch1 consolidates the __ex_table construction, it's a great code
clean up even w/o the 2nd patch.
patch2 does the real job.
Since v2:
- directly check R_RISCV_SUB32 in __ex_table instead of adding
addend_riscv_rela()
Since v1:
- fix build error for NOMMU case, thank lkp@intel.com
Jisheng Zhang (2):
riscv: consolidate __ex_table construction
riscv: switch to relative exception tables
arch/riscv/include/asm/Kbuild | 1 -
arch/riscv/include/asm/extable.h | 25 ++++++++++++++++++++
arch/riscv/include/asm/futex.h | 12 +++-------
arch/riscv/include/asm/uaccess.h | 40 +++++++++++---------------------
arch/riscv/lib/uaccess.S | 4 ++--
arch/riscv/mm/extable.c | 2 +-
scripts/mod/modpost.c | 15 ++++++++++++
scripts/sorttable.c | 2 +-
8 files changed, 61 insertions(+), 40 deletions(-)
create mode 100644 arch/riscv/include/asm/extable.h
--
2.33.0
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v3 0/2] riscv: switch to relative extable @ 2021-10-21 16:19 ` Jisheng Zhang 0 siblings, 0 replies; 8+ messages in thread From: Jisheng Zhang @ 2021-10-21 16:19 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Masahiro Yamada, Michal Marek, Nick Desaulniers Cc: Kefeng Wang, linux-riscv, linux-kernel, linux-kbuild From: Jisheng Zhang <jszhang@kernel.org> Similar as other architectures such as arm64, x86 and so on, use offsets relative to the exception table entry values rather than absolute addresses for both the exception locationand the fixup. patch1 consolidates the __ex_table construction, it's a great code clean up even w/o the 2nd patch. patch2 does the real job. Since v2: - directly check R_RISCV_SUB32 in __ex_table instead of adding addend_riscv_rela() Since v1: - fix build error for NOMMU case, thank lkp@intel.com Jisheng Zhang (2): riscv: consolidate __ex_table construction riscv: switch to relative exception tables arch/riscv/include/asm/Kbuild | 1 - arch/riscv/include/asm/extable.h | 25 ++++++++++++++++++++ arch/riscv/include/asm/futex.h | 12 +++------- arch/riscv/include/asm/uaccess.h | 40 +++++++++++--------------------- arch/riscv/lib/uaccess.S | 4 ++-- arch/riscv/mm/extable.c | 2 +- scripts/mod/modpost.c | 15 ++++++++++++ scripts/sorttable.c | 2 +- 8 files changed, 61 insertions(+), 40 deletions(-) create mode 100644 arch/riscv/include/asm/extable.h -- 2.33.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/2] riscv: consolidate __ex_table construction 2021-10-21 16:19 ` Jisheng Zhang @ 2021-10-21 16:20 ` Jisheng Zhang -1 siblings, 0 replies; 8+ messages in thread From: Jisheng Zhang @ 2021-10-21 16:20 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Masahiro Yamada, Michal Marek, Nick Desaulniers Cc: Kefeng Wang, linux-riscv, linux-kernel, linux-kbuild From: Jisheng Zhang <jszhang@kernel.org> Consolidate all the __ex_table constuction code with a _ASM_EXTABLE helper. There should be no functional change as a result of this patch. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/include/asm/futex.h | 12 +++------- arch/riscv/include/asm/uaccess.h | 40 +++++++++++--------------------- 2 files changed, 17 insertions(+), 35 deletions(-) diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h index 1b00badb9f87..3191574e135c 100644 --- a/arch/riscv/include/asm/futex.h +++ b/arch/riscv/include/asm/futex.h @@ -30,10 +30,7 @@ "3: li %[r],%[e] \n" \ " jump 2b,%[t] \n" \ " .previous \n" \ - " .section __ex_table,\"a\" \n" \ - " .balign " RISCV_SZPTR " \n" \ - " " RISCV_PTR " 1b, 3b \n" \ - " .previous \n" \ + _ASM_EXTABLE(1b, 3b) \ : [r] "+r" (ret), [ov] "=&r" (oldval), \ [u] "+m" (*uaddr), [t] "=&r" (tmp) \ : [op] "Jr" (oparg), [e] "i" (-EFAULT) \ @@ -103,11 +100,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, "4: li %[r],%[e] \n" " jump 3b,%[t] \n" " .previous \n" - " .section __ex_table,\"a\" \n" - " .balign " RISCV_SZPTR " \n" - " " RISCV_PTR " 1b, 4b \n" - " " RISCV_PTR " 2b, 4b \n" - " .previous \n" + _ASM_EXTABLE(1b, 4b) \ + _ASM_EXTABLE(2b, 4b) \ : [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp) : [ov] "Jr" (oldval), [nv] "Jr" (newval), [e] "i" (-EFAULT) : "memory"); diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h index f314ff44c48d..35802e72ace8 100644 --- a/arch/riscv/include/asm/uaccess.h +++ b/arch/riscv/include/asm/uaccess.h @@ -10,6 +10,12 @@ #include <asm/pgtable.h> /* for TASK_SIZE */ +#define _ASM_EXTABLE(from, to) \ + " .pushsection __ex_table, \"a\"\n" \ + " .balign " RISCV_SZPTR " \n" \ + " " RISCV_PTR "(" #from "), (" #to ")\n" \ + " .popsection\n" + /* * User space memory access functions */ @@ -93,10 +99,7 @@ do { \ " li %1, 0\n" \ " jump 2b, %2\n" \ " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 3b\n" \ - " .previous" \ + _ASM_EXTABLE(1b, 3b) \ : "+r" (err), "=&r" (__x), "=r" (__tmp) \ : "m" (*(ptr)), "i" (-EFAULT)); \ (x) = __x; \ @@ -125,11 +128,8 @@ do { \ " li %2, 0\n" \ " jump 3b, %3\n" \ " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 4b\n" \ - " " RISCV_PTR " 2b, 4b\n" \ - " .previous" \ + _ASM_EXTABLE(1b, 4b) \ + _ASM_EXTABLE(2b, 4b) \ : "+r" (err), "=&r" (__lo), "=r" (__hi), \ "=r" (__tmp) \ : "m" (__ptr[__LSW]), "m" (__ptr[__MSW]), \ @@ -233,10 +233,7 @@ do { \ " li %0, %4\n" \ " jump 2b, %1\n" \ " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 3b\n" \ - " .previous" \ + _ASM_EXTABLE(1b, 3b) \ : "+r" (err), "=r" (__tmp), "=m" (*(ptr)) \ : "rJ" (__x), "i" (-EFAULT)); \ } while (0) @@ -262,11 +259,8 @@ do { \ " li %0, %6\n" \ " jump 3b, %1\n" \ " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 4b\n" \ - " " RISCV_PTR " 2b, 4b\n" \ - " .previous" \ + _ASM_EXTABLE(1b, 4b) \ + _ASM_EXTABLE(2b, 4b) \ : "+r" (err), "=r" (__tmp), \ "=m" (__ptr[__LSW]), \ "=m" (__ptr[__MSW]) \ @@ -417,10 +411,7 @@ unsigned long __must_check clear_user(void __user *to, unsigned long n) " li %[err], %[efault]\n" \ " jump 1b, %[rc]\n" \ ".previous\n" \ - ".section __ex_table,\"a\"\n" \ - ".balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 2b\n" \ - ".previous\n" \ + _ASM_EXTABLE(1b, 2b) \ : [ret] "=&r" (__ret), \ [rc] "=&r" (__rc), \ [ptr] "+A" (*__ptr), \ @@ -443,10 +434,7 @@ unsigned long __must_check clear_user(void __user *to, unsigned long n) " li %[err], %[efault]\n" \ " jump 1b, %[rc]\n" \ ".previous\n" \ - ".section __ex_table,\"a\"\n" \ - ".balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 2b\n" \ - ".previous\n" \ + _ASM_EXTABLE(1b, 2b) \ : [ret] "=&r" (__ret), \ [rc] "=&r" (__rc), \ [ptr] "+A" (*__ptr), \ -- 2.33.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 1/2] riscv: consolidate __ex_table construction @ 2021-10-21 16:20 ` Jisheng Zhang 0 siblings, 0 replies; 8+ messages in thread From: Jisheng Zhang @ 2021-10-21 16:20 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Masahiro Yamada, Michal Marek, Nick Desaulniers Cc: Kefeng Wang, linux-riscv, linux-kernel, linux-kbuild From: Jisheng Zhang <jszhang@kernel.org> Consolidate all the __ex_table constuction code with a _ASM_EXTABLE helper. There should be no functional change as a result of this patch. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/include/asm/futex.h | 12 +++------- arch/riscv/include/asm/uaccess.h | 40 +++++++++++--------------------- 2 files changed, 17 insertions(+), 35 deletions(-) diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h index 1b00badb9f87..3191574e135c 100644 --- a/arch/riscv/include/asm/futex.h +++ b/arch/riscv/include/asm/futex.h @@ -30,10 +30,7 @@ "3: li %[r],%[e] \n" \ " jump 2b,%[t] \n" \ " .previous \n" \ - " .section __ex_table,\"a\" \n" \ - " .balign " RISCV_SZPTR " \n" \ - " " RISCV_PTR " 1b, 3b \n" \ - " .previous \n" \ + _ASM_EXTABLE(1b, 3b) \ : [r] "+r" (ret), [ov] "=&r" (oldval), \ [u] "+m" (*uaddr), [t] "=&r" (tmp) \ : [op] "Jr" (oparg), [e] "i" (-EFAULT) \ @@ -103,11 +100,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, "4: li %[r],%[e] \n" " jump 3b,%[t] \n" " .previous \n" - " .section __ex_table,\"a\" \n" - " .balign " RISCV_SZPTR " \n" - " " RISCV_PTR " 1b, 4b \n" - " " RISCV_PTR " 2b, 4b \n" - " .previous \n" + _ASM_EXTABLE(1b, 4b) \ + _ASM_EXTABLE(2b, 4b) \ : [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp) : [ov] "Jr" (oldval), [nv] "Jr" (newval), [e] "i" (-EFAULT) : "memory"); diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h index f314ff44c48d..35802e72ace8 100644 --- a/arch/riscv/include/asm/uaccess.h +++ b/arch/riscv/include/asm/uaccess.h @@ -10,6 +10,12 @@ #include <asm/pgtable.h> /* for TASK_SIZE */ +#define _ASM_EXTABLE(from, to) \ + " .pushsection __ex_table, \"a\"\n" \ + " .balign " RISCV_SZPTR " \n" \ + " " RISCV_PTR "(" #from "), (" #to ")\n" \ + " .popsection\n" + /* * User space memory access functions */ @@ -93,10 +99,7 @@ do { \ " li %1, 0\n" \ " jump 2b, %2\n" \ " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 3b\n" \ - " .previous" \ + _ASM_EXTABLE(1b, 3b) \ : "+r" (err), "=&r" (__x), "=r" (__tmp) \ : "m" (*(ptr)), "i" (-EFAULT)); \ (x) = __x; \ @@ -125,11 +128,8 @@ do { \ " li %2, 0\n" \ " jump 3b, %3\n" \ " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 4b\n" \ - " " RISCV_PTR " 2b, 4b\n" \ - " .previous" \ + _ASM_EXTABLE(1b, 4b) \ + _ASM_EXTABLE(2b, 4b) \ : "+r" (err), "=&r" (__lo), "=r" (__hi), \ "=r" (__tmp) \ : "m" (__ptr[__LSW]), "m" (__ptr[__MSW]), \ @@ -233,10 +233,7 @@ do { \ " li %0, %4\n" \ " jump 2b, %1\n" \ " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 3b\n" \ - " .previous" \ + _ASM_EXTABLE(1b, 3b) \ : "+r" (err), "=r" (__tmp), "=m" (*(ptr)) \ : "rJ" (__x), "i" (-EFAULT)); \ } while (0) @@ -262,11 +259,8 @@ do { \ " li %0, %6\n" \ " jump 3b, %1\n" \ " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 4b\n" \ - " " RISCV_PTR " 2b, 4b\n" \ - " .previous" \ + _ASM_EXTABLE(1b, 4b) \ + _ASM_EXTABLE(2b, 4b) \ : "+r" (err), "=r" (__tmp), \ "=m" (__ptr[__LSW]), \ "=m" (__ptr[__MSW]) \ @@ -417,10 +411,7 @@ unsigned long __must_check clear_user(void __user *to, unsigned long n) " li %[err], %[efault]\n" \ " jump 1b, %[rc]\n" \ ".previous\n" \ - ".section __ex_table,\"a\"\n" \ - ".balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 2b\n" \ - ".previous\n" \ + _ASM_EXTABLE(1b, 2b) \ : [ret] "=&r" (__ret), \ [rc] "=&r" (__rc), \ [ptr] "+A" (*__ptr), \ @@ -443,10 +434,7 @@ unsigned long __must_check clear_user(void __user *to, unsigned long n) " li %[err], %[efault]\n" \ " jump 1b, %[rc]\n" \ ".previous\n" \ - ".section __ex_table,\"a\"\n" \ - ".balign " RISCV_SZPTR "\n" \ - " " RISCV_PTR " 1b, 2b\n" \ - ".previous\n" \ + _ASM_EXTABLE(1b, 2b) \ : [ret] "=&r" (__ret), \ [rc] "=&r" (__rc), \ [ptr] "+A" (*__ptr), \ -- 2.33.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] riscv: switch to relative exception tables 2021-10-21 16:19 ` Jisheng Zhang @ 2021-10-21 16:21 ` Jisheng Zhang -1 siblings, 0 replies; 8+ messages in thread From: Jisheng Zhang @ 2021-10-21 16:21 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Masahiro Yamada, Michal Marek, Nick Desaulniers Cc: Kefeng Wang, linux-riscv, linux-kernel, linux-kbuild From: Jisheng Zhang <jszhang@kernel.org> Similar as other architectures such as arm64, x86 and so on, use offsets relative to the exception table entry values rather than absolute addresses for both the exception locationand the fixup. However, RISCV label difference will actually produce two relocations, a pair of R_RISCV_ADD32 and R_RISCV_SUB32. Take below simple code for example: $ cat test.S .section .text 1: nop .section __ex_table,"a" .balign 4 .long (1b - .) .previous $ riscv64-linux-gnu-gcc -c test.S $ riscv64-linux-gnu-readelf -r test.o Relocation section '.rela__ex_table' at offset 0x100 contains 2 entries: Offset Info Type Sym. Value Sym. Name + Addend 000000000000 000600000023 R_RISCV_ADD32 0000000000000000 .L1^B1 + 0 000000000000 000500000027 R_RISCV_SUB32 0000000000000000 .L0 + 0 The modpost will complain the R_RISCV_SUB32 relocation, so we need to patch modpost.c to skip this relocation for .rela__ex_table section. After this patch, the __ex_table section size of defconfig vmlinux is reduced from 7072 Bytes to 3536 Bytes. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/include/asm/Kbuild | 1 - arch/riscv/include/asm/extable.h | 25 +++++++++++++++++++++++++ arch/riscv/include/asm/uaccess.h | 4 ++-- arch/riscv/lib/uaccess.S | 4 ++-- arch/riscv/mm/extable.c | 2 +- scripts/mod/modpost.c | 15 +++++++++++++++ scripts/sorttable.c | 2 +- 7 files changed, 46 insertions(+), 7 deletions(-) create mode 100644 arch/riscv/include/asm/extable.h diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index 445ccc97305a..57b86fd9916c 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 generic-y += early_ioremap.h -generic-y += extable.h generic-y += flat.h generic-y += kvm_para.h generic-y += user.h diff --git a/arch/riscv/include/asm/extable.h b/arch/riscv/include/asm/extable.h new file mode 100644 index 000000000000..bc439b0fdb29 --- /dev/null +++ b/arch/riscv/include/asm/extable.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_EXTABLE_H +#define _ASM_RISCV_EXTABLE_H + +/* + * The exception table consists of pairs of relative offsets: the first + * is the relative offset to an instruction that is allowed to fault, + * and the second is the relative offset at which the program should + * continue. No registers are modified, so it is entirely up to the + * continuation code to figure out what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry { + int insn, fixup; +}; + +#define ARCH_HAS_RELATIVE_EXTABLE + +extern int fixup_exception(struct pt_regs *regs); +#endif diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h index 35802e72ace8..540903c7d3e8 100644 --- a/arch/riscv/include/asm/uaccess.h +++ b/arch/riscv/include/asm/uaccess.h @@ -12,8 +12,8 @@ #define _ASM_EXTABLE(from, to) \ " .pushsection __ex_table, \"a\"\n" \ - " .balign " RISCV_SZPTR " \n" \ - " " RISCV_PTR "(" #from "), (" #to ")\n" \ + " .balign 4\n" \ + " .long (" #from " - .), (" #to " - .)\n" \ " .popsection\n" /* diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index 63bc691cff91..55f80f84e23f 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -7,8 +7,8 @@ 100: \op \reg, \addr .section __ex_table,"a" - .balign RISCV_SZPTR - RISCV_PTR 100b, \lbl + .balign 4 + .long (100b - .), (\lbl - .) .previous .endm diff --git a/arch/riscv/mm/extable.c b/arch/riscv/mm/extable.c index 2fc729422151..6aa8ffac4be7 100644 --- a/arch/riscv/mm/extable.c +++ b/arch/riscv/mm/extable.c @@ -17,7 +17,7 @@ int fixup_exception(struct pt_regs *regs) fixup = search_exception_tables(regs->epc); if (fixup) { - regs->epc = fixup->fixup; + regs->epc = (unsigned long)&fixup->fixup + fixup->fixup; return 1; } return 0; diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c index cb8ab7d91d30..6bfa33217914 100644 --- a/scripts/mod/modpost.c +++ b/scripts/mod/modpost.c @@ -1830,6 +1830,14 @@ static int addend_mips_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) return 0; } +#ifndef EM_RISCV +#define EM_RISCV 243 +#endif + +#ifndef R_RISCV_SUB32 +#define R_RISCV_SUB32 39 +#endif + static void section_rela(const char *modname, struct elf_info *elf, Elf_Shdr *sechdr) { @@ -1866,6 +1874,13 @@ static void section_rela(const char *modname, struct elf_info *elf, r_sym = ELF_R_SYM(r.r_info); #endif r.r_addend = TO_NATIVE(rela->r_addend); + switch (elf->hdr->e_machine) { + case EM_RISCV: + if (!strcmp("__ex_table", fromsec) && + ELF_R_TYPE(r.r_info) == R_RISCV_SUB32) + continue; + break; + } sym = elf->symtab_start + r_sym; /* Skip special sections */ if (is_shndx_special(sym->st_shndx)) diff --git a/scripts/sorttable.c b/scripts/sorttable.c index 6ee4fa882919..39e86e4acea3 100644 --- a/scripts/sorttable.c +++ b/scripts/sorttable.c @@ -346,6 +346,7 @@ static int do_file(char const *const fname, void *addr) case EM_PARISC: case EM_PPC: case EM_PPC64: + case EM_RISCV: custom_sort = sort_relative_table; break; case EM_ARCOMPACT: @@ -353,7 +354,6 @@ static int do_file(char const *const fname, void *addr) case EM_ARM: case EM_MICROBLAZE: case EM_MIPS: - case EM_RISCV: case EM_XTENSA: break; default: -- 2.33.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] riscv: switch to relative exception tables @ 2021-10-21 16:21 ` Jisheng Zhang 0 siblings, 0 replies; 8+ messages in thread From: Jisheng Zhang @ 2021-10-21 16:21 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Masahiro Yamada, Michal Marek, Nick Desaulniers Cc: Kefeng Wang, linux-riscv, linux-kernel, linux-kbuild From: Jisheng Zhang <jszhang@kernel.org> Similar as other architectures such as arm64, x86 and so on, use offsets relative to the exception table entry values rather than absolute addresses for both the exception locationand the fixup. However, RISCV label difference will actually produce two relocations, a pair of R_RISCV_ADD32 and R_RISCV_SUB32. Take below simple code for example: $ cat test.S .section .text 1: nop .section __ex_table,"a" .balign 4 .long (1b - .) .previous $ riscv64-linux-gnu-gcc -c test.S $ riscv64-linux-gnu-readelf -r test.o Relocation section '.rela__ex_table' at offset 0x100 contains 2 entries: Offset Info Type Sym. Value Sym. Name + Addend 000000000000 000600000023 R_RISCV_ADD32 0000000000000000 .L1^B1 + 0 000000000000 000500000027 R_RISCV_SUB32 0000000000000000 .L0 + 0 The modpost will complain the R_RISCV_SUB32 relocation, so we need to patch modpost.c to skip this relocation for .rela__ex_table section. After this patch, the __ex_table section size of defconfig vmlinux is reduced from 7072 Bytes to 3536 Bytes. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/include/asm/Kbuild | 1 - arch/riscv/include/asm/extable.h | 25 +++++++++++++++++++++++++ arch/riscv/include/asm/uaccess.h | 4 ++-- arch/riscv/lib/uaccess.S | 4 ++-- arch/riscv/mm/extable.c | 2 +- scripts/mod/modpost.c | 15 +++++++++++++++ scripts/sorttable.c | 2 +- 7 files changed, 46 insertions(+), 7 deletions(-) create mode 100644 arch/riscv/include/asm/extable.h diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index 445ccc97305a..57b86fd9916c 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 generic-y += early_ioremap.h -generic-y += extable.h generic-y += flat.h generic-y += kvm_para.h generic-y += user.h diff --git a/arch/riscv/include/asm/extable.h b/arch/riscv/include/asm/extable.h new file mode 100644 index 000000000000..bc439b0fdb29 --- /dev/null +++ b/arch/riscv/include/asm/extable.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_EXTABLE_H +#define _ASM_RISCV_EXTABLE_H + +/* + * The exception table consists of pairs of relative offsets: the first + * is the relative offset to an instruction that is allowed to fault, + * and the second is the relative offset at which the program should + * continue. No registers are modified, so it is entirely up to the + * continuation code to figure out what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry { + int insn, fixup; +}; + +#define ARCH_HAS_RELATIVE_EXTABLE + +extern int fixup_exception(struct pt_regs *regs); +#endif diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h index 35802e72ace8..540903c7d3e8 100644 --- a/arch/riscv/include/asm/uaccess.h +++ b/arch/riscv/include/asm/uaccess.h @@ -12,8 +12,8 @@ #define _ASM_EXTABLE(from, to) \ " .pushsection __ex_table, \"a\"\n" \ - " .balign " RISCV_SZPTR " \n" \ - " " RISCV_PTR "(" #from "), (" #to ")\n" \ + " .balign 4\n" \ + " .long (" #from " - .), (" #to " - .)\n" \ " .popsection\n" /* diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index 63bc691cff91..55f80f84e23f 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -7,8 +7,8 @@ 100: \op \reg, \addr .section __ex_table,"a" - .balign RISCV_SZPTR - RISCV_PTR 100b, \lbl + .balign 4 + .long (100b - .), (\lbl - .) .previous .endm diff --git a/arch/riscv/mm/extable.c b/arch/riscv/mm/extable.c index 2fc729422151..6aa8ffac4be7 100644 --- a/arch/riscv/mm/extable.c +++ b/arch/riscv/mm/extable.c @@ -17,7 +17,7 @@ int fixup_exception(struct pt_regs *regs) fixup = search_exception_tables(regs->epc); if (fixup) { - regs->epc = fixup->fixup; + regs->epc = (unsigned long)&fixup->fixup + fixup->fixup; return 1; } return 0; diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c index cb8ab7d91d30..6bfa33217914 100644 --- a/scripts/mod/modpost.c +++ b/scripts/mod/modpost.c @@ -1830,6 +1830,14 @@ static int addend_mips_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) return 0; } +#ifndef EM_RISCV +#define EM_RISCV 243 +#endif + +#ifndef R_RISCV_SUB32 +#define R_RISCV_SUB32 39 +#endif + static void section_rela(const char *modname, struct elf_info *elf, Elf_Shdr *sechdr) { @@ -1866,6 +1874,13 @@ static void section_rela(const char *modname, struct elf_info *elf, r_sym = ELF_R_SYM(r.r_info); #endif r.r_addend = TO_NATIVE(rela->r_addend); + switch (elf->hdr->e_machine) { + case EM_RISCV: + if (!strcmp("__ex_table", fromsec) && + ELF_R_TYPE(r.r_info) == R_RISCV_SUB32) + continue; + break; + } sym = elf->symtab_start + r_sym; /* Skip special sections */ if (is_shndx_special(sym->st_shndx)) diff --git a/scripts/sorttable.c b/scripts/sorttable.c index 6ee4fa882919..39e86e4acea3 100644 --- a/scripts/sorttable.c +++ b/scripts/sorttable.c @@ -346,6 +346,7 @@ static int do_file(char const *const fname, void *addr) case EM_PARISC: case EM_PPC: case EM_PPC64: + case EM_RISCV: custom_sort = sort_relative_table; break; case EM_ARCOMPACT: @@ -353,7 +354,6 @@ static int do_file(char const *const fname, void *addr) case EM_ARM: case EM_MICROBLAZE: case EM_MIPS: - case EM_RISCV: case EM_XTENSA: break; default: -- 2.33.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 0/2] riscv: switch to relative extable 2021-10-21 16:19 ` Jisheng Zhang @ 2021-10-22 0:46 ` Kefeng Wang -1 siblings, 0 replies; 8+ messages in thread From: Kefeng Wang @ 2021-10-22 0:46 UTC (permalink / raw) To: Jisheng Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou, Masahiro Yamada, Michal Marek, Nick Desaulniers Cc: linux-riscv, linux-kernel, linux-kbuild On 2021/10/22 0:19, Jisheng Zhang wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > Similar as other architectures such as arm64, x86 and so on, use > offsets relative to the exception table entry values rather than > absolute addresses for both the exception locationand the fixup. > > patch1 consolidates the __ex_table construction, it's a great code > clean up even w/o the 2nd patch. > > patch2 does the real job. Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com> ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 0/2] riscv: switch to relative extable @ 2021-10-22 0:46 ` Kefeng Wang 0 siblings, 0 replies; 8+ messages in thread From: Kefeng Wang @ 2021-10-22 0:46 UTC (permalink / raw) To: Jisheng Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou, Masahiro Yamada, Michal Marek, Nick Desaulniers Cc: linux-riscv, linux-kernel, linux-kbuild On 2021/10/22 0:19, Jisheng Zhang wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > Similar as other architectures such as arm64, x86 and so on, use > offsets relative to the exception table entry values rather than > absolute addresses for both the exception locationand the fixup. > > patch1 consolidates the __ex_table construction, it's a great code > clean up even w/o the 2nd patch. > > patch2 does the real job. Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-10-22 0:47 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-10-21 16:19 [PATCH v3 0/2] riscv: switch to relative extable Jisheng Zhang 2021-10-21 16:19 ` Jisheng Zhang 2021-10-21 16:20 ` [PATCH v3 1/2] riscv: consolidate __ex_table construction Jisheng Zhang 2021-10-21 16:20 ` Jisheng Zhang 2021-10-21 16:21 ` [PATCH v3 2/2] riscv: switch to relative exception tables Jisheng Zhang 2021-10-21 16:21 ` Jisheng Zhang 2021-10-22 0:46 ` [PATCH v3 0/2] riscv: switch to relative extable Kefeng Wang 2021-10-22 0:46 ` Kefeng Wang
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