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* [PATCH v2] riscv: cacheinfo: fix typo of homogeneous
       [not found] <750f6239-154d-9190-24ff-ece033add638@infread.org>
@ 2021-10-23 21:07   ` hasheddan
  0 siblings, 0 replies; 2+ messages in thread
From: hasheddan @ 2021-10-23 21:07 UTC (permalink / raw)
  Cc: hasheddan, Paul Walmsley, Palmer Dabbelt, Albert Ou, Kefeng Wang,
	Thomas Gleixner, Peter Zijlstra, Atish Patra, linux-riscv,
	linux-kernel

Updates 'homonogenous' to 'homogeneous' in comment.

Signed-off-by: hasheddan <georgedanielmangum@gmail.com>
---
 arch/riscv/kernel/cacheinfo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 90deabfe63ea..f0c2043943bf 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -29,7 +29,7 @@ static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)
 	/*
 	 * Using raw_smp_processor_id() elides a preemptability check, but this
 	 * is really indicative of a larger problem: the cacheinfo UABI assumes
-	 * that cores have a homonogenous view of the cache hierarchy.  That
+	 * that cores have a homogeneous view of the cache hierarchy.  That
 	 * happens to be the case for the current set of RISC-V systems, but
 	 * likely won't be true in general.  Since there's no way to provide
 	 * correct information for these systems via the current UABI we're
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* [PATCH v2] riscv: cacheinfo: fix typo of homogeneous
@ 2021-10-23 21:07   ` hasheddan
  0 siblings, 0 replies; 2+ messages in thread
From: hasheddan @ 2021-10-23 21:07 UTC (permalink / raw)
  Cc: hasheddan, Paul Walmsley, Palmer Dabbelt, Albert Ou, Kefeng Wang,
	Thomas Gleixner, Peter Zijlstra, Atish Patra, linux-riscv,
	linux-kernel

Updates 'homonogenous' to 'homogeneous' in comment.

Signed-off-by: hasheddan <georgedanielmangum@gmail.com>
---
 arch/riscv/kernel/cacheinfo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 90deabfe63ea..f0c2043943bf 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -29,7 +29,7 @@ static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)
 	/*
 	 * Using raw_smp_processor_id() elides a preemptability check, but this
 	 * is really indicative of a larger problem: the cacheinfo UABI assumes
-	 * that cores have a homonogenous view of the cache hierarchy.  That
+	 * that cores have a homogeneous view of the cache hierarchy.  That
 	 * happens to be the case for the current set of RISC-V systems, but
 	 * likely won't be true in general.  Since there's no way to provide
 	 * correct information for these systems via the current UABI we're
-- 
2.25.1


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^ permalink raw reply related	[flat|nested] 2+ messages in thread

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2021-10-23 21:07 ` [PATCH v2] riscv: cacheinfo: fix typo of homogeneous hasheddan
2021-10-23 21:07   ` hasheddan

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