From: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bin.meng@windriver.com, richard.henderson@linaro.org, alistair.francis@wdc.com, fabien.portas@grenoble-inp.org, palmer@dabbelt.com, "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>, philmd@redhat.com Subject: [PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns Date: Mon, 25 Oct 2021 14:28:16 +0200 [thread overview] Message-ID: <20211025122818.168890-16-frederic.petrot@univ-grenoble-alpes.fr> (raw) In-Reply-To: <20211025122818.168890-1-frederic.petrot@univ-grenoble-alpes.fr> Given the side effects they have, the csr instructions are realized as helpers. We extend this existing infrastructure for 128-bit sized csr. We return 128-bit values using the same approach as for div/rem. Theses helpers all call a unique function that is currently a fallback on the 64-bit version. The trans_csrxx functions supporting 128-bit are yet to be implemented. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/cpu.h | 4 ++++ target/riscv/helper.h | 3 +++ target/riscv/csr.c | 17 ++++++++++++++++ target/riscv/op_helper.c | 44 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d8093be74d..328ba42a30 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -470,6 +470,10 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, target_ulong new_value, target_ulong write_mask); +RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, + Int128 *ret_value, + Int128 new_value, Int128 write_mask); + typedef struct { const char *name; riscv_csr_predicate_fn predicate; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 957ae8a2a2..1ef43e0daf 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -66,6 +66,9 @@ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_2(csrr, tl, env, int) DEF_HELPER_3(csrw, void, env, int, tl) DEF_HELPER_4(csrrw, tl, env, int, tl, tl) +DEF_HELPER_2(csrr_i128, tl, env, int) +DEF_HELPER_4(csrw_i128, void, env, int, tl, tl) +DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_2(sret, tl, env, tl) DEF_HELPER_2(mret, tl, env, tl) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 69e4d65fcd..8a791d6b7c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1516,6 +1516,23 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, + Int128 *ret_value, + Int128 new_value, Int128 write_mask) +{ + /* fall back to 64-bit version for now */ + target_ulong ret_64; + RISCVException ret = riscv_csrrw(env, csrno, &ret_64, + int128_getlo(new_value), + int128_getlo(write_mask)); + + if (ret_value) { + *ret_value = int128_make64(ret_64); + } + + return ret; +} + /* * Debugger support. If not in user mode, set env->debugger before the * riscv_csrrw call and clear it after the call. diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index ee7c24efe7..f4cf9c4698 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -69,6 +69,50 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, return val; } +target_ulong helper_csrr_i128(CPURISCVState *env, int csr) +{ + Int128 rv = int128_zero(); + RISCVException ret = riscv_csrrw_i128(env, csr, &rv, + int128_zero(), + int128_zero()); + + if (ret != RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); + } + + env->retxh = int128_gethi(rv); + return int128_getlo(rv); +} + +void helper_csrw_i128(CPURISCVState *env, int csr, + target_ulong srcl, target_ulong srch) +{ + RISCVException ret = riscv_csrrw_i128(env, csr, NULL, + int128_make128(srcl, srch), + UINT128_MAX); + + if (ret != RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); + } +} + +target_ulong helper_csrrw_i128(CPURISCVState *env, int csr, + target_ulong srcl, target_ulong srch, + target_ulong maskl, target_ulong maskh) +{ + Int128 rv = int128_zero(); + RISCVException ret = riscv_csrrw_i128(env, csr, &rv, + int128_make128(srcl, srch), + int128_make128(maskl, maskh)); + + if (ret != RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); + } + + env->retxh = int128_gethi(rv); + return int128_getlo(rv); +} + #ifndef CONFIG_USER_ONLY target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) -- 2.33.0
WARNING: multiple messages have this Message-ID (diff)
From: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, richard.henderson@linaro.org, bin.meng@windriver.com, philmd@redhat.com, palmer@dabbelt.com, fabien.portas@grenoble-inp.org, "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr> Subject: [PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns Date: Mon, 25 Oct 2021 14:28:16 +0200 [thread overview] Message-ID: <20211025122818.168890-16-frederic.petrot@univ-grenoble-alpes.fr> (raw) In-Reply-To: <20211025122818.168890-1-frederic.petrot@univ-grenoble-alpes.fr> Given the side effects they have, the csr instructions are realized as helpers. We extend this existing infrastructure for 128-bit sized csr. We return 128-bit values using the same approach as for div/rem. Theses helpers all call a unique function that is currently a fallback on the 64-bit version. The trans_csrxx functions supporting 128-bit are yet to be implemented. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/cpu.h | 4 ++++ target/riscv/helper.h | 3 +++ target/riscv/csr.c | 17 ++++++++++++++++ target/riscv/op_helper.c | 44 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d8093be74d..328ba42a30 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -470,6 +470,10 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, target_ulong new_value, target_ulong write_mask); +RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, + Int128 *ret_value, + Int128 new_value, Int128 write_mask); + typedef struct { const char *name; riscv_csr_predicate_fn predicate; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 957ae8a2a2..1ef43e0daf 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -66,6 +66,9 @@ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_2(csrr, tl, env, int) DEF_HELPER_3(csrw, void, env, int, tl) DEF_HELPER_4(csrrw, tl, env, int, tl, tl) +DEF_HELPER_2(csrr_i128, tl, env, int) +DEF_HELPER_4(csrw_i128, void, env, int, tl, tl) +DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_2(sret, tl, env, tl) DEF_HELPER_2(mret, tl, env, tl) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 69e4d65fcd..8a791d6b7c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1516,6 +1516,23 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, + Int128 *ret_value, + Int128 new_value, Int128 write_mask) +{ + /* fall back to 64-bit version for now */ + target_ulong ret_64; + RISCVException ret = riscv_csrrw(env, csrno, &ret_64, + int128_getlo(new_value), + int128_getlo(write_mask)); + + if (ret_value) { + *ret_value = int128_make64(ret_64); + } + + return ret; +} + /* * Debugger support. If not in user mode, set env->debugger before the * riscv_csrrw call and clear it after the call. diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index ee7c24efe7..f4cf9c4698 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -69,6 +69,50 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, return val; } +target_ulong helper_csrr_i128(CPURISCVState *env, int csr) +{ + Int128 rv = int128_zero(); + RISCVException ret = riscv_csrrw_i128(env, csr, &rv, + int128_zero(), + int128_zero()); + + if (ret != RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); + } + + env->retxh = int128_gethi(rv); + return int128_getlo(rv); +} + +void helper_csrw_i128(CPURISCVState *env, int csr, + target_ulong srcl, target_ulong srch) +{ + RISCVException ret = riscv_csrrw_i128(env, csr, NULL, + int128_make128(srcl, srch), + UINT128_MAX); + + if (ret != RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); + } +} + +target_ulong helper_csrrw_i128(CPURISCVState *env, int csr, + target_ulong srcl, target_ulong srch, + target_ulong maskl, target_ulong maskh) +{ + Int128 rv = int128_zero(); + RISCVException ret = riscv_csrrw_i128(env, csr, &rv, + int128_make128(srcl, srch), + int128_make128(maskl, maskh)); + + if (ret != RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); + } + + env->retxh = int128_gethi(rv); + return int128_getlo(rv); +} + #ifndef CONFIG_USER_ONLY target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) -- 2.33.0
next prev parent reply other threads:[~2021-10-25 12:43 UTC|newest] Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-25 12:28 [PATCH v4 00/17] Adding partial support for 128-bit riscv target Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 12:28 ` [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 20:09 ` Richard Henderson 2021-10-25 20:09 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 15:47 ` Philippe Mathieu-Daudé 2021-10-25 15:47 ` Philippe Mathieu-Daudé 2021-10-25 20:16 ` Richard Henderson 2021-10-25 20:16 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 03/17] target/riscv: additional macros to check instruction support Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-30 23:49 ` Richard Henderson 2021-10-30 23:49 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 15:51 ` Philippe Mathieu-Daudé 2021-10-25 15:51 ` Philippe Mathieu-Daudé 2021-10-25 19:08 ` Richard Henderson 2021-10-25 19:08 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 15:55 ` Philippe Mathieu-Daudé 2021-10-25 15:55 ` Philippe Mathieu-Daudé 2021-10-25 19:10 ` Richard Henderson 2021-10-25 19:10 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-30 23:52 ` Richard Henderson 2021-10-30 23:52 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 07/17] target/riscv: moving some insns close to similar insns Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 15:56 ` Philippe Mathieu-Daudé 2021-10-25 15:56 ` Philippe Mathieu-Daudé 2021-10-25 12:28 ` [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-31 3:41 ` Richard Henderson 2021-10-31 3:41 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-31 3:44 ` Richard Henderson 2021-10-31 3:44 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-31 3:49 ` Richard Henderson 2021-10-31 3:49 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-31 4:03 ` Richard Henderson 2021-10-31 4:03 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-11-02 12:43 ` Richard Henderson 2021-11-02 12:43 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 13/17] target/riscv: support for 128-bit M extension Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-11-02 13:05 ` Richard Henderson 2021-11-02 13:05 ` Richard Henderson 2021-10-25 12:28 ` [PATCH v4 14/17] target/riscv: adding high part of some csrs Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot [this message] 2021-10-25 12:28 ` [PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot 2021-10-25 12:28 ` [PATCH v4 16/17] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-10-25 12:28 ` [PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot 2021-10-25 12:28 ` Frédéric Pétrot 2021-11-02 13:22 ` Richard Henderson 2021-11-02 13:22 ` Richard Henderson
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