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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, andi.shyti@intel.com,
	Paulo Zanoni <paulo.r.zanoni@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@intel.com>,
	Matt Roper <matthew.d.roper@intel.com>,
	Andi Shyti <andi.shyti@linux.intel.com>
Subject: [PATCH v3 08/10] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
Date: Thu, 28 Oct 2021 20:28:15 -0700	[thread overview]
Message-ID: <20211029032817.3747750-9-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20211029032817.3747750-1-matthew.d.roper@intel.com>

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Loop through all the tiles when initializing and resetting interrupts.

v2:
 - Access tile0 registers through dev_priv->uncore rather than
   dev_priv->gt.uncore for clarity.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 57a58151eaae..c2955916e0fe 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3194,14 +3194,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_gt *gt = &dev_priv->gt;
 	struct intel_uncore *uncore = gt->uncore;
+	unsigned int i;
 
 	dg1_master_intr_disable(dev_priv->uncore.regs);
 
-	gen11_gt_irq_reset(gt);
-	gen11_display_irq_reset(dev_priv);
+	for_each_gt(dev_priv, i, gt) {
+		gen11_gt_irq_reset(gt);
 
-	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
-	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+		uncore = gt->uncore;
+		GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+		GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+	}
+
+	gen11_display_irq_reset(dev_priv);
 }
 
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3894,13 +3899,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 
 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-	struct intel_gt *gt = &dev_priv->gt;
-	struct intel_uncore *uncore = gt->uncore;
+	struct intel_gt *gt;
 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+	unsigned int i;
 
-	gen11_gt_irq_postinstall(gt);
+	for_each_gt(dev_priv, i, gt) {
+		gen11_gt_irq_postinstall(gt);
 
-	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+		GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
+			      gu_misc_masked);
+	}
 
 	if (HAS_DISPLAY(dev_priv)) {
 		icp_irq_postinstall(dev_priv);
@@ -3909,8 +3917,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 				   GEN11_DISPLAY_IRQ_ENABLE);
 	}
 
-	dg1_master_intr_enable(uncore->regs);
-	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
+	dg1_master_intr_enable(dev_priv->uncore.regs);
+	intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR);
 }
 
 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
-- 
2.33.0


WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, andi.shyti@intel.com,
	Paulo Zanoni <paulo.r.zanoni@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@intel.com>,
	Matt Roper <matthew.d.roper@intel.com>,
	Andi Shyti <andi.shyti@linux.intel.com>
Subject: [Intel-gfx] [PATCH v3 08/10] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
Date: Thu, 28 Oct 2021 20:28:15 -0700	[thread overview]
Message-ID: <20211029032817.3747750-9-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20211029032817.3747750-1-matthew.d.roper@intel.com>

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Loop through all the tiles when initializing and resetting interrupts.

v2:
 - Access tile0 registers through dev_priv->uncore rather than
   dev_priv->gt.uncore for clarity.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 57a58151eaae..c2955916e0fe 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3194,14 +3194,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_gt *gt = &dev_priv->gt;
 	struct intel_uncore *uncore = gt->uncore;
+	unsigned int i;
 
 	dg1_master_intr_disable(dev_priv->uncore.regs);
 
-	gen11_gt_irq_reset(gt);
-	gen11_display_irq_reset(dev_priv);
+	for_each_gt(dev_priv, i, gt) {
+		gen11_gt_irq_reset(gt);
 
-	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
-	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+		uncore = gt->uncore;
+		GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+		GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+	}
+
+	gen11_display_irq_reset(dev_priv);
 }
 
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3894,13 +3899,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 
 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-	struct intel_gt *gt = &dev_priv->gt;
-	struct intel_uncore *uncore = gt->uncore;
+	struct intel_gt *gt;
 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+	unsigned int i;
 
-	gen11_gt_irq_postinstall(gt);
+	for_each_gt(dev_priv, i, gt) {
+		gen11_gt_irq_postinstall(gt);
 
-	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+		GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
+			      gu_misc_masked);
+	}
 
 	if (HAS_DISPLAY(dev_priv)) {
 		icp_irq_postinstall(dev_priv);
@@ -3909,8 +3917,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 				   GEN11_DISPLAY_IRQ_ENABLE);
 	}
 
-	dg1_master_intr_enable(uncore->regs);
-	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
+	dg1_master_intr_enable(dev_priv->uncore.regs);
+	intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR);
 }
 
 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
-- 
2.33.0


  parent reply	other threads:[~2021-10-29  3:29 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-29  3:28 [PATCH v3 00/10] i915: Initial multi-tile support Matt Roper
2021-10-29  3:28 ` [Intel-gfx] " Matt Roper
2021-10-29  3:28 ` [PATCH v3 01/10] drm/i915: rework some irq functions to take intel_gt as argument Matt Roper
2021-10-29  3:28   ` [Intel-gfx] " Matt Roper
2021-10-29  3:28 ` [PATCH v3 02/10] drm/i915: split general MMIO setup from per-GT uncore init Matt Roper
2021-10-29  3:28   ` [Intel-gfx] " Matt Roper
2021-11-11  5:12   ` Matt Roper
2021-11-11  5:12     ` [Intel-gfx] " Matt Roper
2021-10-29  3:28 ` [PATCH v3 03/10] drm/i915: Restructure probe to handle multi-tile platforms Matt Roper
2021-10-29  3:28   ` [Intel-gfx] " Matt Roper
2021-11-01 22:58   ` Andi Shyti
2021-11-01 22:58     ` [Intel-gfx] " Andi Shyti
2021-11-01 23:21   ` Andi Shyti
2021-11-01 23:21     ` [Intel-gfx] " Andi Shyti
2021-10-29  3:28 ` [PATCH v3 04/10] drm/i915: Store backpointer to GT in uncore Matt Roper
2021-10-29  3:28   ` [Intel-gfx] " Matt Roper
2021-10-29  3:28 ` [PATCH v3 05/10] drm/i915: Prepare for multiple gts Matt Roper
2021-10-29  3:28   ` [Intel-gfx] " Matt Roper
2021-11-01 23:11   ` Andi Shyti
2021-11-01 23:11     ` [Intel-gfx] " Andi Shyti
2021-11-02  9:36     ` Tvrtko Ursulin
2021-11-02 11:26       ` Andi Shyti
2021-11-02 11:26         ` Andi Shyti
2021-11-02 13:58         ` Tvrtko Ursulin
2021-11-02 21:08           ` Andi Shyti
2021-11-02 21:08             ` Andi Shyti
2021-10-29  3:28 ` [PATCH v3 06/10] drm/i915: Initial support for per-tile uncore Matt Roper
2021-10-29  3:28   ` [Intel-gfx] " Matt Roper
2021-10-29  3:28 ` [PATCH v3 07/10] drm/i915/xehp: Determine which tile raised an interrupt Matt Roper
2021-10-29  3:28   ` [Intel-gfx] " Matt Roper
2021-11-01 23:33   ` Andi Shyti
2021-11-01 23:33     ` [Intel-gfx] " Andi Shyti
2021-10-29  3:28 ` Matt Roper [this message]
2021-10-29  3:28   ` [Intel-gfx] [PATCH v3 08/10] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Matt Roper
2021-10-29  3:28 ` [PATCH v3 09/10] drm/i915/guc: Update CT debug macro for multi-tile Matt Roper
2021-10-29  3:28   ` [Intel-gfx] " Matt Roper
2021-11-01 23:35   ` Andi Shyti
2021-11-01 23:35     ` [Intel-gfx] " Andi Shyti
2021-10-29  3:28 ` [PATCH v3 10/10] drm/i915/xehpsdv: Initialize multi-tiles Matt Roper
2021-10-29  3:28   ` [Intel-gfx] " Matt Roper
2021-10-29  3:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support (rev3) Patchwork
2021-10-29  4:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-29 10:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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