From: Tudor Ambarus <tudor.ambarus@microchip.com> To: <michael@walle.cc>, <vigneshr@ti.com>, <p.yadav@ti.com> Cc: macromorgan@hotmail.com, jaimeliao@mxic.com.tw, Tudor Ambarus <tudor.ambarus@microchip.com>, richard@nod.at, esben@geanix.com, linux@rasmusvillemoes.dk, knaerzche@gmail.com, nicolas.ferre@microchip.com, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, code@reto-schneider.ch, miquel.raynal@bootlin.com, heiko.thiery@gmail.com, sr@denx.de, mail@david-bauer.net, zhengxunli@mxic.com.tw Subject: [PATCH v3 14/25] mtd: spi-nor: Introduce flash_info flags masks Date: Fri, 29 Oct 2021 20:26:22 +0300 [thread overview] Message-ID: <20211029172633.886453-15-tudor.ambarus@microchip.com> (raw) In-Reply-To: <20211029172633.886453-1-tudor.ambarus@microchip.com> Clarify for what the flash_info flags are used for. Split them in three categories: 1/ NON_SFDP_FLAGS: flags that indicate support that is not defined by the JESD216 standard in its SFDP tables. 2/ SFDP_FLAGS: flags that indicate support that can be discovered via SFDP. These flags are used when the flash does not define the SFDP tables. Used together with SPI_NOR_SKIP_SFDP flag. 3/ FIXUP_FLAGS: flags that indicate support that can be discovered via SFDP ideally, but can not be discovered for this particular flash because the SFDP table that indicates this support is not defined by the flash. In case the table for this support is defined but has wrong values, one should instead use a post_sfdp() hook to set the SNOR_F equivalent flag. Manufacturer specific flags like USE_CLSR, USE_FSR, SPI_NOR_XSR_RDY, will be removed in a future series. BIT(0) was kept for SPI_NOR_PARSE_SFDP (will be introduced in a further patch). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- drivers/mtd/spi-nor/core.h | 89 ++++++++++++++++++++++++-------------- 1 file changed, 57 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 6fc63ef4267b..1fadd0e74103 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -334,56 +334,81 @@ struct flash_info { u16 addr_width; u32 flags; -#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ -#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ -#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ -#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ -#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ -#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ -#define USE_FSR BIT(7) /* use flag status register */ -#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ -#define SPI_NOR_HAS_TB BIT(9) /* +#define SPI_NOR_SKIP_SFDP BIT(1) /* Skip parsing of SFDP tables */ + +/* + * Flags that indicate support that is not defined by the JESD216 standard in + * its SFDP tables. + */ +#define NON_SFDP_FLAGS_MASK GENMASK(15, 2) +#define NON_SFDP_FLAGS(x) ((x) & NON_SFDP_FLAGS_MASK) +#define SPI_NOR_HAS_LOCK BIT(2) /* Flash supports lock/unlock via SR */ +#define SPI_NOR_HAS_TB BIT(3) /* * Flash SR has Top/Bottom (TB) protect * bit. Must be used with * SPI_NOR_HAS_LOCK. */ -#define SPI_NOR_XSR_RDY BIT(10) /* - * S3AN flashes have specific opcode to - * read the status register. - */ -#define SPI_NOR_4B_OPCODES BIT(11) /* - * Use dedicated 4byte address op codes - * to support memory size above 128Mib. - */ -#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ -#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ -#define USE_CLSR BIT(14) /* use CLSR command */ -#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */ -#define SPI_NOR_TB_SR_BIT6 BIT(16) /* +#define SPI_NOR_TB_SR_BIT6 BIT(4) /* * Top/Bottom (TB) is bit 6 of * status register. Must be used with * SPI_NOR_HAS_TB. */ -#define SPI_NOR_4BIT_BP BIT(17) /* +#define SPI_NOR_4BIT_BP BIT(5) /* * Flash SR has 4 bit fields (BP0-3) * for block protection. */ -#define SPI_NOR_BP3_SR_BIT6 BIT(18) /* +#define SPI_NOR_BP3_SR_BIT6 BIT(6) /* * BP3 is bit 6 of status register. * Must be used with SPI_NOR_4BIT_BP. */ -#define SPI_NOR_OCTAL_DTR_READ BIT(19) /* Flash supports octal DTR Read. */ -#define SPI_NOR_OCTAL_DTR_PP BIT(20) /* Flash supports Octal DTR Page Program */ -#define SPI_NOR_IO_MODE_EN_VOLATILE BIT(21) /* - * Flash enables the best - * available I/O mode via a - * volatile bit. - */ -#define SPI_NOR_SWP_IS_VOLATILE BIT(22) /* +#define SPI_NOR_SWP_IS_VOLATILE BIT(7) /* * Flash has volatile software write * protection bits. Usually these will * power-up in a write-protected state. */ +#define SPI_NOR_NO_ERASE BIT(8) /* No erase command needed */ +#define NO_CHIP_ERASE BIT(9) /* Chip does not support chip erase */ +#define SPI_NOR_NO_FR BIT(10) /* Can't do fastread */ +#define USE_CLSR BIT(11) /* use CLSR command */ +#define USE_FSR BIT(12) /* use flag status register */ +#define SPI_NOR_XSR_RDY BIT(13) /* + * S3AN flashes have specific opcode to + * read the status register. + */ + +/* + * Flags that indicate support that can be discovered via SFDP. Used when SFDP + * tables are not defined in the flash. These flags are used together with the + * SPI_NOR_SKIP_SFDP flag. + */ +#define SFDP_FLAGS_MASK GENMASK(23, 16) +#define SFDP_FLAGS(x) ((x) & SFDP_FLAGS_MASK) +#define SECT_4K BIT(16) /* SPINOR_OP_BE_4K works uniformly */ +#define SECT_4K_PMC BIT(17) /* SPINOR_OP_BE_4K_PMC works uniformly */ +#define SPI_NOR_DUAL_READ BIT(18) /* Flash supports Dual Read */ +#define SPI_NOR_QUAD_READ BIT(19) /* Flash supports Quad Read */ +#define SPI_NOR_OCTAL_READ BIT(20) /* Flash supports Octal Read */ +#define SPI_NOR_OCTAL_DTR_READ BIT(21) /* Flash supports octal DTR Read. */ +#define SPI_NOR_OCTAL_DTR_PP BIT(22) /* Flash supports Octal DTR Page Program */ + +/* + * Flags that indicate support that can be discovered via SFDP ideally, but can + * not be discovered for this particular flash because the SFDP table that + * indicates this support is not defined by the flash. In case the table for + * this support is defined but has wrong values, one should instead use a + * post_sfdp() hook to set the SNOR_F equivalent flag. + */ +#define FIXUP_FLAGS_MASK GENMASK(31, 24) +#define FIXUP_FLAGS(x) ((x) & FIXUP_FLAGS_MASK) +#define SPI_NOR_4B_OPCODES BIT(24) /* + * Use dedicated 4byte address op codes + * to support memory size above 128Mib. + */ +#define SPI_NOR_IO_MODE_EN_VOLATILE BIT(25) /* + * Flash enables the best + * available I/O mode via a + * volatile bit. + */ const struct spi_nor_otp_organization otp_org; -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: Tudor Ambarus <tudor.ambarus@microchip.com> To: <michael@walle.cc>, <vigneshr@ti.com>, <p.yadav@ti.com> Cc: macromorgan@hotmail.com, jaimeliao@mxic.com.tw, Tudor Ambarus <tudor.ambarus@microchip.com>, richard@nod.at, esben@geanix.com, linux@rasmusvillemoes.dk, knaerzche@gmail.com, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, code@reto-schneider.ch, miquel.raynal@bootlin.com, heiko.thiery@gmail.com, sr@denx.de, figgyc@figgyc.uk, mail@david-bauer.net, zhengxunli@mxic.com.tw Subject: [PATCH v3 14/25] mtd: spi-nor: Introduce flash_info flags masks Date: Fri, 29 Oct 2021 20:26:22 +0300 [thread overview] Message-ID: <20211029172633.886453-15-tudor.ambarus@microchip.com> (raw) In-Reply-To: <20211029172633.886453-1-tudor.ambarus@microchip.com> Clarify for what the flash_info flags are used for. Split them in three categories: 1/ NON_SFDP_FLAGS: flags that indicate support that is not defined by the JESD216 standard in its SFDP tables. 2/ SFDP_FLAGS: flags that indicate support that can be discovered via SFDP. These flags are used when the flash does not define the SFDP tables. Used together with SPI_NOR_SKIP_SFDP flag. 3/ FIXUP_FLAGS: flags that indicate support that can be discovered via SFDP ideally, but can not be discovered for this particular flash because the SFDP table that indicates this support is not defined by the flash. In case the table for this support is defined but has wrong values, one should instead use a post_sfdp() hook to set the SNOR_F equivalent flag. Manufacturer specific flags like USE_CLSR, USE_FSR, SPI_NOR_XSR_RDY, will be removed in a future series. BIT(0) was kept for SPI_NOR_PARSE_SFDP (will be introduced in a further patch). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> --- drivers/mtd/spi-nor/core.h | 89 ++++++++++++++++++++++++-------------- 1 file changed, 57 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 6fc63ef4267b..1fadd0e74103 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -334,56 +334,81 @@ struct flash_info { u16 addr_width; u32 flags; -#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ -#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ -#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ -#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ -#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ -#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ -#define USE_FSR BIT(7) /* use flag status register */ -#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ -#define SPI_NOR_HAS_TB BIT(9) /* +#define SPI_NOR_SKIP_SFDP BIT(1) /* Skip parsing of SFDP tables */ + +/* + * Flags that indicate support that is not defined by the JESD216 standard in + * its SFDP tables. + */ +#define NON_SFDP_FLAGS_MASK GENMASK(15, 2) +#define NON_SFDP_FLAGS(x) ((x) & NON_SFDP_FLAGS_MASK) +#define SPI_NOR_HAS_LOCK BIT(2) /* Flash supports lock/unlock via SR */ +#define SPI_NOR_HAS_TB BIT(3) /* * Flash SR has Top/Bottom (TB) protect * bit. Must be used with * SPI_NOR_HAS_LOCK. */ -#define SPI_NOR_XSR_RDY BIT(10) /* - * S3AN flashes have specific opcode to - * read the status register. - */ -#define SPI_NOR_4B_OPCODES BIT(11) /* - * Use dedicated 4byte address op codes - * to support memory size above 128Mib. - */ -#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ -#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ -#define USE_CLSR BIT(14) /* use CLSR command */ -#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */ -#define SPI_NOR_TB_SR_BIT6 BIT(16) /* +#define SPI_NOR_TB_SR_BIT6 BIT(4) /* * Top/Bottom (TB) is bit 6 of * status register. Must be used with * SPI_NOR_HAS_TB. */ -#define SPI_NOR_4BIT_BP BIT(17) /* +#define SPI_NOR_4BIT_BP BIT(5) /* * Flash SR has 4 bit fields (BP0-3) * for block protection. */ -#define SPI_NOR_BP3_SR_BIT6 BIT(18) /* +#define SPI_NOR_BP3_SR_BIT6 BIT(6) /* * BP3 is bit 6 of status register. * Must be used with SPI_NOR_4BIT_BP. */ -#define SPI_NOR_OCTAL_DTR_READ BIT(19) /* Flash supports octal DTR Read. */ -#define SPI_NOR_OCTAL_DTR_PP BIT(20) /* Flash supports Octal DTR Page Program */ -#define SPI_NOR_IO_MODE_EN_VOLATILE BIT(21) /* - * Flash enables the best - * available I/O mode via a - * volatile bit. - */ -#define SPI_NOR_SWP_IS_VOLATILE BIT(22) /* +#define SPI_NOR_SWP_IS_VOLATILE BIT(7) /* * Flash has volatile software write * protection bits. Usually these will * power-up in a write-protected state. */ +#define SPI_NOR_NO_ERASE BIT(8) /* No erase command needed */ +#define NO_CHIP_ERASE BIT(9) /* Chip does not support chip erase */ +#define SPI_NOR_NO_FR BIT(10) /* Can't do fastread */ +#define USE_CLSR BIT(11) /* use CLSR command */ +#define USE_FSR BIT(12) /* use flag status register */ +#define SPI_NOR_XSR_RDY BIT(13) /* + * S3AN flashes have specific opcode to + * read the status register. + */ + +/* + * Flags that indicate support that can be discovered via SFDP. Used when SFDP + * tables are not defined in the flash. These flags are used together with the + * SPI_NOR_SKIP_SFDP flag. + */ +#define SFDP_FLAGS_MASK GENMASK(23, 16) +#define SFDP_FLAGS(x) ((x) & SFDP_FLAGS_MASK) +#define SECT_4K BIT(16) /* SPINOR_OP_BE_4K works uniformly */ +#define SECT_4K_PMC BIT(17) /* SPINOR_OP_BE_4K_PMC works uniformly */ +#define SPI_NOR_DUAL_READ BIT(18) /* Flash supports Dual Read */ +#define SPI_NOR_QUAD_READ BIT(19) /* Flash supports Quad Read */ +#define SPI_NOR_OCTAL_READ BIT(20) /* Flash supports Octal Read */ +#define SPI_NOR_OCTAL_DTR_READ BIT(21) /* Flash supports octal DTR Read. */ +#define SPI_NOR_OCTAL_DTR_PP BIT(22) /* Flash supports Octal DTR Page Program */ + +/* + * Flags that indicate support that can be discovered via SFDP ideally, but can + * not be discovered for this particular flash because the SFDP table that + * indicates this support is not defined by the flash. In case the table for + * this support is defined but has wrong values, one should instead use a + * post_sfdp() hook to set the SNOR_F equivalent flag. + */ +#define FIXUP_FLAGS_MASK GENMASK(31, 24) +#define FIXUP_FLAGS(x) ((x) & FIXUP_FLAGS_MASK) +#define SPI_NOR_4B_OPCODES BIT(24) /* + * Use dedicated 4byte address op codes + * to support memory size above 128Mib. + */ +#define SPI_NOR_IO_MODE_EN_VOLATILE BIT(25) /* + * Flash enables the best + * available I/O mode via a + * volatile bit. + */ const struct spi_nor_otp_organization otp_org; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-29 18:04 UTC|newest] Thread overview: 156+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-29 17:26 [PATCH v3 00/25] mtd: spi-nor: Clean params init Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-10-29 17:26 ` [PATCH v3 01/25] mtd: spi-nor: core: Fix spi_nor_flash_parameter otp description Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 8:18 ` Michael Walle 2021-11-09 8:18 ` Michael Walle 2021-10-29 17:26 ` [PATCH v3 02/25] mtd: spi-nor: core: Use container_of to get the pointer to struct spi_nor Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 8:21 ` Michael Walle 2021-11-09 8:21 ` Michael Walle 2021-11-15 10:59 ` Pratyush Yadav 2021-11-15 10:59 ` Pratyush Yadav 2021-10-29 17:26 ` [PATCH v3 03/25] mtd: spi-nor: Introduce spi_nor_set_mtd_info() Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 8:22 ` Michael Walle 2021-11-09 8:22 ` Michael Walle 2021-11-15 18:52 ` Pratyush Yadav 2021-11-15 18:52 ` Pratyush Yadav 2021-11-16 14:25 ` Tudor.Ambarus 2021-11-16 14:25 ` Tudor.Ambarus 2021-11-16 18:11 ` Pratyush Yadav 2021-11-16 18:11 ` Pratyush Yadav 2021-11-17 14:36 ` Tudor.Ambarus 2021-11-17 14:36 ` Tudor.Ambarus 2021-11-19 18:23 ` Pratyush Yadav 2021-11-19 18:23 ` Pratyush Yadav 2021-11-22 8:38 ` Tudor.Ambarus 2021-11-22 8:38 ` Tudor.Ambarus 2021-10-29 17:26 ` [PATCH v3 04/25] mtd: spi-nor: Get rid of nor->page_size Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 8:24 ` Michael Walle 2021-11-09 8:24 ` Michael Walle 2021-11-09 8:34 ` Tudor.Ambarus 2021-11-09 8:34 ` Tudor.Ambarus 2021-10-29 17:26 ` [PATCH v3 05/25] mtd: spi-nor: core: Introduce the late_init() hook Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 9:31 ` Michael Walle 2021-11-09 9:31 ` Michael Walle 2021-11-15 18:56 ` Pratyush Yadav 2021-11-15 18:56 ` Pratyush Yadav 2021-10-29 17:26 ` [PATCH v3 06/25] mtd: spi-nor: atmel: Use flash late_init() for locking Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 9:31 ` Michael Walle 2021-11-09 9:31 ` Michael Walle 2021-11-15 18:59 ` Pratyush Yadav 2021-11-15 18:59 ` Pratyush Yadav 2021-10-29 17:26 ` [PATCH v3 07/25] mtd: spi-nor: sst: " Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 9:34 ` Michael Walle 2021-11-09 9:34 ` Michael Walle 2021-11-15 19:00 ` Pratyush Yadav 2021-11-15 19:00 ` Pratyush Yadav 2021-10-29 17:26 ` [PATCH v3 08/25] mtd: spi-nor: winbond: Use manufacturer late_init() for OTP ops Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 9:36 ` Michael Walle 2021-11-09 9:36 ` Michael Walle 2021-11-15 19:00 ` Pratyush Yadav 2021-11-15 19:00 ` Pratyush Yadav 2021-10-29 17:26 ` [PATCH v3 09/25] mtd: spi-nor: xilinx: Use manufacturer late_init() to set setup method Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 9:43 ` Michael Walle 2021-11-09 9:43 ` Michael Walle 2021-11-15 19:01 ` Pratyush Yadav 2021-11-15 19:01 ` Pratyush Yadav 2021-10-29 17:26 ` [PATCH v3 10/25] mtd: spi-nor: sst: Use manufacturer late_init() to set _write() Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 9:47 ` Michael Walle 2021-11-09 9:47 ` Michael Walle 2021-11-09 10:22 ` Tudor.Ambarus 2021-11-09 10:22 ` Tudor.Ambarus 2021-11-09 10:23 ` Tudor.Ambarus 2021-11-09 10:23 ` Tudor.Ambarus 2021-11-09 10:24 ` Michael Walle 2021-11-09 10:24 ` Michael Walle 2021-11-15 19:03 ` Pratyush Yadav 2021-11-15 19:03 ` Pratyush Yadav 2021-10-29 17:26 ` [PATCH v3 11/25] mtd: spi-nor: spansion: Use manufacturer late_init() Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 9:48 ` Michael Walle 2021-11-09 9:48 ` Michael Walle 2021-11-15 19:06 ` Pratyush Yadav 2021-11-15 19:06 ` Pratyush Yadav 2021-10-29 17:26 ` [PATCH v3 12/25] mtd: spi-nor: core: Call spi_nor_post_sfdp_fixups() only when SFDP is defined Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 10:18 ` Michael Walle 2021-11-09 10:18 ` Michael Walle 2021-10-29 17:26 ` [PATCH v3 13/25] mtd: spi-nor: sst: Get rid of SST_WRITE flash_info flag Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-09 12:21 ` Michael Walle 2021-11-09 12:21 ` Michael Walle 2021-11-09 12:31 ` Tudor.Ambarus 2021-11-09 12:31 ` Tudor.Ambarus 2021-11-12 21:28 ` Michael Walle 2021-11-12 21:28 ` Michael Walle 2021-10-29 17:26 ` Tudor Ambarus [this message] 2021-10-29 17:26 ` [PATCH v3 14/25] mtd: spi-nor: Introduce flash_info flags masks Tudor Ambarus 2021-11-12 21:50 ` Michael Walle 2021-11-12 21:50 ` Michael Walle 2021-11-15 4:55 ` Tudor.Ambarus 2021-11-15 4:55 ` Tudor.Ambarus 2021-10-29 17:26 ` [PATCH v3 15/25] mtd: spi-nor: Introduce spi_nor_nonsfdp_init_flags() Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-15 19:12 ` Pratyush Yadav 2021-11-15 19:12 ` Pratyush Yadav 2021-10-29 17:26 ` [PATCH v3 16/25] mtd: spi-nor: Introduce spi_nor_init_fixup_flags() Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-16 10:57 ` Pratyush Yadav 2021-11-16 10:57 ` Pratyush Yadav 2021-10-29 17:26 ` [PATCH v3 17/25] mtd: spi-nor: core: Introduce SPI_NOR_PARSE_SFDP Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-10-29 17:26 ` [PATCH v3 18/25] mtd: spi-nor: core: Init flash params based on SFDP first for new flash additions Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-16 11:07 ` Pratyush Yadav 2021-11-16 11:07 ` Pratyush Yadav 2021-10-29 17:26 ` [PATCH v3 19/25] mtd: spi-nor: core: Move spi_nor_set_addr_width() in spi_nor_setup() Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-11-12 21:53 ` Michael Walle 2021-11-12 21:53 ` Michael Walle 2021-10-29 17:26 ` [PATCH v3 20/25] mtd: spi-nor: sst: sst26vf064b: Init flash based on SFDP Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-10-29 17:31 ` Tudor.Ambarus 2021-10-29 17:31 ` Tudor.Ambarus 2021-11-09 12:25 ` Michael Walle 2021-11-09 12:25 ` Michael Walle 2021-11-09 12:33 ` Tudor.Ambarus 2021-11-09 12:33 ` Tudor.Ambarus 2021-11-09 12:37 ` Michael Walle 2021-11-09 12:37 ` Michael Walle 2021-10-29 17:26 ` [PATCH v3 21/25] mtd: spi-nor: winbond: w25q256jvm: " Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-10-29 17:31 ` Tudor.Ambarus 2021-10-29 17:31 ` Tudor.Ambarus 2021-10-29 17:26 ` [PATCH v3 22/25] mtd: spi-nor: spansion: s25fl256s0: Skip SFDP parsing Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-10-29 17:26 ` [PATCH v3 23/25] mtd: spi-nor: gigadevice: gd25q256: Init flash based on SFDP Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-10-29 17:33 ` Tudor.Ambarus 2021-10-29 17:33 ` Tudor.Ambarus 2021-10-29 17:26 ` [PATCH v3 24/25] mtd: spi-nor: issi: is25lp256: " Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-10-29 17:33 ` Tudor.Ambarus 2021-10-29 17:33 ` Tudor.Ambarus 2021-10-29 17:26 ` [PATCH v3 25/25] mtd: spi-nor: macronix: mx25l25635e: " Tudor Ambarus 2021-10-29 17:26 ` Tudor Ambarus 2021-10-29 17:34 ` Tudor.Ambarus 2021-10-29 17:34 ` Tudor.Ambarus 2021-11-08 10:15 ` [PATCH v3 00/25] mtd: spi-nor: Clean params init Tudor.Ambarus 2021-11-08 10:15 ` Tudor.Ambarus 2021-11-08 10:31 ` Michael Walle 2021-11-08 10:31 ` Michael Walle 2021-11-16 11:36 ` Pratyush Yadav 2021-11-16 11:36 ` Pratyush Yadav 2021-11-16 11:56 ` Michael Walle 2021-11-16 11:56 ` Michael Walle 2021-11-17 13:17 ` (subset)[PATCH " Tudor Ambarus 2021-11-17 13:17 ` Tudor Ambarus
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