From: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com> To: Herbert Xu <herbert@gondor.apana.org.au>, "David S . Miller" <davem@davemloft.net>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Marek Vasut <marex@denx.de>, Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>, Ard Biesheuvel <ardb@kernel.org>, <linux-crypto@vger.kernel.org>, <linux-stm32@st-md-mailman.stormreply.com>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v2 3/8] crypto: stm32/cryp - fix CTR counter carry Date: Tue, 2 Nov 2021 17:47:24 +0100 [thread overview] Message-ID: <20211102164729.9957-4-nicolas.toromanoff@foss.st.com> (raw) In-Reply-To: <20211102164729.9957-1-nicolas.toromanoff@foss.st.com> STM32 CRYP hardware doesn't manage CTR counter bigger than max U32, as a workaround, at each block the current IV is saved, if the saved IV lower u32 is 0xFFFFFFFF, the full IV is manually incremented, and set in hardware. Fixes: bbb2832620ac ("crypto: stm32 - Fix sparse warnings") Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com> --- drivers/crypto/stm32/stm32-cryp.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/stm32/stm32-cryp.c b/drivers/crypto/stm32/stm32-cryp.c index 7b55ad6d2f1a..9d6ccf1eb4ce 100644 --- a/drivers/crypto/stm32/stm32-cryp.c +++ b/drivers/crypto/stm32/stm32-cryp.c @@ -163,7 +163,7 @@ struct stm32_cryp { struct scatter_walk in_walk; struct scatter_walk out_walk; - u32 last_ctr[4]; + __be32 last_ctr[4]; u32 gcm_ctr; }; @@ -1218,26 +1218,25 @@ static void stm32_cryp_check_ctr_counter(struct stm32_cryp *cryp) u32 cr; if (unlikely(cryp->last_ctr[3] == 0xFFFFFFFF)) { - cryp->last_ctr[3] = 0; - cryp->last_ctr[2]++; - if (!cryp->last_ctr[2]) { - cryp->last_ctr[1]++; - if (!cryp->last_ctr[1]) - cryp->last_ctr[0]++; - } + /* + * In this case, we need to increment manually the ctr counter, + * as HW doesn't handle the U32 carry. + */ + crypto_inc((u8 *)cryp->last_ctr, sizeof(cryp->last_ctr)); cr = stm32_cryp_read(cryp, CRYP_CR); stm32_cryp_write(cryp, CRYP_CR, cr & ~CR_CRYPEN); - stm32_cryp_hw_write_iv(cryp, (__be32 *)cryp->last_ctr); + stm32_cryp_hw_write_iv(cryp, cryp->last_ctr); stm32_cryp_write(cryp, CRYP_CR, cr); } - cryp->last_ctr[0] = stm32_cryp_read(cryp, CRYP_IV0LR); - cryp->last_ctr[1] = stm32_cryp_read(cryp, CRYP_IV0RR); - cryp->last_ctr[2] = stm32_cryp_read(cryp, CRYP_IV1LR); - cryp->last_ctr[3] = stm32_cryp_read(cryp, CRYP_IV1RR); + /* The IV registers are BE */ + cryp->last_ctr[0] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0LR)); + cryp->last_ctr[1] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0RR)); + cryp->last_ctr[2] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1LR)); + cryp->last_ctr[3] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1RR)); } static bool stm32_cryp_irq_read_data(struct stm32_cryp *cryp) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com> To: Herbert Xu <herbert@gondor.apana.org.au>, "David S . Miller" <davem@davemloft.net>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Marek Vasut <marex@denx.de>, Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>, Ard Biesheuvel <ardb@kernel.org>, <linux-crypto@vger.kernel.org>, <linux-stm32@st-md-mailman.stormreply.com>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v2 3/8] crypto: stm32/cryp - fix CTR counter carry Date: Tue, 2 Nov 2021 17:47:24 +0100 [thread overview] Message-ID: <20211102164729.9957-4-nicolas.toromanoff@foss.st.com> (raw) In-Reply-To: <20211102164729.9957-1-nicolas.toromanoff@foss.st.com> STM32 CRYP hardware doesn't manage CTR counter bigger than max U32, as a workaround, at each block the current IV is saved, if the saved IV lower u32 is 0xFFFFFFFF, the full IV is manually incremented, and set in hardware. Fixes: bbb2832620ac ("crypto: stm32 - Fix sparse warnings") Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com> --- drivers/crypto/stm32/stm32-cryp.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/stm32/stm32-cryp.c b/drivers/crypto/stm32/stm32-cryp.c index 7b55ad6d2f1a..9d6ccf1eb4ce 100644 --- a/drivers/crypto/stm32/stm32-cryp.c +++ b/drivers/crypto/stm32/stm32-cryp.c @@ -163,7 +163,7 @@ struct stm32_cryp { struct scatter_walk in_walk; struct scatter_walk out_walk; - u32 last_ctr[4]; + __be32 last_ctr[4]; u32 gcm_ctr; }; @@ -1218,26 +1218,25 @@ static void stm32_cryp_check_ctr_counter(struct stm32_cryp *cryp) u32 cr; if (unlikely(cryp->last_ctr[3] == 0xFFFFFFFF)) { - cryp->last_ctr[3] = 0; - cryp->last_ctr[2]++; - if (!cryp->last_ctr[2]) { - cryp->last_ctr[1]++; - if (!cryp->last_ctr[1]) - cryp->last_ctr[0]++; - } + /* + * In this case, we need to increment manually the ctr counter, + * as HW doesn't handle the U32 carry. + */ + crypto_inc((u8 *)cryp->last_ctr, sizeof(cryp->last_ctr)); cr = stm32_cryp_read(cryp, CRYP_CR); stm32_cryp_write(cryp, CRYP_CR, cr & ~CR_CRYPEN); - stm32_cryp_hw_write_iv(cryp, (__be32 *)cryp->last_ctr); + stm32_cryp_hw_write_iv(cryp, cryp->last_ctr); stm32_cryp_write(cryp, CRYP_CR, cr); } - cryp->last_ctr[0] = stm32_cryp_read(cryp, CRYP_IV0LR); - cryp->last_ctr[1] = stm32_cryp_read(cryp, CRYP_IV0RR); - cryp->last_ctr[2] = stm32_cryp_read(cryp, CRYP_IV1LR); - cryp->last_ctr[3] = stm32_cryp_read(cryp, CRYP_IV1RR); + /* The IV registers are BE */ + cryp->last_ctr[0] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0LR)); + cryp->last_ctr[1] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0RR)); + cryp->last_ctr[2] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1LR)); + cryp->last_ctr[3] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1RR)); } static bool stm32_cryp_irq_read_data(struct stm32_cryp *cryp) -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-11-02 16:48 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-02 16:47 [PATCH v2 0/8] STM32 CRYP driver: many fixes Nicolas Toromanoff 2021-11-02 16:47 ` Nicolas Toromanoff 2021-11-02 16:47 ` [PATCH v2 1/8] crypto: stm32/cryp - defer probe for reset controller Nicolas Toromanoff 2021-11-02 16:47 ` Nicolas Toromanoff 2021-11-02 16:47 ` [PATCH v2 2/8] crypto: stm32/cryp - don't print error on probe deferral Nicolas Toromanoff 2021-11-02 16:47 ` Nicolas Toromanoff 2021-11-02 16:47 ` Nicolas Toromanoff [this message] 2021-11-02 16:47 ` [PATCH v2 3/8] crypto: stm32/cryp - fix CTR counter carry Nicolas Toromanoff 2021-11-02 16:47 ` [PATCH v2 4/8] crypto: stm32/cryp - fix race condition in crypto_engine requests Nicolas Toromanoff 2021-11-02 16:47 ` Nicolas Toromanoff 2021-11-02 16:47 ` [PATCH v2 5/8] crypto: stm32/cryp - check early input data Nicolas Toromanoff 2021-11-02 16:47 ` Nicolas Toromanoff 2021-11-02 16:47 ` [PATCH v2 6/8] crypto: stm32/cryp - fix double pm exit Nicolas Toromanoff 2021-11-02 16:47 ` Nicolas Toromanoff 2021-11-02 16:47 ` [PATCH v2 7/8] crypto: stm32/cryp - fix bugs and crash in tests Nicolas Toromanoff 2021-11-02 16:47 ` Nicolas Toromanoff 2021-11-16 15:20 ` Nicolas Toromanoff 2021-11-16 15:20 ` Nicolas Toromanoff 2021-11-02 16:47 ` [PATCH v2 8/8] crypto: stm32/cryp - reorder hw initialization Nicolas Toromanoff 2021-11-02 16:47 ` Nicolas Toromanoff
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