[PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI and OSPI nodes

[PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI and OSPI nodes

[Tudor Ambarus]

sama7g5 embedds an OSPI and a QSPI controller:
1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash
   and OctaFlash Protocols Supported.
2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 arch/arm/dts/sama7g5.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi
index b951aff43e..4a3c675d34 100644
--- a/arch/arm/dts/sama7g5.dtsi
+++ b/arch/arm/dts/sama7g5.dtsi
@@ -91,6 +91,32 @@
 				#clock-cells = <1>;
 			};
 
+			qspi0: spi@e080c000 {
+				compatible = "microchip,sama7g5-ospi";
+				reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
+				reg-names = "qspi_base", "qspi_mmap";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>;
+				clock-names = "pclk", "gclk";
+				assigned-clocks = <&pmc PMC_TYPE_GCK 78>;
+				assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			qspi1: spi@e0810000 {
+				compatible = "microchip,sama7g5-qspi";
+				reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
+				reg-names = "qspi_base", "qspi_mmap";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
+				clock-names = "pclk", "gclk";
+				assigned-clocks = <&pmc PMC_TYPE_GCK 78>;
+				assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			sdmmc0: sdio-host@e1204000 {
 				compatible = "microchip,sama7g5-sdhci";
 				reg = <0xe1204000 0x300>;
-- 
2.25.1

[PATCH 2/2] ARM: dts: at91: sama7g5ek: Add QSPI0 node

[Tudor Ambarus]

QSPI0 has a MX66LM1G45G SPI NOR flash connected.
Enable the controller and describe the flash.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 arch/arm/dts/sama7g5ek.dts | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/dts/sama7g5ek.dts b/arch/arm/dts/sama7g5ek.dts
index 1c59a8aaf8..16192ca0b1 100644
--- a/arch/arm/dts/sama7g5ek.dts
+++ b/arch/arm/dts/sama7g5ek.dts
@@ -11,6 +11,7 @@
 #include <dt-bindings/mfd/atmel-flexcom.h>
 #include "sama7g5.dtsi"
 #include "sama7g5-pinfunc.h"
+#include <dt-bindings/pinctrl/at91.h>
 
 / {
 	model = "Microchip SAMA7G5 Evaluation Kit";
@@ -64,6 +65,24 @@
 	};
 };
 
+&qspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <133000000>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+		m25p,fast-read;
+
+	};
+};
+
 &flx1 {
 	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
 	status = "okay";
@@ -126,6 +145,25 @@
 		bias-pull-up;
 	};
 
+	pinctrl_qspi: qspi {
+		pinmux = <PIN_PB12__QSPI0_IO0>,
+			 <PIN_PB11__QSPI0_IO1>,
+			 <PIN_PB10__QSPI0_IO2>,
+			 <PIN_PB9__QSPI0_IO3>,
+			 <PIN_PB16__QSPI0_IO4>,
+			 <PIN_PB17__QSPI0_IO5>,
+			 <PIN_PB18__QSPI0_IO6>,
+			 <PIN_PB19__QSPI0_IO7>,
+			 <PIN_PB13__QSPI0_CS>,
+			 <PIN_PB14__QSPI0_SCK>,
+			 <PIN_PB15__QSPI0_SCKN>,
+			 <PIN_PB20__QSPI0_DQS>,
+			 <PIN_PB21__QSPI0_INT>;
+		bias-disable;
+		slew-rate = <0>;
+		atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>;
+	};
+
 	pinctrl_sdmmc0_cmd_data_default: sdmmc0_cmd_data_default {
 		pinmux = <PIN_PA1__SDMMC0_CMD>,
 			 <PIN_PA3__SDMMC0_DAT0>,
-- 
2.25.1

Re: [PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI and OSPI nodes

[Eugen.Hristev]

On 11/3/21 7:07 PM, Tudor Ambarus wrote:
> sama7g5 embedds an OSPI and a QSPI controller:
> 1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash
>     and OctaFlash Protocols Supported.
> 2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR.
> 
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---

Applied both to u-boot-at91/next , thanks !