[RFC PATCH 1/3] drm/amdgpu: add HIQ ring to amdgpu

[RFC PATCH 1/3] drm/amdgpu: add HIQ ring to amdgpu

[Nirmoy Das]

Add HIQ ring structs and functions that will map HIQ
using KIQ.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c      | 142 +++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h      |  24 ++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h     |   3 +-
 4 files changed, 169 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index 89e6ad30396f..2d9295adac06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -40,6 +40,7 @@ struct amdgpu_doorbell {
  */
 struct amdgpu_doorbell_index {
 	uint32_t kiq;
+	uint32_t hiq;
 	uint32_t mec_ring0;
 	uint32_t mec_ring1;
 	uint32_t mec_ring2;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 1916ec84dd71..5b8cb76e35a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -256,6 +256,148 @@ void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 		bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 }
 
+int amdgpu_gfx_hiq_acquire(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+{
+	int queue_bit;
+	int mec, pipe, queue;
+
+	queue_bit = adev->gfx.mec.num_mec
+		    * adev->gfx.mec.num_pipe_per_mec
+		    * adev->gfx.mec.num_queue_per_pipe;
+
+	while (queue_bit-- >= 0) {
+		if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
+			continue;
+
+		amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
+
+		if (mec == 1 && pipe > 1)
+			continue;
+
+		ring->me = mec + 1;
+		ring->pipe = pipe;
+		ring->queue = queue;
+
+		return 0;
+	}
+
+	dev_err(adev->dev, "Failed to find a queue for HIQ\n");
+	return -EINVAL;
+}
+
+int amdgpu_gfx_hiq_init_ring(struct amdgpu_device *adev,
+			     struct amdgpu_ring *ring,
+			     struct amdgpu_irq_src *irq)
+{
+	struct amdgpu_hiq *hiq = &adev->gfx.hiq;
+	int r = 0;
+
+	ring->adev = NULL;
+	ring->ring_obj = NULL;
+	ring->use_doorbell = true;
+	ring->doorbell_index = adev->doorbell_index.hiq;
+
+	r = amdgpu_gfx_hiq_acquire(adev, ring);
+	if (r)
+		return r;
+
+	ring->eop_gpu_addr = hiq->eop_gpu_addr;
+	ring->no_scheduler = true;
+	sprintf(ring->name, "hiq_%d.%d.%d", ring->me, ring->pipe, ring->queue);
+	r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
+			     AMDGPU_RING_PRIO_DEFAULT, NULL);
+	if (r)
+		dev_warn(adev->dev, "(%d) failed to init hiq ring\n", r);
+
+	return r;
+}
+
+void amdgpu_gfx_hiq_free_ring(struct amdgpu_ring *ring)
+{
+	amdgpu_ring_fini(ring);
+}
+
+void amdgpu_gfx_hiq_init_ring_fini(struct amdgpu_device *adev)
+{
+	struct amdgpu_hiq *hiq = &adev->gfx.hiq;
+
+	amdgpu_bo_free_kernel(&hiq->eop_obj, &hiq->eop_gpu_addr, NULL);
+}
+
+int amdgpu_gfx_hiq_init(struct amdgpu_device *adev,
+			unsigned hpd_size)
+{
+	int r;
+	u32 *hpd;
+	struct amdgpu_hiq *hiq = &adev->gfx.hiq;
+
+	r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
+				    AMDGPU_GEM_DOMAIN_GTT, &hiq->eop_obj,
+				    &hiq->eop_gpu_addr, (void **)&hpd);
+	if (r) {
+		dev_warn(adev->dev, "failed to create HIQ bo (%d).\n", r);
+		return r;
+	}
+
+	memset(hpd, 0, hpd_size);
+
+	r = amdgpu_bo_reserve(hiq->eop_obj, true);
+	if (unlikely(r != 0))
+		dev_warn(adev->dev, "(%d) reserve hiq eop bo failed\n", r);
+	amdgpu_bo_kunmap(hiq->eop_obj);
+	amdgpu_bo_unreserve(hiq->eop_obj);
+
+	return 0;
+}
+
+int amdgpu_gfx_disable_hiq(struct amdgpu_device *adev)
+{
+	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+	struct amdgpu_ring *kiq_ring = &kiq->ring;
+	int r;
+
+	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
+		return -EINVAL;
+
+	spin_lock(&adev->gfx.kiq.ring_lock);
+	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
+		spin_unlock(&adev->gfx.kiq.ring_lock);
+		return -ENOMEM;
+	}
+
+	kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.kiq.ring, RESET_QUEUES,
+				   0, 0);
+	r = amdgpu_ring_test_helper(kiq_ring);
+	spin_unlock(&adev->gfx.kiq.ring_lock);
+
+	return r;
+}
+
+int amdgpu_gfx_enable_hiq(struct amdgpu_device *adev)
+{
+	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
+	struct amdgpu_ring *hiq_ring = &adev->gfx.hiq.ring;
+	int r;
+
+	spin_lock(&adev->gfx.kiq.ring_lock);
+	r = amdgpu_ring_alloc(kiq_ring, 7);
+	if (r) {
+		pr_err("Failed to alloc KIQ (%d).\n", r);
+		return r;
+	}
+
+	kiq->pmf->kiq_map_queues(kiq_ring, hiq_ring);
+	amdgpu_ring_commit(kiq_ring);
+	r = amdgpu_ring_test_helper(kiq_ring);
+	spin_unlock(&adev->gfx.kiq.ring_lock);
+	if (r)
+		DRM_ERROR("HIQ enable failed\n");
+
+	return r;
+
+ }
+
 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 				  struct amdgpu_ring *ring)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index f851196c83a5..4d9c91f4400d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -111,6 +111,20 @@ struct amdgpu_kiq {
 	const struct kiq_pm4_funcs *pmf;
 };
 
+/*
+ * Because of a HW bug HIQ need to be mapped so that CP can handle
+ * TMZ buffers. amdgpu is not going to use HIQ in any way other than
+ * mapping it using KIQ. KFD will map HIQ as well, so when KFD is enabled
+ * then amdgpu don't need to map HIQ.
+ */
+
+struct amdgpu_hiq {
+	u64			eop_gpu_addr;
+	struct amdgpu_bo	*eop_obj;
+	struct amdgpu_ring	ring;
+	struct amdgpu_irq_src	irq;
+};
+
 /*
  * GPU scratch registers structures, functions & helpers
  */
@@ -275,6 +289,7 @@ struct amdgpu_gfx {
 	struct amdgpu_me		me;
 	struct amdgpu_mec		mec;
 	struct amdgpu_kiq		kiq;
+	struct amdgpu_hiq		hiq;
 	struct amdgpu_scratch		scratch;
 	const struct firmware		*me_fw;	/* ME firmware */
 	uint32_t			me_fw_version;
@@ -411,4 +426,13 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
 void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);
+
+int amdgpu_gfx_hiq_init_ring(struct amdgpu_device *adev,
+			     struct amdgpu_ring *ring,
+			     struct amdgpu_irq_src *irq);
+void amdgpu_gfx_hiq_free_ring(struct amdgpu_ring *ring);
+void amdgpu_gfx_hiq_fini(struct amdgpu_device *adev);
+int amdgpu_gfx_hiq_init(struct amdgpu_device *adev, unsigned int hpd_size);
+int amdgpu_gfx_enable_hiq(struct amdgpu_device *adev);
+int amdgpu_gfx_disable_hiq(struct amdgpu_device *adev);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 4d380e79752c..438ed4ab86b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -71,7 +71,8 @@ enum amdgpu_ring_type {
 	AMDGPU_RING_TYPE_VCN_ENC	= AMDGPU_HW_IP_VCN_ENC,
 	AMDGPU_RING_TYPE_VCN_JPEG	= AMDGPU_HW_IP_VCN_JPEG,
 	AMDGPU_RING_TYPE_KIQ,
-	AMDGPU_RING_TYPE_MES
+	AMDGPU_RING_TYPE_MES,
+	AMDGPU_RING_TYPE_HIQ
 };
 
 enum amdgpu_ib_pool_type {
-- 
2.31.1

[RFC PATCH 2/3] drm/amdgpu: add HIQ eng_sel to KIQ packets

[Nirmoy Das]

Allow KIQ to map/unmap HIQ MQD as well.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 14 ++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  |  4 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  4 ++--
 4 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 5b8cb76e35a0..053a1119ebfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -1010,3 +1010,17 @@ void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_sta
 			(adev)->powerplay.pp_handle, state));
 	mutex_unlock(&adev->pm.mutex);
 }
+
+int amdgpu_kiq_get_eng_num(struct amdgpu_ring *ring)
+{
+
+	switch (ring->funcs->type) {
+	case AMDGPU_RING_TYPE_GFX:
+		return 4;
+	case AMDGPU_RING_TYPE_HIQ:
+		return 1;
+	default:
+		return 0;
+	}
+
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 4d9c91f4400d..88d942b1ef08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -373,6 +373,8 @@ static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
 	return (u32)((1ULL << bit_width) - 1);
 }
 
+int amdgpu_kiq_get_eng_num(struct amdgpu_ring *ring);
+
 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 90a834dc4008..538130c453a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3633,7 +3633,7 @@ static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 				   enum amdgpu_unmap_queues_action action,
 				   u64 gpu_addr, u64 seq)
 {
-	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
+	uint32_t eng_sel = amdgpu_kiq_get_eng_num(ring);
 
 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
@@ -3660,7 +3660,7 @@ static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
 				   u64 addr,
 				   u64 seq)
 {
-	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
+	uint32_t eng_sel = amdgpu_kiq_get_eng_num(ring);
 
 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 	amdgpu_ring_write(kiq_ring,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7f944bb11298..2b29e42bde62 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -847,7 +847,7 @@ static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 	struct amdgpu_device *adev = kiq_ring->adev;
 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 	uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
+	uint32_t eng_sel = amdgpu_kiq_get_eng_num(ring);
 
 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
@@ -877,7 +877,7 @@ static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 				   enum amdgpu_unmap_queues_action action,
 				   u64 gpu_addr, u64 seq)
 {
-	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
+	uint32_t eng_sel = amdgpu_kiq_get_eng_num(ring);
 
 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
-- 
2.31.1

[RFC PATCH 3/3] drm/amdgpu: enable HIQ in amdgpu without kfd

[Nirmoy Das]

There is a HW bug which prevents CP to read secure buffers
with HIQ being configured and mapped using KIQ. KFD already
does this for amdgpu but when kfd is not enabled amdgpu
should that for itself.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 14 ++++-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 77 ++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 80 +++++++++++++++++++++++++
 3 files changed, 170 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 053a1119ebfe..837f76550242 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -519,7 +519,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 					    AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
 					    &ring->mqd_gpu_addr, &ring->mqd_ptr);
 		if (r) {
-			dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
+			dev_warn(adev->dev, "failed to create KIQ ring mqd ob (%d)", r);
 			return r;
 		}
 
@@ -569,6 +569,18 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 		}
 	}
 
+	/* create MQD for HIQ */
+	ring = &adev->gfx.hiq.ring;
+	if (!ring->mqd_obj) {
+		r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
+					    AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
+					    &ring->mqd_gpu_addr, &ring->mqd_ptr);
+		if (r) {
+			dev_warn(adev->dev, "failed to create HIQ ring mqd ob (%d)", r);
+			return r;
+		}
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 538130c453a6..9532f013128f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4794,6 +4794,7 @@ static int gfx_v10_0_sw_init(void *handle)
 {
 	int i, j, k, r, ring_id = 0;
 	struct amdgpu_kiq *kiq;
+	struct amdgpu_hiq *hiq;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	switch (adev->ip_versions[GC_HWIP][0]) {
@@ -4923,6 +4924,18 @@ static int gfx_v10_0_sw_init(void *handle)
 	if (r)
 		return r;
 
+	if (!adev->kfd.dev) {
+		r = amdgpu_gfx_hiq_init(adev, GFX10_MEC_HPD_SIZE);
+		if (r) {
+			DRM_ERROR("Failed to init HIQ BOs!\n");
+			return r;
+		}
+
+		hiq = &adev->gfx.hiq;
+		r = amdgpu_gfx_hiq_init_ring(adev, &hiq->ring, &hiq->irq);
+		if (r)
+			return r;
+	}
 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
 	if (r)
 		return r;
@@ -7215,6 +7228,54 @@ static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
 	return r;
 }
 
+static int gfx_v10_0_hiq_init_queue(struct amdgpu_ring *ring)
+{
+	struct amdgpu_device *adev = ring->adev;
+	struct v10_compute_mqd *mqd = ring->mqd_ptr;
+
+
+	if (amdgpu_in_reset(adev)) {
+		/* reset ring buffer */
+		ring->wptr = 0;
+		amdgpu_ring_clear_ring(ring);
+
+	} else {
+		memset((void *)mqd, 0, sizeof(*mqd));
+		mutex_lock(&adev->srbm_mutex);
+		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+		gfx_v10_0_compute_mqd_init(ring);
+		nv_grbm_select(adev, 0, 0, 0, 0);
+		mutex_unlock(&adev->srbm_mutex);
+	}
+
+	return 0;
+}
+
+static int gfx_v10_0_hiq_resume(struct amdgpu_device *adev)
+{
+	struct amdgpu_ring *ring;
+	int r;
+
+	ring = &adev->gfx.hiq.ring;
+
+	r = amdgpu_bo_reserve(ring->mqd_obj, false);
+	if (unlikely(r != 0))
+		return r;
+
+	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
+	if (unlikely(r != 0))
+		return r;
+
+	gfx_v10_0_hiq_init_queue(ring);
+	amdgpu_bo_kunmap(ring->mqd_obj);
+	ring->mqd_ptr = NULL;
+	amdgpu_bo_unreserve(ring->mqd_obj);
+	ring->sched.ready = true;
+
+	amdgpu_gfx_enable_hiq(adev);
+	return 0;
+}
+
 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
 {
 	int r, i;
@@ -7252,6 +7313,12 @@ static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
 			return r;
 	}
 
+	if (!adev->kfd.dev) {
+		r = gfx_v10_0_hiq_resume(adev);
+		if (r)
+			return r;
+	}
+
 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 		ring = &adev->gfx.gfx_ring[i];
 		r = amdgpu_ring_test_helper(ring);
@@ -7557,6 +7624,11 @@ static int gfx_v10_0_hw_fini(void *handle)
 #endif
 		if (amdgpu_gfx_disable_kcq(adev))
 			DRM_ERROR("KCQ disable failed\n");
+
+		if (!adev->kfd.dev) {
+			if (amdgpu_gfx_disable_hiq(adev))
+				DRM_ERROR("HIQ disable failed\n");
+		}
 	}
 
 	if (amdgpu_sriov_vf(adev)) {
@@ -9470,11 +9542,16 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
 };
 
+static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_hiq = {
+	.type = AMDGPU_RING_TYPE_HIQ,
+};
+
 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
 {
 	int i;
 
 	adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
+	adev->gfx.hiq.ring.funcs = &gfx_v10_0_ring_funcs_hiq;
 
 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 		adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2b29e42bde62..9653ea8743d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2309,6 +2309,7 @@ static int gfx_v9_0_sw_init(void *handle)
 	int i, j, k, r, ring_id;
 	struct amdgpu_ring *ring;
 	struct amdgpu_kiq *kiq;
+	struct amdgpu_hiq *hiq;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	switch (adev->ip_versions[GC_HWIP][0]) {
@@ -2428,6 +2429,19 @@ static int gfx_v9_0_sw_init(void *handle)
 	if (r)
 		return r;
 
+	if (!adev->kfd.dev) {
+		r = amdgpu_gfx_hiq_init(adev, GFX9_MEC_HPD_SIZE);
+		if (r) {
+			DRM_ERROR("Failed to init HIQ BOs!\n");
+			return r;
+		}
+
+		hiq = &adev->gfx.hiq;
+		r = amdgpu_gfx_hiq_init_ring(adev, &hiq->ring, &hiq->irq);
+		if (r)
+			return r;
+	}
+
 	/* create MQD for all compute queues as wel as KIQ for SRIOV case */
 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
 	if (r)
@@ -3911,6 +3925,56 @@ static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
 	return r;
 }
 
+static int gfx_v9_0_hiq_init_queue(struct amdgpu_ring *ring)
+{
+	struct amdgpu_device *adev = ring->adev;
+	struct v9_mqd *mqd = ring->mqd_ptr;
+
+
+	if (amdgpu_in_reset(adev)) {
+		/* reset ring buffer */
+		ring->wptr = 0;
+		amdgpu_ring_clear_ring(ring);
+
+	} else {
+		memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
+		((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
+		((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
+		mutex_lock(&adev->srbm_mutex);
+		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+		gfx_v9_0_mqd_init(ring);
+		soc15_grbm_select(adev, 0, 0, 0, 0);
+		mutex_unlock(&adev->srbm_mutex);
+	}
+
+	return 0;
+}
+
+static int gfx_v9_0_hiq_resume(struct amdgpu_device *adev)
+{
+	struct amdgpu_ring *ring;
+	int r;
+
+	ring = &adev->gfx.hiq.ring;
+
+	r = amdgpu_bo_reserve(ring->mqd_obj, false);
+	if (unlikely(r != 0))
+		return r;
+
+	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
+	if (unlikely(r != 0))
+		return r;
+
+	gfx_v9_0_hiq_init_queue(ring);
+	amdgpu_bo_kunmap(ring->mqd_obj);
+	ring->mqd_ptr = NULL;
+	amdgpu_bo_unreserve(ring->mqd_obj);
+	ring->sched.ready = true;
+
+	amdgpu_gfx_enable_hiq(adev);
+	return 0;
+}
+
 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
 {
 	int r, i;
@@ -3946,6 +4010,12 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
 	if (r)
 		return r;
 
+	if (!adev->kfd.dev) {
+		r = gfx_v9_0_hiq_resume(adev);
+		if (r)
+			return r;
+	}
+
 	if (adev->gfx.num_gfx_rings) {
 		ring = &adev->gfx.gfx_ring[0];
 		r = amdgpu_ring_test_helper(ring);
@@ -4027,6 +4097,11 @@ static int gfx_v9_0_hw_fini(void *handle)
 		/* disable KCQ to avoid CPC touch memory not valid anymore */
 		amdgpu_gfx_disable_kcq(adev);
 
+	if (!adev->kfd.dev) {
+		if (amdgpu_gfx_disable_hiq(adev))
+			DRM_ERROR("HIQ disable failed");
+	}
+
 	if (amdgpu_sriov_vf(adev)) {
 		gfx_v9_0_cp_gfx_enable(adev, false);
 		/* must disable polling for SRIOV when hw finished, otherwise
@@ -6986,11 +7061,16 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
 	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
 };
 
+static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_hiq = {
+	.type = AMDGPU_RING_TYPE_HIQ,
+};
+
 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
 {
 	int i;
 
 	adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
+	adev->gfx.hiq.ring.funcs = &gfx_v9_0_ring_funcs_hiq;
 
 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 		adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
-- 
2.31.1

Re: [RFC PATCH 3/3] drm/amdgpu: enable HIQ in amdgpu without kfd

[Alex Deucher]

On Fri, Nov 5, 2021 at 10:09 AM Nirmoy Das <nirmoy.das@amd.com> wrote:
>
> There is a HW bug which prevents CP to read secure buffers
> with HIQ being configured and mapped using KIQ. KFD already
> does this for amdgpu but when kfd is not enabled amdgpu
> should that for itself.

Can we just move the HIQ init/fini into the KGD and then have KFD call
into the KGD when it needs to interact with it?  I'd rather not have
two code paths to maintain to handle the HIQ ring.

Alex

>
> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 14 ++++-
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 77 ++++++++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 80 +++++++++++++++++++++++++
>  3 files changed, 170 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 053a1119ebfe..837f76550242 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -519,7 +519,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
>                                             AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
>                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
>                 if (r) {
> -                       dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
> +                       dev_warn(adev->dev, "failed to create KIQ ring mqd ob (%d)", r);
>                         return r;
>                 }
>
> @@ -569,6 +569,18 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
>                 }
>         }
>
> +       /* create MQD for HIQ */
> +       ring = &adev->gfx.hiq.ring;
> +       if (!ring->mqd_obj) {
> +               r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
> +                                           AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
> +                                           &ring->mqd_gpu_addr, &ring->mqd_ptr);
> +               if (r) {
> +                       dev_warn(adev->dev, "failed to create HIQ ring mqd ob (%d)", r);
> +                       return r;
> +               }
> +       }
> +
>         return 0;
>  }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 538130c453a6..9532f013128f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4794,6 +4794,7 @@ static int gfx_v10_0_sw_init(void *handle)
>  {
>         int i, j, k, r, ring_id = 0;
>         struct amdgpu_kiq *kiq;
> +       struct amdgpu_hiq *hiq;
>         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
>         switch (adev->ip_versions[GC_HWIP][0]) {
> @@ -4923,6 +4924,18 @@ static int gfx_v10_0_sw_init(void *handle)
>         if (r)
>                 return r;
>
> +       if (!adev->kfd.dev) {
> +               r = amdgpu_gfx_hiq_init(adev, GFX10_MEC_HPD_SIZE);
> +               if (r) {
> +                       DRM_ERROR("Failed to init HIQ BOs!\n");
> +                       return r;
> +               }
> +
> +               hiq = &adev->gfx.hiq;
> +               r = amdgpu_gfx_hiq_init_ring(adev, &hiq->ring, &hiq->irq);
> +               if (r)
> +                       return r;
> +       }
>         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
>         if (r)
>                 return r;
> @@ -7215,6 +7228,54 @@ static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
>         return r;
>  }
>
> +static int gfx_v10_0_hiq_init_queue(struct amdgpu_ring *ring)
> +{
> +       struct amdgpu_device *adev = ring->adev;
> +       struct v10_compute_mqd *mqd = ring->mqd_ptr;
> +
> +
> +       if (amdgpu_in_reset(adev)) {
> +               /* reset ring buffer */
> +               ring->wptr = 0;
> +               amdgpu_ring_clear_ring(ring);
> +
> +       } else {
> +               memset((void *)mqd, 0, sizeof(*mqd));
> +               mutex_lock(&adev->srbm_mutex);
> +               nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
> +               gfx_v10_0_compute_mqd_init(ring);
> +               nv_grbm_select(adev, 0, 0, 0, 0);
> +               mutex_unlock(&adev->srbm_mutex);
> +       }
> +
> +       return 0;
> +}
> +
> +static int gfx_v10_0_hiq_resume(struct amdgpu_device *adev)
> +{
> +       struct amdgpu_ring *ring;
> +       int r;
> +
> +       ring = &adev->gfx.hiq.ring;
> +
> +       r = amdgpu_bo_reserve(ring->mqd_obj, false);
> +       if (unlikely(r != 0))
> +               return r;
> +
> +       r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
> +       if (unlikely(r != 0))
> +               return r;
> +
> +       gfx_v10_0_hiq_init_queue(ring);
> +       amdgpu_bo_kunmap(ring->mqd_obj);
> +       ring->mqd_ptr = NULL;
> +       amdgpu_bo_unreserve(ring->mqd_obj);
> +       ring->sched.ready = true;
> +
> +       amdgpu_gfx_enable_hiq(adev);
> +       return 0;
> +}
> +
>  static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
>  {
>         int r, i;
> @@ -7252,6 +7313,12 @@ static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
>                         return r;
>         }
>
> +       if (!adev->kfd.dev) {
> +               r = gfx_v10_0_hiq_resume(adev);
> +               if (r)
> +                       return r;
> +       }
> +
>         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
>                 ring = &adev->gfx.gfx_ring[i];
>                 r = amdgpu_ring_test_helper(ring);
> @@ -7557,6 +7624,11 @@ static int gfx_v10_0_hw_fini(void *handle)
>  #endif
>                 if (amdgpu_gfx_disable_kcq(adev))
>                         DRM_ERROR("KCQ disable failed\n");
> +
> +               if (!adev->kfd.dev) {
> +                       if (amdgpu_gfx_disable_hiq(adev))
> +                               DRM_ERROR("HIQ disable failed\n");
> +               }
>         }
>
>         if (amdgpu_sriov_vf(adev)) {
> @@ -9470,11 +9542,16 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
>         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
>  };
>
> +static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_hiq = {
> +       .type = AMDGPU_RING_TYPE_HIQ,
> +};
> +
>  static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
>  {
>         int i;
>
>         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
> +       adev->gfx.hiq.ring.funcs = &gfx_v10_0_ring_funcs_hiq;
>
>         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
>                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 2b29e42bde62..9653ea8743d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2309,6 +2309,7 @@ static int gfx_v9_0_sw_init(void *handle)
>         int i, j, k, r, ring_id;
>         struct amdgpu_ring *ring;
>         struct amdgpu_kiq *kiq;
> +       struct amdgpu_hiq *hiq;
>         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
>         switch (adev->ip_versions[GC_HWIP][0]) {
> @@ -2428,6 +2429,19 @@ static int gfx_v9_0_sw_init(void *handle)
>         if (r)
>                 return r;
>
> +       if (!adev->kfd.dev) {
> +               r = amdgpu_gfx_hiq_init(adev, GFX9_MEC_HPD_SIZE);
> +               if (r) {
> +                       DRM_ERROR("Failed to init HIQ BOs!\n");
> +                       return r;
> +               }
> +
> +               hiq = &adev->gfx.hiq;
> +               r = amdgpu_gfx_hiq_init_ring(adev, &hiq->ring, &hiq->irq);
> +               if (r)
> +                       return r;
> +       }
> +
>         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
>         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
>         if (r)
> @@ -3911,6 +3925,56 @@ static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
>         return r;
>  }
>
> +static int gfx_v9_0_hiq_init_queue(struct amdgpu_ring *ring)
> +{
> +       struct amdgpu_device *adev = ring->adev;
> +       struct v9_mqd *mqd = ring->mqd_ptr;
> +
> +
> +       if (amdgpu_in_reset(adev)) {
> +               /* reset ring buffer */
> +               ring->wptr = 0;
> +               amdgpu_ring_clear_ring(ring);
> +
> +       } else {
> +               memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
> +               ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
> +               ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
> +               mutex_lock(&adev->srbm_mutex);
> +               soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
> +               gfx_v9_0_mqd_init(ring);
> +               soc15_grbm_select(adev, 0, 0, 0, 0);
> +               mutex_unlock(&adev->srbm_mutex);
> +       }
> +
> +       return 0;
> +}
> +
> +static int gfx_v9_0_hiq_resume(struct amdgpu_device *adev)
> +{
> +       struct amdgpu_ring *ring;
> +       int r;
> +
> +       ring = &adev->gfx.hiq.ring;
> +
> +       r = amdgpu_bo_reserve(ring->mqd_obj, false);
> +       if (unlikely(r != 0))
> +               return r;
> +
> +       r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
> +       if (unlikely(r != 0))
> +               return r;
> +
> +       gfx_v9_0_hiq_init_queue(ring);
> +       amdgpu_bo_kunmap(ring->mqd_obj);
> +       ring->mqd_ptr = NULL;
> +       amdgpu_bo_unreserve(ring->mqd_obj);
> +       ring->sched.ready = true;
> +
> +       amdgpu_gfx_enable_hiq(adev);
> +       return 0;
> +}
> +
>  static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
>  {
>         int r, i;
> @@ -3946,6 +4010,12 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
>         if (r)
>                 return r;
>
> +       if (!adev->kfd.dev) {
> +               r = gfx_v9_0_hiq_resume(adev);
> +               if (r)
> +                       return r;
> +       }
> +
>         if (adev->gfx.num_gfx_rings) {
>                 ring = &adev->gfx.gfx_ring[0];
>                 r = amdgpu_ring_test_helper(ring);
> @@ -4027,6 +4097,11 @@ static int gfx_v9_0_hw_fini(void *handle)
>                 /* disable KCQ to avoid CPC touch memory not valid anymore */
>                 amdgpu_gfx_disable_kcq(adev);
>
> +       if (!adev->kfd.dev) {
> +               if (amdgpu_gfx_disable_hiq(adev))
> +                       DRM_ERROR("HIQ disable failed");
> +       }
> +
>         if (amdgpu_sriov_vf(adev)) {
>                 gfx_v9_0_cp_gfx_enable(adev, false);
>                 /* must disable polling for SRIOV when hw finished, otherwise
> @@ -6986,11 +7061,16 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
>         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
>  };
>
> +static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_hiq = {
> +       .type = AMDGPU_RING_TYPE_HIQ,
> +};
> +
>  static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
>  {
>         int i;
>
>         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
> +       adev->gfx.hiq.ring.funcs = &gfx_v9_0_ring_funcs_hiq;
>
>         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
>                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
> --
> 2.31.1
>

Re: [RFC PATCH 3/3] drm/amdgpu: enable HIQ in amdgpu without kfd

[Das, Nirmoy]

On 11/5/2021 3:17 PM, Alex Deucher wrote:
> On Fri, Nov 5, 2021 at 10:09 AM Nirmoy Das <nirmoy.das@amd.com> wrote:
>> There is a HW bug which prevents CP to read secure buffers
>> with HIQ being configured and mapped using KIQ. KFD already
>> does this for amdgpu but when kfd is not enabled amdgpu
>> should that for itself.
> Can we just move the HIQ init/fini into the KGD and then have KFD call
> into the KGD when it needs to interact with it?  I'd rather not have
> two code paths to maintain to handle the HIQ ring.


I looked into the kfd code a bit, AFAIU kfd deals with struct 
v{9|10}_mqd instead of amdgpu_ring.

I could try to expose a function in KGD to map HIQ with a mqd struct 
which kfd can use.


Regards,

Nirmoy


>
> Alex
>
>> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 14 ++++-
>>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 77 ++++++++++++++++++++++++
>>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 80 +++++++++++++++++++++++++
>>   3 files changed, 170 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> index 053a1119ebfe..837f76550242 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> @@ -519,7 +519,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
>>                                              AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
>>                                              &ring->mqd_gpu_addr, &ring->mqd_ptr);
>>                  if (r) {
>> -                       dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
>> +                       dev_warn(adev->dev, "failed to create KIQ ring mqd ob (%d)", r);
>>                          return r;
>>                  }
>>
>> @@ -569,6 +569,18 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
>>                  }
>>          }
>>
>> +       /* create MQD for HIQ */
>> +       ring = &adev->gfx.hiq.ring;
>> +       if (!ring->mqd_obj) {
>> +               r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
>> +                                           AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
>> +                                           &ring->mqd_gpu_addr, &ring->mqd_ptr);
>> +               if (r) {
>> +                       dev_warn(adev->dev, "failed to create HIQ ring mqd ob (%d)", r);
>> +                       return r;
>> +               }
>> +       }
>> +
>>          return 0;
>>   }
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index 538130c453a6..9532f013128f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -4794,6 +4794,7 @@ static int gfx_v10_0_sw_init(void *handle)
>>   {
>>          int i, j, k, r, ring_id = 0;
>>          struct amdgpu_kiq *kiq;
>> +       struct amdgpu_hiq *hiq;
>>          struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>>          switch (adev->ip_versions[GC_HWIP][0]) {
>> @@ -4923,6 +4924,18 @@ static int gfx_v10_0_sw_init(void *handle)
>>          if (r)
>>                  return r;
>>
>> +       if (!adev->kfd.dev) {
>> +               r = amdgpu_gfx_hiq_init(adev, GFX10_MEC_HPD_SIZE);
>> +               if (r) {
>> +                       DRM_ERROR("Failed to init HIQ BOs!\n");
>> +                       return r;
>> +               }
>> +
>> +               hiq = &adev->gfx.hiq;
>> +               r = amdgpu_gfx_hiq_init_ring(adev, &hiq->ring, &hiq->irq);
>> +               if (r)
>> +                       return r;
>> +       }
>>          r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
>>          if (r)
>>                  return r;
>> @@ -7215,6 +7228,54 @@ static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
>>          return r;
>>   }
>>
>> +static int gfx_v10_0_hiq_init_queue(struct amdgpu_ring *ring)
>> +{
>> +       struct amdgpu_device *adev = ring->adev;
>> +       struct v10_compute_mqd *mqd = ring->mqd_ptr;
>> +
>> +
>> +       if (amdgpu_in_reset(adev)) {
>> +               /* reset ring buffer */
>> +               ring->wptr = 0;
>> +               amdgpu_ring_clear_ring(ring);
>> +
>> +       } else {
>> +               memset((void *)mqd, 0, sizeof(*mqd));
>> +               mutex_lock(&adev->srbm_mutex);
>> +               nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
>> +               gfx_v10_0_compute_mqd_init(ring);
>> +               nv_grbm_select(adev, 0, 0, 0, 0);
>> +               mutex_unlock(&adev->srbm_mutex);
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +static int gfx_v10_0_hiq_resume(struct amdgpu_device *adev)
>> +{
>> +       struct amdgpu_ring *ring;
>> +       int r;
>> +
>> +       ring = &adev->gfx.hiq.ring;
>> +
>> +       r = amdgpu_bo_reserve(ring->mqd_obj, false);
>> +       if (unlikely(r != 0))
>> +               return r;
>> +
>> +       r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
>> +       if (unlikely(r != 0))
>> +               return r;
>> +
>> +       gfx_v10_0_hiq_init_queue(ring);
>> +       amdgpu_bo_kunmap(ring->mqd_obj);
>> +       ring->mqd_ptr = NULL;
>> +       amdgpu_bo_unreserve(ring->mqd_obj);
>> +       ring->sched.ready = true;
>> +
>> +       amdgpu_gfx_enable_hiq(adev);
>> +       return 0;
>> +}
>> +
>>   static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
>>   {
>>          int r, i;
>> @@ -7252,6 +7313,12 @@ static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
>>                          return r;
>>          }
>>
>> +       if (!adev->kfd.dev) {
>> +               r = gfx_v10_0_hiq_resume(adev);
>> +               if (r)
>> +                       return r;
>> +       }
>> +
>>          for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
>>                  ring = &adev->gfx.gfx_ring[i];
>>                  r = amdgpu_ring_test_helper(ring);
>> @@ -7557,6 +7624,11 @@ static int gfx_v10_0_hw_fini(void *handle)
>>   #endif
>>                  if (amdgpu_gfx_disable_kcq(adev))
>>                          DRM_ERROR("KCQ disable failed\n");
>> +
>> +               if (!adev->kfd.dev) {
>> +                       if (amdgpu_gfx_disable_hiq(adev))
>> +                               DRM_ERROR("HIQ disable failed\n");
>> +               }
>>          }
>>
>>          if (amdgpu_sriov_vf(adev)) {
>> @@ -9470,11 +9542,16 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
>>          .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
>>   };
>>
>> +static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_hiq = {
>> +       .type = AMDGPU_RING_TYPE_HIQ,
>> +};
>> +
>>   static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
>>   {
>>          int i;
>>
>>          adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
>> +       adev->gfx.hiq.ring.funcs = &gfx_v10_0_ring_funcs_hiq;
>>
>>          for (i = 0; i < adev->gfx.num_gfx_rings; i++)
>>                  adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 2b29e42bde62..9653ea8743d3 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -2309,6 +2309,7 @@ static int gfx_v9_0_sw_init(void *handle)
>>          int i, j, k, r, ring_id;
>>          struct amdgpu_ring *ring;
>>          struct amdgpu_kiq *kiq;
>> +       struct amdgpu_hiq *hiq;
>>          struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>>          switch (adev->ip_versions[GC_HWIP][0]) {
>> @@ -2428,6 +2429,19 @@ static int gfx_v9_0_sw_init(void *handle)
>>          if (r)
>>                  return r;
>>
>> +       if (!adev->kfd.dev) {
>> +               r = amdgpu_gfx_hiq_init(adev, GFX9_MEC_HPD_SIZE);
>> +               if (r) {
>> +                       DRM_ERROR("Failed to init HIQ BOs!\n");
>> +                       return r;
>> +               }
>> +
>> +               hiq = &adev->gfx.hiq;
>> +               r = amdgpu_gfx_hiq_init_ring(adev, &hiq->ring, &hiq->irq);
>> +               if (r)
>> +                       return r;
>> +       }
>> +
>>          /* create MQD for all compute queues as wel as KIQ for SRIOV case */
>>          r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
>>          if (r)
>> @@ -3911,6 +3925,56 @@ static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
>>          return r;
>>   }
>>
>> +static int gfx_v9_0_hiq_init_queue(struct amdgpu_ring *ring)
>> +{
>> +       struct amdgpu_device *adev = ring->adev;
>> +       struct v9_mqd *mqd = ring->mqd_ptr;
>> +
>> +
>> +       if (amdgpu_in_reset(adev)) {
>> +               /* reset ring buffer */
>> +               ring->wptr = 0;
>> +               amdgpu_ring_clear_ring(ring);
>> +
>> +       } else {
>> +               memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
>> +               ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
>> +               ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
>> +               mutex_lock(&adev->srbm_mutex);
>> +               soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
>> +               gfx_v9_0_mqd_init(ring);
>> +               soc15_grbm_select(adev, 0, 0, 0, 0);
>> +               mutex_unlock(&adev->srbm_mutex);
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +static int gfx_v9_0_hiq_resume(struct amdgpu_device *adev)
>> +{
>> +       struct amdgpu_ring *ring;
>> +       int r;
>> +
>> +       ring = &adev->gfx.hiq.ring;
>> +
>> +       r = amdgpu_bo_reserve(ring->mqd_obj, false);
>> +       if (unlikely(r != 0))
>> +               return r;
>> +
>> +       r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
>> +       if (unlikely(r != 0))
>> +               return r;
>> +
>> +       gfx_v9_0_hiq_init_queue(ring);
>> +       amdgpu_bo_kunmap(ring->mqd_obj);
>> +       ring->mqd_ptr = NULL;
>> +       amdgpu_bo_unreserve(ring->mqd_obj);
>> +       ring->sched.ready = true;
>> +
>> +       amdgpu_gfx_enable_hiq(adev);
>> +       return 0;
>> +}
>> +
>>   static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
>>   {
>>          int r, i;
>> @@ -3946,6 +4010,12 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
>>          if (r)
>>                  return r;
>>
>> +       if (!adev->kfd.dev) {
>> +               r = gfx_v9_0_hiq_resume(adev);
>> +               if (r)
>> +                       return r;
>> +       }
>> +
>>          if (adev->gfx.num_gfx_rings) {
>>                  ring = &adev->gfx.gfx_ring[0];
>>                  r = amdgpu_ring_test_helper(ring);
>> @@ -4027,6 +4097,11 @@ static int gfx_v9_0_hw_fini(void *handle)
>>                  /* disable KCQ to avoid CPC touch memory not valid anymore */
>>                  amdgpu_gfx_disable_kcq(adev);
>>
>> +       if (!adev->kfd.dev) {
>> +               if (amdgpu_gfx_disable_hiq(adev))
>> +                       DRM_ERROR("HIQ disable failed");
>> +       }
>> +
>>          if (amdgpu_sriov_vf(adev)) {
>>                  gfx_v9_0_cp_gfx_enable(adev, false);
>>                  /* must disable polling for SRIOV when hw finished, otherwise
>> @@ -6986,11 +7061,16 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
>>          .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
>>   };
>>
>> +static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_hiq = {
>> +       .type = AMDGPU_RING_TYPE_HIQ,
>> +};
>> +
>>   static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
>>   {
>>          int i;
>>
>>          adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
>> +       adev->gfx.hiq.ring.funcs = &gfx_v9_0_ring_funcs_hiq;
>>
>>          for (i = 0; i < adev->gfx.num_gfx_rings; i++)
>>                  adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
>> --
>> 2.31.1
>>