* [igt-dev] [PATCH i-g-t 0/2] Add testing for CCS
@ 2021-11-08 5:51 apoorva1.singh
2021-11-08 5:51 ` [igt-dev] [PATCH i-g-t 1/2] lib/i915: Introduce libraries i915_blt and intel_mocs apoorva1.singh
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: apoorva1.singh @ 2021-11-08 5:51 UTC (permalink / raw)
To: apoorva1.singh, igt-dev, zbigniew.kempczynski, arjun.melkaveri
From: Apoorva Singh <apoorva1.singh@intel.com>
- Add new libraries i915_blt and intel_mocs for various blt
commands and mocs settings.
- Add gem_ccs test for CCS testing.
Commands are constructed with XY_BLOCK_COPY_BLT
and XY_CTRL_SURF_COPY_BLT instructions.
Apoorva Singh (1):
lib/i915: Introduce libraries i915_blt and intel_mocs
CQ Tang (1):
i915/gem_ccs: Add testing for CCS
lib/i915/gem_engine_topology.c | 38 ++
lib/i915/gem_engine_topology.h | 5 +
lib/i915/i915_blt.c | 419 +++++++++++++++++++++
lib/i915/i915_blt.h | 93 +++++
lib/i915/intel_mocs.c | 75 ++++
lib/i915/intel_mocs.h | 43 +++
lib/meson.build | 2 +
tests/i915/gem_ccs.c | 639 +++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
9 files changed, 1315 insertions(+)
create mode 100644 lib/i915/i915_blt.c
create mode 100644 lib/i915/i915_blt.h
create mode 100644 lib/i915/intel_mocs.c
create mode 100644 lib/i915/intel_mocs.h
create mode 100644 tests/i915/gem_ccs.c
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] lib/i915: Introduce libraries i915_blt and intel_mocs
2021-11-08 5:51 [igt-dev] [PATCH i-g-t 0/2] Add testing for CCS apoorva1.singh
@ 2021-11-08 5:51 ` apoorva1.singh
2021-11-08 5:51 ` [igt-dev] [PATCH i-g-t 2/2] i915/gem_ccs: Add testing for CCS apoorva1.singh
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: apoorva1.singh @ 2021-11-08 5:51 UTC (permalink / raw)
To: apoorva1.singh, igt-dev, zbigniew.kempczynski, arjun.melkaveri
From: Apoorva Singh <apoorva1.singh@intel.com>
Add new libraries i915_blt and intel_mocs for various blt
commands and mocs settings.
Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
---
lib/i915/i915_blt.c | 419 ++++++++++++++++++++++++++++++++++++++++++
lib/i915/i915_blt.h | 93 ++++++++++
lib/i915/intel_mocs.c | 75 ++++++++
lib/i915/intel_mocs.h | 43 +++++
lib/meson.build | 2 +
5 files changed, 632 insertions(+)
create mode 100644 lib/i915/i915_blt.c
create mode 100644 lib/i915/i915_blt.h
create mode 100644 lib/i915/intel_mocs.c
create mode 100644 lib/i915/intel_mocs.h
diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
new file mode 100644
index 00000000..a3771f40
--- /dev/null
+++ b/lib/i915/i915_blt.c
@@ -0,0 +1,419 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
+ *
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+#include "i915_blt.h"
+#include "i915/intel_mocs.h"
+
+/*
+ * make_block_copy_batch:
+ * @fd: open i915 drm file descriptor
+ * @batch_buf: the batch buffer to populate with the command
+ * @src: fd of the source BO
+ * @dst: fd of the destination BO
+ * @length: size of the src and dest BOs
+ * @reloc: pointer to the relocation entyr for this command
+ * @src_mem_type: source memory type (denotes direct or indirect
+ * addressing)
+ * @dst_mem_type: destination memory type (denotes direct or indirect
+ * addressing)
+ * @src_compression: flag to enable uncompressed read of compressed data
+ * at the source
+ * @dst_compression: flag to enable compressed write at the destination
+ * @resolve: flag to enable resolve of compressed data
+ */
+static int make_block_copy_batch(int fd, uint32_t *batch_buf,
+ uint32_t src, uint32_t dst, uint32_t length,
+ struct drm_i915_gem_relocation_entry *reloc,
+ int src_mem_type, int dst_mem_type,
+ int src_compression, int dst_compression,
+ int resolve)
+{
+ uint32_t *b = batch_buf;
+ uint8_t src_mocs = intel_get_uc_mocs(fd);
+ uint8_t dst_mocs = src_mocs;
+
+ /* BG 0 */
+ b[0] = BLOCK_COPY_BLT_CMD | resolve;
+
+ /* BG 1
+ *
+ * Using Tile 4 dimensions. Height = 32 rows
+ * Width = 128 bytes
+ */
+ b[1] = dst_compression | TILE_4_FORMAT | TILE_4_WIDTH_DWORD |
+ dst_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
+
+ /* BG 3
+ *
+ * X2 = TILE_4_WIDTH
+ * Y2 = (length / TILE_4_WIDTH) << 16:
+ */
+ b[3] = TILE_4_WIDTH | (length >> 7) << DEST_Y2_COORDINATE_SHIFT;
+
+ /* relocate address in b[4] and b[5] */
+ reloc->offset = 4 * (sizeof(uint32_t));
+ reloc->delta = 0;
+ reloc->target_handle = dst;
+ reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc->write_domain = I915_GEM_DOMAIN_RENDER;
+ reloc->presumed_offset = 0;
+ reloc++;
+
+ /* BG 6 */
+ b[6] = dst_mem_type << DEST_MEM_TYPE_SHIFT;
+
+ /* BG 8 */
+ b[8] = src_compression | TILE_4_WIDTH_DWORD | TILE_4_FORMAT |
+ src_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
+
+ /* relocate address in b[9] and b[10] */
+ reloc->offset = 9 * sizeof(uint32_t);
+ reloc->delta = 0;
+ reloc->target_handle = src;
+ reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc->write_domain = 0;
+ reloc->presumed_offset = 0;
+ reloc++;
+
+ /* BG 11 */
+ b[11] = src_mem_type << SRC_MEM_TYPE_SHIFT;
+
+ /* BG 16 */
+ b[16] = SURFACE_TYPE_2D |
+ ((TILE_4_WIDTH - 1) << DEST_SURF_WIDTH_SHIFT) |
+ (TILE_4_HEIGHT - 1);
+
+ /* BG 19 */
+ b[19] = SURFACE_TYPE_2D |
+ ((TILE_4_WIDTH - 1) << SRC_SURF_WIDTH_SHIFT) |
+ (TILE_4_HEIGHT - 1);
+
+ b += XY_BLOCK_COPY_BLT_LEN_DWORD;
+
+ b[0] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
+ reloc->offset = 23 * sizeof(uint32_t);
+ reloc->delta = 0;
+ reloc->target_handle = dst_compression > 0 ? dst : src;
+ reloc->read_domains = 0;
+ reloc->write_domain = 0;
+ reloc->presumed_offset = 0;
+ reloc++;
+ b[3] = 0;
+
+ b[4] = MI_FLUSH_DW | MI_FLUSH_CCS;
+ reloc->offset = 27 * sizeof(uint32_t);
+ reloc->delta = 0;
+ reloc->target_handle = dst_compression > 0 ? dst : src;
+ reloc->read_domains = 0;
+ reloc->write_domain = 0;
+ reloc->presumed_offset = 0;
+ reloc++;
+ b[7] = 0;
+
+ b[8] = MI_BATCH_BUFFER_END;
+ b[9] = 0;
+
+ b += 10;
+
+ return (b - batch_buf) * sizeof(uint32_t);
+}
+
+static int __xy_block_copy_blt(int fd, uint32_t cmd,
+ uint32_t *batch_buf,
+ uint32_t src, uint32_t dst,
+ uint32_t length, int mode, uint32_t ctx,
+ struct intel_execution_engine2 *e)
+{
+ struct drm_i915_gem_relocation_entry reloc[4];
+ struct drm_i915_gem_exec_object2 exec[3];
+ struct drm_i915_gem_execbuffer2 execbuf;
+ int len;
+ int src_mem_type, dst_mem_type;
+ int dst_compression, src_compression;
+ int resolve;
+ uint64_t ahnd = get_reloc_ahnd(fd, 0);
+
+ if (mode == 2) { /* in-place decompress */
+ src_mem_type = MEM_TYPE_LOCAL;
+ dst_mem_type = MEM_TYPE_LOCAL;
+ src_compression = COMPRESSION_ENABLE | AUX_CCS_E;
+ dst_compression = COMPRESSION_ENABLE | AUX_CCS_E;
+ resolve = FULL_RESOLVE;
+ } else if (mode == 1) { /* copy from smem to lmem */
+ src_mem_type = MEM_TYPE_SYS;
+ dst_mem_type = MEM_TYPE_LOCAL;
+ src_compression = 0;
+ dst_compression = COMPRESSION_ENABLE | AUX_CCS_E;
+ resolve = 0;
+ } else { /* copy from lmem to smem */
+ src_mem_type = MEM_TYPE_LOCAL;
+ dst_mem_type = MEM_TYPE_SYS;
+ src_compression = COMPRESSION_ENABLE | AUX_CCS_E;
+ dst_compression = 0;
+ resolve = 0;
+ }
+
+ /* construct the batch buffer */
+ memset(reloc, 0, sizeof(reloc));
+ memset(batch_buf, 0, BATCH_SIZE);
+ len = make_block_copy_batch(fd, batch_buf,
+ src, dst, length, reloc,
+ src_mem_type, dst_mem_type,
+ src_compression, dst_compression,
+ resolve);
+ igt_assert(len > 0);
+
+ /* write batch buffer to 'cmd' BO */
+ gem_write(fd, cmd, 0, batch_buf, len);
+
+ /* Execute the batch buffer */
+ memset(exec, 0, sizeof(exec));
+ if (mode == 2) {
+ exec[0].handle = dst;
+ exec[1].handle = cmd;
+ exec[1].relocation_count = !ahnd ? 4 : 0;
+ exec[1].relocs_ptr = to_user_pointer(reloc);
+ if (ahnd) {
+ exec[0].offset = get_offset(ahnd, exec[0].handle, length * CCS_RATIO, 0);
+ exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+ exec[1].offset = get_offset(ahnd, exec[1].handle, BATCH_SIZE, 0);
+ exec[1].flags |= EXEC_OBJECT_PINNED;
+ }
+ } else {
+ exec[0].handle = src;
+ exec[1].handle = dst;
+ exec[2].handle = cmd;
+ exec[2].relocation_count = !ahnd ? 4 : 0;
+ exec[2].relocs_ptr = to_user_pointer(reloc);
+ if (ahnd) {
+ exec[0].offset = get_offset(ahnd, exec[0].handle, length * CCS_RATIO, 0);
+ exec[0].flags |= EXEC_OBJECT_PINNED;
+ exec[1].offset = get_offset(ahnd, exec[1].handle, length * CCS_RATIO, 0);
+ exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+ exec[2].offset = get_offset(ahnd, exec[2].handle, BATCH_SIZE, 0);
+ exec[2].flags |= EXEC_OBJECT_PINNED;
+ }
+ }
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(exec);
+ if (mode == 2)
+ execbuf.buffer_count = 2;
+ else
+ execbuf.buffer_count = 3;
+ execbuf.batch_len = len;
+
+ if (ctx)
+ execbuf.rsvd1 = ctx;
+
+ execbuf.flags = I915_EXEC_BLT;
+ if (e)
+ execbuf.flags = e->flags;
+
+ gem_execbuf(fd, &execbuf);
+ gem_sync(fd, cmd);
+
+ return 0;
+}
+
+int xy_block_copy_blt(int fd, uint32_t cmd,
+ uint32_t *batch_buf,
+ uint32_t src, uint32_t dst,
+ uint32_t length, int mode,
+ struct intel_execution_engine2 *e)
+{
+ return __xy_block_copy_blt(fd, cmd, batch_buf, src,
+ dst, length, mode, 0, e);
+}
+
+int xy_block_copy_blt_ctx(int fd, uint32_t cmd,
+ uint32_t *batch_buf,
+ uint32_t src, uint32_t dst,
+ uint32_t length, int mode, uint32_t ctx)
+{
+ return __xy_block_copy_blt(fd, cmd, batch_buf, src,
+ dst, length, mode, ctx, 0);
+}
+
+/*
+ * make_ctrl_surf_batch:
+ * @fd: open i915 drm file descriptor
+ * @batch_buf: the batch buffer to populate with the command
+ * @src: fd of the source BO
+ * @dst: fd of the destination BO
+ * @length: size of the ctrl surf in bytes
+ * @reloc: pointer to the relocation entyr for this command
+ * @src_mem_access: source memory type (denotes direct or indirect
+ * addressing)
+ * @dst_mem_acdcess: destination memory type (denotes direct or indirect
+ * addressing)
+ */
+static int make_ctrl_surf_batch(int fd, uint32_t *batch_buf,
+ uint32_t src, uint32_t dst, uint32_t length,
+ struct drm_i915_gem_relocation_entry *reloc,
+ int src_mem_access, int dst_mem_access)
+{
+ int num_ccs_blocks;
+ uint32_t *b = batch_buf;
+ uint8_t src_mocs = intel_get_uc_mocs(fd);
+ uint8_t dst_mocs = src_mocs;
+
+ num_ccs_blocks = length / CCS_RATIO;
+ if (num_ccs_blocks < 1)
+ num_ccs_blocks = 1;
+ if (num_ccs_blocks > NUM_CCS_BLKS_PER_XFER)
+ return 0;
+
+ /*
+ * We use logical AND with 1023 since the size field
+ * takes values which is in the range of 0 - 1023
+ */
+ b[0] = ((XY_CTRL_SURF_COPY_BLT) |
+ (src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
+ (dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
+ (((num_ccs_blocks - 1) & 1023) << CCS_SIZE_SHIFT));
+
+ b[2] = src_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
+
+ /* relocate address in b[1] and b[2] */
+ reloc->offset = 1 * sizeof(uint32_t);
+ reloc->delta = 0;
+ reloc->target_handle = src;
+ reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc->write_domain = 0;
+ reloc->presumed_offset = 0;
+ reloc++;
+
+ b[4] = dst_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
+
+ /* relocate address in b[3] and b[4] */
+ reloc->offset = 3 * (sizeof(uint32_t));
+ reloc->delta = 0;
+ reloc->target_handle = dst;
+ reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc->write_domain = I915_GEM_DOMAIN_RENDER;
+ reloc->presumed_offset = 0;
+ reloc++;
+
+ b[5] = 0;
+
+ b[6] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
+ reloc->offset = 7 * sizeof(uint32_t);
+ reloc->delta = 0;
+ reloc->target_handle =
+ dst_mem_access == INDIRECT_ACCESS ? dst : src;
+ reloc->read_domains = 0;
+ reloc->write_domain = 0;
+ reloc->presumed_offset = 0;
+ reloc++;
+ b[9] = 0;
+
+ b[10] = MI_FLUSH_DW | MI_FLUSH_CCS;
+ reloc->offset = 11 * sizeof(uint32_t);
+ reloc->delta = 0;
+ reloc->target_handle =
+ dst_mem_access == INDIRECT_ACCESS ? dst : src;
+ reloc->read_domains = 0;
+ reloc->write_domain = 0;
+ reloc->presumed_offset = 0;
+ reloc++;
+ b[13] = 0;
+
+ b[14] = MI_BATCH_BUFFER_END;
+ b[15] = 0;
+
+ b += 16;
+
+ return (b - batch_buf) * sizeof(uint32_t);
+}
+
+int xy_ctrl_surf_copy_blt(int fd, uint32_t cmd,
+ uint32_t *batch_buf,
+ uint32_t src, uint32_t dst,
+ uint32_t length, bool writetodev,
+ struct intel_execution_engine2 *e)
+{
+ struct drm_i915_gem_relocation_entry reloc[4];
+ struct drm_i915_gem_exec_object2 exec[3];
+ struct drm_i915_gem_execbuffer2 execbuf;
+ int len, src_mem_access, dst_mem_access;
+ uint64_t ahnd = get_reloc_ahnd(fd, 0);
+
+ if (writetodev) {
+ src_mem_access = DIRECT_ACCESS;
+ dst_mem_access = INDIRECT_ACCESS;
+ } else {
+ src_mem_access = INDIRECT_ACCESS;
+ dst_mem_access = DIRECT_ACCESS;
+ }
+
+ /* construct batch command buffer */
+ memset(reloc, 0, sizeof(reloc));
+ memset(batch_buf, 0, BATCH_SIZE);
+ len = make_ctrl_surf_batch(fd, batch_buf,
+ src, dst, length, reloc,
+ src_mem_access, dst_mem_access);
+ igt_assert(len > 0);
+
+ /* Copy the batch buff to BO cmd */
+ gem_write(fd, cmd, 0, batch_buf, len);
+
+ /* Execute the batch buffer */
+ memset(exec, 0, sizeof(exec));
+ exec[0].handle = src;
+ exec[1].handle = dst;
+ exec[2].handle = cmd;
+ exec[2].relocation_count = !ahnd ? 4 : 0;
+ exec[2].relocs_ptr = to_user_pointer(reloc);
+ if (ahnd) {
+ exec[0].offset = get_offset(ahnd, exec[0].handle, length * CCS_RATIO, 0);
+ exec[0].flags |= EXEC_OBJECT_PINNED;
+ exec[1].offset = get_offset(ahnd, exec[1].handle, length * CCS_RATIO, 0);
+ exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+ exec[2].offset = get_offset(ahnd, exec[2].handle, BATCH_SIZE, 0);
+ exec[2].flags |= EXEC_OBJECT_PINNED;
+ }
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(exec);
+ execbuf.buffer_count = 3;
+ execbuf.batch_len = len;
+ execbuf.flags = I915_EXEC_BLT;
+ if (e)
+ execbuf.flags = e->flags;
+
+ gem_execbuf(fd, &execbuf);
+ gem_sync(fd, cmd);
+
+ return 0;
+}
diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
new file mode 100644
index 00000000..f091c46a
--- /dev/null
+++ b/lib/i915/i915_blt.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
+ *
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+
+#define MI_FLUSH_DW_LEN_DWORD 4
+#define MI_FLUSH_DW (0x26 << 23 | 1)
+#define MI_FLUSH_CCS (1 << 16)
+#define MI_FLUSH_LLC (1 << 9)
+#define MI_INVALIDATE_TLB (1 << 18)
+
+/* XY_BLOCK_COPY_BLT instruction has 22 bit groups 1 DWORD each */
+#define XY_BLOCK_COPY_BLT_LEN_DWORD 22
+#define BLOCK_COPY_BLT_CMD (2 << 29 | 0x41 << 22 | 0x14)
+#define COMPRESSION_ENABLE (1 << 29)
+#define AUX_CCS_E (5 << 18)
+#define FULL_RESOLVE (1 << 12)
+#define PARTIAL_RESOLVE (2 << 12)
+#define TILE_4_FORMAT (2 << 30)
+#define TILE_4_WIDTH (128)
+#define TILE_4_WIDTH_DWORD ((128 >> 2) - 1)
+#define TILE_4_HEIGHT (32)
+#define SURFACE_TYPE_2D (1 << 29)
+
+#define DEST_Y2_COORDINATE_SHIFT (16)
+#define DEST_MEM_TYPE_SHIFT (31)
+#define SRC_MEM_TYPE_SHIFT (31)
+#define DEST_SURF_WIDTH_SHIFT (14)
+#define SRC_SURF_WIDTH_SHIFT (14)
+
+#define XY_CTRL_SURF_COPY_BLT (2 << 29 | 0x48 << 22 | 3)
+#define SRC_ACCESS_TYPE_SHIFT 21
+#define DST_ACCESS_TYPE_SHIFT 20
+#define CCS_SIZE_SHIFT 8
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+#define MI_ARB_CHECK MI_INSTR(0x05, 0)
+#define NUM_CCS_BLKS_PER_XFER 1024
+#define INDIRECT_ACCESS 0
+#define DIRECT_ACCESS 1
+
+#define BATCH_SIZE 4096
+#define BOSIZE_MIN (4 * 1024)
+#define BOSIZE_MAX (4 * 1024 * 1024)
+#define CCS_RATIO 256
+
+#define MEM_TYPE_SYS 1
+#define MEM_TYPE_LOCAL 0
+
+int xy_block_copy_blt(int fd, uint32_t cmd,
+ uint32_t *batch_buf,
+ uint32_t src, uint32_t dst,
+ uint32_t length, int mode,
+ struct intel_execution_engine2 *e);
+
+int xy_ctrl_surf_copy_blt(int fd, uint32_t cmd,
+ uint32_t *batch_buf,
+ uint32_t src, uint32_t dst,
+ uint32_t length, bool writetodev,
+ struct intel_execution_engine2 *e);
+
+int xy_block_copy_blt_ctx(int fd, uint32_t cmd,
+ uint32_t *batch_buf,
+ uint32_t src, uint32_t dst,
+ uint32_t length, int mode, uint32_t ctx);
diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
new file mode 100644
index 00000000..cbb1cc69
--- /dev/null
+++ b/lib/i915/intel_mocs.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright © 2021 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Apoorva Singh <apoorva1.singh@intel.com>
+ *
+ */
+#include "igt.h"
+#include "i915/gem.h"
+#include "intel_mocs.h"
+
+static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
+{
+ uint16_t devid = intel_get_drm_devid(fd);
+
+ /*
+ * Gen >= 12 onwards don't have a setting for PTE,
+ * so using I915_MOCS_PTE as mocs index may leads to
+ * some undefined MOCS behavior.
+ * Correct MOCS index should be referred from BSPCES
+ * and programmed accordingly.
+ * This helper function is providing current UC as well
+ * as WB MOCS index based on platform.
+
+ */
+ if (IS_DG1(devid)) {
+ mocs->uc_index = 1;
+ mocs->wb_index = 5;
+ } else if (IS_GEN12(devid)) {
+ mocs->uc_index = 3;
+ mocs->wb_index = 2;
+ } else {
+ mocs->uc_index = I915_MOCS_PTE;
+ mocs->wb_index = I915_MOCS_CACHED;
+ }
+}
+
+/* BitField [6:1] represents index to MOCS Tables
+ * BitField [0] represents Encryption/Decryption
+ */
+
+uint8_t intel_get_wb_mocs(int fd)
+{
+ struct drm_i915_mocs_index mocs;
+
+ get_mocs_index(fd, &mocs);
+ return mocs.wb_index << 1;
+}
+
+uint8_t intel_get_uc_mocs(int fd)
+{
+ struct drm_i915_mocs_index mocs;
+
+ get_mocs_index(fd, &mocs);
+ return mocs.uc_index << 1;
+}
diff --git a/lib/i915/intel_mocs.h b/lib/i915/intel_mocs.h
new file mode 100644
index 00000000..8289ab1f
--- /dev/null
+++ b/lib/i915/intel_mocs.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright © 2021 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Apoorva Singh <apoorva1.singh@intel.com>
+ *
+ */
+#ifndef _INTEL_MOCS_H
+#define _INTEL_MOCS_H
+
+#define XY_FAST_COLOR_BLT_MOCS_SHIFT 21
+#define XY_BLOCK_COPY_BLT_MOCS_SHIFT 21
+#define XY_FAST_COPY_BLT_MOCS_SHIFT 17
+#define XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT 25
+#define MEM_COPY_MOCS_SHIFT 25
+
+struct drm_i915_mocs_index {
+ uint8_t uc_index;
+ uint8_t wb_index;
+};
+
+uint8_t intel_get_wb_mocs(int fd);
+uint8_t intel_get_uc_mocs(int fd);
+#endif /* _INTEL_MOCS_H */
diff --git a/lib/meson.build b/lib/meson.build
index 297b0ad2..525d62f9 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -11,6 +11,8 @@ lib_sources = [
'i915/gem_mman.c',
'i915/gem_vm.c',
'i915/intel_memory_region.c',
+ 'i915/intel_mocs.c',
+ 'i915/i915_blt.c',
'igt_collection.c',
'igt_color_encoding.c',
'igt_debugfs.c',
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] i915/gem_ccs: Add testing for CCS
2021-11-08 5:51 [igt-dev] [PATCH i-g-t 0/2] Add testing for CCS apoorva1.singh
2021-11-08 5:51 ` [igt-dev] [PATCH i-g-t 1/2] lib/i915: Introduce libraries i915_blt and intel_mocs apoorva1.singh
@ 2021-11-08 5:51 ` apoorva1.singh
2021-11-08 8:52 ` Zbigniew Kempczyński
2021-11-08 6:42 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2021-11-08 8:00 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 1 reply; 6+ messages in thread
From: apoorva1.singh @ 2021-11-08 5:51 UTC (permalink / raw)
To: apoorva1.singh, igt-dev, zbigniew.kempczynski, arjun.melkaveri
From: CQ Tang <cq.tang@intel.com>
Add gem_ccs test for CCS testing.
Commands are constructed with XY_BLOCK_COPY_BLT
and XY_CTRL_SURF_COPY_BLT instructions.
Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
---
lib/i915/gem_engine_topology.c | 38 ++
lib/i915/gem_engine_topology.h | 5 +
tests/i915/gem_ccs.c | 639 +++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
4 files changed, 683 insertions(+)
create mode 100644 tests/i915/gem_ccs.c
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 729f42b0..37b5875e 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -488,6 +488,44 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
return ret;
}
+static bool
+__gem_engine_has_capability(int i915, const char *engine,
+ const char *attr, const char *cap)
+{
+ char buf[4096] = {};
+ FILE *file;
+
+ file = __open_attr(igt_sysfs_open(i915), "r",
+ "engine", engine, attr, NULL);
+ if (file) {
+ fread(buf, 1, sizeof(buf) - 1, file);
+ fclose(file);
+ }
+
+ return strstr(buf, cap);
+}
+
+bool gem_engine_has_capability(int i915, const char *engine, const char *cap)
+{
+ return __gem_engine_has_capability(i915, engine, "capabilities", cap);
+}
+
+bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap)
+{
+ return __gem_engine_has_capability(i915, engine, "known_capabilities", cap);
+}
+
+bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine)
+{
+ if (engine->class != I915_ENGINE_CLASS_COPY)
+ return false;
+
+ if (!gem_engine_has_known_capability(i915, engine->name, "block_copy"))
+ return intel_gen(intel_get_drm_devid(i915)) >= 12;
+
+ return gem_engine_has_capability(i915, engine->name, "block_copy");
+}
+
uint32_t gem_engine_mmio_base(int i915, const char *engine)
{
unsigned int mmio = 0;
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index 4cfab560..d24bc9e8 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -124,6 +124,11 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
uint32_t gem_engine_mmio_base(int i915, const char *engine);
+bool gem_engine_has_capability(int i915, const char *engine, const char *cap);
+bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap);
+
+bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine);
+
void dyn_sysfs_engines(int i915, int engines, const char *file,
void (*test)(int i915, int engine));
diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
new file mode 100644
index 00000000..d144a6d0
--- /dev/null
+++ b/tests/i915/gem_ccs.c
@@ -0,0 +1,639 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * CQ Tang <cq.tang@intel.com>
+ * Neel Desai <neel.desai@intel.com>
+ *
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+#include "i915/gem.h"
+#include "i915/gem_create.h"
+#include "lib/intel_chipset.h"
+#include "i915/i915_blt.h"
+
+IGT_TEST_DESCRIPTION("Exercise the memory bandwidth compression and "
+ "decompression when copying data between "
+ "system and local memory");
+
+static void igt_wr_xy_ctrl_surf_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
+ uint32_t src, uint32_t dst, uint32_t out,
+ int ccssize, uint8_t *pattern_buf,
+ uint8_t *read_buf, int bosize,
+ struct intel_execution_engine2 *e)
+{
+ int ret, i;
+
+ /* set 'src' to random pattern */
+ gem_write(fd, src, 0, pattern_buf, bosize);
+
+ /*
+ * 'dst' is lmem BO with ccs, directly
+ * copy content in 'src' BO to 'dst' BO's ccs
+ */
+ ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+ src, dst, ccssize, true, e);
+
+ igt_assert(!ret);
+
+ /* clear out BO */
+ memset(read_buf, 0, ccssize);
+ gem_write(fd, out, 0, read_buf, ccssize);
+
+ /* copy 'dst' BO's ccs into 'out' BO */
+ ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+ dst, out, ccssize, false, e);
+ igt_assert(!ret);
+
+ /* read 'out' BO into read_buf */
+ gem_read(fd, out, 0, read_buf, ccssize);
+ /*
+ * check 'read_buf',
+ * it should have original pattern
+ */
+ for (i = 0; i < ccssize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+ igt_assert(!ret);
+}
+
+static void igt_overwritten_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
+ uint32_t src, uint32_t dst, uint32_t out,
+ int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
+ int bosize, struct intel_execution_engine2 *e)
+{
+ int ret, i;
+
+ /************************************************/
+ /* #2 CCS is overwritten by XY_BLOCK_COPY_BLT */
+ /************************************************/
+ igt_info("copy random pattern to lmem BO with compression\n");
+
+ /* set 'src' to random pattern */
+ gem_write(fd, src, 0, pattern_buf, bosize);
+ /* set 'dst' to random pattern */
+ gem_write(fd, dst, 0, pattern_buf, bosize);
+
+ /*
+ * 'dst' is lmem BO with ccs,
+ * copy content in 'src' BO to 'dst' BO
+ */
+ ret = xy_block_copy_blt(fd, cmd, batch_buf,
+ src, dst, bosize, 1, e);
+ igt_assert(!ret);
+
+ /* clear out BO */
+ memset(read_buf, 0, ccssize);
+ gem_write(fd, out, 0, read_buf, ccssize);
+
+ /* copy 'dst' BO's ccs into 'out' BO */
+ ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+ dst, out, ccssize, false, e);
+ igt_assert(!ret);
+
+ /* read 'out' BO into read_buf */
+ gem_read(fd, out, 0, read_buf, ccssize);
+
+ /*
+ * check 'read_buf',
+ * it should NOT have original pattern
+ * (overwrite by XY_BLOCK_COPY_BLT)
+ */
+ for (i = 0; i < ccssize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+ igt_assert(ret);
+
+ /* read 'dst' BO into read_buf */
+ memset(read_buf, 0, bosize);
+ gem_read(fd, dst, 0, read_buf, bosize);
+
+ /*
+ * check 'read_buf',
+ * it should not have original pattern
+ */
+ for (i = 0; i < bosize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+ igt_assert(ret);
+
+ /* clear out BO */
+ memset(read_buf, 0, bosize);
+ gem_write(fd, out, 0, read_buf, bosize);
+
+ /* copy 'dst' BO into 'out' BO */
+ ret = xy_block_copy_blt(fd, cmd, batch_buf,
+ dst, out, bosize, 0, e);
+ igt_assert(!ret);
+
+ /* read 'out' BO into read_buf */
+ gem_read(fd, out, 0, read_buf, bosize);
+
+ /*
+ * check 'read_buf',
+ * it should have original pattern
+ */
+ for (i = 0; i < bosize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+ igt_assert(!ret);
+
+ /* decompress 'dst' in place */
+ ret = xy_block_copy_blt(fd, cmd, batch_buf,
+ dst, dst, bosize, 2, e);
+ igt_assert(!ret);
+
+ /* read 'out' BO into read_buf */
+ memset(read_buf, 0, bosize);
+ gem_read(fd, dst, 0, read_buf, bosize);
+
+ /*
+ * check 'read_buf',
+ * it should have original pattern
+ */
+ for (i = 0; i < bosize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+ igt_assert(!ret);
+
+ /* clear out BO */
+ memset(read_buf, 0, bosize);
+ gem_write(fd, out, 0, read_buf, bosize);
+
+ /* copy decompressed 'dst' to 'out' */
+ ret = xy_block_copy_blt(fd, cmd, batch_buf,
+ dst, out, bosize, 0, e);
+ igt_assert(!ret);
+
+ /* read 'out' BO into read_buf */
+ gem_read(fd, out, 0, read_buf, bosize);
+
+ /*
+ * check 'read_buf',
+ * it should have original pattern
+ */
+ for (i = 0; i < bosize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+
+ igt_assert(!ret);
+}
+
+static void igt_corrupted_xy_ctrl_surf_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
+ uint32_t src, uint32_t dst, uint32_t out,
+ int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
+ int bosize, struct intel_execution_engine2 *e)
+{
+ int ret, i;
+
+ /* set 'src' to random pattern */
+ gem_write(fd, src, 0, pattern_buf, bosize);
+
+ /************************************************/
+ /* #3 CCS is corrupted by XY_CTRL_SURF_COPY_BLT */
+ /************************************************/
+ igt_info("corrupt CCS via XY_CTRL_SURF_COPY_BLT\n");
+
+ /*
+ * corrupt 'dst' BO's ccs by writing directly
+ */
+ ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+ src, dst, ccssize, true, e);
+ igt_assert(!ret);
+
+ /* clear out BO */
+ memset(read_buf, 0, bosize);
+ gem_write(fd, out, 0, read_buf, bosize);
+
+ /* copy 'dst' BO into 'out' BO */
+ ret = xy_block_copy_blt(fd, cmd, batch_buf,
+ dst, out, bosize, 0, e);
+ igt_assert(!ret);
+
+ /* read 'out' BO into read_buf */
+ gem_read(fd, out, 0, read_buf, bosize);
+
+ /*
+ * check 'read_buf',
+ * it should have corrupted pattern
+ */
+ for (i = 0; i < bosize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+ igt_assert(ret);
+
+ /* clear out BO */
+ memset(read_buf, 0, ccssize);
+ gem_write(fd, out, 0, read_buf, ccssize);
+
+ /* copy 'dst' BO's ccs into 'out' BO */
+ ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+ dst, out, ccssize, false, e);
+ igt_assert(!ret);
+
+ /* read 'out' BO into read_buf */
+ gem_read(fd, out, 0, read_buf, ccssize);
+
+ /*
+ * check 'read_buf',
+ * it should have original pattern
+ */
+ for (i = 0; i < ccssize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+ igt_assert(!ret);
+}
+
+static void igt_copy_zero_pattern_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
+ uint32_t src, uint32_t dst, uint32_t out,
+ int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
+ uint8_t *input_buf, int bosize,
+ struct intel_execution_engine2 *e)
+{
+ int ret, i;
+
+ /************************************************/
+ /* #4 Copy zeros pattern with XY_BLOCK_COPY_BLT */
+ /************************************************/
+ igt_info("copy zeros pattern to lmem BO with compression\n");
+
+ /* set src BO to random pattern */
+ gem_write(fd, src, 0, pattern_buf, bosize);
+ /* set dst BO to random pattern */
+ gem_write(fd, dst, 0, pattern_buf, bosize);
+ /* set ccs to random pattern */
+ ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+ src, dst, ccssize, true, e);
+ igt_assert(!ret);
+
+ /* clear 'src' BO */
+ memset(input_buf, 0, bosize);
+ gem_write(fd, src, 0, input_buf, bosize);
+
+ /* copy 'src' to 'dst' with compression */
+ ret = xy_block_copy_blt(fd, cmd, batch_buf,
+ src, dst, bosize, 1, e);
+ igt_assert(!ret);
+
+ /* set out BO to random pattern */
+ gem_write(fd, out, 0, pattern_buf, bosize);
+
+ /* copy 'dst' BO back into 'out' BO */
+ ret = xy_block_copy_blt(fd, cmd, batch_buf,
+ dst, out, bosize, 0, e);
+ igt_assert(!ret);
+
+ /* read 'out' BO into read_buf */
+ gem_read(fd, out, 0, read_buf, bosize);
+
+ /*
+ * check 'read_buf',
+ * it should have same zero pattern
+ */
+ for (i = 0; i < bosize; i++) {
+ if (read_buf[i] != input_buf[i])
+ ret++;
+ }
+ igt_assert(!ret);
+
+ /* clear read_buf */
+ memset(read_buf, 0, bosize);
+ /* read 'dst' BO into read_buf */
+ gem_read(fd, dst, 0, read_buf, bosize);
+
+ /*
+ * check 'read_buf',
+ * it should have the same pattern
+ * as zero pattern compression won't change
+ * target pages, only change ccs.
+ */
+ for (i = 0; i < bosize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+ igt_assert(!ret);
+
+ /* clear out BO */
+ memset(read_buf, 0, ccssize);
+ gem_write(fd, out, 0, read_buf, ccssize);
+
+ /* copy 'dst' BO's ccs into 'out' BO */
+ ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+ dst, out, ccssize, false, e);
+ igt_assert(!ret);
+
+ /* read 'out' BO into read_buf */
+ gem_read(fd, out, 0, read_buf, ccssize);
+
+ /*
+ * check 'read_buf',
+ * it should have different pattern
+ */
+ for (i = 0; i < ccssize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+ igt_assert(ret);
+}
+
+static void igt_copy_repeat_pattern_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
+ uint32_t src, uint32_t dst, uint32_t out,
+ int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
+ uint8_t *input_buf, int bosize,
+ struct intel_execution_engine2 *e)
+{
+ int ret, i;
+
+ /************************************************/
+ /* #5 Copy repeat pattern with XY_BLOCK_COPY_BLT*/
+ /************************************************/
+ igt_info("copy repeat pattern to lmem BO with compression\n");
+
+ /* Set 'src' to random pattern */
+ gem_write(fd, src, 0, pattern_buf, bosize);
+ /* Set 'dst' and 'ccs' to random pattern */
+ gem_write(fd, src, 0, pattern_buf, ccssize);
+ ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+ src, dst, ccssize, true, e);
+ igt_assert(!ret);
+ gem_write(fd, dst, 0, pattern_buf, bosize);
+
+ /* generate repeating pattern */
+ input_buf[0] = (uint8_t)rand();
+ input_buf[1] = (uint8_t)rand();
+ input_buf[2] = (uint8_t)rand();
+ input_buf[3] = (uint8_t)rand();
+ for (i = 4; i < bosize; i++)
+ input_buf[i] = input_buf[i - 4];
+ gem_write(fd, src, 0, input_buf, bosize);
+ ret = xy_block_copy_blt(fd, cmd, batch_buf,
+ src, dst, bosize, 1, e);
+ igt_assert(!ret);
+
+ /* clear out BO */
+ memset(read_buf, 0, bosize);
+ gem_write(fd, out, 0, read_buf, bosize);
+
+ /* copy 'dst' BO back into 'out' BO */
+ ret = xy_block_copy_blt(fd, cmd, batch_buf,
+ dst, out, bosize, 0, e);
+ igt_assert(!ret);
+
+ /* read 'out' BO into read_buf */
+ gem_read(fd, out, 0, read_buf, bosize);
+
+ /*
+ * check 'read_buf',
+ * it should have same pattern
+ */
+ for (i = 0; i < bosize; i++) {
+ if (read_buf[i] != input_buf[i])
+ ret++;
+ }
+ igt_assert(!ret);
+
+ /* clear read_buf */
+ memset(read_buf, 0, bosize);
+ /* read 'dst' BO into read_buf */
+ gem_read(fd, dst, 0, read_buf, bosize);
+
+ /*
+ * check 'read_buf',
+ * it should have different pattern
+ */
+ for (i = 0; i < bosize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+ igt_assert(ret);
+
+ /* clear out BO */
+ memset(read_buf, 0, ccssize);
+ gem_write(fd, out, 0, read_buf, ccssize);
+
+ /* copy 'dst' BO's ccs into 'out' BO */
+ ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+ dst, out, ccssize, false, e);
+ igt_assert(!ret);
+
+ /* read 'out' BO into read_buf */
+ gem_read(fd, out, 0, read_buf, ccssize);
+
+ /*
+ * check 'read_buf',
+ * it should have different pattern
+ */
+ for (i = 0; i < ccssize; i++) {
+ if (read_buf[i] != pattern_buf[i])
+ ret++;
+ }
+ igt_assert(ret);
+}
+
+/*
+ * Allocate a BO in SMEM.
+ * Fill a pattern
+ * Use XY_BLOCK_COPY_BLT to copy it to LMEM with compression enabled
+ * Clear the BO in SMEM, and the pattern_buf in which the pattern was
+ * stored
+ * Use XY_BLOCK_COPY_BLT to copy it back to the BO in SMEM with
+ * resolve
+ * Compare the value in the BO in SMEM matches the pattern
+ */
+static void test_ccs(int fd, int size, uint32_t region, char *sub_name,
+ struct intel_execution_engine2 *e)
+{
+ int bosize, ccssize, ret, i;
+ int start, end;
+ uint32_t cmd, src, dst, out;
+ uint32_t batch_buf[BATCH_SIZE / sizeof(uint32_t)];
+ uint8_t *pattern_buf, *input_buf, *read_buf;
+ struct timeval tv;
+
+ if (size > 0) {
+ start = size;
+ end = start + 1;
+ } else {
+ start = BOSIZE_MIN;
+ end = BOSIZE_MAX;
+ }
+
+ /*
+ * create batch BO in smem for execution.
+ */
+ cmd = gem_create(fd, BATCH_SIZE);
+
+ for (bosize = start; bosize < end; bosize *= 2) {
+ /* allocate working buffers */
+ pattern_buf = malloc(bosize);
+ igt_assert(pattern_buf);
+ input_buf = malloc(bosize);
+ igt_assert(input_buf);
+ read_buf = malloc(bosize);
+ igt_assert(read_buf);
+
+ ccssize = bosize / CCS_RATIO;
+
+ /* allocate working BOs in the right location */
+ src = gem_create_in_memory_regions(fd, bosize,
+ INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
+ dst = gem_create_in_memory_regions(fd, bosize, region);
+ out = gem_create_in_memory_regions(fd, bosize,
+ INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
+
+ /* fill in random pattern */
+ ret = gettimeofday(&tv, NULL);
+ igt_assert(!ret);
+ srandom((int)tv.tv_usec);
+
+ for (i = 0; i < bosize; i++)
+ pattern_buf[i] = (uint8_t)rand();
+
+ igt_info("progress: bosize %d, ccssize %d\n", bosize, ccssize);
+
+ igt_dynamic_f("write_read_in_ccs_surface-%s-%s", sub_name, e->name)
+ igt_wr_xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+ src, dst, out, ccssize,
+ pattern_buf, read_buf, bosize, e);
+ igt_dynamic_f("verify_compression_of_random_data-%s-%s", sub_name, e->name)
+ igt_overwritten_xy_block_copy_blt(fd, cmd, batch_buf,
+ src, dst, out, ccssize,
+ pattern_buf, read_buf, bosize, e);
+ igt_dynamic_f("verify_corrupted_pattern_in_ccs_surface-%s-%s", sub_name, e->name)
+ igt_corrupted_xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
+ src, dst, out, ccssize,
+ pattern_buf, read_buf, bosize, e);
+ igt_dynamic_f("copy_zero_pattern_with_compression-%s-%s", sub_name, e->name)
+ igt_copy_zero_pattern_xy_block_copy_blt(fd, cmd, batch_buf,
+ src, dst, out, ccssize, pattern_buf,
+ read_buf, input_buf, bosize, e);
+ igt_dynamic_f("copy_repeat_pattern_with_compression-%s-%s", sub_name, e->name)
+ igt_copy_repeat_pattern_xy_block_copy_blt(fd, cmd, batch_buf,
+ src, dst, out, ccssize, pattern_buf,
+ read_buf, input_buf, bosize, e);
+
+ /* cleanup... */
+ gem_close(fd, out);
+ gem_close(fd, dst);
+ gem_close(fd, src);
+ free(read_buf);
+ free(input_buf);
+ free(pattern_buf);
+ }
+
+ gem_close(fd, cmd);
+}
+
+igt_main
+{
+ struct drm_i915_query_memory_regions *query_info;
+ struct intel_execution_engine2 *e;
+ struct igt_collection *regions, *set;
+ char *sub_name;
+ uint32_t region;
+ int drm_fd;
+
+ igt_fixture {
+ drm_fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(drm_fd);
+ igt_require(AT_LEAST_GEN(intel_get_drm_devid(drm_fd), 12) > 0);
+
+ query_info = gem_get_query_memory_regions(drm_fd);
+ igt_require(query_info);
+
+ set = get_memory_region_set(query_info, I915_DEVICE_MEMORY);
+ }
+
+ igt_subtest_with_dynamic("basic-gem-ccs-4K") {
+ for_each_physical_engine(drm_fd, e) {
+ if (!gem_engine_can_block_copy(drm_fd, e))
+ continue;
+
+ for_each_combination(regions, 1, set) {
+ sub_name = memregion_dynamic_subtest_name(regions);
+ region = igt_collection_get_value(regions, 0);
+ test_ccs(drm_fd, 4 * 1024, region, sub_name, e);
+ free(sub_name);
+ }
+ }
+ }
+
+ igt_subtest_with_dynamic("basic-gem-ccs-64K") {
+ for_each_physical_engine(drm_fd, e) {
+ if (!gem_engine_can_block_copy(drm_fd, e))
+ continue;
+
+ for_each_combination(regions, 1, set) {
+ sub_name = memregion_dynamic_subtest_name(regions);
+ region = igt_collection_get_value(regions, 0);
+ test_ccs(drm_fd, 64 * 1024, region, sub_name, e);
+ free(sub_name);
+ }
+ }
+ }
+
+ igt_subtest_with_dynamic("basic-gem-ccs-1M") {
+ for_each_physical_engine(drm_fd, e) {
+ if (!gem_engine_can_block_copy(drm_fd, e))
+ continue;
+
+ for_each_combination(regions, 1, set) {
+ sub_name = memregion_dynamic_subtest_name(regions);
+ region = igt_collection_get_value(regions, 0);
+ test_ccs(drm_fd, 1024 * 1024, region, sub_name, e);
+ free(sub_name);
+ }
+ }
+ }
+
+ igt_subtest_with_dynamic("basic-gem-ccs-all") {
+ for_each_physical_engine(drm_fd, e) {
+ if (!gem_engine_can_block_copy(drm_fd, e))
+ continue;
+
+ for_each_combination(regions, 1, set) {
+ sub_name = memregion_dynamic_subtest_name(regions);
+ region = igt_collection_get_value(regions, 0);
+ test_ccs(drm_fd, 0, region, sub_name, e);
+ free(sub_name);
+ }
+ }
+ }
+
+ igt_fixture {
+ close(drm_fd);
+ }
+}
diff --git a/tests/meson.build b/tests/meson.build
index 0af3e03a..d3e76122 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -105,6 +105,7 @@ i915_progs = [
'gem_blits',
'gem_busy',
'gem_caching',
+ 'gem_ccs',
'gem_close',
'gem_close_race',
'gem_concurrent_blit',
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Add testing for CCS
2021-11-08 5:51 [igt-dev] [PATCH i-g-t 0/2] Add testing for CCS apoorva1.singh
2021-11-08 5:51 ` [igt-dev] [PATCH i-g-t 1/2] lib/i915: Introduce libraries i915_blt and intel_mocs apoorva1.singh
2021-11-08 5:51 ` [igt-dev] [PATCH i-g-t 2/2] i915/gem_ccs: Add testing for CCS apoorva1.singh
@ 2021-11-08 6:42 ` Patchwork
2021-11-08 8:00 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-11-08 6:42 UTC (permalink / raw)
To: apoorva1.singh; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 2708 bytes --]
== Series Details ==
Series: Add testing for CCS
URL : https://patchwork.freedesktop.org/series/96648/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10853 -> IGTPW_6380
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/index.html
Participating hosts (41 -> 35)
------------------------------
Additional (1): fi-bdw-samus
Missing (7): bat-dg1-6 fi-tgl-u2 fi-bsw-n3050 bat-dg1-5 fi-bsw-cyan bat-adlp-4 fi-ctg-p8600
Known issues
------------
Here are the changes found in IGTPW_6380 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][1] -> [INCOMPLETE][2] ([i915#3921])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-bdw-samus: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/fi-bdw-samus/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-bdw-samus: NOTRUN -> [SKIP][4] ([fdo#109271]) +29 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/fi-bdw-samus/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6274 -> IGTPW_6380
CI-20190529: 20190529
CI_DRM_10853: 215295e7b0a3deb2015c6d6b343b319e4f6d9a1d @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_6380: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/index.html
IGT_6274: 569de51145fba197a8d93b2417348d47507bf485 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Testlist changes ==
+igt@gem_ccs@basic-gem-ccs-1m
+igt@gem_ccs@basic-gem-ccs-4k
+igt@gem_ccs@basic-gem-ccs-64k
+igt@gem_ccs@basic-gem-ccs-all
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/index.html
[-- Attachment #2: Type: text/html, Size: 3328 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Add testing for CCS
2021-11-08 5:51 [igt-dev] [PATCH i-g-t 0/2] Add testing for CCS apoorva1.singh
` (2 preceding siblings ...)
2021-11-08 6:42 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
@ 2021-11-08 8:00 ` Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-11-08 8:00 UTC (permalink / raw)
To: apoorva1.singh; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 30237 bytes --]
== Series Details ==
Series: Add testing for CCS
URL : https://patchwork.freedesktop.org/series/96648/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10853_full -> IGTPW_6380_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/index.html
Participating hosts (11 -> 7)
------------------------------
Missing (4): pig-skl-6260u pig-kbl-iris shard-rkl pig-glk-j5005
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_6380_full:
### IGT changes ###
#### Possible regressions ####
* {igt@gem_ccs@basic-gem-ccs-1m} (NEW):
- shard-iclb: NOTRUN -> [SKIP][1] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb3/igt@gem_ccs@basic-gem-ccs-1m.html
* {igt@gem_ccs@basic-gem-ccs-all} (NEW):
- shard-tglb: NOTRUN -> [FAIL][2] +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb7/igt@gem_ccs@basic-gem-ccs-all.html
New tests
---------
New tests have been introduced between CI_DRM_10853_full and IGTPW_6380_full:
### New IGT tests (4) ###
* igt@gem_ccs@basic-gem-ccs-1m:
- Statuses : 1 fail(s) 4 skip(s)
- Exec time: [0.0] s
* igt@gem_ccs@basic-gem-ccs-4k:
- Statuses :
- Exec time: [None] s
* igt@gem_ccs@basic-gem-ccs-64k:
- Statuses : 1 fail(s) 3 skip(s)
- Exec time: [0.0] s
* igt@gem_ccs@basic-gem-ccs-all:
- Statuses : 1 fail(s) 5 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_6380_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_allocator@execbuf-with-allocator:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271]) +43 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-snb2/igt@api_intel_allocator@execbuf-with-allocator.html
* igt@feature_discovery@display-2x:
- shard-tglb: NOTRUN -> [SKIP][4] ([i915#1839])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb3/igt@feature_discovery@display-2x.html
- shard-iclb: NOTRUN -> [SKIP][5] ([i915#1839])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb7/igt@feature_discovery@display-2x.html
* igt@gem_ctx_persistence@engines-hostile:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-snb2/igt@gem_ctx_persistence@engines-hostile.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: NOTRUN -> [FAIL][7] ([i915#2846])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-glk2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-iclb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: NOTRUN -> [FAIL][12] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglb: NOTRUN -> [SKIP][13] ([i915#3297])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb7/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen3_render_mixed_blits:
- shard-tglb: NOTRUN -> [SKIP][14] ([fdo#109289]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb5/igt@gen3_render_mixed_blits.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-iclb: NOTRUN -> [SKIP][15] ([fdo#109289]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb3/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@bb-start-far:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#2856])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb2/igt@gen9_exec_parse@bb-start-far.html
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#2856])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb8/igt@gen9_exec_parse@bb-start-far.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [PASS][18] -> [TIMEOUT][19] ([i915#3953])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-tglb1/igt@i915_module_load@reload-with-fault-injection.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb8/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#1937])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-tglb: NOTRUN -> [WARN][21] ([i915#2681] / [i915#2684])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb7/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_pm_sseu@full-enable:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#4387])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb5/igt@i915_pm_sseu@full-enable.html
- shard-iclb: NOTRUN -> [SKIP][23] ([i915#4387])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb8/igt@i915_pm_sseu@full-enable.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: NOTRUN -> [DMESG-WARN][24] ([i915#180]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl1/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-tglb: NOTRUN -> [SKIP][25] ([i915#1769])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3777]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-glk: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3777])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-glk3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#3689]) +4 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb6/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +5 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl6/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#3689] / [i915#3886])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb7/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html
- shard-glk: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-glk3/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109278] / [i915#3886]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb7/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +9 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl1/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs:
- shard-iclb: NOTRUN -> [SKIP][34] ([fdo#109278]) +10 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb8/igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109284] / [fdo#111827]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-c-degamma:
- shard-tglb: NOTRUN -> [SKIP][36] ([fdo#109284] / [fdo#111827]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb2/igt@kms_color_chamelium@pipe-c-degamma.html
- shard-glk: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-glk7/igt@kms_color_chamelium@pipe-c-degamma.html
- shard-snb: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-snb4/igt@kms_color_chamelium@pipe-c-degamma.html
* igt@kms_color_chamelium@pipe-c-gamma:
- shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +8 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl7/igt@kms_color_chamelium@pipe-c-gamma.html
* igt@kms_color_chamelium@pipe-d-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +4 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl4/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][41] ([i915#1319]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl7/igt@kms_content_protection@atomic.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][42] ([i915#3359]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-512x170-rapid-movement.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-onscreen:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#109279] / [i915#3359]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-512x512-onscreen.html
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#109278] / [fdo#109279])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb2/igt@kms_cursor_crc@pipe-c-cursor-512x512-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][45] -> [DMESG-WARN][46] ([i915#180]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109274] / [fdo#109278])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb1/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-glk: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#533])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-glk6/igt@kms_cursor_legacy@pipe-d-single-bo.html
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#533])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl4/igt@kms_cursor_legacy@pipe-d-single-bo.html
- shard-apl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#533])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl1/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][51] -> [FAIL][52] ([i915#2122])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-glk7/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-glk2/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-kbl: NOTRUN -> [INCOMPLETE][53] ([i915#636])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271]) +58 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#111825]) +13 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
- shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109280]) +8 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [PASS][57] -> [INCOMPLETE][58] ([i915#2411] / [i915#456])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
- shard-glk: NOTRUN -> [SKIP][59] ([fdo#109271]) +50 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-glk2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][60] ([fdo#109271]) +189 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl4/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [PASS][61] -> [DMESG-WARN][62] ([i915#180]) +3 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
- shard-tglb: [PASS][63] -> [INCOMPLETE][64] ([i915#4182])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-tglb1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_lowres@pipe-b-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][66] ([i915#3536])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb8/igt@kms_plane_lowres@pipe-b-tiling-none.html
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#3536])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb8/igt@kms_plane_lowres@pipe-b-tiling-none.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2733])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#658]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][70] -> [SKIP][71] ([fdo#109441]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
* igt@kms_psr@psr2_suspend:
- shard-tglb: NOTRUN -> [FAIL][72] ([i915#132] / [i915#3467])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb2/igt@kms_psr@psr2_suspend.html
* igt@nouveau_crc@pipe-a-source-outp-inactive:
- shard-tglb: NOTRUN -> [SKIP][73] ([i915#2530])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb6/igt@nouveau_crc@pipe-a-source-outp-inactive.html
* igt@prime_nv_pcopy@test3_5:
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109291]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb3/igt@prime_nv_pcopy@test3_5.html
* igt@prime_nv_test@nv_write_i915_gtt_mmap_read:
- shard-tglb: NOTRUN -> [SKIP][75] ([fdo#109291]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb6/igt@prime_nv_test@nv_write_i915_gtt_mmap_read.html
* igt@sysfs_clients@sema-50:
- shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2994]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl1/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][77] ([i915#2842]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
- shard-glk: [FAIL][79] ([i915#2842]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-glk1/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][81] ([i915#2849]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-tglb: [INCOMPLETE][83] ([i915#456]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-tglb7/igt@i915_pm_backlight@fade_with_suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb5/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][85] ([i915#4281]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_big_fb@linear-32bpp-rotate-180:
- shard-glk: [DMESG-WARN][87] ([i915#118]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-glk5/igt@kms_big_fb@linear-32bpp-rotate-180.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-glk4/igt@kms_big_fb@linear-32bpp-rotate-180.html
* igt@kms_flip@flip-vs-suspend-interruptible@d-edp1:
- shard-tglb: [DMESG-WARN][89] ([i915#2411] / [i915#2867]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-tglb6/igt@kms_flip@flip-vs-suspend-interruptible@d-edp1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb2/igt@kms_flip@flip-vs-suspend-interruptible@d-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-iclb: [SKIP][91] ([i915#3701]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-apl: [DMESG-WARN][93] ([i915#180]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-apl7/igt@kms_hdr@bpc-switch-suspend.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][95] ([i915#180]) -> [PASS][96] +8 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][97] ([fdo#109441]) -> [PASS][98] +3 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_vblank@pipe-c-accuracy-idle:
- shard-glk: [FAIL][99] ([i915#43]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-glk9/igt@kms_vblank@pipe-c-accuracy-idle.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-glk8/igt@kms_vblank@pipe-c-accuracy-idle.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][101] ([i915#2684]) -> [WARN][102] ([i915#1804] / [i915#2684])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-tglb: [SKIP][103] ([fdo#111644] / [i915#1397] / [i915#2411]) -> [SKIP][104] ([i915#579])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-tglb7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-tglb8/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][105] ([i915#2920]) -> [SKIP][106] ([i915#658]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][107] ([i915#658]) -> [SKIP][108] ([i915#2920]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@runner@aborted:
- shard-apl: ([FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112]) ([i915#1814] / [i915#3002] / [i915#3363] / [i915#4312]) -> ([FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#3363] / [i915#4312])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-apl4/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-apl4/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-apl7/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10853/shard-apl6/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl3/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl6/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl4/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl1/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl1/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/shard-apl3/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2733]: https://gitlab.freedesktop.org/drm/intel/issues/2733
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3777]: https://gitlab.freedesktop.org/drm/intel/issues/3777
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3953]: https://gitlab.freedesktop.org/drm/intel/issues/3953
[i915#4182]: https://gitlab.freedesktop.org/drm/intel/issues/4182
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6274 -> IGTPW_
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6380/index.html
[-- Attachment #2: Type: text/html, Size: 37915 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] i915/gem_ccs: Add testing for CCS
2021-11-08 5:51 ` [igt-dev] [PATCH i-g-t 2/2] i915/gem_ccs: Add testing for CCS apoorva1.singh
@ 2021-11-08 8:52 ` Zbigniew Kempczyński
0 siblings, 0 replies; 6+ messages in thread
From: Zbigniew Kempczyński @ 2021-11-08 8:52 UTC (permalink / raw)
To: apoorva1.singh; +Cc: igt-dev
On Mon, Nov 08, 2021 at 11:21:49AM +0530, apoorva1.singh@intel.com wrote:
> From: CQ Tang <cq.tang@intel.com>
>
> Add gem_ccs test for CCS testing.
> Commands are constructed with XY_BLOCK_COPY_BLT
> and XY_CTRL_SURF_COPY_BLT instructions.
>
> Signed-off-by: CQ Tang <cq.tang@intel.com>
> Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
> ---
> lib/i915/gem_engine_topology.c | 38 ++
> lib/i915/gem_engine_topology.h | 5 +
> tests/i915/gem_ccs.c | 639 +++++++++++++++++++++++++++++++++
> tests/meson.build | 1 +
> 4 files changed, 683 insertions(+)
> create mode 100644 tests/i915/gem_ccs.c
>
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> index 729f42b0..37b5875e 100644
> --- a/lib/i915/gem_engine_topology.c
> +++ b/lib/i915/gem_engine_topology.c
> @@ -488,6 +488,44 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
> return ret;
> }
>
> +static bool
> +__gem_engine_has_capability(int i915, const char *engine,
> + const char *attr, const char *cap)
> +{
> + char buf[4096] = {};
> + FILE *file;
> +
> + file = __open_attr(igt_sysfs_open(i915), "r",
> + "engine", engine, attr, NULL);
> + if (file) {
> + fread(buf, 1, sizeof(buf) - 1, file);
> + fclose(file);
> + }
> +
> + return strstr(buf, cap);
> +}
> +
> +bool gem_engine_has_capability(int i915, const char *engine, const char *cap)
> +{
> + return __gem_engine_has_capability(i915, engine, "capabilities", cap);
> +}
> +
> +bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap)
> +{
> + return __gem_engine_has_capability(i915, engine, "known_capabilities", cap);
> +}
> +
> +bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine)
> +{
> + if (engine->class != I915_ENGINE_CLASS_COPY)
> + return false;
> +
> + if (!gem_engine_has_known_capability(i915, engine->name, "block_copy"))
> + return intel_gen(intel_get_drm_devid(i915)) >= 12;
> +
> + return gem_engine_has_capability(i915, engine->name, "block_copy");
> +}
> +
> uint32_t gem_engine_mmio_base(int i915, const char *engine)
> {
> unsigned int mmio = 0;
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> index 4cfab560..d24bc9e8 100644
> --- a/lib/i915/gem_engine_topology.h
> +++ b/lib/i915/gem_engine_topology.h
> @@ -124,6 +124,11 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
>
> uint32_t gem_engine_mmio_base(int i915, const char *engine);
>
> +bool gem_engine_has_capability(int i915, const char *engine, const char *cap);
> +bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap);
> +
> +bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine);
> +
> void dyn_sysfs_engines(int i915, int engines, const char *file,
> void (*test)(int i915, int engine));
>
> diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
> new file mode 100644
> index 00000000..d144a6d0
> --- /dev/null
> +++ b/tests/i915/gem_ccs.c
> @@ -0,0 +1,639 @@
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + * CQ Tang <cq.tang@intel.com>
> + * Neel Desai <neel.desai@intel.com>
> + *
> + */
> +
> +#include <errno.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include "drm.h"
> +#include "igt.h"
> +#include "i915/gem.h"
> +#include "i915/gem_create.h"
> +#include "lib/intel_chipset.h"
> +#include "i915/i915_blt.h"
> +
> +IGT_TEST_DESCRIPTION("Exercise the memory bandwidth compression and "
> + "decompression when copying data between "
> + "system and local memory");
> +
> +static void igt_wr_xy_ctrl_surf_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
> + uint32_t src, uint32_t dst, uint32_t out,
> + int ccssize, uint8_t *pattern_buf,
> + uint8_t *read_buf, int bosize,
> + struct intel_execution_engine2 *e)
> +{
> + int ret, i;
> +
> + /* set 'src' to random pattern */
> + gem_write(fd, src, 0, pattern_buf, bosize);
> +
> + /*
> + * 'dst' is lmem BO with ccs, directly
> + * copy content in 'src' BO to 'dst' BO's ccs
> + */
> + ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> + src, dst, ccssize, true, e);
> +
> + igt_assert(!ret);
> +
> + /* clear out BO */
> + memset(read_buf, 0, ccssize);
> + gem_write(fd, out, 0, read_buf, ccssize);
> +
> + /* copy 'dst' BO's ccs into 'out' BO */
> + ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> + dst, out, ccssize, false, e);
> + igt_assert(!ret);
> +
> + /* read 'out' BO into read_buf */
> + gem_read(fd, out, 0, read_buf, ccssize);
> + /*
> + * check 'read_buf',
> + * it should have original pattern
> + */
> + for (i = 0; i < ccssize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> + igt_assert(!ret);
> +}
> +
> +static void igt_overwritten_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
> + uint32_t src, uint32_t dst, uint32_t out,
> + int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
> + int bosize, struct intel_execution_engine2 *e)
> +{
> + int ret, i;
> +
> + /************************************************/
> + /* #2 CCS is overwritten by XY_BLOCK_COPY_BLT */
> + /************************************************/
> + igt_info("copy random pattern to lmem BO with compression\n");
> +
> + /* set 'src' to random pattern */
> + gem_write(fd, src, 0, pattern_buf, bosize);
> + /* set 'dst' to random pattern */
> + gem_write(fd, dst, 0, pattern_buf, bosize);
> +
> + /*
> + * 'dst' is lmem BO with ccs,
> + * copy content in 'src' BO to 'dst' BO
> + */
> + ret = xy_block_copy_blt(fd, cmd, batch_buf,
> + src, dst, bosize, 1, e);
> + igt_assert(!ret);
> +
> + /* clear out BO */
> + memset(read_buf, 0, ccssize);
> + gem_write(fd, out, 0, read_buf, ccssize);
> +
> + /* copy 'dst' BO's ccs into 'out' BO */
> + ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> + dst, out, ccssize, false, e);
> + igt_assert(!ret);
> +
> + /* read 'out' BO into read_buf */
> + gem_read(fd, out, 0, read_buf, ccssize);
> +
> + /*
> + * check 'read_buf',
> + * it should NOT have original pattern
> + * (overwrite by XY_BLOCK_COPY_BLT)
> + */
> + for (i = 0; i < ccssize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> + igt_assert(ret);
> +
> + /* read 'dst' BO into read_buf */
> + memset(read_buf, 0, bosize);
> + gem_read(fd, dst, 0, read_buf, bosize);
> +
> + /*
> + * check 'read_buf',
> + * it should not have original pattern
> + */
> + for (i = 0; i < bosize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> + igt_assert(ret);
> +
> + /* clear out BO */
> + memset(read_buf, 0, bosize);
> + gem_write(fd, out, 0, read_buf, bosize);
> +
> + /* copy 'dst' BO into 'out' BO */
> + ret = xy_block_copy_blt(fd, cmd, batch_buf,
> + dst, out, bosize, 0, e);
> + igt_assert(!ret);
> +
> + /* read 'out' BO into read_buf */
> + gem_read(fd, out, 0, read_buf, bosize);
> +
> + /*
> + * check 'read_buf',
> + * it should have original pattern
> + */
> + for (i = 0; i < bosize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> + igt_assert(!ret);
> +
> + /* decompress 'dst' in place */
> + ret = xy_block_copy_blt(fd, cmd, batch_buf,
> + dst, dst, bosize, 2, e);
> + igt_assert(!ret);
> +
> + /* read 'out' BO into read_buf */
> + memset(read_buf, 0, bosize);
> + gem_read(fd, dst, 0, read_buf, bosize);
> +
> + /*
> + * check 'read_buf',
> + * it should have original pattern
> + */
> + for (i = 0; i < bosize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> + igt_assert(!ret);
> +
> + /* clear out BO */
> + memset(read_buf, 0, bosize);
> + gem_write(fd, out, 0, read_buf, bosize);
> +
> + /* copy decompressed 'dst' to 'out' */
> + ret = xy_block_copy_blt(fd, cmd, batch_buf,
> + dst, out, bosize, 0, e);
> + igt_assert(!ret);
> +
> + /* read 'out' BO into read_buf */
> + gem_read(fd, out, 0, read_buf, bosize);
> +
> + /*
> + * check 'read_buf',
> + * it should have original pattern
> + */
> + for (i = 0; i < bosize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> +
> + igt_assert(!ret);
> +}
> +
> +static void igt_corrupted_xy_ctrl_surf_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
> + uint32_t src, uint32_t dst, uint32_t out,
> + int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
> + int bosize, struct intel_execution_engine2 *e)
> +{
> + int ret, i;
> +
> + /* set 'src' to random pattern */
> + gem_write(fd, src, 0, pattern_buf, bosize);
> +
> + /************************************************/
> + /* #3 CCS is corrupted by XY_CTRL_SURF_COPY_BLT */
> + /************************************************/
> + igt_info("corrupt CCS via XY_CTRL_SURF_COPY_BLT\n");
> +
> + /*
> + * corrupt 'dst' BO's ccs by writing directly
> + */
> + ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> + src, dst, ccssize, true, e);
> + igt_assert(!ret);
> +
> + /* clear out BO */
> + memset(read_buf, 0, bosize);
> + gem_write(fd, out, 0, read_buf, bosize);
> +
> + /* copy 'dst' BO into 'out' BO */
> + ret = xy_block_copy_blt(fd, cmd, batch_buf,
> + dst, out, bosize, 0, e);
> + igt_assert(!ret);
> +
> + /* read 'out' BO into read_buf */
> + gem_read(fd, out, 0, read_buf, bosize);
> +
> + /*
> + * check 'read_buf',
> + * it should have corrupted pattern
> + */
> + for (i = 0; i < bosize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> + igt_assert(ret);
> +
> + /* clear out BO */
> + memset(read_buf, 0, ccssize);
> + gem_write(fd, out, 0, read_buf, ccssize);
> +
> + /* copy 'dst' BO's ccs into 'out' BO */
> + ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> + dst, out, ccssize, false, e);
> + igt_assert(!ret);
> +
> + /* read 'out' BO into read_buf */
> + gem_read(fd, out, 0, read_buf, ccssize);
> +
> + /*
> + * check 'read_buf',
> + * it should have original pattern
> + */
> + for (i = 0; i < ccssize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> + igt_assert(!ret);
> +}
> +
> +static void igt_copy_zero_pattern_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
> + uint32_t src, uint32_t dst, uint32_t out,
> + int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
> + uint8_t *input_buf, int bosize,
> + struct intel_execution_engine2 *e)
> +{
> + int ret, i;
> +
> + /************************************************/
> + /* #4 Copy zeros pattern with XY_BLOCK_COPY_BLT */
> + /************************************************/
> + igt_info("copy zeros pattern to lmem BO with compression\n");
> +
> + /* set src BO to random pattern */
> + gem_write(fd, src, 0, pattern_buf, bosize);
> + /* set dst BO to random pattern */
> + gem_write(fd, dst, 0, pattern_buf, bosize);
> + /* set ccs to random pattern */
> + ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> + src, dst, ccssize, true, e);
> + igt_assert(!ret);
> +
> + /* clear 'src' BO */
> + memset(input_buf, 0, bosize);
> + gem_write(fd, src, 0, input_buf, bosize);
> +
> + /* copy 'src' to 'dst' with compression */
> + ret = xy_block_copy_blt(fd, cmd, batch_buf,
> + src, dst, bosize, 1, e);
> + igt_assert(!ret);
> +
> + /* set out BO to random pattern */
> + gem_write(fd, out, 0, pattern_buf, bosize);
> +
> + /* copy 'dst' BO back into 'out' BO */
> + ret = xy_block_copy_blt(fd, cmd, batch_buf,
> + dst, out, bosize, 0, e);
> + igt_assert(!ret);
> +
> + /* read 'out' BO into read_buf */
> + gem_read(fd, out, 0, read_buf, bosize);
> +
> + /*
> + * check 'read_buf',
> + * it should have same zero pattern
> + */
> + for (i = 0; i < bosize; i++) {
> + if (read_buf[i] != input_buf[i])
> + ret++;
> + }
> + igt_assert(!ret);
> +
> + /* clear read_buf */
> + memset(read_buf, 0, bosize);
> + /* read 'dst' BO into read_buf */
> + gem_read(fd, dst, 0, read_buf, bosize);
> +
> + /*
> + * check 'read_buf',
> + * it should have the same pattern
> + * as zero pattern compression won't change
> + * target pages, only change ccs.
> + */
> + for (i = 0; i < bosize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> + igt_assert(!ret);
> +
> + /* clear out BO */
> + memset(read_buf, 0, ccssize);
> + gem_write(fd, out, 0, read_buf, ccssize);
> +
> + /* copy 'dst' BO's ccs into 'out' BO */
> + ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> + dst, out, ccssize, false, e);
> + igt_assert(!ret);
> +
> + /* read 'out' BO into read_buf */
> + gem_read(fd, out, 0, read_buf, ccssize);
> +
> + /*
> + * check 'read_buf',
> + * it should have different pattern
> + */
> + for (i = 0; i < ccssize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> + igt_assert(ret);
> +}
> +
> +static void igt_copy_repeat_pattern_xy_block_copy_blt(int fd, uint32_t cmd, uint32_t *batch_buf,
> + uint32_t src, uint32_t dst, uint32_t out,
> + int ccssize, uint8_t *pattern_buf, uint8_t *read_buf,
> + uint8_t *input_buf, int bosize,
> + struct intel_execution_engine2 *e)
> +{
> + int ret, i;
> +
> + /************************************************/
> + /* #5 Copy repeat pattern with XY_BLOCK_COPY_BLT*/
> + /************************************************/
> + igt_info("copy repeat pattern to lmem BO with compression\n");
> +
> + /* Set 'src' to random pattern */
> + gem_write(fd, src, 0, pattern_buf, bosize);
> + /* Set 'dst' and 'ccs' to random pattern */
> + gem_write(fd, src, 0, pattern_buf, ccssize);
> + ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> + src, dst, ccssize, true, e);
> + igt_assert(!ret);
> + gem_write(fd, dst, 0, pattern_buf, bosize);
> +
> + /* generate repeating pattern */
> + input_buf[0] = (uint8_t)rand();
> + input_buf[1] = (uint8_t)rand();
> + input_buf[2] = (uint8_t)rand();
> + input_buf[3] = (uint8_t)rand();
> + for (i = 4; i < bosize; i++)
> + input_buf[i] = input_buf[i - 4];
> + gem_write(fd, src, 0, input_buf, bosize);
> + ret = xy_block_copy_blt(fd, cmd, batch_buf,
> + src, dst, bosize, 1, e);
> + igt_assert(!ret);
> +
> + /* clear out BO */
> + memset(read_buf, 0, bosize);
> + gem_write(fd, out, 0, read_buf, bosize);
> +
> + /* copy 'dst' BO back into 'out' BO */
> + ret = xy_block_copy_blt(fd, cmd, batch_buf,
> + dst, out, bosize, 0, e);
> + igt_assert(!ret);
> +
> + /* read 'out' BO into read_buf */
> + gem_read(fd, out, 0, read_buf, bosize);
> +
> + /*
> + * check 'read_buf',
> + * it should have same pattern
> + */
> + for (i = 0; i < bosize; i++) {
> + if (read_buf[i] != input_buf[i])
> + ret++;
> + }
> + igt_assert(!ret);
> +
> + /* clear read_buf */
> + memset(read_buf, 0, bosize);
> + /* read 'dst' BO into read_buf */
> + gem_read(fd, dst, 0, read_buf, bosize);
> +
> + /*
> + * check 'read_buf',
> + * it should have different pattern
> + */
> + for (i = 0; i < bosize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> + igt_assert(ret);
> +
> + /* clear out BO */
> + memset(read_buf, 0, ccssize);
> + gem_write(fd, out, 0, read_buf, ccssize);
> +
> + /* copy 'dst' BO's ccs into 'out' BO */
> + ret = xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> + dst, out, ccssize, false, e);
> + igt_assert(!ret);
> +
> + /* read 'out' BO into read_buf */
> + gem_read(fd, out, 0, read_buf, ccssize);
> +
> + /*
> + * check 'read_buf',
> + * it should have different pattern
> + */
> + for (i = 0; i < ccssize; i++) {
> + if (read_buf[i] != pattern_buf[i])
> + ret++;
> + }
> + igt_assert(ret);
> +}
> +
> +/*
> + * Allocate a BO in SMEM.
> + * Fill a pattern
> + * Use XY_BLOCK_COPY_BLT to copy it to LMEM with compression enabled
> + * Clear the BO in SMEM, and the pattern_buf in which the pattern was
> + * stored
> + * Use XY_BLOCK_COPY_BLT to copy it back to the BO in SMEM with
> + * resolve
> + * Compare the value in the BO in SMEM matches the pattern
> + */
> +static void test_ccs(int fd, int size, uint32_t region, char *sub_name,
> + struct intel_execution_engine2 *e)
> +{
> + int bosize, ccssize, ret, i;
> + int start, end;
> + uint32_t cmd, src, dst, out;
> + uint32_t batch_buf[BATCH_SIZE / sizeof(uint32_t)];
> + uint8_t *pattern_buf, *input_buf, *read_buf;
> + struct timeval tv;
> +
> + if (size > 0) {
> + start = size;
> + end = start + 1;
> + } else {
> + start = BOSIZE_MIN;
> + end = BOSIZE_MAX;
> + }
> +
> + /*
> + * create batch BO in smem for execution.
> + */
> + cmd = gem_create(fd, BATCH_SIZE);
> +
> + for (bosize = start; bosize < end; bosize *= 2) {
> + /* allocate working buffers */
> + pattern_buf = malloc(bosize);
> + igt_assert(pattern_buf);
> + input_buf = malloc(bosize);
> + igt_assert(input_buf);
> + read_buf = malloc(bosize);
> + igt_assert(read_buf);
> +
> + ccssize = bosize / CCS_RATIO;
> +
> + /* allocate working BOs in the right location */
> + src = gem_create_in_memory_regions(fd, bosize,
> + INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
> + dst = gem_create_in_memory_regions(fd, bosize, region);
> + out = gem_create_in_memory_regions(fd, bosize,
> + INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
> +
> + /* fill in random pattern */
> + ret = gettimeofday(&tv, NULL);
> + igt_assert(!ret);
> + srandom((int)tv.tv_usec);
> +
> + for (i = 0; i < bosize; i++)
> + pattern_buf[i] = (uint8_t)rand();
> +
> + igt_info("progress: bosize %d, ccssize %d\n", bosize, ccssize);
> +
> + igt_dynamic_f("write_read_in_ccs_surface-%s-%s", sub_name, e->name)
> + igt_wr_xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> + src, dst, out, ccssize,
> + pattern_buf, read_buf, bosize, e);
> + igt_dynamic_f("verify_compression_of_random_data-%s-%s", sub_name, e->name)
> + igt_overwritten_xy_block_copy_blt(fd, cmd, batch_buf,
> + src, dst, out, ccssize,
> + pattern_buf, read_buf, bosize, e);
> + igt_dynamic_f("verify_corrupted_pattern_in_ccs_surface-%s-%s", sub_name, e->name)
> + igt_corrupted_xy_ctrl_surf_copy_blt(fd, cmd, batch_buf,
> + src, dst, out, ccssize,
> + pattern_buf, read_buf, bosize, e);
> + igt_dynamic_f("copy_zero_pattern_with_compression-%s-%s", sub_name, e->name)
> + igt_copy_zero_pattern_xy_block_copy_blt(fd, cmd, batch_buf,
> + src, dst, out, ccssize, pattern_buf,
> + read_buf, input_buf, bosize, e);
> + igt_dynamic_f("copy_repeat_pattern_with_compression-%s-%s", sub_name, e->name)
> + igt_copy_repeat_pattern_xy_block_copy_blt(fd, cmd, batch_buf,
> + src, dst, out, ccssize, pattern_buf,
> + read_buf, input_buf, bosize, e);
> +
> + /* cleanup... */
> + gem_close(fd, out);
> + gem_close(fd, dst);
> + gem_close(fd, src);
> + free(read_buf);
> + free(input_buf);
> + free(pattern_buf);
> + }
> +
> + gem_close(fd, cmd);
> +}
> +
> +igt_main
> +{
> + struct drm_i915_query_memory_regions *query_info;
> + struct intel_execution_engine2 *e;
> + struct igt_collection *regions, *set;
> + char *sub_name;
> + uint32_t region;
> + int drm_fd;
> +
> + igt_fixture {
> + drm_fd = drm_open_driver(DRIVER_INTEL);
> + igt_require_gem(drm_fd);
> + igt_require(AT_LEAST_GEN(intel_get_drm_devid(drm_fd), 12) > 0);
> +
> + query_info = gem_get_query_memory_regions(drm_fd);
> + igt_require(query_info);
> +
> + set = get_memory_region_set(query_info, I915_DEVICE_MEMORY);
I've enforced to run in BAT on gens >= 12:
https://intel-gfx-ci.01.org/tree/drm-tip/TrybotIGT_442/fi-rkl-11600/igt@gem_ccs@basic-gem-ccs-4k.html
Try to find out what's wrong there.
--
Zbigniew
> + }
> +
> + igt_subtest_with_dynamic("basic-gem-ccs-4K") {
> + for_each_physical_engine(drm_fd, e) {
> + if (!gem_engine_can_block_copy(drm_fd, e))
> + continue;
> +
> + for_each_combination(regions, 1, set) {
> + sub_name = memregion_dynamic_subtest_name(regions);
> + region = igt_collection_get_value(regions, 0);
> + test_ccs(drm_fd, 4 * 1024, region, sub_name, e);
> + free(sub_name);
> + }
> + }
> + }
> +
> + igt_subtest_with_dynamic("basic-gem-ccs-64K") {
> + for_each_physical_engine(drm_fd, e) {
> + if (!gem_engine_can_block_copy(drm_fd, e))
> + continue;
> +
> + for_each_combination(regions, 1, set) {
> + sub_name = memregion_dynamic_subtest_name(regions);
> + region = igt_collection_get_value(regions, 0);
> + test_ccs(drm_fd, 64 * 1024, region, sub_name, e);
> + free(sub_name);
> + }
> + }
> + }
> +
> + igt_subtest_with_dynamic("basic-gem-ccs-1M") {
> + for_each_physical_engine(drm_fd, e) {
> + if (!gem_engine_can_block_copy(drm_fd, e))
> + continue;
> +
> + for_each_combination(regions, 1, set) {
> + sub_name = memregion_dynamic_subtest_name(regions);
> + region = igt_collection_get_value(regions, 0);
> + test_ccs(drm_fd, 1024 * 1024, region, sub_name, e);
> + free(sub_name);
> + }
> + }
> + }
> +
> + igt_subtest_with_dynamic("basic-gem-ccs-all") {
> + for_each_physical_engine(drm_fd, e) {
> + if (!gem_engine_can_block_copy(drm_fd, e))
> + continue;
> +
> + for_each_combination(regions, 1, set) {
> + sub_name = memregion_dynamic_subtest_name(regions);
> + region = igt_collection_get_value(regions, 0);
> + test_ccs(drm_fd, 0, region, sub_name, e);
> + free(sub_name);
> + }
> + }
> + }
> +
> + igt_fixture {
> + close(drm_fd);
> + }
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index 0af3e03a..d3e76122 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -105,6 +105,7 @@ i915_progs = [
> 'gem_blits',
> 'gem_busy',
> 'gem_caching',
> + 'gem_ccs',
> 'gem_close',
> 'gem_close_race',
> 'gem_concurrent_blit',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-11-08 8:52 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-08 5:51 [igt-dev] [PATCH i-g-t 0/2] Add testing for CCS apoorva1.singh
2021-11-08 5:51 ` [igt-dev] [PATCH i-g-t 1/2] lib/i915: Introduce libraries i915_blt and intel_mocs apoorva1.singh
2021-11-08 5:51 ` [igt-dev] [PATCH i-g-t 2/2] i915/gem_ccs: Add testing for CCS apoorva1.singh
2021-11-08 8:52 ` Zbigniew Kempczyński
2021-11-08 6:42 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2021-11-08 8:00 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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