[PATCH V2 00/17] Add support for J721E SK

[PATCH V2 00/17] Add support for J721E SK

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Hi All,
This series adds support for J721E SK [1]. Below is the detailed description
of the J721E SoC and the SK board supporting features.

Changes in V2:
Board name updated from EAIK to SK. 
* So changed the occurrences of EAIK to SK. 
* Rename files from eaik to sk.

[1]  https://www.ti.com/tool/SK-TDA4VM

Sinthu Raja (17):
  common: make: Support show_board_info() as part of SPL build
  drivers: power: pmic: Add support for tps659412 PMIC
  drivers: power: regulator: tps65941_regulator: Add support for 3Phase
    buck
  board: ti: j721e: Guard functions with right #ifdef to avoid build
    warnings
  board: ti: j721e: Enable support for reading EEPROM at next alternate
    address
  board: ti: j721e: Add support to update board_name for j721e-sk
  board: ti: j721e: Disable probing of daughtercards
  board: ti: j721e: Add support for detecting multiple device trees
  arm: j721e: Add support for selecting DT based on EEPROM
  arm: dts: k3-j721e-r5-common-proc-board: Do not use power-domains for
    I2C
  arm: dts: k3-j721e-sk: Add initial A72 specific dts support
  arm: dts: k3-j721e-r5-sk: Add initial R5 specific dts support for
    j721e-sk
  configs: j721e_evm_r5: Enable support for building multiple dtbs into
    FIT
  configs: j721e_evm_a72: Add SK dtb as part of DTB FIT
  configs: j721e_evm_a72: Align OSPI partitions on erase block boundary
  configs: j721e_evm: Store env in MMC FAT partition
  include: configs: Update env for selecting right dtb

 arch/arm/dts/Makefile                         |   4 +-
 .../arm/dts/k3-j721e-r5-common-proc-board.dts |   5 +
 arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi       |  31 +
 arch/arm/dts/k3-j721e-r5-sk.dts               | 646 ++++++++++++++
 arch/arm/dts/k3-j721e-sk-u-boot.dtsi          | 280 +++++++
 arch/arm/dts/k3-j721e-sk.dts                  | 791 ++++++++++++++++++
 arch/arm/mach-k3/j721e_init.c                 |  62 ++
 board/ti/j721e/evm.c                          |  46 +-
 common/Makefile                               |   3 +-
 configs/j721e_evm_a72_defconfig               |  11 +-
 configs/j721e_evm_r5_defconfig                |   4 +
 drivers/power/pmic/tps65941.c                 |   1 +
 drivers/power/regulator/tps65941_regulator.c  |   2 +
 include/configs/j721e_evm.h                   |   4 +
 14 files changed, 1876 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
 create mode 100644 arch/arm/dts/k3-j721e-r5-sk.dts
 create mode 100644 arch/arm/dts/k3-j721e-sk-u-boot.dtsi
 create mode 100644 arch/arm/dts/k3-j721e-sk.dts

-- 
2.31.1

[PATCH V2 01/17] common: make: Support show_board_info() as part of SPL build

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Enable support for show_board_info() in SPL build.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---
 common/Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/common/Makefile b/common/Makefile
index e7839027b6..55e455c5b8 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -19,7 +19,6 @@ endif
 # # boards
 obj-y += board_f.o
 obj-y += board_r.o
-obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
 obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o
 
 obj-$(CONFIG_CMD_BOOTM) += bootm.o bootm_os.o
@@ -61,6 +60,8 @@ endif # !CONFIG_SPL_BUILD
 obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o
 obj-$(CONFIG_$(SPL_TPL_)BLOBLIST) += bloblist.o
 
+obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_SPL_DFU
 obj-$(CONFIG_DFU_OVER_USB) += dfu.o
-- 
2.31.1

[PATCH V2 02/17] drivers: power: pmic: Add support for tps659412 PMIC

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Since TPS659412 and TPS659413 are both software compatible,
add a compatible string for the same inside tps65941.c.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
---

No changes in V2.

 drivers/power/pmic/tps65941.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c
index 114ef4d238..83d0f83c64 100644
--- a/drivers/power/pmic/tps65941.c
+++ b/drivers/power/pmic/tps65941.c
@@ -71,6 +71,7 @@ static struct dm_pmic_ops tps65941_ops = {
 
 static const struct udevice_id tps65941_ids[] = {
 	{ .compatible = "ti,tps659411", .data = TPS659411 },
+	{ .compatible = "ti,tps659412", .data = TPS659411 },
 	{ .compatible = "ti,tps659413", .data = TPS659413 },
 	{ .compatible = "ti,lp876441",  .data =  LP876441 },
 	{ }
-- 
2.31.1

[PATCH V2 03/17] drivers: power: regulator: tps65941_regulator: Add support for 3Phase buck

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Buck regulator 1, 2 and 3 of TPS6594132 on j721e-sk is in 3 Phase
confguration, in-order to support this, add configuring 3 Phase buck
in tps65941 while driver probing.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
---

No changes in V2.

 drivers/power/regulator/tps65941_regulator.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/power/regulator/tps65941_regulator.c b/drivers/power/regulator/tps65941_regulator.c
index d73f832483..89918c38fa 100644
--- a/drivers/power/regulator/tps65941_regulator.c
+++ b/drivers/power/regulator/tps65941_regulator.c
@@ -299,6 +299,8 @@ static int tps65941_buck_probe(struct udevice *dev)
 		idx = 1;
 	} else if (idx == 34) {
 		idx = 3;
+	} else if (idx == 123) {
+		idx = 1;
 	} else if (idx == 1234) {
 		idx = 1;
 	} else {
-- 
2.31.1

[PATCH V2 04/17] board: ti: j721e: Guard functions with right #ifdef to avoid build warnings

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

board_late_init(), setup_board_eeprom_env() and setup_serial() is
called only under CONFIG_BOARD_LATE_INIT, so guard these functions
with the same.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

No chnages in V2.

 board/ti/j721e/evm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 077d83420c..9cdb963221 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -172,6 +172,7 @@ int checkboard(void)
 	return 0;
 }
 
+#ifdef CONFIG_BOARD_LATE_INIT
 static void setup_board_eeprom_env(void)
 {
 	char *name = "j721e";
@@ -210,6 +211,7 @@ static void setup_serial(void)
 	snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
 	env_set("serial#", serial_string);
 }
+#endif
 
 /*
  * Declaration of daughtercards to probe. Note that when adding more
@@ -413,6 +415,7 @@ void configure_serdes_torrent(void)
 		printf("phy_power_on failed !!\n");
 }
 
+#ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
 	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
@@ -428,6 +431,7 @@ int board_late_init(void)
 
 	return 0;
 }
+#endif
 
 void spl_board_init(void)
 {
-- 
2.31.1

[PATCH V2 05/17] board: ti: j721e: Enable support for reading EEPROM at next alternate address

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

J721E EVM has EEPROM populated at 0x50. J721E SK has EEPROM populated
at next address 0x51 in order to be compatible with RBPi. So start
looking for TI specific EEPROM at 0x50, if not found look for EEPROM at
0x51.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

No changes in V2.

 board/ti/j721e/evm.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 9cdb963221..989e15e666 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -152,9 +152,15 @@ int do_board_detect(void)
 
 	ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
 					 CONFIG_EEPROM_CHIP_ADDRESS);
-	if (ret)
-		pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
-		       CONFIG_EEPROM_CHIP_ADDRESS, ret);
+	if (ret) {
+		printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
+		       CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
+		ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+						 CONFIG_EEPROM_CHIP_ADDRESS + 1);
+		if (ret)
+			pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+			       CONFIG_EEPROM_CHIP_ADDRESS + 1, ret);
+	}
 
 	return ret;
 }
-- 
2.31.1

[PATCH V2 06/17] board: ti: j721e: Add support to update board_name for j721e-sk

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Update setup_board_eeprom_env() to choose the right board name
for j721e-sk.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

Changes in V2:
* J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik 
to sk
* Quite amount of SK boards are preprogrammed as EAIK in EEPROM, so retaining the
condition to check the board name as eaik.

 board/ti/j721e/evm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 989e15e666..9d4609cfe9 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -30,6 +30,9 @@
 #define board_is_j721e_som()	(board_ti_k3_is("J721EX-PM1-SOM") || \
 				 board_ti_k3_is("J721EX-PM2-SOM"))
 
+#define board_is_j721e_sk()	(board_ti_k3_is("J721EX-EAIK") || \
+				 board_ti_k3_is("J721EX-SK"))
+
 #define board_is_j7200_som()	(board_ti_k3_is("J7200X-PM1-SOM") || \
 				 board_ti_k3_is("J7200X-PM2-SOM"))
 
@@ -188,6 +191,8 @@ static void setup_board_eeprom_env(void)
 
 	if (board_is_j721e_som())
 		name = "j721e";
+	else if (board_is_j721e_sk())
+		name = "j721e-sk";
 	else if (board_is_j7200_som())
 		name = "j7200";
 	else
-- 
2.31.1

[PATCH V2 07/17] board: ti: j721e: Disable probing of daughtercards

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

j721e-sk doesn't have any daughter cards, so disable daughter
card probing inside board_late_init() and spl_board_init() for
j721e-sk.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

Changes in V2:
* J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik 
to sk.

 board/ti/j721e/evm.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 9d4609cfe9..cb491ad950 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -434,7 +434,8 @@ int board_late_init(void)
 		setup_serial();
 
 		/* Check for and probe any plugged-in daughtercards */
-		probe_daughtercards();
+		if (!board_is_j721e_sk())
+			probe_daughtercards();
 	}
 
 	if (board_is_j7200_som())
@@ -453,8 +454,10 @@ void spl_board_init(void)
 
 	if ((IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM) ||
 	     IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM)) &&
-	    IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
-		probe_daughtercards();
+	    IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
+		if (!board_is_j721e_sk())
+			probe_daughtercards();
+	}
 
 #ifdef CONFIG_ESM_K3
 	if (board_ti_k3_is("J721EX-PM2-SOM")) {
-- 
2.31.1

[PATCH V2 08/17] board: ti: j721e: Add support for detecting multiple device trees

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Update the board_fit_config_name_match() to choose the right dtb
based on the board name read from EEPROM.

Also restrict multpile EEPROM reads by verifying if EEPROM is already
read.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

Changes in V2:
* J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik 
to sk.

 board/ti/j721e/evm.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index cb491ad950..31de53ea71 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -88,8 +88,17 @@ int dram_init_banksize(void)
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-	if (!strcmp(name, "k3-j721e-common-proc-board"))
-		return 0;
+	bool eeprom_read = board_ti_was_eeprom_read();
+
+	if (!eeprom_read || board_is_j721e_som()) {
+		if (!strcmp(name, "k3-j721e-common-proc-board") ||
+		    !strcmp(name, "k3-j721e-r5-common-proc-board"))
+			return 0;
+	} else if (board_is_j721e_sk()) {
+		if (!strcmp(name, "k3-j721e-sk") ||
+		    !strcmp(name, "k3-j721e-r5-sk"))
+			return 0;
+	}
 
 	return -1;
 }
@@ -153,6 +162,9 @@ int do_board_detect(void)
 {
 	int ret;
 
+	if (board_ti_was_eeprom_read())
+		return 0;
+
 	ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
 					 CONFIG_EEPROM_CHIP_ADDRESS);
 	if (ret) {
-- 
2.31.1

[PATCH V2 09/17] arm: j721e: Add support for selecting DT based on EEPROM

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Enable support for selecting DTB from FIT within SPL based on the
board name read from EEPROM. This will help to use single defconfig
for both EVM and SK.

Also print FDT model name and board name read from EEPROM on SPL debug
console. This is useful to verify that right dtb is loaded in each boot
stage.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

No changes in V2.

 arch/arm/mach-k3/j721e_init.c | 62 +++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 78d80be175..53ea4692f6 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -21,6 +21,7 @@
 #include <dm/pinctrl.h>
 #include <mmc.h>
 #include <remoteproc.h>
+#include <dm/root.h>
 
 #ifdef CONFIG_SPL_BUILD
 #ifdef CONFIG_K3_LOAD_SYSFW
@@ -135,6 +136,59 @@ static void store_boot_info_from_rom(void)
 	       sizeof(struct rom_extended_boot_data));
 }
 
+#ifdef CONFIG_SPL_OF_LIST
+void do_dt_magic(void)
+{
+	int ret, rescan, mmc_dev = -1;
+	static struct mmc *mmc;
+
+	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
+		do_board_detect();
+
+	/*
+	 * Board detection has been done.
+	 * Let us see if another dtb wouldn't be a better match
+	 * for our board
+	 */
+	if (IS_ENABLED(CONFIG_CPU_V7R)) {
+		ret = fdtdec_resetup(&rescan);
+		if (!ret && rescan) {
+			dm_uninit();
+			dm_init_and_scan(true);
+		}
+	}
+
+	/*
+	 * Because of multi DTB configuration, the MMC device has
+	 * to be re-initialized after reconfiguring FDT inorder to
+	 * boot from MMC. Do this when boot mode is MMC and ROM has
+	 * not loaded SYSFW.
+	 */
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		mmc_dev = 0;
+		break;
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
+		mmc_dev = 1;
+		break;
+	}
+
+	if (mmc_dev > 0 && !is_rom_loaded_sysfw(&bootdata)) {
+		ret = mmc_init_device(mmc_dev);
+		if (!ret) {
+			mmc = find_mmc_device(mmc_dev);
+			if (mmc) {
+				ret = mmc_init(mmc);
+				if (ret) {
+					printf("mmc init failed with error: %d\n", ret);
+				}
+			}
+		}
+	}
+}
+#endif
+
 void board_init_f(ulong dummy)
 {
 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
@@ -180,6 +234,10 @@ void board_init_f(ulong dummy)
 	k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
 			k3_mmc_stop_clock, k3_mmc_restart_clock);
 
+#ifdef CONFIG_SPL_OF_LIST
+	do_dt_magic();
+#endif
+
 	/*
 	 * Force probe of clk_k3 driver here to ensure basic default clock
 	 * configuration is always done.
@@ -210,6 +268,10 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 #endif
 
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	show_board_info();
+#endif
+
 	/* Output System Firmware version info */
 	k3_sysfw_print_ver();
 
-- 
2.31.1

[PATCH V2 10/17] arm: dts: k3-j721e-r5-common-proc-board: Do not use power-domains for I2C

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Board ID I2C EEPROM will be probed before SYSFW is available.
So drop the power-domains property for wakup_i2c0 on which
board ID EEPROM is connected.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

No Changes in V2.

 arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 4b2362a5dd..88a69bf066 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -361,3 +361,8 @@
 &mcu_udmap {
 	ti,sci = <&dm_tifs>;
 };
+
+/* EEPROM might be read before SYSFW is available */
+&wkup_i2c0 {
+	/delete-property/ power-domains;
+};
-- 
2.31.1

[PATCH V2 11/17] arm: dts: k3-j721e-sk: Add initial A72 specific dts support

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

J721E Starter Kit (SK)[1] is a low cost, small form factor board designed
for TI’s J721E SoC. TI’s J721E SoC comprises of dual core A72, high
performance vision accelerators, video codec accelerators, latest C71x
and C66x DSP, high bandwidth real-time IPs for capture and display, GPU,
dedicated safety island and security accelerators. The SoC is power
optimized to provide best in class performance for industrial and
automotive applications.

    J721E SK supports the following interfaces:
    * 4 GB LPDDR4 RAM
    * x1 Gigabit Ethernet interface
    * x1 USB 3.0 Type-C port
    * x3 USB 3.0 Type-A ports
    * x1 PCIe M.2 E Key
    * x1 PCIe M.2 M Key
    * 512 Mbit OSPI flash
    * x2 CSI2 Camera interface (RPi and TI Camera connector)
    * 40-pin Raspberry Pi GPIO header

Add A72 specific dts for J721E-SK.

[1] https://www.ti.com/tool/SK-TDA4VM

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

Changes in V2:
* J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik 
to sk.
* Rename file from eaik to sk.

 arch/arm/dts/Makefile                |   3 +-
 arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 280 ++++++++++
 arch/arm/dts/k3-j721e-sk.dts         | 791 +++++++++++++++++++++++++++
 3 files changed, 1073 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/k3-j721e-sk-u-boot.dtsi
 create mode 100644 arch/arm/dts/k3-j721e-sk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a88aecc5bd..8918dfc48e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1113,7 +1113,8 @@ dtb-$(CONFIG_SOC_K3_AM6) += \
 dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
 			      k3-j721e-r5-common-proc-board.dtb \
 			      k3-j7200-common-proc-board.dtb \
-			      k3-j7200-r5-common-proc-board.dtb
+			      k3-j7200-r5-common-proc-board.dtb \
+			      k3-j721e-sk.dtb
 dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
 			      k3-am642-r5-evm.dtb \
 			      k3-am642-sk.dtb \
diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
new file mode 100644
index 0000000000..94b9e09e30
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+	chosen {
+		stdout-path = "serial2:115200n8";
+		tick-timer = &timer1;
+	};
+
+	aliases {
+		ethernet0 = &cpsw_port1;
+		spi0 = &ospi0;
+		remoteproc0 = &mcu_r5fss0_core0;
+		remoteproc1 = &mcu_r5fss0_core1;
+		remoteproc2 = &main_r5fss0_core0;
+		remoteproc3 = &main_r5fss0_core1;
+		remoteproc4 = &main_r5fss1_core0;
+		remoteproc5 = &main_r5fss1_core1;
+		remoteproc6 = &c66_0;
+		remoteproc7 = &c66_1;
+		remoteproc8 = &c71_0;
+		i2c0 = &wkup_i2c0;
+		i2c1 = &mcu_i2c0;
+		i2c2 = &main_i2c0;
+		mmc1 = &main_sdhci1;  /* SD Card */
+	};
+};
+
+&cbass_main{
+	u-boot,dm-spl;
+
+	main-navss {
+		u-boot,dm-spl;
+	};
+};
+
+&cbass_mcu_wakeup {
+	u-boot,dm-spl;
+
+	timer1: timer@40400000 {
+		compatible = "ti,omap5430-timer";
+		reg = <0x0 0x40400000 0x0 0x80>;
+		ti,timer-alwon;
+		clock-frequency = <25000000>;
+		u-boot,dm-spl;
+	};
+
+	mcu-navss {
+		u-boot,dm-spl;
+
+		ringacc@2b800000 {
+			reg =	<0x0 0x2b800000 0x0 0x400000>,
+				<0x0 0x2b000000 0x0 0x400000>,
+				<0x0 0x28590000 0x0 0x100>,
+				<0x0 0x2a500000 0x0 0x40000>,
+				<0x0 0x28440000 0x0 0x40000>;
+			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+			u-boot,dm-spl;
+		};
+
+		dma-controller@285c0000 {
+			reg =	<0x0 0x285c0000 0x0 0x100>,
+				<0x0 0x284c0000 0x0 0x4000>,
+				<0x0 0x2a800000 0x0 0x40000>,
+				<0x0 0x284a0000 0x0 0x4000>,
+				<0x0 0x2aa00000 0x0 0x40000>,
+				<0x0 0x28400000 0x0 0x2000>;
+			reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+					    "tchanrt", "rflow";
+			u-boot,dm-spl;
+		};
+	};
+
+	chipid@43000014 {
+		u-boot,dm-spl;
+	};
+};
+
+&secure_proxy_main {
+	u-boot,dm-spl;
+};
+
+&dmsc {
+	u-boot,dm-spl;
+	k3_sysreset: sysreset-controller {
+		compatible = "ti,sci-sysreset";
+		u-boot,dm-spl;
+	};
+};
+
+&k3_pds {
+	u-boot,dm-spl;
+};
+
+&k3_clks {
+	u-boot,dm-spl;
+};
+
+&k3_reset {
+	u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+	u-boot,dm-spl;
+};
+
+&main_pmx0 {
+	u-boot,dm-spl;
+};
+
+&main_uart0 {
+	u-boot,dm-spl;
+};
+
+&mcu_uart0 {
+	u-boot,dm-spl;
+};
+
+&main_sdhci0 {
+	status = "disabled";
+};
+
+&main_sdhci1 {
+	u-boot,dm-spl;
+};
+
+&wiz3_pll1_refclk {
+	assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
+	assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
+};
+
+&main_usbss0_pins_default {
+	u-boot,dm-spl;
+};
+
+&usbss0 {
+	u-boot,dm-spl;
+};
+
+&usb0 {
+	dr_mode = "host";
+	u-boot,dm-spl;
+};
+
+&wiz2_pll1_refclk {
+	assigned-clocks = <&wiz2_pll1_refclk>, <&wiz2_pll0_refclk>;
+	assigned-clock-parents = <&k3_clks 294 0>, <&k3_clks 294 11>;
+};
+
+&main_usbss1_pins_default {
+	u-boot,dm-spl;
+};
+
+&usbss1 {
+	u-boot,dm-spl;
+};
+
+&usb1 {
+	dr_mode = "host";
+	u-boot,dm-spl;
+};
+
+&mcu_cpsw {
+	reg = <0x0 0x46000000 0x0 0x200000>,
+	      <0x0 0x40f00200 0x0 0x2>;
+	reg-names = "cpsw_nuss", "mac_efuse";
+	/delete-property/ ranges;
+
+	cpsw-phy-sel@40f04040 {
+		compatible = "ti,am654-cpsw-phy-sel";
+		reg= <0x0 0x40f04040 0x0 0x4>;
+		reg-names = "gmii-sel";
+	};
+};
+
+&main_mmc1_pins_default {
+	u-boot,dm-spl;
+};
+
+&wkup_i2c0_pins_default {
+	u-boot,dm-spl;
+};
+
+&wkup_i2c0 {
+	u-boot,dm-spl;
+};
+
+&mcu_i2c0 {
+	u-boot,dm-spl;
+};
+
+&mcu_i2c1 {
+	status = "disabled";
+};
+
+&main_i2c0 {
+	status = "disabled";
+};
+
+&main_i2c1 {
+	status = "disabled";
+};
+
+&main_i2c2 {
+	status = "disabled";
+};
+
+&main_i2c3 {
+	status = "disabled";
+};
+
+&main_i2c4 {
+	status = "disabled";
+};
+
+&main_i2c5 {
+	status = "disabled";
+};
+
+&main_i2c6 {
+	status = "disabled";
+};
+
+&mcu_i2c0_pins_default {
+	u-boot,dm-spl;
+};
+
+&mcu_fss0_ospi0_pins_default {
+	u-boot,dm-spl;
+};
+
+&fss {
+	u-boot,dm-spl;
+};
+
+&ospi0 {
+	u-boot,dm-spl;
+
+	flash@0 {
+		u-boot,dm-spl;
+
+		partition@3fc0000 {
+			label = "ospi.phypattern";
+			reg = <0x3fc0000 0x40000>;
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&serdes_ln_ctrl {
+	u-boot,mux-autoprobe;
+};
+
+&usb_serdes_mux {
+	u-boot,mux-autoprobe;
+};
+
+&pcie0_rc {
+	status = "disabled";
+};
+
+&pcie1_rc {
+	status = "disabled";
+};
+
+&pcie0_ep {
+	status = "disabled";
+};
+
+&pcie1_ep {
+	status = "disabled";
+};
+
+&dss {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/k3-j721e-sk.dts b/arch/arm/dts/k3-j721e-sk.dts
new file mode 100644
index 0000000000..4443cd0128
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-sk.dts
@@ -0,0 +1,791 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721e.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+	compatible = "ti,j721e-sk", "ti,j721e";
+	model = "Texas Instruments J721E SK A72";
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 4G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+		      <0x00000008 0x80000000 0x00000000 0x80000000>;
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa5000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa5100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_0_memory_region: c66-memory@a6100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_1_memory_region: c66-memory@a7100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_0_memory_region: c71-memory@a8100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		rtos_ipc_memory_region: ipc-memories@aa000000 {
+			reg = <0x00 0xaa000000 0x00 0x01c00000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+
+	vusb_main: fixedregulator-vusb-main5v0 {
+		/* USB MAIN INPUT 5V DC */
+		compatible = "regulator-fixed";
+		regulator-name = "vusb-main5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_3v3: fixedregulator-vsys3v3 {
+		/* Output of LM5141 */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vusb_main>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_mmc1: fixedregulator-sd {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vdd_mmc1_en_pins_default>;
+		regulator-name = "vdd_mmc1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		enable-active-high;
+		vin-supply = <&vsys_3v3>;
+		gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>;
+	};
+
+	vdd_sd_dv_alt: gpio-regulator-tps659411 {
+		compatible = "regulator-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+		regulator-name = "tps659411";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		vin-supply = <&vsys_3v3>;
+		gpios = <&wkup_gpio0 9 GPIO_ACTIVE_LOW>;
+		states = <3300000 0x0>,
+			 <1800000 0x1>;
+	};
+};
+
+&main_pmx0 {
+	main_mmc1_pins_default: main-mmc1-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+		>;
+	};
+
+	main_uart0_pins_default: main-uart0-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
+			J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
+			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+		>;
+	};
+
+	main_i2c0_pins_default: main-i2c0-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+		>;
+	};
+
+	main_i2c1_pins_default: main-i2c1-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+			J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+		>;
+	};
+
+	main_i2c3_pins_default: main-i2c3-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+			J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+		>;
+	};
+
+	mcu_i2c0_pins_default: mcu-i2c0-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
+			J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
+		>;
+	};
+
+	main_usbss0_pins_default: main-usbss0-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+		>;
+	};
+
+	main_usbss1_pins_default: main-usbss1-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+		>;
+	};
+};
+
+&wkup_pmx0 {
+	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
+			J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
+			J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
+			J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
+			J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
+			J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
+			J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
+			J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
+			J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
+			J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
+			J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
+			J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
+		>;
+	};
+
+	mcu_mdio_pins_default: mcu-mdio1-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
+			J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
+		>;
+	};
+
+	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
+			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
+			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
+			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
+			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
+			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
+			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
+			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
+			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
+			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
+			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
+		>;
+	};
+
+	vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
+		>;
+	};
+
+	vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
+		>;
+	};
+
+	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+		>;
+	};
+};
+
+&wkup_uart0 {
+	/* Wakeup UART is used by System firmware */
+	status = "reserved";
+};
+
+&main_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+	/* Shared with ATF on this platform */
+	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_uart2 {
+	/* Brought out on RPi header */
+	status = "disabled";
+};
+
+&main_uart3 {
+	/* UART not brought out */
+	status = "disabled";
+};
+
+&main_uart5 {
+	/* UART not brought out */
+	status = "disabled";
+};
+
+&main_uart6 {
+	/* UART not brought out */
+	status = "disabled";
+};
+
+&main_uart7 {
+	/* UART not brought out */
+	status = "disabled";
+};
+
+&main_uart8 {
+	/* UART not brought out */
+	status = "disabled";
+};
+
+&main_uart9 {
+	/* Brought out on M.2 E Key */
+	status = "disabled";
+};
+
+&main_sdhci0 {
+	/* Unused */
+	status = "disabled";
+};
+
+&main_sdhci1 {
+	/* SD Card */
+	vmmc-supply = <&vdd_mmc1>;
+	vqmmc-supply = <&vdd_sd_dv_alt>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+};
+
+&main_sdhci2 {
+	/* Unused */
+	status = "disabled";
+};
+
+&ospi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+	flash@0{
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+		spi-max-frequency = <25000000>;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <4>;
+		cdns,phy-mode;
+		cdns,phy-tx-start = <18>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+&ospi1 {
+	/* Unused */
+	status = "disabled";
+};
+
+&main_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+};
+
+&main_i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c1_pins_default>;
+	clock-frequency = <400000>;
+};
+
+&main_i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c3_pins_default>;
+	clock-frequency = <400000>;
+};
+
+&main_i2c4 {
+	/* Unused */
+	status = "disabled";
+};
+
+&main_i2c5 {
+	/* Brought out on RPi Header */
+	status = "disabled";
+};
+
+&main_i2c6 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcu_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_i2c0_pins_default>;
+	clock-frequency = <400000>;
+};
+
+&usb_serdes_mux {
+	idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+};
+
+&serdes_ln_ctrl {
+	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
+		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+		      <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
+		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
+};
+
+&serdes3 {
+	serdes3_usb_link: link@0 {
+		reg = <0>;
+		cdns,num-lanes = <2>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_USB3>;
+		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+	};
+};
+
+&usbss0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_usbss0_pins_default>;
+	ti,vbus-divider;
+};
+
+&usb0 {
+	dr_mode = "otg";
+	maximum-speed = "super-speed";
+	phys = <&serdes3_usb_link>;
+	phy-names = "cdns3,usb3-phy";
+};
+
+&serdes2 {
+	serdes2_usb_link: link@1 {
+		reg = <1>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_USB3>;
+		resets = <&serdes_wiz2 2>;
+	};
+};
+
+&usbss1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_usbss1_pins_default>;
+	ti,vbus-divider;
+};
+
+&usb1 {
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+	phys = <&serdes2_usb_link>;
+	phy-names = "cdns3,usb3-phy";
+};
+
+&tscadc0 {
+	/* Unused */
+	status = "disabled";
+};
+
+&tscadc1 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcu_cpsw {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+	};
+};
+
+&cpsw_port1 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&phy0>;
+};
+
+&dss {
+	assigned-clocks = <&k3_clks 152 1>,	/* VP 1 pixel clock */
+			  <&k3_clks 152 4>,	/* VP 2 pixel clock */
+			  <&k3_clks 152 9>,	/* VP 3 pixel clock */
+			  <&k3_clks 152 13>;	/* VP 4 pixel clock */
+	assigned-clock-parents = <&k3_clks 152 2>,	/* PLL16_HSDIV0 */
+				 <&k3_clks 152 6>,	/* DPI0_EXT_CLKSEL_OUT0 */
+				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */
+				 <&k3_clks 152 18>;	/* DPI1_EXT_CLKSEL_OUT0 */
+};
+
+&mcasp0 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcasp1 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcasp2 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcasp3 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcasp4 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcasp5 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcasp6 {
+	/* Brought out on RPi header */
+	status = "disabled";
+};
+
+&mcasp7 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcasp8 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcasp9 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcasp10 {
+	/* Unused */
+	status = "disabled";
+};
+
+&mcasp11 {
+	/* Brought out on M.2 E Key */
+	status = "disabled";
+};
+
+&pcie2_rc {
+	/* Unused */
+	status = "disabled";
+};
+
+&pcie2_ep {
+	/* Unused */
+	status = "disabled";
+};
+
+&pcie3_rc {
+	/* Unused */
+	status = "disabled";
+};
+
+&pcie3_ep {
+	/* Unused */
+	status = "disabled";
+};
+
+&mailbox0_cluster0 {
+	interrupts = <436>;
+
+	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster1 {
+	interrupts = <432>;
+
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster2 {
+	interrupts = <428>;
+
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster3 {
+	interrupts = <424>;
+
+	mbox_c66_0: mbox-c66-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_c66_1: mbox-c66-1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster4 {
+	interrupts = <420>;
+
+	mbox_c71_0: mbox-c71-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	status = "disabled";
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
+
+&mailbox0_cluster8 {
+	status = "disabled";
+};
+
+&mailbox0_cluster9 {
+	status = "disabled";
+};
+
+&mailbox0_cluster10 {
+	status = "disabled";
+};
+
+&mailbox0_cluster11 {
+	status = "disabled";
+};
+
+&mcu_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+			<&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+			<&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	memory-region = <&main_r5fss0_core0_dma_memory_region>,
+			<&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	memory-region = <&main_r5fss0_core1_dma_memory_region>,
+			<&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+	memory-region = <&main_r5fss1_core0_dma_memory_region>,
+			<&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+	memory-region = <&main_r5fss1_core1_dma_memory_region>,
+			<&main_r5fss1_core1_memory_region>;
+};
+
+&c66_0 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+	memory-region = <&c66_0_dma_memory_region>,
+			<&c66_0_memory_region>;
+};
+
+&c66_1 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+	memory-region = <&c66_1_dma_memory_region>,
+			<&c66_1_memory_region>;
+};
+
+&c71_0 {
+	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	memory-region = <&c71_0_dma_memory_region>,
+			<&c71_0_memory_region>;
+};
-- 
2.31.1

[PATCH V2 12/17] arm: dts: k3-j721e-r5-sk: Add initial R5 specific dts support for j721e-sk

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Add R5 specific dts for J721E-SK

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

Changes in V2:
* J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik 
to sk.
* Rename file from eaik to sk.

 arch/arm/dts/Makefile                   |   3 +-
 arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi |  31 ++
 arch/arm/dts/k3-j721e-r5-sk.dts         | 646 ++++++++++++++++++++++++
 3 files changed, 679 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
 create mode 100644 arch/arm/dts/k3-j721e-r5-sk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8918dfc48e..3581c925fc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1114,7 +1114,8 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
 			      k3-j721e-r5-common-proc-board.dtb \
 			      k3-j7200-common-proc-board.dtb \
 			      k3-j7200-r5-common-proc-board.dtb \
-			      k3-j721e-sk.dtb
+			      k3-j721e-sk.dtb \
+			      k3-j721e-r5-sk.dtb
 dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
 			      k3-am642-r5-evm.dtb \
 			      k3-am642-sk.dtb \
diff --git a/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
new file mode 100644
index 0000000000..71d16f193f
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-j721e-sk-u-boot.dtsi"
+
+/ {
+	chosen {
+		firmware-loader = &fs_loader0;
+	};
+
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a72_0;
+		remoteproc2 = &main_r5fss0_core0;
+		remoteproc3 = &main_r5fss0_core1;
+	};
+
+	fs_loader0: fs_loader@0 {
+		u-boot,dm-pre-reloc;
+		compatible = "u-boot,fs-loader";
+	};
+};
+
+&tps659412 {
+	esm: esm {
+		compatible = "ti,tps659413-esm";
+		u-boot,dm-spl;
+	};
+};
diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts
new file mode 100644
index 0000000000..abce864fff
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-r5-sk.dts
@@ -0,0 +1,646 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721e.dtsi"
+#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
+#include "k3-j721e-ddr.dtsi"
+
+/ {
+	model = "Texas Instruments J721E SK R5";
+
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a72_0;
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+		tick-timer = &timer1;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 4G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+		      <0x00000008 0x80000000 0x00000000 0x80000000>;
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa5000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa5100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_0_memory_region: c66-memory@a6100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c66_1_memory_region: c66-memory@a7100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_0_memory_region: c71-memory@a8100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		rtos_ipc_memory_region: ipc-memories@aa000000 {
+			reg = <0x00 0xaa000000 0x00 0x01c00000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+
+	a72_0: a72@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x0 0x00a90000 0x0 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 202 0>;
+		clocks = <&k3_clks 61 1>;
+		assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
+		assigned-clock-rates = <2000000000>, <200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		u-boot,dm-spl;
+	};
+
+	clk_200mhz: dummy_clock_200mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+		u-boot,dm-spl;
+	};
+
+	clk_19_2mhz: dummy_clock_19_2mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <19200000>;
+		u-boot,dm-spl;
+	};
+};
+
+&cbass_mcu_wakeup {
+	mcu_secproxy: secproxy@28380000 {
+		u-boot,dm-spl;
+		compatible = "ti,am654-secure-proxy";
+		reg = <0x0 0x2a380000 0x0 0x80000>,
+		      <0x0 0x2a400000 0x0 0x80000>,
+		      <0x0 0x2a480000 0x0 0x80000>;
+		reg-names = "rt", "scfg", "target_data";
+		#mbox-cells = <1>;
+	};
+
+	sysctrler: sysctrler {
+		u-boot,dm-spl;
+		compatible = "ti,am654-system-controller";
+		mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
+		mbox-names = "tx", "rx";
+	};
+
+	wkup_vtm0: wkup_vtm@42040000 {
+		compatible = "ti,am654-vtm", "ti,j721e-avs";
+		reg = <0x0 0x42040000 0x0 0x330>;
+		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+		#thermal-sensor-cells = <1>;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <3>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&mcu_secproxy 21>,
+				<&mcu_secproxy 23>;
+		u-boot,dm-spl;
+	};
+};
+
+&cbass_main {
+	main_esm: esm@700000 {
+		compatible = "ti,j721e-esm";
+		reg = <0x0 0x700000 0x0 0x1000>;
+		ti,esm-pins = <344>, <345>;
+		u-boot,dm-spl;
+	};
+};
+
+&dmsc {
+	mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+	mbox-names = "tx", "rx", "notify";
+	ti,host-id = <4>;
+	ti,secure-host;
+};
+
+&wkup_pmx0 {
+	wkup_uart0_pins_default: wkup_uart0_pins_default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
+			J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
+		>;
+	};
+
+	mcu_uart0_pins_default: mcu_uart0_pins_default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
+			J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
+			J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
+			J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
+		>;
+	};
+
+	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+		>;
+	};
+
+	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
+			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
+			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
+			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
+			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
+			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
+			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
+			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
+			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
+			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
+			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
+		>;
+	};
+
+	mcu_i2c0_pins_default: mcu_i2c0_pins_default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
+			J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
+		>;
+	};
+};
+
+&main_pmx0 {
+	main_uart0_pins_default: main_uart0_pins_default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
+			J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
+			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+		>;
+	};
+
+	main_usbss0_pins_default: main_usbss0_pins_default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+		>;
+	};
+
+	main_usbss1_pins_default: main-usbss1-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+		>;
+	};
+
+	main_mmc1_pins_default: main_mmc1_pins_default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+		>;
+	};
+
+	main_i2c0_pins_default: main-i2c0-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+		>;
+	};
+
+	main_i2c1_pins_default: main-i2c1-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+			J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+		>;
+	};
+
+	main_i2c2_pins_default: main-i2c2-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x158, PIN_INPUT_PULLUP, 2) /* (U23) RGMII5_TX_CTL.I2C2_SCL */
+			J721E_IOPAD(0x15c, PIN_INPUT_PULLUP, 2) /* (U26) RGMII5_RX_CTL.I2C2_SDA */
+		>;
+	};
+
+	main_i2c3_pins_default: main-i2c3-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+			J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+		>;
+	};
+
+	main_i2c5_pins_default: main-i2c5-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+			J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+		>;
+	};
+};
+
+&wkup_uart0 {
+	u-boot,dm-spl;
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+	status = "okay";
+};
+
+&mcu_uart0 {
+	/delete-property/ power-domains;
+	/delete-property/ clocks;
+	/delete-property/ clock-names;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_uart0_pins_default>;
+	status = "okay";
+	clock-frequency = <48000000>;
+};
+
+&main_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+	status = "okay";
+	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_sdhci0 {
+	status = "disabled";
+};
+
+&main_sdhci1 {
+	/delete-property/ power-domains;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	clock-names = "clk_xin";
+	clocks = <&clk_200mhz>;
+	ti,driver-strength-ohm = <50>;
+};
+
+&wkup_i2c0 {
+	u-boot,dm-spl;
+	tps659412: tps659412@48 {
+		reg = <0x48>;
+		compatible = "ti,tps659412";
+		u-boot,dm-spl;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wkup_i2c0_pins_default>;
+		clock-frequency = <400000>;
+
+		regulators: regulators {
+			u-boot,dm-spl;
+			/* 3 Phase Buck */
+			buck123_reg: buck123 {
+				/* VDD_CPU */
+				regulator-name = "buck123";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1250000>;
+				regulator-always-on;
+				regulator-boot-on;
+				u-boot,dm-spl;
+			};
+		};
+	};
+};
+
+&wkup_vtm0 {
+	vdd-supply-2 = <&buck123_reg>;
+	u-boot,dm-spl;
+};
+
+&usbss0 {
+	/delete-property/ power-domains;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clocks = <&clk_19_2mhz>;
+	clock-names = "usb2_refclk";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_usbss0_pins_default>;
+	ti,vbus-divider;
+};
+
+&usbss1 {
+	/delete-property/ power-domains;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clocks = <&clk_19_2mhz>;
+	clock-names = "usb2_refclk";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_usbss1_pins_default>;
+};
+
+&main_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+};
+
+&ospi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+	reg = <0x0 0x47040000 0x0 0x100>,
+	      <0x0 0x50000000 0x0 0x8000000>;
+
+	flash@0{
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+		spi-max-frequency = <25000000>;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <4>;
+		cdns,phy-mode;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+&ospi1 {
+	status = "disabled";
+};
+
+&mcu_ringacc {
+	ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+	ti,sci = <&dm_tifs>;
+};
+
+&mailbox0_cluster0 {
+	interrupts = <436>;
+
+	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster1 {
+	interrupts = <432>;
+
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster2 {
+	interrupts = <428>;
+
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster3 {
+	interrupts = <424>;
+
+	mbox_c66_0: mbox-c66-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_c66_1: mbox-c66-1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster4 {
+	interrupts = <420>;
+
+	mbox_c71_0: mbox-c71-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	status = "disabled";
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
+
+&mailbox0_cluster8 {
+	status = "disabled";
+};
+
+&mailbox0_cluster9 {
+	status = "disabled";
+};
+
+&mailbox0_cluster10 {
+	status = "disabled";
+};
+
+&mailbox0_cluster11 {
+	status = "disabled";
+};
+
+&mcu_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+			<&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+			<&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	memory-region = <&main_r5fss0_core0_dma_memory_region>,
+			<&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	memory-region = <&main_r5fss0_core1_dma_memory_region>,
+			<&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+	memory-region = <&main_r5fss1_core0_dma_memory_region>,
+			<&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+	memory-region = <&main_r5fss1_core1_dma_memory_region>,
+			<&main_r5fss1_core1_memory_region>;
+};
+
+&c66_0 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+	memory-region = <&c66_0_dma_memory_region>,
+			<&c66_0_memory_region>;
+};
+
+&c66_1 {
+	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+	memory-region = <&c66_1_dma_memory_region>,
+			<&c66_1_memory_region>;
+};
+
+&c71_0 {
+	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	memory-region = <&c71_0_dma_memory_region>,
+			<&c71_0_memory_region>;
+};
+
+/* EEPROM might be read before SYSFW is available */
+&wkup_i2c0 {
+	/delete-property/ power-domains;
+};
-- 
2.31.1

[PATCH V2 13/17] configs: j721e_evm_r5: Enable support for building multiple dtbs into FIT

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Enable configs for building multiple dtbs into a single fit image
and load the right dtb for next stage. This will help to use same
defconfig for both J721E EVM and SK boards.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

Changes in V2:
* J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik 
to sk.

 configs/j721e_evm_r5_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 1a58135da4..43bddfdb19 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -63,6 +63,9 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board k3-j721e-r5-sk"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
-- 
2.31.1

[PATCH V2 14/17] configs: j721e_evm_a72: Add SK dtb as part of DTB FIT

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Add k3-j721e-sk dtb along with other dtbs inside DTB FIT image.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

Changes in V2:
* J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik 
to sk.

 configs/j721e_evm_a72_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index df1b850f42..81bd5937be 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -75,6 +75,8 @@ CONFIG_CMD_UBI=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="k3-j721e-common-proc-board k3-j721e-sk"
+CONFIG_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_OVERWRITE=y
-- 
2.31.1

[PATCH V2 15/17] configs: j721e_evm_a72: Align OSPI partitions on erase block boundary

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

S28HS512T on TI SK has sector size of 256KB, so update OSPI partition
to align on 256KB sector size. Since the sector size for MT35XU512ABA
on EVM is 128KB, partitions will remain aligned for EVM.

Also, now since the sector size is 256KB ospi.env.backup will collide
with ospi.sysfw, so move ospi.env.backup to the padding space (0x7C0000)
before ospi.rootfs partition.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

No changes in V2.

 configs/j721e_evm_a72_defconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 81bd5937be..18a66cb051 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -18,7 +18,7 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x6A0000
+CONFIG_ENV_OFFSET_REDUND=0x7C0000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -69,7 +69,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),1m(ospi.sysfw),256k(ospi.env.backup),57344k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
 CONFIG_CMD_UBI=y
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
-- 
2.31.1

[PATCH V2 16/17] configs: j721e_evm: Store env in MMC FAT partition

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Enable defconfigs relevant for storing env on FAT partion of MMC.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

No changes in v2.

 configs/j721e_evm_a72_defconfig | 5 +++--
 configs/j721e_evm_r5_defconfig  | 1 +
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 18a66cb051..1de4d85336 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -80,10 +80,11 @@ CONFIG_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 43bddfdb19..38ac0b4296 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -67,6 +67,7 @@ CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board k3-j721e-r5-sk"
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
-- 
2.31.1

[PATCH V2 17/17] include: configs: Update env for selecting right dtb

[Sinthu Raja]

From: Sinthu Raja <sinthu.raja@ti.com>

Now that single defconfig can be used for booting J721E EVM and
SK, default device tree will not work for selecting dtb for
kernel. Update the findfdt env to select right dtb based on
board_name env variable.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---

No Changes in V2.

 include/configs/j721e_evm.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 10555d1a6c..f7e2962efd 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -67,6 +67,10 @@
 	"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"	\
 	"findfdt="							\
 		"setenv name_fdt ${default_device_tree};"		\
+		"if test $board_name = j721e; then "			\
+			"setenv name_fdt k3-j721e-common-proc-board.dtb; fi;" \
+		"if test $board_name = j721e-eaik || test $board_name = j721e-sk; then "		\
+			"setenv name_fdt k3-j721e-sk.dtb; fi;"	\
 		"setenv fdtfile ${name_fdt}\0"				\
 	"name_kern=Image\0"						\
 	"console=ttyS2,115200n8\0"					\
-- 
2.31.1

Re: [PATCH V2 10/17] arm: dts: k3-j721e-r5-common-proc-board: Do not use power-domains for I2C

[Tom Rini]

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On Tue, Nov 02, 2021 at 07:35:51PM +0530, Sinthu Raja wrote:
> From: Sinthu Raja <sinthu.raja@ti.com>
> 
> Board ID I2C EEPROM will be probed before SYSFW is available.
> So drop the power-domains property for wakup_i2c0 on which
> board ID EEPROM is connected.
> 
> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> ---
> 
> No Changes in V2.
> 
>  arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
> index 4b2362a5dd..88a69bf066 100644
> --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
> +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
> @@ -361,3 +361,8 @@
>  &mcu_udmap {
>  	ti,sci = <&dm_tifs>;
>  };
> +
> +/* EEPROM might be read before SYSFW is available */
> +&wkup_i2c0 {
> +	/delete-property/ power-domains;
> +};

Has this been queued up for linux-next or similar yet?

-- 
Tom

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Re: [PATCH V2 12/17] arm: dts: k3-j721e-r5-sk: Add initial R5 specific dts support for j721e-sk

[Tom Rini]

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On Tue, Nov 02, 2021 at 07:35:53PM +0530, Sinthu Raja wrote:
> From: Sinthu Raja <sinthu.raja@ti.com>
> 
> Add R5 specific dts for J721E-SK
> 
> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> ---
> 
> Changes in V2:
> * J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik 
> to sk.
> * Rename file from eaik to sk.
> 
>  arch/arm/dts/Makefile                   |   3 +-
>  arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi |  31 ++
>  arch/arm/dts/k3-j721e-r5-sk.dts         | 646 ++++++++++++++++++++++++
>  3 files changed, 679 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
>  create mode 100644 arch/arm/dts/k3-j721e-r5-sk.dts

Has arch/arm/dts/k3-j721e-r5-sk.dts been queued up in linux-next or
similar yet?

-- 
Tom

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Re: [PATCH V2 11/17] arm: dts: k3-j721e-sk: Add initial A72 specific dts support

[Tom Rini]

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On Tue, Nov 02, 2021 at 07:35:52PM +0530, Sinthu Raja wrote:

> From: Sinthu Raja <sinthu.raja@ti.com>
> 
> J721E Starter Kit (SK)[1] is a low cost, small form factor board designed
> for TI’s J721E SoC. TI’s J721E SoC comprises of dual core A72, high
> performance vision accelerators, video codec accelerators, latest C71x
> and C66x DSP, high bandwidth real-time IPs for capture and display, GPU,
> dedicated safety island and security accelerators. The SoC is power
> optimized to provide best in class performance for industrial and
> automotive applications.
> 
>     J721E SK supports the following interfaces:
>     * 4 GB LPDDR4 RAM
>     * x1 Gigabit Ethernet interface
>     * x1 USB 3.0 Type-C port
>     * x3 USB 3.0 Type-A ports
>     * x1 PCIe M.2 E Key
>     * x1 PCIe M.2 M Key
>     * 512 Mbit OSPI flash
>     * x2 CSI2 Camera interface (RPi and TI Camera connector)
>     * 40-pin Raspberry Pi GPIO header
> 
> Add A72 specific dts for J721E-SK.
> 
> [1] https://www.ti.com/tool/SK-TDA4VM
> 
> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> ---
> 
> Changes in V2:
> * J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik 
> to sk.
> * Rename file from eaik to sk.
> 
>  arch/arm/dts/Makefile                |   3 +-
>  arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 280 ++++++++++
>  arch/arm/dts/k3-j721e-sk.dts         | 791 +++++++++++++++++++++++++++
>  3 files changed, 1073 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/k3-j721e-sk-u-boot.dtsi
>  create mode 100644 arch/arm/dts/k3-j721e-sk.dts

Has arch/arm/dts/k3-j721e-sk.dts been queued up in linux-next or similar
yet?

-- 
Tom

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Re: [PATCH V2 01/17] common: make: Support show_board_info() as part of SPL build

[Tom Rini]

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On Tue, Nov 02, 2021 at 07:35:42PM +0530, Sinthu Raja wrote:

> From: Sinthu Raja <sinthu.raja@ti.com>
> 
> Enable support for show_board_info() in SPL build.
> 
> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>

OK, but why do we need this, and won't it cause every platform that has
this defined to now grow in size?

-- 
Tom

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Re: [PATCH V2 04/17] board: ti: j721e: Guard functions with right #ifdef to avoid build warnings

[Tom Rini]

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On Tue, Nov 02, 2021 at 07:35:45PM +0530, Sinthu Raja wrote:

> From: Sinthu Raja <sinthu.raja@ti.com>
> 
> board_late_init(), setup_board_eeprom_env() and setup_serial() is
> called only under CONFIG_BOARD_LATE_INIT, so guard these functions
> with the same.
> 
> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> ---
> 
> No chnages in V2.
> 
>  board/ti/j721e/evm.c | 4 ++++
>  1 file changed, 4 insertions(+)

We should probably re-order the code so that everything is under a
single #ifdef.

-- 
Tom

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Re: [PATCH V2 05/17] board: ti: j721e: Enable support for reading EEPROM at next alternate address

[Tom Rini]

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On Tue, Nov 02, 2021 at 07:35:46PM +0530, Sinthu Raja wrote:

> From: Sinthu Raja <sinthu.raja@ti.com>
> 
> J721E EVM has EEPROM populated at 0x50. J721E SK has EEPROM populated
> at next address 0x51 in order to be compatible with RBPi. So start
> looking for TI specific EEPROM at 0x50, if not found look for EEPROM at
> 0x51.

Minor, since I'm asking for other changes, please say "RPi" or
"Raspberry Pi" not "RBPi".

-- 
Tom

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Re: [PATCH V2 07/17] board: ti: j721e: Disable probing of daughtercards

[Tom Rini]

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On Tue, Nov 02, 2021 at 07:35:48PM +0530, Sinthu Raja wrote:
> From: Sinthu Raja <sinthu.raja@ti.com>
> 
> j721e-sk doesn't have any daughter cards, so disable daughter
> card probing inside board_late_init() and spl_board_init() for
> j721e-sk.
> 
> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> ---
> 
> Changes in V2:
> * J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik 
> to sk.
> 
>  board/ti/j721e/evm.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
> index 9d4609cfe9..cb491ad950 100644
> --- a/board/ti/j721e/evm.c
> +++ b/board/ti/j721e/evm.c
> @@ -434,7 +434,8 @@ int board_late_init(void)
>  		setup_serial();
>  
>  		/* Check for and probe any plugged-in daughtercards */
> -		probe_daughtercards();
> +		if (!board_is_j721e_sk())
> +			probe_daughtercards();

This should be a positive check for the board(s) which can even have
daughtercards.

-- 
Tom

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Re: [PATCH V2 09/17] arm: j721e: Add support for selecting DT based on EEPROM

[Tom Rini]

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On Tue, Nov 02, 2021 at 07:35:50PM +0530, Sinthu Raja wrote:

> From: Sinthu Raja <sinthu.raja@ti.com>
> 
> Enable support for selecting DTB from FIT within SPL based on the
> board name read from EEPROM. This will help to use single defconfig
> for both EVM and SK.
> 
> Also print FDT model name and board name read from EEPROM on SPL debug
> console. This is useful to verify that right dtb is loaded in each boot
> stage.
> 
> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> ---
> 
> No changes in V2.
> 
>  arch/arm/mach-k3/j721e_init.c | 62 +++++++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)

The EEPROM scheme is not K3-generic, but rather TI reference platform
specific, so this needs to be abstracted to exist and be called from
under board/ti/j721e/.. thanks.

-- 
Tom

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Re: [PATCH V2 10/17] arm: dts: k3-j721e-r5-common-proc-board: Do not use power-domains for I2C

[Sinthu Raja M]

Hi Tom,

On Mon, Nov 8, 2021 at 9:16 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Tue, Nov 02, 2021 at 07:35:51PM +0530, Sinthu Raja wrote:
> > From: Sinthu Raja <sinthu.raja@ti.com>
> >
> > Board ID I2C EEPROM will be probed before SYSFW is available.
> > So drop the power-domains property for wakup_i2c0 on which
> > board ID EEPROM is connected.
> >
> > Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> > ---
> >
> > No Changes in V2.
> >
> >  arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
> > index 4b2362a5dd..88a69bf066 100644
> > --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
> > +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
> > @@ -361,3 +361,8 @@
> >  &mcu_udmap {
> >       ti,sci = <&dm_tifs>;
> >  };
> > +
> > +/* EEPROM might be read before SYSFW is available */
> > +&wkup_i2c0 {
> > +     /delete-property/ power-domains;
> > +};
>
> Has this been queued up for linux-next or similar yet?
Yes, this is queued in linux-next [1].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/ti/k3-j721e-sk.dts

>
> --
> Tom



-- 
With Regards
Sinthu Raja

Re: [PATCH V2 12/17] arm: dts: k3-j721e-r5-sk: Add initial R5 specific dts support for j721e-sk

[Sinthu Raja M]

Hi Tom,

On Mon, Nov 8, 2021 at 9:17 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Tue, Nov 02, 2021 at 07:35:53PM +0530, Sinthu Raja wrote:
> > From: Sinthu Raja <sinthu.raja@ti.com>
> >
> > Add R5 specific dts for J721E-SK
> >
> > Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> > ---
> >
> > Changes in V2:
> > * J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik
> > to sk.
> > * Rename file from eaik to sk.
> >
> >  arch/arm/dts/Makefile                   |   3 +-
> >  arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi |  31 ++
> >  arch/arm/dts/k3-j721e-r5-sk.dts         | 646 ++++++++++++++++++++++++
> >  3 files changed, 679 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
> >  create mode 100644 arch/arm/dts/k3-j721e-r5-sk.dts
>
> Has arch/arm/dts/k3-j721e-r5-sk.dts been queued up in linux-next or
> similar yet?
Yes, this is queued in linux-next [1].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/ti/k3-j721e-sk.dts

>
> --
> Tom



-- 
With Regards
Sinthu Raja

Re: [PATCH V2 11/17] arm: dts: k3-j721e-sk: Add initial A72 specific dts support

[Sinthu Raja M]

Hi Tom,

On Mon, Nov 8, 2021 at 9:18 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Tue, Nov 02, 2021 at 07:35:52PM +0530, Sinthu Raja wrote:
>
> > From: Sinthu Raja <sinthu.raja@ti.com>
> >
> > J721E Starter Kit (SK)[1] is a low cost, small form factor board designed
> > for TI’s J721E SoC. TI’s J721E SoC comprises of dual core A72, high
> > performance vision accelerators, video codec accelerators, latest C71x
> > and C66x DSP, high bandwidth real-time IPs for capture and display, GPU,
> > dedicated safety island and security accelerators. The SoC is power
> > optimized to provide best in class performance for industrial and
> > automotive applications.
> >
> >     J721E SK supports the following interfaces:
> >     * 4 GB LPDDR4 RAM
> >     * x1 Gigabit Ethernet interface
> >     * x1 USB 3.0 Type-C port
> >     * x3 USB 3.0 Type-A ports
> >     * x1 PCIe M.2 E Key
> >     * x1 PCIe M.2 M Key
> >     * 512 Mbit OSPI flash
> >     * x2 CSI2 Camera interface (RPi and TI Camera connector)
> >     * 40-pin Raspberry Pi GPIO header
> >
> > Add A72 specific dts for J721E-SK.
> >
> > [1] https://www.ti.com/tool/SK-TDA4VM
> >
> > Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> > ---
> >
> > Changes in V2:
> > * J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik
> > to sk.
> > * Rename file from eaik to sk.
> >
> >  arch/arm/dts/Makefile                |   3 +-
> >  arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 280 ++++++++++
> >  arch/arm/dts/k3-j721e-sk.dts         | 791 +++++++++++++++++++++++++++
> >  3 files changed, 1073 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/arm/dts/k3-j721e-sk-u-boot.dtsi
> >  create mode 100644 arch/arm/dts/k3-j721e-sk.dts
>
> Has arch/arm/dts/k3-j721e-sk.dts been queued up in linux-next or similar
> yet?

Yes, this is queued in linux-next [1].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/ti/k3-j721e-sk.dts

Regards,
Sinthu Raja.
>
> --
> Tom



-- 
With Regards
Sinthu Raja

Re: [PATCH V2 07/17] board: ti: j721e: Disable probing of daughtercards

[Sinthu Raja M]

Hi Tom,

On Mon, Nov 8, 2021 at 9:22 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Tue, Nov 02, 2021 at 07:35:48PM +0530, Sinthu Raja wrote:
> > From: Sinthu Raja <sinthu.raja@ti.com>
> >
> > j721e-sk doesn't have any daughter cards, so disable daughter
> > card probing inside board_late_init() and spl_board_init() for
> > j721e-sk.
> >
> > Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> > ---
> >
> > Changes in V2:
> > * J721E EAIK board name is changed to J721E SK, rename all occurrences of eaik
> > to sk.
> >
> >  board/ti/j721e/evm.c | 9 ++++++---
> >  1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
> > index 9d4609cfe9..cb491ad950 100644
> > --- a/board/ti/j721e/evm.c
> > +++ b/board/ti/j721e/evm.c
> > @@ -434,7 +434,8 @@ int board_late_init(void)
> >               setup_serial();
> >
> >               /* Check for and probe any plugged-in daughtercards */
> > -             probe_daughtercards();
> > +             if (!board_is_j721e_sk())
> > +                     probe_daughtercards();
>
> This should be a positive check for the board(s) which can even have
> daughtercards.

Agreed, will update as positive check.

Regards
Sinthu Raja
>
> --
> Tom



-- 
With Regards
Sinthu Raja

Re: [PATCH V2 09/17] arm: j721e: Add support for selecting DT based on EEPROM

[Sinthu Raja M]

Hi Tom,

On Mon, Nov 8, 2021 at 9:23 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Tue, Nov 02, 2021 at 07:35:50PM +0530, Sinthu Raja wrote:
>
> > From: Sinthu Raja <sinthu.raja@ti.com>
> >
> > Enable support for selecting DTB from FIT within SPL based on the
> > board name read from EEPROM. This will help to use single defconfig
> > for both EVM and SK.
> >
> > Also print FDT model name and board name read from EEPROM on SPL debug
> > console. This is useful to verify that right dtb is loaded in each boot
> > stage.
> >
> > Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> > ---
> >
> > No changes in V2.
> >
> >  arch/arm/mach-k3/j721e_init.c | 62 +++++++++++++++++++++++++++++++++++
> >  1 file changed, 62 insertions(+)
>
> The EEPROM scheme is not K3-generic, but rather TI reference platform
> specific, so this needs to be abstracted to exist and be called from
> under board/ti/j721e/.. thanks.
>
I guess the commit description is a little misleading. It just calls
the board_detect function which is existed under the board/ti/j721e.
Printing of board info is not required here which can be removed.

Regards,
Sinthu Raja.
> --
> Tom



-- 
With Regards
Sinthu Raja

Re: [PATCH V2 10/17] arm: dts: k3-j721e-r5-common-proc-board: Do not use power-domains for I2C

[Tom Rini]

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On Fri, Nov 12, 2021 at 05:28:07PM +0530, Sinthu Raja M wrote:
> Hi Tom,
> 
> On Mon, Nov 8, 2021 at 9:16 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Tue, Nov 02, 2021 at 07:35:51PM +0530, Sinthu Raja wrote:
> > > From: Sinthu Raja <sinthu.raja@ti.com>
> > >
> > > Board ID I2C EEPROM will be probed before SYSFW is available.
> > > So drop the power-domains property for wakup_i2c0 on which
> > > board ID EEPROM is connected.
> > >
> > > Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> > > ---
> > >
> > > No Changes in V2.
> > >
> > >  arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 5 +++++
> > >  1 file changed, 5 insertions(+)
> > >
> > > diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
> > > index 4b2362a5dd..88a69bf066 100644
> > > --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
> > > +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
> > > @@ -361,3 +361,8 @@
> > >  &mcu_udmap {
> > >       ti,sci = <&dm_tifs>;
> > >  };
> > > +
> > > +/* EEPROM might be read before SYSFW is available */
> > > +&wkup_i2c0 {
> > > +     /delete-property/ power-domains;
> > > +};
> >
> > Has this been queued up for linux-next or similar yet?
> Yes, this is queued in linux-next [1].
> 
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/ti/k3-j721e-sk.dts

OK, since all of the dts stuff is queued up, that's good and important
as it will also be re-synced later directly from kernel.org so anything
not there must be in -u-boot.dtsi files and with very good reasoning.

-- 
Tom

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Re: [PATCH V2 09/17] arm: j721e: Add support for selecting DT based on EEPROM

[Tom Rini]

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On Fri, Nov 12, 2021 at 07:02:49PM +0530, Sinthu Raja M wrote:
> Hi Tom,
> 
> On Mon, Nov 8, 2021 at 9:23 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Tue, Nov 02, 2021 at 07:35:50PM +0530, Sinthu Raja wrote:
> >
> > > From: Sinthu Raja <sinthu.raja@ti.com>
> > >
> > > Enable support for selecting DTB from FIT within SPL based on the
> > > board name read from EEPROM. This will help to use single defconfig
> > > for both EVM and SK.
> > >
> > > Also print FDT model name and board name read from EEPROM on SPL debug
> > > console. This is useful to verify that right dtb is loaded in each boot
> > > stage.
> > >
> > > Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> > > ---
> > >
> > > No changes in V2.
> > >
> > >  arch/arm/mach-k3/j721e_init.c | 62 +++++++++++++++++++++++++++++++++++
> > >  1 file changed, 62 insertions(+)
> >
> > The EEPROM scheme is not K3-generic, but rather TI reference platform
> > specific, so this needs to be abstracted to exist and be called from
> > under board/ti/j721e/.. thanks.
>
> I guess the commit description is a little misleading. It just calls
> the board_detect function which is existed under the board/ti/j721e.
> Printing of board info is not required here which can be removed.

Right, but board/ti/j721e/ code is not relevant to non-TI reference
platforms.  The code under arch/arm/mach-k3/ needs to be SoC centric,
and the TI reference platforms and their shared EEPROM stuff needs to
be under board/ti/.  It also needs to be as clear as possible how to
remove it as custom platforms don't usually copy this EEPROM scheme and
this adds confusion on their part.

-- 
Tom

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