* [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-08 21:27 ` Zhi Wang
0 siblings, 0 replies; 35+ messages in thread
From: Zhi Wang @ 2021-11-08 21:27 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, zhenyuw, zhi.a.wang,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
Cc: Zhi Wang
From: Zhi Wang <zhi.wang.linux@gmail.com>
To support the new mdev interfaces and the re-factor patches from
Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
MMIO snapshot still needs to be saved in i915 so that the inital clean HW
state can be used for the further vGPU. Seperate the tracked MMIO table
from GVT-g, so that GVT-g and i915 can both use it.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
---
drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
drivers/gpu/drm/i915/gvt/reg.h | 6 +
drivers/gpu/drm/i915/intel_gvt.c | 11 +
4 files changed, 1592 insertions(+), 1534 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index cde0a477fb49..6a08d362bf66 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -41,13 +41,6 @@
#include "i915_pvinfo.h"
#include "display/intel_display_types.h"
-/* XXX FIXME i915 has changed PP_XXX definition */
-#define PCH_PP_STATUS _MMIO(0xc7200)
-#define PCH_PP_CONTROL _MMIO(0xc7204)
-#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
-#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
-#define PCH_PP_DIVISOR _MMIO(0xc7210)
-
unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
{
struct drm_i915_private *i915 = gvt->gt->i915;
@@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
return 0;
}
-#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
- ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
- f, s, am, rm, d, r, w); \
- if (ret) \
- return ret; \
-} while (0)
-
-#define MMIO_D(reg, d) \
- MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
-
-#define MMIO_DH(reg, d, r, w) \
- MMIO_F(reg, 4, 0, 0, 0, d, r, w)
-
-#define MMIO_DFH(reg, d, f, r, w) \
- MMIO_F(reg, 4, f, 0, 0, d, r, w)
-
-#define MMIO_GM(reg, d, r, w) \
- MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
-
-#define MMIO_GM_RDR(reg, d, r, w) \
- MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
-
-#define MMIO_RO(reg, d, f, rm, r, w) \
- MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
-
-#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
- MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
- MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
- MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
- MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
- if (HAS_ENGINE(gvt->gt, VCS1)) \
- MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
-} while (0)
-
-#define MMIO_RING_D(prefix, d) \
- MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
-
-#define MMIO_RING_DFH(prefix, d, f, r, w) \
- MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
-
-#define MMIO_RING_GM(prefix, d, r, w) \
- MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
-
-#define MMIO_RING_GM_RDR(prefix, d, r, w) \
- MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
-
-#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
- MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
-
-static int init_generic_mmio_info(struct intel_gvt *gvt)
-{
- struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
-
- MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
- intel_vgpu_reg_imr_handler);
-
- MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(SDEISR, D_ALL);
-
- MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
-
-
- MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
- gamw_echo_dev_rw_ia_write);
-
- MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
- MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
- MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
-
-#define RING_REG(base) _MMIO((base) + 0x28)
- MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x134)
- MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x6c)
- MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
-#undef RING_REG
- MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
-
- MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
- MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
- MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
- MMIO_D(GEN7_CXT_SIZE, D_ALL);
-
- MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
- MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
- MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
- MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
- MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
-
- /* RING MODE */
-#define RING_REG(base) _MMIO((base) + 0x29c)
- MMIO_RING_DFH(RING_REG, D_ALL,
- F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
- ring_mode_mmio_write);
-#undef RING_REG
-
- MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
- mmio_read_from_hw, NULL);
- MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
- mmio_read_from_hw, NULL);
-
- MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
- F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
-
- /* display */
- MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_D(_MMIO(0x602a0), D_ALL);
-
- MMIO_D(_MMIO(0x65050), D_ALL);
- MMIO_D(_MMIO(0x650b4), D_ALL);
-
- MMIO_D(_MMIO(0xc4040), D_ALL);
- MMIO_D(DERRMR, D_ALL);
-
- MMIO_D(PIPEDSL(PIPE_A), D_ALL);
- MMIO_D(PIPEDSL(PIPE_B), D_ALL);
- MMIO_D(PIPEDSL(PIPE_C), D_ALL);
- MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
-
- MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
- MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
- MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
- MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
-
- MMIO_D(PIPESTAT(PIPE_A), D_ALL);
- MMIO_D(PIPESTAT(PIPE_B), D_ALL);
- MMIO_D(PIPESTAT(PIPE_C), D_ALL);
- MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
-
- MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
- MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
- MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
- MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
-
- MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
- MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
- MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
- MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
-
- MMIO_D(CURCNTR(PIPE_A), D_ALL);
- MMIO_D(CURCNTR(PIPE_B), D_ALL);
- MMIO_D(CURCNTR(PIPE_C), D_ALL);
-
- MMIO_D(CURPOS(PIPE_A), D_ALL);
- MMIO_D(CURPOS(PIPE_B), D_ALL);
- MMIO_D(CURPOS(PIPE_C), D_ALL);
-
- MMIO_D(CURBASE(PIPE_A), D_ALL);
- MMIO_D(CURBASE(PIPE_B), D_ALL);
- MMIO_D(CURBASE(PIPE_C), D_ALL);
-
- MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
- MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
- MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
-
- MMIO_D(_MMIO(0x700ac), D_ALL);
- MMIO_D(_MMIO(0x710ac), D_ALL);
- MMIO_D(_MMIO(0x720ac), D_ALL);
-
- MMIO_D(_MMIO(0x70090), D_ALL);
- MMIO_D(_MMIO(0x70094), D_ALL);
- MMIO_D(_MMIO(0x70098), D_ALL);
- MMIO_D(_MMIO(0x7009c), D_ALL);
-
- MMIO_D(DSPCNTR(PIPE_A), D_ALL);
- MMIO_D(DSPADDR(PIPE_A), D_ALL);
- MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
- MMIO_D(DSPPOS(PIPE_A), D_ALL);
- MMIO_D(DSPSIZE(PIPE_A), D_ALL);
- MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
- MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
- MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
- MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(DSPCNTR(PIPE_B), D_ALL);
- MMIO_D(DSPADDR(PIPE_B), D_ALL);
- MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
- MMIO_D(DSPPOS(PIPE_B), D_ALL);
- MMIO_D(DSPSIZE(PIPE_B), D_ALL);
- MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
- MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
- MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
- MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(DSPCNTR(PIPE_C), D_ALL);
- MMIO_D(DSPADDR(PIPE_C), D_ALL);
- MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
- MMIO_D(DSPPOS(PIPE_C), D_ALL);
- MMIO_D(DSPSIZE(PIPE_C), D_ALL);
- MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
- MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
- MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
- MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(SPRCTL(PIPE_A), D_ALL);
- MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
- MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
- MMIO_D(SPRPOS(PIPE_A), D_ALL);
- MMIO_D(SPRSIZE(PIPE_A), D_ALL);
- MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
- MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
- MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
- MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
- MMIO_D(SPROFFSET(PIPE_A), D_ALL);
- MMIO_D(SPRSCALE(PIPE_A), D_ALL);
- MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
- MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(SPRCTL(PIPE_B), D_ALL);
- MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
- MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
- MMIO_D(SPRPOS(PIPE_B), D_ALL);
- MMIO_D(SPRSIZE(PIPE_B), D_ALL);
- MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
- MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
- MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
- MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
- MMIO_D(SPROFFSET(PIPE_B), D_ALL);
- MMIO_D(SPRSCALE(PIPE_B), D_ALL);
- MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
- MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(SPRCTL(PIPE_C), D_ALL);
- MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
- MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
- MMIO_D(SPRPOS(PIPE_C), D_ALL);
- MMIO_D(SPRSIZE(PIPE_C), D_ALL);
- MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
- MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
- MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
- MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
- MMIO_D(SPROFFSET(PIPE_C), D_ALL);
- MMIO_D(SPRSCALE(PIPE_C), D_ALL);
- MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
- MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
- MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
- MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
- MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
- MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
- MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
- MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
- MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
- MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
-
- MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
- MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
- MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
- MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
- MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
- MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
- MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
- MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
- MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
-
- MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
- MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
- MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
- MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
- MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
- MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
- MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
- MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
- MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
-
- MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
- MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
- MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
- MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
- MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
- MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
- MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
- MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
-
- MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
-
- MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
-
- MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
-
- MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
-
- MMIO_D(PF_CTL(PIPE_A), D_ALL);
- MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
- MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
- MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
- MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
-
- MMIO_D(PF_CTL(PIPE_B), D_ALL);
- MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
- MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
- MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
- MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
-
- MMIO_D(PF_CTL(PIPE_C), D_ALL);
- MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
- MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
- MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
- MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
-
- MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
- MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
- MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
- MMIO_D(WM1_LP_ILK, D_ALL);
- MMIO_D(WM2_LP_ILK, D_ALL);
- MMIO_D(WM3_LP_ILK, D_ALL);
- MMIO_D(WM1S_LP_ILK, D_ALL);
- MMIO_D(WM2S_LP_IVB, D_ALL);
- MMIO_D(WM3S_LP_IVB, D_ALL);
-
- MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
- MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
- MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
- MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
-
- MMIO_D(_MMIO(0x48268), D_ALL);
-
- MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
- gmbus_mmio_write);
- MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
- dp_aux_ch_ctl_mmio_write);
- MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
- dp_aux_ch_ctl_mmio_write);
- MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
- dp_aux_ch_ctl_mmio_write);
-
- MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
-
- MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
- MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
-
- MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
- MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
- MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
- MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
- MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
- MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
- MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
- MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
- MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
-
- MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
-
- MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
-
- MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
-
- MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
- MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
- MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
-
- MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
- MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
- MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
-
- MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
- MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
- MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
-
- MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
- MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
- MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
-
- MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
- MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
- MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
- MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
- MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
- MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
-
- MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
- MMIO_D(PCH_PP_DIVISOR, D_ALL);
- MMIO_D(PCH_PP_STATUS, D_ALL);
- MMIO_D(PCH_LVDS, D_ALL);
- MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
- MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
- MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
- MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
- MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
- MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
- MMIO_D(PCH_DREF_CONTROL, D_ALL);
- MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
- MMIO_D(PCH_DPLL_SEL, D_ALL);
-
- MMIO_D(_MMIO(0x61208), D_ALL);
- MMIO_D(_MMIO(0x6120c), D_ALL);
- MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
- MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
-
- MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
- MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
- MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
- MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
- MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
- MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
-
- MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
- PORTA_HOTPLUG_STATUS_MASK
- | PORTB_HOTPLUG_STATUS_MASK
- | PORTC_HOTPLUG_STATUS_MASK
- | PORTD_HOTPLUG_STATUS_MASK,
- NULL, NULL);
-
- MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
- MMIO_D(FUSE_STRAP, D_ALL);
- MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
-
- MMIO_D(DISP_ARB_CTL, D_ALL);
- MMIO_D(DISP_ARB_CTL2, D_ALL);
-
- MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
- MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
- MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
-
- MMIO_D(SOUTH_CHICKEN1, D_ALL);
- MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
- MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
- MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
- MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
- MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
- MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
-
- MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
- MMIO_D(ILK_DPFC_CONTROL, D_ALL);
- MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
- MMIO_D(ILK_DPFC_STATUS, D_ALL);
- MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
- MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
- MMIO_D(ILK_FBC_RT_BASE, D_ALL);
-
- MMIO_D(IPS_CTL, D_ALL);
-
- MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
-
- MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
-
- MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
-
- MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
- MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
- MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
- MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
- MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
- MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
- MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(_MMIO(0x60110), D_ALL);
- MMIO_D(_MMIO(0x61110), D_ALL);
- MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
-
- MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
- MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
- MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
- MMIO_D(SPLL_CTL, D_ALL);
- MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
- MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
- MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
- MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
- MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
- MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
- MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
- MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
- MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
- MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
-
- MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
- MMIO_D(_MMIO(0x46508), D_ALL);
-
- MMIO_D(_MMIO(0x49080), D_ALL);
- MMIO_D(_MMIO(0x49180), D_ALL);
- MMIO_D(_MMIO(0x49280), D_ALL);
-
- MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
- MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
- MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
-
- MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
- MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
- MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
-
- MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
- MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
- MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
-
- MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
- MMIO_D(SBI_ADDR, D_ALL);
- MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
- MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
- MMIO_D(PIXCLK_GATE, D_ALL);
-
- MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
- dp_aux_ch_ctl_mmio_write);
-
- MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
-
- MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
- MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
- MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
- MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
- MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
-
- MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
- MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
- MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
- MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
- MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
-
- MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
- MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
- MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
-
- MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
- MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
- MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
- MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
-
- MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
- MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
- MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
- MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
-
- MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
- MMIO_D(FORCEWAKE_ACK, D_ALL);
- MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
- MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
- MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
- MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
- MMIO_D(ECOBUS, D_ALL);
- MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
- MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
- MMIO_D(GEN6_RPNSWREQ, D_ALL);
- MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
- MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
- MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
- MMIO_D(GEN6_RPSTAT1, D_ALL);
- MMIO_D(GEN6_RP_CONTROL, D_ALL);
- MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
- MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
- MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
- MMIO_D(GEN6_RP_CUR_UP, D_ALL);
- MMIO_D(GEN6_RP_PREV_UP, D_ALL);
- MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
- MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
- MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
- MMIO_D(GEN6_RP_UP_EI, D_ALL);
- MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
- MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
- MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
- MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
- MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
- MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
- MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
- MMIO_D(GEN6_RC_SLEEP, D_ALL);
- MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
- MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
- MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
- MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
- MMIO_D(GEN6_PMINTRMSK, D_ALL);
- MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
-
- MMIO_D(RSTDBYCTL, D_ALL);
-
- MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
- MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
- MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
-
- MMIO_D(TILECTL, D_ALL);
-
- MMIO_D(GEN6_UCGCTL1, D_ALL);
- MMIO_D(GEN6_UCGCTL2, D_ALL);
-
- MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(GEN6_PCODE_DATA, D_ALL);
- MMIO_D(_MMIO(0x13812c), D_ALL);
- MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
- MMIO_D(HSW_EDRAM_CAP, D_ALL);
- MMIO_D(HSW_IDICR, D_ALL);
- MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
-
- MMIO_D(_MMIO(0x3c), D_ALL);
- MMIO_D(_MMIO(0x860), D_ALL);
- MMIO_D(ECOSKPD, D_ALL);
- MMIO_D(_MMIO(0x121d0), D_ALL);
- MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
- MMIO_D(_MMIO(0x41d0), D_ALL);
- MMIO_D(GAC_ECO_BITS, D_ALL);
- MMIO_D(_MMIO(0x6200), D_ALL);
- MMIO_D(_MMIO(0x6204), D_ALL);
- MMIO_D(_MMIO(0x6208), D_ALL);
- MMIO_D(_MMIO(0x7118), D_ALL);
- MMIO_D(_MMIO(0x7180), D_ALL);
- MMIO_D(_MMIO(0x7408), D_ALL);
- MMIO_D(_MMIO(0x7c00), D_ALL);
- MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
- MMIO_D(_MMIO(0x911c), D_ALL);
- MMIO_D(_MMIO(0x9120), D_ALL);
- MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_D(GAB_CTL, D_ALL);
- MMIO_D(_MMIO(0x48800), D_ALL);
- MMIO_D(_MMIO(0xce044), D_ALL);
- MMIO_D(_MMIO(0xe6500), D_ALL);
- MMIO_D(_MMIO(0xe6504), D_ALL);
- MMIO_D(_MMIO(0xe6600), D_ALL);
- MMIO_D(_MMIO(0xe6604), D_ALL);
- MMIO_D(_MMIO(0xe6700), D_ALL);
- MMIO_D(_MMIO(0xe6704), D_ALL);
- MMIO_D(_MMIO(0xe6800), D_ALL);
- MMIO_D(_MMIO(0xe6804), D_ALL);
- MMIO_D(PCH_GMBUS4, D_ALL);
- MMIO_D(PCH_GMBUS5, D_ALL);
-
- MMIO_D(_MMIO(0x902c), D_ALL);
- MMIO_D(_MMIO(0xec008), D_ALL);
- MMIO_D(_MMIO(0xec00c), D_ALL);
- MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
- MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
- MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
- MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
- MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
- MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
- MMIO_D(_MMIO(0xec408), D_ALL);
- MMIO_D(_MMIO(0xec40c), D_ALL);
- MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
- MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
- MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
- MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
- MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
- MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
- MMIO_D(_MMIO(0xfc810), D_ALL);
- MMIO_D(_MMIO(0xfc81c), D_ALL);
- MMIO_D(_MMIO(0xfc828), D_ALL);
- MMIO_D(_MMIO(0xfc834), D_ALL);
- MMIO_D(_MMIO(0xfcc00), D_ALL);
- MMIO_D(_MMIO(0xfcc0c), D_ALL);
- MMIO_D(_MMIO(0xfcc18), D_ALL);
- MMIO_D(_MMIO(0xfcc24), D_ALL);
- MMIO_D(_MMIO(0xfd000), D_ALL);
- MMIO_D(_MMIO(0xfd00c), D_ALL);
- MMIO_D(_MMIO(0xfd018), D_ALL);
- MMIO_D(_MMIO(0xfd024), D_ALL);
- MMIO_D(_MMIO(0xfd034), D_ALL);
-
- MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
- MMIO_D(_MMIO(0x2054), D_ALL);
- MMIO_D(_MMIO(0x12054), D_ALL);
- MMIO_D(_MMIO(0x22054), D_ALL);
- MMIO_D(_MMIO(0x1a054), D_ALL);
-
- MMIO_D(_MMIO(0x44070), D_ALL);
- MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
- MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
- MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
- MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
- MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
- MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
- MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
- MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
- MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
- MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
- MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
- MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
-
- return 0;
-}
-
-static int init_bdw_mmio_info(struct intel_gvt *gvt)
-{
- struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
-
- MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
-
- MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
-
- MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
-
- MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
-
- MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
- intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
- intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
- intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
-
- MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
- intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
- intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
- intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
-
- MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
- intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
- intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
- intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
-
- MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
-
- MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
-
- MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
-
- MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
- intel_vgpu_reg_master_irq_handler);
-
- MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
- mmio_read_from_hw, NULL);
-
-#define RING_REG(base) _MMIO((base) + 0xd0)
- MMIO_RING_F(RING_REG, 4, F_RO, 0,
- ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
- ring_reset_ctl_write);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x230)
- MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x234)
- MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
- NULL, NULL);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x244)
- MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x370)
- MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x3a0)
- MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
-#undef RING_REG
-
- MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
- MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
- MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
- MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
- MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
- MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
- MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
-
- MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
-
- MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
- MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
-
- MMIO_D(GAMTARBMODE, D_BDW_PLUS);
-
-#define RING_REG(base) _MMIO((base) + 0x270)
- MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
-#undef RING_REG
-
- MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
-
- MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
-
- MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
- MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
- MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
-
- MMIO_D(WM_MISC, D_BDW);
- MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
-
- MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
- MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
- MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
-
- MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
-
- MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
- MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
- MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
-
- MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
- MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_D(_MMIO(0xb110), D_BDW);
- MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
-
- MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
- D_BDW_PLUS, NULL, force_nonpriv_write);
-
- MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
- MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
-
- MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
-
- MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
-
- MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
-
- MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
- MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
-
- MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- return 0;
-}
-
-static int init_skl_mmio_info(struct intel_gvt *gvt)
-{
- struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
-
- MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
- MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
- MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
- MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
- MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
- MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
-
- MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
- dp_aux_ch_ctl_mmio_write);
- MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
- dp_aux_ch_ctl_mmio_write);
- MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
- dp_aux_ch_ctl_mmio_write);
-
- MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
- MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
-
- MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
-
- MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
- MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
- MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
- MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
- MMIO_D(DC_STATE_EN, D_SKL_PLUS);
- MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
- MMIO_D(CDCLK_CTL, D_SKL_PLUS);
- MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
- MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
- MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
- MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
- MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
- MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
- MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
- MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
- MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
- MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
- MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
-
- MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
-
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
-
- MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
-
- MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
-
- MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
-
- MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
-
- MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
-
- MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
- MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
- MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
-
- MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
- MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
- MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
-
- MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_D(SKL_DFSM, D_SKL_PLUS);
- MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
-
- MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
- NULL, NULL);
- MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
- NULL, NULL);
-
- MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
- MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
- MMIO_D(RC6_LOCATION, D_SKL_PLUS);
- MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
- F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
-
- /* TRTT */
- MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
- NULL, gen9_trtte_write);
- MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
- NULL, gen9_trtt_chicken_write);
-
- MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
-
- MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
-
- MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
- MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
-
- MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
- MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
- MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
- MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
- MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
- MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
- MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
- MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
- MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
- MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
-
- MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
- MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
- MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
-
- MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
-
- MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
-#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
- MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, csfe_chicken1_mmio_write);
-#undef CSFE_CHICKEN1_REG
- MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
-
- MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
- MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
-
- return 0;
-}
-
-static int init_bxt_mmio_info(struct intel_gvt *gvt)
-{
- struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
-
- MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
-
- MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
- MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
- MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
- MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
- MMIO_D(ERROR_GEN6, D_BXT);
- MMIO_D(DONE_REG, D_BXT);
- MMIO_D(EIR, D_BXT);
- MMIO_D(PGTBL_ER, D_BXT);
- MMIO_D(_MMIO(0x4194), D_BXT);
- MMIO_D(_MMIO(0x4294), D_BXT);
- MMIO_D(_MMIO(0x4494), D_BXT);
-
- MMIO_RING_D(RING_PSMI_CTL, D_BXT);
- MMIO_RING_D(RING_DMA_FADD, D_BXT);
- MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
- MMIO_RING_D(RING_IPEHR, D_BXT);
- MMIO_RING_D(RING_INSTPS, D_BXT);
- MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
- MMIO_RING_D(RING_BBSTATE, D_BXT);
- MMIO_RING_D(RING_IPEIR, D_BXT);
-
- MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
-
- MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
- MMIO_D(BXT_RP_STATE_CAP, D_BXT);
- MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
- NULL, bxt_phy_ctl_family_write);
- MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
- NULL, bxt_phy_ctl_family_write);
- MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
- MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
- MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
- MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
- NULL, bxt_port_pll_enable_write);
- MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
- NULL, bxt_port_pll_enable_write);
- MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
- bxt_port_pll_enable_write);
-
- MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
-
- MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
-
- MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
- NULL, bxt_pcs_dw12_grp_write);
- MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
- bxt_port_tx_dw3_read, NULL);
- MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
-
- MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
- NULL, bxt_pcs_dw12_grp_write);
- MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
- bxt_port_tx_dw3_read, NULL);
- MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
-
- MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
- NULL, bxt_pcs_dw12_grp_write);
- MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
- bxt_port_tx_dw3_read, NULL);
- MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
-
- MMIO_D(BXT_DE_PLL_CTL, D_BXT);
- MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
- MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
- MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
-
- MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
- MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
-
- MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
- MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
- MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
-
- MMIO_D(RC6_CTX_BASE, D_BXT);
-
- MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
- MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
- MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
- MMIO_D(GEN6_GFXPAUSE, D_BXT);
- MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
- MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
- 0, 0, D_BXT, NULL, NULL);
- MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
- 0, 0, D_BXT, NULL, NULL);
- MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
- 0, 0, D_BXT, NULL, NULL);
- MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
- 0, 0, D_BXT, NULL, NULL);
-
- MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
-
- return 0;
-}
+#include "mmio_table.h"
static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
unsigned int offset)
@@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
{
struct intel_gvt_device_info *info = &gvt->device_info;
- struct drm_i915_private *i915 = gvt->gt->i915;
int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
int ret;
@@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
if (!gvt->mmio.mmio_attribute)
return -ENOMEM;
- ret = init_generic_mmio_info(gvt);
- if (ret)
- goto err;
-
- if (IS_BROADWELL(i915)) {
- ret = init_bdw_mmio_info(gvt);
- if (ret)
- goto err;
- } else if (IS_SKYLAKE(i915) ||
- IS_KABYLAKE(i915) ||
- IS_COFFEELAKE(i915) ||
- IS_COMETLAKE(i915)) {
- ret = init_bdw_mmio_info(gvt);
- if (ret)
- goto err;
- ret = init_skl_mmio_info(gvt);
- if (ret)
- goto err;
- } else if (IS_BROXTON(i915)) {
- ret = init_bdw_mmio_info(gvt);
- if (ret)
- goto err;
- ret = init_skl_mmio_info(gvt);
- if (ret)
- goto err;
- ret = init_bxt_mmio_info(gvt);
- if (ret)
- goto err;
+ ret = intel_gvt_init_mmio_info(gvt);
+ if (ret) {
+ intel_gvt_clean_mmio_info(gvt);
+ return ret;
}
gvt->mmio.mmio_block = mmio_blocks;
gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
return 0;
-err:
- intel_gvt_clean_mmio_info(gvt);
- return ret;
}
/**
diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
new file mode 100644
index 000000000000..39a4cb59695a
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
@@ -0,0 +1,1570 @@
+/*
+ * Copyright © 2021 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _GVT_MMIO_TABLE_H_
+#define _GVT_MMIO_TABLE_H_
+
+#ifdef GENERATE_MMIO_TABLE_IN_I915
+#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
+ ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
+ if (ret) \
+ return ret; \
+} while (0)
+#else
+#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
+ ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
+ f, s, am, rm, d, r, w); \
+ if (ret) \
+ return ret; \
+} while (0)
+#endif
+
+#define MMIO_D(reg, d) \
+ MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
+
+#define MMIO_DH(reg, d, r, w) \
+ MMIO_F(reg, 4, 0, 0, 0, d, r, w)
+
+#define MMIO_DFH(reg, d, f, r, w) \
+ MMIO_F(reg, 4, f, 0, 0, d, r, w)
+
+#define MMIO_GM(reg, d, r, w) \
+ MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
+
+#define MMIO_GM_RDR(reg, d, r, w) \
+ MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
+
+#define MMIO_RO(reg, d, f, rm, r, w) \
+ MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
+
+#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
+ MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
+ MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
+ MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
+ MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
+ if (HAS_ENGINE(gvt->gt, VCS1)) \
+ MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
+} while (0)
+
+#define MMIO_RING_D(prefix, d) \
+ MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
+
+#define MMIO_RING_DFH(prefix, d, f, r, w) \
+ MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
+
+#define MMIO_RING_GM(prefix, d, r, w) \
+ MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
+
+#define MMIO_RING_GM_RDR(prefix, d, r, w) \
+ MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
+
+#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
+ MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
+
+static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
+{
+ struct drm_i915_private *dev_priv = gvt->gt->i915;
+
+ int ret;
+
+ MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
+ intel_vgpu_reg_imr_handler);
+
+ MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(SDEISR, D_ALL);
+
+ MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
+
+
+ MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
+ gamw_echo_dev_rw_ia_write);
+
+ MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
+ MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
+ MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
+
+#define RING_REG(base) _MMIO((base) + 0x28)
+ MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x134)
+ MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x6c)
+ MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
+#undef RING_REG
+ MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
+
+ MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
+ MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
+ MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
+ MMIO_D(GEN7_CXT_SIZE, D_ALL);
+
+ MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
+ MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
+ MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
+ MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
+ MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
+
+ /* RING MODE */
+#define RING_REG(base) _MMIO((base) + 0x29c)
+ MMIO_RING_DFH(RING_REG, D_ALL,
+ F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
+ ring_mode_mmio_write);
+#undef RING_REG
+
+ MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
+ mmio_read_from_hw, NULL);
+ MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
+ mmio_read_from_hw, NULL);
+
+ MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
+ F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+
+ /* display */
+ MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_D(_MMIO(0x602a0), D_ALL);
+
+ MMIO_D(_MMIO(0x65050), D_ALL);
+ MMIO_D(_MMIO(0x650b4), D_ALL);
+
+ MMIO_D(_MMIO(0xc4040), D_ALL);
+ MMIO_D(DERRMR, D_ALL);
+
+ MMIO_D(PIPEDSL(PIPE_A), D_ALL);
+ MMIO_D(PIPEDSL(PIPE_B), D_ALL);
+ MMIO_D(PIPEDSL(PIPE_C), D_ALL);
+ MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
+
+ MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
+ MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
+ MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
+ MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
+
+ MMIO_D(PIPESTAT(PIPE_A), D_ALL);
+ MMIO_D(PIPESTAT(PIPE_B), D_ALL);
+ MMIO_D(PIPESTAT(PIPE_C), D_ALL);
+ MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
+
+ MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
+ MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
+ MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
+ MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
+
+ MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
+ MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
+ MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
+ MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
+
+ MMIO_D(CURCNTR(PIPE_A), D_ALL);
+ MMIO_D(CURCNTR(PIPE_B), D_ALL);
+ MMIO_D(CURCNTR(PIPE_C), D_ALL);
+
+ MMIO_D(CURPOS(PIPE_A), D_ALL);
+ MMIO_D(CURPOS(PIPE_B), D_ALL);
+ MMIO_D(CURPOS(PIPE_C), D_ALL);
+
+ MMIO_D(CURBASE(PIPE_A), D_ALL);
+ MMIO_D(CURBASE(PIPE_B), D_ALL);
+ MMIO_D(CURBASE(PIPE_C), D_ALL);
+
+ MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
+ MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
+ MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
+
+ MMIO_D(_MMIO(0x700ac), D_ALL);
+ MMIO_D(_MMIO(0x710ac), D_ALL);
+ MMIO_D(_MMIO(0x720ac), D_ALL);
+
+ MMIO_D(_MMIO(0x70090), D_ALL);
+ MMIO_D(_MMIO(0x70094), D_ALL);
+ MMIO_D(_MMIO(0x70098), D_ALL);
+ MMIO_D(_MMIO(0x7009c), D_ALL);
+
+ MMIO_D(DSPCNTR(PIPE_A), D_ALL);
+ MMIO_D(DSPADDR(PIPE_A), D_ALL);
+ MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
+ MMIO_D(DSPPOS(PIPE_A), D_ALL);
+ MMIO_D(DSPSIZE(PIPE_A), D_ALL);
+ MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
+ MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
+ MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
+ MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(DSPCNTR(PIPE_B), D_ALL);
+ MMIO_D(DSPADDR(PIPE_B), D_ALL);
+ MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
+ MMIO_D(DSPPOS(PIPE_B), D_ALL);
+ MMIO_D(DSPSIZE(PIPE_B), D_ALL);
+ MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
+ MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
+ MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
+ MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(DSPCNTR(PIPE_C), D_ALL);
+ MMIO_D(DSPADDR(PIPE_C), D_ALL);
+ MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
+ MMIO_D(DSPPOS(PIPE_C), D_ALL);
+ MMIO_D(DSPSIZE(PIPE_C), D_ALL);
+ MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
+ MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
+ MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
+ MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(SPRCTL(PIPE_A), D_ALL);
+ MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
+ MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
+ MMIO_D(SPRPOS(PIPE_A), D_ALL);
+ MMIO_D(SPRSIZE(PIPE_A), D_ALL);
+ MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
+ MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
+ MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
+ MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
+ MMIO_D(SPROFFSET(PIPE_A), D_ALL);
+ MMIO_D(SPRSCALE(PIPE_A), D_ALL);
+ MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
+ MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(SPRCTL(PIPE_B), D_ALL);
+ MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
+ MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
+ MMIO_D(SPRPOS(PIPE_B), D_ALL);
+ MMIO_D(SPRSIZE(PIPE_B), D_ALL);
+ MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
+ MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
+ MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
+ MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
+ MMIO_D(SPROFFSET(PIPE_B), D_ALL);
+ MMIO_D(SPRSCALE(PIPE_B), D_ALL);
+ MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
+ MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(SPRCTL(PIPE_C), D_ALL);
+ MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
+ MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
+ MMIO_D(SPRPOS(PIPE_C), D_ALL);
+ MMIO_D(SPRSIZE(PIPE_C), D_ALL);
+ MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
+ MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
+ MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
+ MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
+ MMIO_D(SPROFFSET(PIPE_C), D_ALL);
+ MMIO_D(SPRSCALE(PIPE_C), D_ALL);
+ MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
+ MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
+ MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
+ MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
+ MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
+ MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
+ MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
+ MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
+ MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
+
+ MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
+ MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
+ MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
+ MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
+ MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
+ MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
+ MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
+ MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
+
+ MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
+ MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
+ MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
+ MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
+ MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
+ MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
+ MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
+ MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
+
+ MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
+ MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
+ MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
+ MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
+ MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
+ MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
+ MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
+ MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
+
+ MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
+
+ MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
+
+ MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
+
+ MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
+
+ MMIO_D(PF_CTL(PIPE_A), D_ALL);
+ MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
+ MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
+ MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
+ MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
+
+ MMIO_D(PF_CTL(PIPE_B), D_ALL);
+ MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
+ MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
+ MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
+ MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
+
+ MMIO_D(PF_CTL(PIPE_C), D_ALL);
+ MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
+ MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
+ MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
+ MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
+
+ MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
+ MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
+ MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
+ MMIO_D(WM1_LP_ILK, D_ALL);
+ MMIO_D(WM2_LP_ILK, D_ALL);
+ MMIO_D(WM3_LP_ILK, D_ALL);
+ MMIO_D(WM1S_LP_ILK, D_ALL);
+ MMIO_D(WM2S_LP_IVB, D_ALL);
+ MMIO_D(WM3S_LP_IVB, D_ALL);
+
+ MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
+ MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
+ MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
+ MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
+
+ MMIO_D(_MMIO(0x48268), D_ALL);
+
+ MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
+ gmbus_mmio_write);
+ MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
+ dp_aux_ch_ctl_mmio_write);
+ MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
+ dp_aux_ch_ctl_mmio_write);
+ MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
+ dp_aux_ch_ctl_mmio_write);
+
+ MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
+
+ MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
+ MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
+
+ MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
+ MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
+ MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
+ MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
+ MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
+ MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
+ MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
+ MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
+ MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
+
+ MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
+
+ MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
+
+ MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
+
+ MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
+ MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
+ MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
+
+ MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
+ MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
+ MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
+
+ MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
+ MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
+ MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
+
+ MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
+ MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
+ MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
+
+ MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
+ MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
+ MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
+ MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
+ MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
+ MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
+
+ MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
+ MMIO_D(PCH_PP_DIVISOR, D_ALL);
+ MMIO_D(PCH_PP_STATUS, D_ALL);
+ MMIO_D(PCH_LVDS, D_ALL);
+ MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
+ MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
+ MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
+ MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
+ MMIO_D(PCH_DREF_CONTROL, D_ALL);
+ MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
+ MMIO_D(PCH_DPLL_SEL, D_ALL);
+
+ MMIO_D(_MMIO(0x61208), D_ALL);
+ MMIO_D(_MMIO(0x6120c), D_ALL);
+ MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
+ MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
+
+ MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
+ MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
+ MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
+ MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
+ MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
+ MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
+
+ MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
+ PORTA_HOTPLUG_STATUS_MASK
+ | PORTB_HOTPLUG_STATUS_MASK
+ | PORTC_HOTPLUG_STATUS_MASK
+ | PORTD_HOTPLUG_STATUS_MASK,
+ NULL, NULL);
+
+ MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
+ MMIO_D(FUSE_STRAP, D_ALL);
+ MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
+
+ MMIO_D(DISP_ARB_CTL, D_ALL);
+ MMIO_D(DISP_ARB_CTL2, D_ALL);
+
+ MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
+ MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
+ MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
+
+ MMIO_D(SOUTH_CHICKEN1, D_ALL);
+ MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
+ MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
+ MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
+ MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
+ MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
+ MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
+
+ MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
+ MMIO_D(ILK_DPFC_CONTROL, D_ALL);
+ MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
+ MMIO_D(ILK_DPFC_STATUS, D_ALL);
+ MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
+ MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
+ MMIO_D(ILK_FBC_RT_BASE, D_ALL);
+
+ MMIO_D(IPS_CTL, D_ALL);
+
+ MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
+
+ MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
+
+ MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
+
+ MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
+ MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
+ MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
+ MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
+ MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
+ MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
+ MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(_MMIO(0x60110), D_ALL);
+ MMIO_D(_MMIO(0x61110), D_ALL);
+ MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+ MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+ MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+ MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+ MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+ MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+
+ MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
+ MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
+ MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
+ MMIO_D(SPLL_CTL, D_ALL);
+ MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
+ MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
+ MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
+ MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
+ MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
+ MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
+ MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
+ MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
+ MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
+ MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
+
+ MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
+ MMIO_D(_MMIO(0x46508), D_ALL);
+
+ MMIO_D(_MMIO(0x49080), D_ALL);
+ MMIO_D(_MMIO(0x49180), D_ALL);
+ MMIO_D(_MMIO(0x49280), D_ALL);
+
+ MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
+ MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
+ MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
+
+ MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
+ MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
+ MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
+
+ MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
+ MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
+ MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
+
+ MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
+ MMIO_D(SBI_ADDR, D_ALL);
+ MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
+ MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
+ MMIO_D(PIXCLK_GATE, D_ALL);
+
+ MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
+ dp_aux_ch_ctl_mmio_write);
+
+ MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+
+ MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
+ MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
+ MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
+ MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
+ MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
+
+ MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
+ MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
+ MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
+ MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
+ MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
+
+ MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
+ MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
+ MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
+
+ MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
+ MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
+ MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
+ MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
+
+ MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
+ MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
+ MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
+ MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
+
+ MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
+ MMIO_D(FORCEWAKE_ACK, D_ALL);
+ MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
+ MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
+ MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
+ MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
+ MMIO_D(ECOBUS, D_ALL);
+ MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
+ MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
+ MMIO_D(GEN6_RPNSWREQ, D_ALL);
+ MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
+ MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
+ MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
+ MMIO_D(GEN6_RPSTAT1, D_ALL);
+ MMIO_D(GEN6_RP_CONTROL, D_ALL);
+ MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
+ MMIO_D(GEN6_RP_CUR_UP, D_ALL);
+ MMIO_D(GEN6_RP_PREV_UP, D_ALL);
+ MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
+ MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
+ MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
+ MMIO_D(GEN6_RP_UP_EI, D_ALL);
+ MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
+ MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
+ MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
+ MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
+ MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
+ MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
+ MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
+ MMIO_D(GEN6_RC_SLEEP, D_ALL);
+ MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_PMINTRMSK, D_ALL);
+ MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
+
+ MMIO_D(RSTDBYCTL, D_ALL);
+
+ MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
+ MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
+ MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
+
+ MMIO_D(TILECTL, D_ALL);
+
+ MMIO_D(GEN6_UCGCTL1, D_ALL);
+ MMIO_D(GEN6_UCGCTL2, D_ALL);
+
+ MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(GEN6_PCODE_DATA, D_ALL);
+ MMIO_D(_MMIO(0x13812c), D_ALL);
+ MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
+ MMIO_D(HSW_EDRAM_CAP, D_ALL);
+ MMIO_D(HSW_IDICR, D_ALL);
+ MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
+
+ MMIO_D(_MMIO(0x3c), D_ALL);
+ MMIO_D(_MMIO(0x860), D_ALL);
+ MMIO_D(ECOSKPD, D_ALL);
+ MMIO_D(_MMIO(0x121d0), D_ALL);
+ MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
+ MMIO_D(_MMIO(0x41d0), D_ALL);
+ MMIO_D(GAC_ECO_BITS, D_ALL);
+ MMIO_D(_MMIO(0x6200), D_ALL);
+ MMIO_D(_MMIO(0x6204), D_ALL);
+ MMIO_D(_MMIO(0x6208), D_ALL);
+ MMIO_D(_MMIO(0x7118), D_ALL);
+ MMIO_D(_MMIO(0x7180), D_ALL);
+ MMIO_D(_MMIO(0x7408), D_ALL);
+ MMIO_D(_MMIO(0x7c00), D_ALL);
+ MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
+ MMIO_D(_MMIO(0x911c), D_ALL);
+ MMIO_D(_MMIO(0x9120), D_ALL);
+ MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_D(GAB_CTL, D_ALL);
+ MMIO_D(_MMIO(0x48800), D_ALL);
+ MMIO_D(_MMIO(0xce044), D_ALL);
+ MMIO_D(_MMIO(0xe6500), D_ALL);
+ MMIO_D(_MMIO(0xe6504), D_ALL);
+ MMIO_D(_MMIO(0xe6600), D_ALL);
+ MMIO_D(_MMIO(0xe6604), D_ALL);
+ MMIO_D(_MMIO(0xe6700), D_ALL);
+ MMIO_D(_MMIO(0xe6704), D_ALL);
+ MMIO_D(_MMIO(0xe6800), D_ALL);
+ MMIO_D(_MMIO(0xe6804), D_ALL);
+ MMIO_D(PCH_GMBUS4, D_ALL);
+ MMIO_D(PCH_GMBUS5, D_ALL);
+
+ MMIO_D(_MMIO(0x902c), D_ALL);
+ MMIO_D(_MMIO(0xec008), D_ALL);
+ MMIO_D(_MMIO(0xec00c), D_ALL);
+ MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
+ MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
+ MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
+ MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
+ MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
+ MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
+ MMIO_D(_MMIO(0xec408), D_ALL);
+ MMIO_D(_MMIO(0xec40c), D_ALL);
+ MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
+ MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
+ MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
+ MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
+ MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
+ MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
+ MMIO_D(_MMIO(0xfc810), D_ALL);
+ MMIO_D(_MMIO(0xfc81c), D_ALL);
+ MMIO_D(_MMIO(0xfc828), D_ALL);
+ MMIO_D(_MMIO(0xfc834), D_ALL);
+ MMIO_D(_MMIO(0xfcc00), D_ALL);
+ MMIO_D(_MMIO(0xfcc0c), D_ALL);
+ MMIO_D(_MMIO(0xfcc18), D_ALL);
+ MMIO_D(_MMIO(0xfcc24), D_ALL);
+ MMIO_D(_MMIO(0xfd000), D_ALL);
+ MMIO_D(_MMIO(0xfd00c), D_ALL);
+ MMIO_D(_MMIO(0xfd018), D_ALL);
+ MMIO_D(_MMIO(0xfd024), D_ALL);
+ MMIO_D(_MMIO(0xfd034), D_ALL);
+
+ MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
+ MMIO_D(_MMIO(0x2054), D_ALL);
+ MMIO_D(_MMIO(0x12054), D_ALL);
+ MMIO_D(_MMIO(0x22054), D_ALL);
+ MMIO_D(_MMIO(0x1a054), D_ALL);
+
+ MMIO_D(_MMIO(0x44070), D_ALL);
+ MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
+ MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
+ MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
+ MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
+ MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
+ MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
+ MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
+ MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
+ MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
+ MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
+
+ return 0;
+}
+
+static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
+{
+ struct drm_i915_private *dev_priv = gvt->gt->i915;
+ int ret;
+
+ MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
+
+ MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
+
+ MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
+
+ MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
+ intel_vgpu_reg_master_irq_handler);
+
+ MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
+ mmio_read_from_hw, NULL);
+
+#define RING_REG(base) _MMIO((base) + 0xd0)
+ MMIO_RING_F(RING_REG, 4, F_RO, 0,
+ ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
+ ring_reset_ctl_write);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x230)
+ MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x234)
+ MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
+ NULL, NULL);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x244)
+ MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x370)
+ MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x3a0)
+ MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
+#undef RING_REG
+
+ MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
+ MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
+ MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
+ MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
+ MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
+ MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
+
+ MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
+
+ MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
+ MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
+
+ MMIO_D(GAMTARBMODE, D_BDW_PLUS);
+
+#define RING_REG(base) _MMIO((base) + 0x270)
+ MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
+#undef RING_REG
+
+ MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
+
+ MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
+ MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
+ MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
+
+ MMIO_D(WM_MISC, D_BDW);
+ MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
+
+ MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
+
+ MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
+
+ MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
+ MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
+ MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
+
+ MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
+ MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
+ MMIO_D(_MMIO(0xb110), D_BDW);
+ MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
+
+ MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
+ D_BDW_PLUS, NULL, force_nonpriv_write);
+
+ MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
+
+ MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
+ MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
+
+ MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
+
+ MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
+
+ MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
+
+ MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ return 0;
+}
+
+static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
+{
+ struct drm_i915_private *dev_priv = gvt->gt->i915;
+ int ret;
+
+ MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
+ MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
+ MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
+ MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
+
+ MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
+ dp_aux_ch_ctl_mmio_write);
+ MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
+ dp_aux_ch_ctl_mmio_write);
+ MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
+ dp_aux_ch_ctl_mmio_write);
+
+ MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
+ MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
+
+ MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
+
+ MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
+ MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
+ MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
+ MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
+ MMIO_D(DC_STATE_EN, D_SKL_PLUS);
+ MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
+ MMIO_D(CDCLK_CTL, D_SKL_PLUS);
+ MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
+ MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
+ MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
+ MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
+ MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
+ MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
+ MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
+ MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
+ MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
+ MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
+ MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
+
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
+
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
+
+ MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
+
+ MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+
+ MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+
+ MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+
+ MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
+
+ MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
+ MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
+ MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
+
+ MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_D(SKL_DFSM, D_SKL_PLUS);
+ MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
+
+ MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
+ NULL, NULL);
+ MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
+ NULL, NULL);
+
+ MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
+ MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
+ MMIO_D(RC6_LOCATION, D_SKL_PLUS);
+ MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
+ F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+
+ /* TRTT */
+ MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
+ NULL, gen9_trtte_write);
+ MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
+ NULL, gen9_trtt_chicken_write);
+
+ MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
+
+ MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
+
+ MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
+ MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
+
+ MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
+ MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
+ MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
+
+ MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
+
+ MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
+
+ MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
+#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
+ MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, csfe_chicken1_mmio_write);
+#undef CSFE_CHICKEN1_REG
+ MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+
+ MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
+
+ return 0;
+}
+
+static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
+{
+ struct drm_i915_private *dev_priv = gvt->gt->i915;
+ int ret;
+
+ MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
+
+ MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
+ MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
+ MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
+ MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
+ MMIO_D(ERROR_GEN6, D_BXT);
+ MMIO_D(DONE_REG, D_BXT);
+ MMIO_D(EIR, D_BXT);
+ MMIO_D(PGTBL_ER, D_BXT);
+ MMIO_D(_MMIO(0x4194), D_BXT);
+ MMIO_D(_MMIO(0x4294), D_BXT);
+ MMIO_D(_MMIO(0x4494), D_BXT);
+
+ MMIO_RING_D(RING_PSMI_CTL, D_BXT);
+ MMIO_RING_D(RING_DMA_FADD, D_BXT);
+ MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
+ MMIO_RING_D(RING_IPEHR, D_BXT);
+ MMIO_RING_D(RING_INSTPS, D_BXT);
+ MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
+ MMIO_RING_D(RING_BBSTATE, D_BXT);
+ MMIO_RING_D(RING_IPEIR, D_BXT);
+
+ MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
+
+ MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
+ MMIO_D(BXT_RP_STATE_CAP, D_BXT);
+ MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
+ NULL, bxt_phy_ctl_family_write);
+ MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
+ NULL, bxt_phy_ctl_family_write);
+ MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
+ MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
+ MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
+ MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
+ NULL, bxt_port_pll_enable_write);
+ MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
+ NULL, bxt_port_pll_enable_write);
+ MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
+ bxt_port_pll_enable_write);
+
+ MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
+
+ MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
+
+ MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
+ NULL, bxt_pcs_dw12_grp_write);
+ MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
+ bxt_port_tx_dw3_read, NULL);
+ MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
+
+ MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
+ NULL, bxt_pcs_dw12_grp_write);
+ MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
+ bxt_port_tx_dw3_read, NULL);
+ MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
+
+ MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
+ NULL, bxt_pcs_dw12_grp_write);
+ MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
+ bxt_port_tx_dw3_read, NULL);
+ MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
+
+ MMIO_D(BXT_DE_PLL_CTL, D_BXT);
+ MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
+ MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
+ MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
+
+ MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
+ MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
+
+ MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
+ MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
+ MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
+
+ MMIO_D(RC6_CTX_BASE, D_BXT);
+
+ MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
+ MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
+ MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
+ MMIO_D(GEN6_GFXPAUSE, D_BXT);
+ MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
+ MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+ 0, 0, D_BXT, NULL, NULL);
+ MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+ 0, 0, D_BXT, NULL, NULL);
+ MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+ 0, 0, D_BXT, NULL, NULL);
+ MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+ 0, 0, D_BXT, NULL, NULL);
+
+ MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
+
+ return 0;
+}
+
+static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
+{
+ struct drm_i915_private *i915 = gvt->gt->i915;
+ int ret;
+
+ ret = intel_gvt_init_generic_mmio_info(gvt);
+ if (ret)
+ return ret;
+
+ if (IS_BROADWELL(i915)) {
+ ret = intel_gvt_init_bdw_mmio_info(gvt);
+ if (ret)
+ return ret;
+ } else if (IS_SKYLAKE(i915) ||
+ IS_KABYLAKE(i915) ||
+ IS_COFFEELAKE(i915) ||
+ IS_COMETLAKE(i915)) {
+ ret = intel_gvt_init_bdw_mmio_info(gvt);
+ if (ret)
+ return ret;
+ ret = intel_gvt_init_skl_mmio_info(gvt);
+ if (ret)
+ return ret;
+ } else if (IS_BROXTON(i915)) {
+ ret = intel_gvt_init_bdw_mmio_info(gvt);
+ if (ret)
+ return ret;
+ ret = intel_gvt_init_skl_mmio_info(gvt);
+ if (ret)
+ return ret;
+ ret = intel_gvt_init_bxt_mmio_info(gvt);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index 244cc7320b54..05bd2f8e9d94 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -133,6 +133,12 @@
#define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
#define VF_GUARDBAND _MMIO(0x83a4)
+/* XXX FIXME i915 has changed PP_XXX definition */
+#define PCH_PP_STATUS _MMIO(0xc7200)
+#define PCH_PP_CONTROL _MMIO(0xc7204)
+#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
+#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
+#define PCH_PP_DIVISOR _MMIO(0xc7210)
#define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
#endif
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index 4e70c1a9ef2e..64846d9bff0b 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
dev_priv->params.enable_gvt = 0;
}
+#define GENERATE_MMIO_TABLE_IN_I915
+static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
+{
+ return 0;
+}
+
+#include "gvt/reg.h"
+#include "gvt/mmio_table.h"
+#undef GENERATE_MMIO_TABLE_IN_I915
+
+
/**
* intel_gvt_init - initialize GVT components
* @dev_priv: drm i915 private data
--
2.25.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-08 21:27 ` Zhi Wang
0 siblings, 0 replies; 35+ messages in thread
From: Zhi Wang @ 2021-11-08 21:27 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, zhenyuw, zhi.a.wang,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
Cc: Zhi Wang
From: Zhi Wang <zhi.wang.linux@gmail.com>
To support the new mdev interfaces and the re-factor patches from
Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
MMIO snapshot still needs to be saved in i915 so that the inital clean HW
state can be used for the further vGPU. Seperate the tracked MMIO table
from GVT-g, so that GVT-g and i915 can both use it.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
---
drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
drivers/gpu/drm/i915/gvt/reg.h | 6 +
drivers/gpu/drm/i915/intel_gvt.c | 11 +
4 files changed, 1592 insertions(+), 1534 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index cde0a477fb49..6a08d362bf66 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -41,13 +41,6 @@
#include "i915_pvinfo.h"
#include "display/intel_display_types.h"
-/* XXX FIXME i915 has changed PP_XXX definition */
-#define PCH_PP_STATUS _MMIO(0xc7200)
-#define PCH_PP_CONTROL _MMIO(0xc7204)
-#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
-#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
-#define PCH_PP_DIVISOR _MMIO(0xc7210)
-
unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
{
struct drm_i915_private *i915 = gvt->gt->i915;
@@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
return 0;
}
-#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
- ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
- f, s, am, rm, d, r, w); \
- if (ret) \
- return ret; \
-} while (0)
-
-#define MMIO_D(reg, d) \
- MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
-
-#define MMIO_DH(reg, d, r, w) \
- MMIO_F(reg, 4, 0, 0, 0, d, r, w)
-
-#define MMIO_DFH(reg, d, f, r, w) \
- MMIO_F(reg, 4, f, 0, 0, d, r, w)
-
-#define MMIO_GM(reg, d, r, w) \
- MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
-
-#define MMIO_GM_RDR(reg, d, r, w) \
- MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
-
-#define MMIO_RO(reg, d, f, rm, r, w) \
- MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
-
-#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
- MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
- MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
- MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
- MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
- if (HAS_ENGINE(gvt->gt, VCS1)) \
- MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
-} while (0)
-
-#define MMIO_RING_D(prefix, d) \
- MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
-
-#define MMIO_RING_DFH(prefix, d, f, r, w) \
- MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
-
-#define MMIO_RING_GM(prefix, d, r, w) \
- MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
-
-#define MMIO_RING_GM_RDR(prefix, d, r, w) \
- MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
-
-#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
- MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
-
-static int init_generic_mmio_info(struct intel_gvt *gvt)
-{
- struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
-
- MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
- intel_vgpu_reg_imr_handler);
-
- MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(SDEISR, D_ALL);
-
- MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
-
-
- MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
- gamw_echo_dev_rw_ia_write);
-
- MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
- MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
- MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
-
-#define RING_REG(base) _MMIO((base) + 0x28)
- MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x134)
- MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x6c)
- MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
-#undef RING_REG
- MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
-
- MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
- MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
- MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
- MMIO_D(GEN7_CXT_SIZE, D_ALL);
-
- MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
- MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
- MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
- MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
- MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
-
- /* RING MODE */
-#define RING_REG(base) _MMIO((base) + 0x29c)
- MMIO_RING_DFH(RING_REG, D_ALL,
- F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
- ring_mode_mmio_write);
-#undef RING_REG
-
- MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
- mmio_read_from_hw, NULL);
- MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
- mmio_read_from_hw, NULL);
-
- MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
- F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
-
- /* display */
- MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_D(_MMIO(0x602a0), D_ALL);
-
- MMIO_D(_MMIO(0x65050), D_ALL);
- MMIO_D(_MMIO(0x650b4), D_ALL);
-
- MMIO_D(_MMIO(0xc4040), D_ALL);
- MMIO_D(DERRMR, D_ALL);
-
- MMIO_D(PIPEDSL(PIPE_A), D_ALL);
- MMIO_D(PIPEDSL(PIPE_B), D_ALL);
- MMIO_D(PIPEDSL(PIPE_C), D_ALL);
- MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
-
- MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
- MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
- MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
- MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
-
- MMIO_D(PIPESTAT(PIPE_A), D_ALL);
- MMIO_D(PIPESTAT(PIPE_B), D_ALL);
- MMIO_D(PIPESTAT(PIPE_C), D_ALL);
- MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
-
- MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
- MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
- MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
- MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
-
- MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
- MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
- MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
- MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
-
- MMIO_D(CURCNTR(PIPE_A), D_ALL);
- MMIO_D(CURCNTR(PIPE_B), D_ALL);
- MMIO_D(CURCNTR(PIPE_C), D_ALL);
-
- MMIO_D(CURPOS(PIPE_A), D_ALL);
- MMIO_D(CURPOS(PIPE_B), D_ALL);
- MMIO_D(CURPOS(PIPE_C), D_ALL);
-
- MMIO_D(CURBASE(PIPE_A), D_ALL);
- MMIO_D(CURBASE(PIPE_B), D_ALL);
- MMIO_D(CURBASE(PIPE_C), D_ALL);
-
- MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
- MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
- MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
-
- MMIO_D(_MMIO(0x700ac), D_ALL);
- MMIO_D(_MMIO(0x710ac), D_ALL);
- MMIO_D(_MMIO(0x720ac), D_ALL);
-
- MMIO_D(_MMIO(0x70090), D_ALL);
- MMIO_D(_MMIO(0x70094), D_ALL);
- MMIO_D(_MMIO(0x70098), D_ALL);
- MMIO_D(_MMIO(0x7009c), D_ALL);
-
- MMIO_D(DSPCNTR(PIPE_A), D_ALL);
- MMIO_D(DSPADDR(PIPE_A), D_ALL);
- MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
- MMIO_D(DSPPOS(PIPE_A), D_ALL);
- MMIO_D(DSPSIZE(PIPE_A), D_ALL);
- MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
- MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
- MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
- MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(DSPCNTR(PIPE_B), D_ALL);
- MMIO_D(DSPADDR(PIPE_B), D_ALL);
- MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
- MMIO_D(DSPPOS(PIPE_B), D_ALL);
- MMIO_D(DSPSIZE(PIPE_B), D_ALL);
- MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
- MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
- MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
- MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(DSPCNTR(PIPE_C), D_ALL);
- MMIO_D(DSPADDR(PIPE_C), D_ALL);
- MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
- MMIO_D(DSPPOS(PIPE_C), D_ALL);
- MMIO_D(DSPSIZE(PIPE_C), D_ALL);
- MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
- MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
- MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
- MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(SPRCTL(PIPE_A), D_ALL);
- MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
- MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
- MMIO_D(SPRPOS(PIPE_A), D_ALL);
- MMIO_D(SPRSIZE(PIPE_A), D_ALL);
- MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
- MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
- MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
- MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
- MMIO_D(SPROFFSET(PIPE_A), D_ALL);
- MMIO_D(SPRSCALE(PIPE_A), D_ALL);
- MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
- MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(SPRCTL(PIPE_B), D_ALL);
- MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
- MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
- MMIO_D(SPRPOS(PIPE_B), D_ALL);
- MMIO_D(SPRSIZE(PIPE_B), D_ALL);
- MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
- MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
- MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
- MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
- MMIO_D(SPROFFSET(PIPE_B), D_ALL);
- MMIO_D(SPRSCALE(PIPE_B), D_ALL);
- MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
- MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(SPRCTL(PIPE_C), D_ALL);
- MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
- MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
- MMIO_D(SPRPOS(PIPE_C), D_ALL);
- MMIO_D(SPRSIZE(PIPE_C), D_ALL);
- MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
- MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
- MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
- MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
- MMIO_D(SPROFFSET(PIPE_C), D_ALL);
- MMIO_D(SPRSCALE(PIPE_C), D_ALL);
- MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
- MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
- reg50080_mmio_write);
-
- MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
- MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
- MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
- MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
- MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
- MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
- MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
- MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
- MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
-
- MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
- MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
- MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
- MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
- MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
- MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
- MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
- MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
- MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
-
- MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
- MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
- MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
- MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
- MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
- MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
- MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
- MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
- MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
-
- MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
- MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
- MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
- MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
- MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
- MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
- MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
- MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
-
- MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
- MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
-
- MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
- MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
-
- MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
- MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
-
- MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
- MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
-
- MMIO_D(PF_CTL(PIPE_A), D_ALL);
- MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
- MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
- MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
- MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
-
- MMIO_D(PF_CTL(PIPE_B), D_ALL);
- MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
- MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
- MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
- MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
-
- MMIO_D(PF_CTL(PIPE_C), D_ALL);
- MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
- MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
- MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
- MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
-
- MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
- MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
- MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
- MMIO_D(WM1_LP_ILK, D_ALL);
- MMIO_D(WM2_LP_ILK, D_ALL);
- MMIO_D(WM3_LP_ILK, D_ALL);
- MMIO_D(WM1S_LP_ILK, D_ALL);
- MMIO_D(WM2S_LP_IVB, D_ALL);
- MMIO_D(WM3S_LP_IVB, D_ALL);
-
- MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
- MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
- MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
- MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
-
- MMIO_D(_MMIO(0x48268), D_ALL);
-
- MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
- gmbus_mmio_write);
- MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
- dp_aux_ch_ctl_mmio_write);
- MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
- dp_aux_ch_ctl_mmio_write);
- MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
- dp_aux_ch_ctl_mmio_write);
-
- MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
-
- MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
- MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
-
- MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
- MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
- MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
- MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
- MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
- MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
- MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
- MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
- MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
-
- MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
-
- MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
-
- MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
- MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
-
- MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
- MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
- MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
-
- MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
- MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
- MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
-
- MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
- MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
- MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
-
- MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
- MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
- MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
-
- MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
- MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
- MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
- MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
- MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
- MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
-
- MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
- MMIO_D(PCH_PP_DIVISOR, D_ALL);
- MMIO_D(PCH_PP_STATUS, D_ALL);
- MMIO_D(PCH_LVDS, D_ALL);
- MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
- MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
- MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
- MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
- MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
- MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
- MMIO_D(PCH_DREF_CONTROL, D_ALL);
- MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
- MMIO_D(PCH_DPLL_SEL, D_ALL);
-
- MMIO_D(_MMIO(0x61208), D_ALL);
- MMIO_D(_MMIO(0x6120c), D_ALL);
- MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
- MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
-
- MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
- MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
- MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
- MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
- MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
- MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
-
- MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
- PORTA_HOTPLUG_STATUS_MASK
- | PORTB_HOTPLUG_STATUS_MASK
- | PORTC_HOTPLUG_STATUS_MASK
- | PORTD_HOTPLUG_STATUS_MASK,
- NULL, NULL);
-
- MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
- MMIO_D(FUSE_STRAP, D_ALL);
- MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
-
- MMIO_D(DISP_ARB_CTL, D_ALL);
- MMIO_D(DISP_ARB_CTL2, D_ALL);
-
- MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
- MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
- MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
-
- MMIO_D(SOUTH_CHICKEN1, D_ALL);
- MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
- MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
- MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
- MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
- MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
- MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
-
- MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
- MMIO_D(ILK_DPFC_CONTROL, D_ALL);
- MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
- MMIO_D(ILK_DPFC_STATUS, D_ALL);
- MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
- MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
- MMIO_D(ILK_FBC_RT_BASE, D_ALL);
-
- MMIO_D(IPS_CTL, D_ALL);
-
- MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
-
- MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
-
- MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
- MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
-
- MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
- MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
- MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
- MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
- MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
- MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
- MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(_MMIO(0x60110), D_ALL);
- MMIO_D(_MMIO(0x61110), D_ALL);
- MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
- MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
-
- MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
- MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
- MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
- MMIO_D(SPLL_CTL, D_ALL);
- MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
- MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
- MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
- MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
- MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
- MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
- MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
- MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
- MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
- MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
-
- MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
- MMIO_D(_MMIO(0x46508), D_ALL);
-
- MMIO_D(_MMIO(0x49080), D_ALL);
- MMIO_D(_MMIO(0x49180), D_ALL);
- MMIO_D(_MMIO(0x49280), D_ALL);
-
- MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
- MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
- MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
-
- MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
- MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
- MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
-
- MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
- MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
- MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
-
- MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
- MMIO_D(SBI_ADDR, D_ALL);
- MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
- MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
- MMIO_D(PIXCLK_GATE, D_ALL);
-
- MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
- dp_aux_ch_ctl_mmio_write);
-
- MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
- MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
-
- MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
- MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
- MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
- MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
- MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
-
- MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
- MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
- MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
- MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
- MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
-
- MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
- MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
- MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
-
- MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
- MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
- MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
- MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
-
- MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
- MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
- MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
- MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
-
- MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
- MMIO_D(FORCEWAKE_ACK, D_ALL);
- MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
- MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
- MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
- MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
- MMIO_D(ECOBUS, D_ALL);
- MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
- MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
- MMIO_D(GEN6_RPNSWREQ, D_ALL);
- MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
- MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
- MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
- MMIO_D(GEN6_RPSTAT1, D_ALL);
- MMIO_D(GEN6_RP_CONTROL, D_ALL);
- MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
- MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
- MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
- MMIO_D(GEN6_RP_CUR_UP, D_ALL);
- MMIO_D(GEN6_RP_PREV_UP, D_ALL);
- MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
- MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
- MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
- MMIO_D(GEN6_RP_UP_EI, D_ALL);
- MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
- MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
- MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
- MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
- MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
- MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
- MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
- MMIO_D(GEN6_RC_SLEEP, D_ALL);
- MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
- MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
- MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
- MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
- MMIO_D(GEN6_PMINTRMSK, D_ALL);
- MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
-
- MMIO_D(RSTDBYCTL, D_ALL);
-
- MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
- MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
- MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
-
- MMIO_D(TILECTL, D_ALL);
-
- MMIO_D(GEN6_UCGCTL1, D_ALL);
- MMIO_D(GEN6_UCGCTL2, D_ALL);
-
- MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_D(GEN6_PCODE_DATA, D_ALL);
- MMIO_D(_MMIO(0x13812c), D_ALL);
- MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
- MMIO_D(HSW_EDRAM_CAP, D_ALL);
- MMIO_D(HSW_IDICR, D_ALL);
- MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
-
- MMIO_D(_MMIO(0x3c), D_ALL);
- MMIO_D(_MMIO(0x860), D_ALL);
- MMIO_D(ECOSKPD, D_ALL);
- MMIO_D(_MMIO(0x121d0), D_ALL);
- MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
- MMIO_D(_MMIO(0x41d0), D_ALL);
- MMIO_D(GAC_ECO_BITS, D_ALL);
- MMIO_D(_MMIO(0x6200), D_ALL);
- MMIO_D(_MMIO(0x6204), D_ALL);
- MMIO_D(_MMIO(0x6208), D_ALL);
- MMIO_D(_MMIO(0x7118), D_ALL);
- MMIO_D(_MMIO(0x7180), D_ALL);
- MMIO_D(_MMIO(0x7408), D_ALL);
- MMIO_D(_MMIO(0x7c00), D_ALL);
- MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
- MMIO_D(_MMIO(0x911c), D_ALL);
- MMIO_D(_MMIO(0x9120), D_ALL);
- MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_D(GAB_CTL, D_ALL);
- MMIO_D(_MMIO(0x48800), D_ALL);
- MMIO_D(_MMIO(0xce044), D_ALL);
- MMIO_D(_MMIO(0xe6500), D_ALL);
- MMIO_D(_MMIO(0xe6504), D_ALL);
- MMIO_D(_MMIO(0xe6600), D_ALL);
- MMIO_D(_MMIO(0xe6604), D_ALL);
- MMIO_D(_MMIO(0xe6700), D_ALL);
- MMIO_D(_MMIO(0xe6704), D_ALL);
- MMIO_D(_MMIO(0xe6800), D_ALL);
- MMIO_D(_MMIO(0xe6804), D_ALL);
- MMIO_D(PCH_GMBUS4, D_ALL);
- MMIO_D(PCH_GMBUS5, D_ALL);
-
- MMIO_D(_MMIO(0x902c), D_ALL);
- MMIO_D(_MMIO(0xec008), D_ALL);
- MMIO_D(_MMIO(0xec00c), D_ALL);
- MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
- MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
- MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
- MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
- MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
- MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
- MMIO_D(_MMIO(0xec408), D_ALL);
- MMIO_D(_MMIO(0xec40c), D_ALL);
- MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
- MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
- MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
- MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
- MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
- MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
- MMIO_D(_MMIO(0xfc810), D_ALL);
- MMIO_D(_MMIO(0xfc81c), D_ALL);
- MMIO_D(_MMIO(0xfc828), D_ALL);
- MMIO_D(_MMIO(0xfc834), D_ALL);
- MMIO_D(_MMIO(0xfcc00), D_ALL);
- MMIO_D(_MMIO(0xfcc0c), D_ALL);
- MMIO_D(_MMIO(0xfcc18), D_ALL);
- MMIO_D(_MMIO(0xfcc24), D_ALL);
- MMIO_D(_MMIO(0xfd000), D_ALL);
- MMIO_D(_MMIO(0xfd00c), D_ALL);
- MMIO_D(_MMIO(0xfd018), D_ALL);
- MMIO_D(_MMIO(0xfd024), D_ALL);
- MMIO_D(_MMIO(0xfd034), D_ALL);
-
- MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
- MMIO_D(_MMIO(0x2054), D_ALL);
- MMIO_D(_MMIO(0x12054), D_ALL);
- MMIO_D(_MMIO(0x22054), D_ALL);
- MMIO_D(_MMIO(0x1a054), D_ALL);
-
- MMIO_D(_MMIO(0x44070), D_ALL);
- MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
- MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
- MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
- MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
-
- MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
- MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
- MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
- MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
- MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
- MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
- MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
- MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
- MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
- MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
-
- return 0;
-}
-
-static int init_bdw_mmio_info(struct intel_gvt *gvt)
-{
- struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
-
- MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
-
- MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
-
- MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
-
- MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
-
- MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
- intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
- intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
- intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
-
- MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
- intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
- intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
- intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
-
- MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
- intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
- intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
- intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
-
- MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
-
- MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
-
- MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
- MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
- MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
- MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
-
- MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
- intel_vgpu_reg_master_irq_handler);
-
- MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
- mmio_read_from_hw, NULL);
-
-#define RING_REG(base) _MMIO((base) + 0xd0)
- MMIO_RING_F(RING_REG, 4, F_RO, 0,
- ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
- ring_reset_ctl_write);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x230)
- MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x234)
- MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
- NULL, NULL);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x244)
- MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x370)
- MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
-#undef RING_REG
-
-#define RING_REG(base) _MMIO((base) + 0x3a0)
- MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
-#undef RING_REG
-
- MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
- MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
- MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
- MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
- MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
- MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
- MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
-
- MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
-
- MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
- MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
-
- MMIO_D(GAMTARBMODE, D_BDW_PLUS);
-
-#define RING_REG(base) _MMIO((base) + 0x270)
- MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
-#undef RING_REG
-
- MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
-
- MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
-
- MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
- MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
- MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
-
- MMIO_D(WM_MISC, D_BDW);
- MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
-
- MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
- MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
- MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
-
- MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
-
- MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
- MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
- MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
-
- MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
- MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_D(_MMIO(0xb110), D_BDW);
- MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
-
- MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
- D_BDW_PLUS, NULL, force_nonpriv_write);
-
- MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
- MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
-
- MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
-
- MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
-
- MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
-
- MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
- MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
-
- MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
- return 0;
-}
-
-static int init_skl_mmio_info(struct intel_gvt *gvt)
-{
- struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
-
- MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
- MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
- MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
- MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
- MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
- MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
-
- MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
- dp_aux_ch_ctl_mmio_write);
- MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
- dp_aux_ch_ctl_mmio_write);
- MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
- dp_aux_ch_ctl_mmio_write);
-
- MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
- MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
-
- MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
-
- MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
- MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
- MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
- MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
- MMIO_D(DC_STATE_EN, D_SKL_PLUS);
- MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
- MMIO_D(CDCLK_CTL, D_SKL_PLUS);
- MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
- MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
- MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
- MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
- MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
- MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
- MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
- MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
- MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
- MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
- MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
-
- MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
-
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
-
- MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
- MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
-
- MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
-
- MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
-
- MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
-
- MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
-
- MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
- MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
-
- MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
- MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
- MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
-
- MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
- MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
- MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
-
- MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_D(SKL_DFSM, D_SKL_PLUS);
- MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
-
- MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
- NULL, NULL);
- MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
- NULL, NULL);
-
- MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
- MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
- MMIO_D(RC6_LOCATION, D_SKL_PLUS);
- MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
- F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
-
- /* TRTT */
- MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
- NULL, gen9_trtte_write);
- MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
- NULL, gen9_trtt_chicken_write);
-
- MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
-
- MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
-
- MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
- MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
- MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
-
- MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
- MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
- MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
- MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
- MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
- MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
- MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
- MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
- MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
- MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
-
- MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
- MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
- MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
-
- MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
- MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
-
- MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
-#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
- MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, csfe_chicken1_mmio_write);
-#undef CSFE_CHICKEN1_REG
- MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
- MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
-
- MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
- MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
-
- return 0;
-}
-
-static int init_bxt_mmio_info(struct intel_gvt *gvt)
-{
- struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
-
- MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
-
- MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
- MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
- MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
- MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
- MMIO_D(ERROR_GEN6, D_BXT);
- MMIO_D(DONE_REG, D_BXT);
- MMIO_D(EIR, D_BXT);
- MMIO_D(PGTBL_ER, D_BXT);
- MMIO_D(_MMIO(0x4194), D_BXT);
- MMIO_D(_MMIO(0x4294), D_BXT);
- MMIO_D(_MMIO(0x4494), D_BXT);
-
- MMIO_RING_D(RING_PSMI_CTL, D_BXT);
- MMIO_RING_D(RING_DMA_FADD, D_BXT);
- MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
- MMIO_RING_D(RING_IPEHR, D_BXT);
- MMIO_RING_D(RING_INSTPS, D_BXT);
- MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
- MMIO_RING_D(RING_BBSTATE, D_BXT);
- MMIO_RING_D(RING_IPEIR, D_BXT);
-
- MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
-
- MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
- MMIO_D(BXT_RP_STATE_CAP, D_BXT);
- MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
- NULL, bxt_phy_ctl_family_write);
- MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
- NULL, bxt_phy_ctl_family_write);
- MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
- MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
- MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
- MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
- NULL, bxt_port_pll_enable_write);
- MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
- NULL, bxt_port_pll_enable_write);
- MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
- bxt_port_pll_enable_write);
-
- MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
- MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
-
- MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
- MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
-
- MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
- NULL, bxt_pcs_dw12_grp_write);
- MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
- bxt_port_tx_dw3_read, NULL);
- MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
-
- MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
- NULL, bxt_pcs_dw12_grp_write);
- MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
- bxt_port_tx_dw3_read, NULL);
- MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
-
- MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
- NULL, bxt_pcs_dw12_grp_write);
- MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
- bxt_port_tx_dw3_read, NULL);
- MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
- MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
- MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
-
- MMIO_D(BXT_DE_PLL_CTL, D_BXT);
- MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
- MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
- MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
-
- MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
- MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
-
- MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
- MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
- MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
-
- MMIO_D(RC6_CTX_BASE, D_BXT);
-
- MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
- MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
- MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
- MMIO_D(GEN6_GFXPAUSE, D_BXT);
- MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
- MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
- 0, 0, D_BXT, NULL, NULL);
- MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
- 0, 0, D_BXT, NULL, NULL);
- MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
- 0, 0, D_BXT, NULL, NULL);
- MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
- 0, 0, D_BXT, NULL, NULL);
-
- MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
-
- MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
-
- return 0;
-}
+#include "mmio_table.h"
static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
unsigned int offset)
@@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
{
struct intel_gvt_device_info *info = &gvt->device_info;
- struct drm_i915_private *i915 = gvt->gt->i915;
int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
int ret;
@@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
if (!gvt->mmio.mmio_attribute)
return -ENOMEM;
- ret = init_generic_mmio_info(gvt);
- if (ret)
- goto err;
-
- if (IS_BROADWELL(i915)) {
- ret = init_bdw_mmio_info(gvt);
- if (ret)
- goto err;
- } else if (IS_SKYLAKE(i915) ||
- IS_KABYLAKE(i915) ||
- IS_COFFEELAKE(i915) ||
- IS_COMETLAKE(i915)) {
- ret = init_bdw_mmio_info(gvt);
- if (ret)
- goto err;
- ret = init_skl_mmio_info(gvt);
- if (ret)
- goto err;
- } else if (IS_BROXTON(i915)) {
- ret = init_bdw_mmio_info(gvt);
- if (ret)
- goto err;
- ret = init_skl_mmio_info(gvt);
- if (ret)
- goto err;
- ret = init_bxt_mmio_info(gvt);
- if (ret)
- goto err;
+ ret = intel_gvt_init_mmio_info(gvt);
+ if (ret) {
+ intel_gvt_clean_mmio_info(gvt);
+ return ret;
}
gvt->mmio.mmio_block = mmio_blocks;
gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
return 0;
-err:
- intel_gvt_clean_mmio_info(gvt);
- return ret;
}
/**
diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
new file mode 100644
index 000000000000..39a4cb59695a
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
@@ -0,0 +1,1570 @@
+/*
+ * Copyright © 2021 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _GVT_MMIO_TABLE_H_
+#define _GVT_MMIO_TABLE_H_
+
+#ifdef GENERATE_MMIO_TABLE_IN_I915
+#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
+ ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
+ if (ret) \
+ return ret; \
+} while (0)
+#else
+#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
+ ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
+ f, s, am, rm, d, r, w); \
+ if (ret) \
+ return ret; \
+} while (0)
+#endif
+
+#define MMIO_D(reg, d) \
+ MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
+
+#define MMIO_DH(reg, d, r, w) \
+ MMIO_F(reg, 4, 0, 0, 0, d, r, w)
+
+#define MMIO_DFH(reg, d, f, r, w) \
+ MMIO_F(reg, 4, f, 0, 0, d, r, w)
+
+#define MMIO_GM(reg, d, r, w) \
+ MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
+
+#define MMIO_GM_RDR(reg, d, r, w) \
+ MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
+
+#define MMIO_RO(reg, d, f, rm, r, w) \
+ MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
+
+#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
+ MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
+ MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
+ MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
+ MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
+ if (HAS_ENGINE(gvt->gt, VCS1)) \
+ MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
+} while (0)
+
+#define MMIO_RING_D(prefix, d) \
+ MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
+
+#define MMIO_RING_DFH(prefix, d, f, r, w) \
+ MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
+
+#define MMIO_RING_GM(prefix, d, r, w) \
+ MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
+
+#define MMIO_RING_GM_RDR(prefix, d, r, w) \
+ MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
+
+#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
+ MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
+
+static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
+{
+ struct drm_i915_private *dev_priv = gvt->gt->i915;
+
+ int ret;
+
+ MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
+ intel_vgpu_reg_imr_handler);
+
+ MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(SDEISR, D_ALL);
+
+ MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
+
+
+ MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
+ gamw_echo_dev_rw_ia_write);
+
+ MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
+ MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
+ MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
+
+#define RING_REG(base) _MMIO((base) + 0x28)
+ MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x134)
+ MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x6c)
+ MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
+#undef RING_REG
+ MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
+
+ MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
+ MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
+ MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
+ MMIO_D(GEN7_CXT_SIZE, D_ALL);
+
+ MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
+ MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
+ MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
+ MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
+ MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
+
+ /* RING MODE */
+#define RING_REG(base) _MMIO((base) + 0x29c)
+ MMIO_RING_DFH(RING_REG, D_ALL,
+ F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
+ ring_mode_mmio_write);
+#undef RING_REG
+
+ MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
+ mmio_read_from_hw, NULL);
+ MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
+ mmio_read_from_hw, NULL);
+
+ MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
+ F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+
+ /* display */
+ MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_D(_MMIO(0x602a0), D_ALL);
+
+ MMIO_D(_MMIO(0x65050), D_ALL);
+ MMIO_D(_MMIO(0x650b4), D_ALL);
+
+ MMIO_D(_MMIO(0xc4040), D_ALL);
+ MMIO_D(DERRMR, D_ALL);
+
+ MMIO_D(PIPEDSL(PIPE_A), D_ALL);
+ MMIO_D(PIPEDSL(PIPE_B), D_ALL);
+ MMIO_D(PIPEDSL(PIPE_C), D_ALL);
+ MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
+
+ MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
+ MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
+ MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
+ MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
+
+ MMIO_D(PIPESTAT(PIPE_A), D_ALL);
+ MMIO_D(PIPESTAT(PIPE_B), D_ALL);
+ MMIO_D(PIPESTAT(PIPE_C), D_ALL);
+ MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
+
+ MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
+ MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
+ MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
+ MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
+
+ MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
+ MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
+ MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
+ MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
+
+ MMIO_D(CURCNTR(PIPE_A), D_ALL);
+ MMIO_D(CURCNTR(PIPE_B), D_ALL);
+ MMIO_D(CURCNTR(PIPE_C), D_ALL);
+
+ MMIO_D(CURPOS(PIPE_A), D_ALL);
+ MMIO_D(CURPOS(PIPE_B), D_ALL);
+ MMIO_D(CURPOS(PIPE_C), D_ALL);
+
+ MMIO_D(CURBASE(PIPE_A), D_ALL);
+ MMIO_D(CURBASE(PIPE_B), D_ALL);
+ MMIO_D(CURBASE(PIPE_C), D_ALL);
+
+ MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
+ MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
+ MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
+
+ MMIO_D(_MMIO(0x700ac), D_ALL);
+ MMIO_D(_MMIO(0x710ac), D_ALL);
+ MMIO_D(_MMIO(0x720ac), D_ALL);
+
+ MMIO_D(_MMIO(0x70090), D_ALL);
+ MMIO_D(_MMIO(0x70094), D_ALL);
+ MMIO_D(_MMIO(0x70098), D_ALL);
+ MMIO_D(_MMIO(0x7009c), D_ALL);
+
+ MMIO_D(DSPCNTR(PIPE_A), D_ALL);
+ MMIO_D(DSPADDR(PIPE_A), D_ALL);
+ MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
+ MMIO_D(DSPPOS(PIPE_A), D_ALL);
+ MMIO_D(DSPSIZE(PIPE_A), D_ALL);
+ MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
+ MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
+ MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
+ MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(DSPCNTR(PIPE_B), D_ALL);
+ MMIO_D(DSPADDR(PIPE_B), D_ALL);
+ MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
+ MMIO_D(DSPPOS(PIPE_B), D_ALL);
+ MMIO_D(DSPSIZE(PIPE_B), D_ALL);
+ MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
+ MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
+ MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
+ MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(DSPCNTR(PIPE_C), D_ALL);
+ MMIO_D(DSPADDR(PIPE_C), D_ALL);
+ MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
+ MMIO_D(DSPPOS(PIPE_C), D_ALL);
+ MMIO_D(DSPSIZE(PIPE_C), D_ALL);
+ MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
+ MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
+ MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
+ MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(SPRCTL(PIPE_A), D_ALL);
+ MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
+ MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
+ MMIO_D(SPRPOS(PIPE_A), D_ALL);
+ MMIO_D(SPRSIZE(PIPE_A), D_ALL);
+ MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
+ MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
+ MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
+ MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
+ MMIO_D(SPROFFSET(PIPE_A), D_ALL);
+ MMIO_D(SPRSCALE(PIPE_A), D_ALL);
+ MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
+ MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(SPRCTL(PIPE_B), D_ALL);
+ MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
+ MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
+ MMIO_D(SPRPOS(PIPE_B), D_ALL);
+ MMIO_D(SPRSIZE(PIPE_B), D_ALL);
+ MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
+ MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
+ MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
+ MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
+ MMIO_D(SPROFFSET(PIPE_B), D_ALL);
+ MMIO_D(SPRSCALE(PIPE_B), D_ALL);
+ MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
+ MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(SPRCTL(PIPE_C), D_ALL);
+ MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
+ MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
+ MMIO_D(SPRPOS(PIPE_C), D_ALL);
+ MMIO_D(SPRSIZE(PIPE_C), D_ALL);
+ MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
+ MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
+ MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
+ MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
+ MMIO_D(SPROFFSET(PIPE_C), D_ALL);
+ MMIO_D(SPRSCALE(PIPE_C), D_ALL);
+ MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
+ MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
+ reg50080_mmio_write);
+
+ MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
+ MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
+ MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
+ MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
+ MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
+ MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
+ MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
+ MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
+
+ MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
+ MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
+ MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
+ MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
+ MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
+ MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
+ MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
+ MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
+
+ MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
+ MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
+ MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
+ MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
+ MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
+ MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
+ MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
+ MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
+
+ MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
+ MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
+ MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
+ MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
+ MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
+ MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
+ MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
+ MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
+
+ MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
+ MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
+
+ MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
+ MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
+
+ MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
+ MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
+
+ MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
+ MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
+
+ MMIO_D(PF_CTL(PIPE_A), D_ALL);
+ MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
+ MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
+ MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
+ MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
+
+ MMIO_D(PF_CTL(PIPE_B), D_ALL);
+ MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
+ MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
+ MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
+ MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
+
+ MMIO_D(PF_CTL(PIPE_C), D_ALL);
+ MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
+ MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
+ MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
+ MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
+
+ MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
+ MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
+ MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
+ MMIO_D(WM1_LP_ILK, D_ALL);
+ MMIO_D(WM2_LP_ILK, D_ALL);
+ MMIO_D(WM3_LP_ILK, D_ALL);
+ MMIO_D(WM1S_LP_ILK, D_ALL);
+ MMIO_D(WM2S_LP_IVB, D_ALL);
+ MMIO_D(WM3S_LP_IVB, D_ALL);
+
+ MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
+ MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
+ MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
+ MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
+
+ MMIO_D(_MMIO(0x48268), D_ALL);
+
+ MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
+ gmbus_mmio_write);
+ MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
+ dp_aux_ch_ctl_mmio_write);
+ MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
+ dp_aux_ch_ctl_mmio_write);
+ MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
+ dp_aux_ch_ctl_mmio_write);
+
+ MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
+
+ MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
+ MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
+
+ MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
+ MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
+ MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
+ MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
+ MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
+ MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
+ MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
+ MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
+ MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
+
+ MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
+
+ MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
+
+ MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
+ MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
+
+ MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
+ MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
+ MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
+
+ MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
+ MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
+ MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
+
+ MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
+ MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
+ MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
+
+ MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
+ MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
+ MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
+
+ MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
+ MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
+ MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
+ MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
+ MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
+ MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
+
+ MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
+ MMIO_D(PCH_PP_DIVISOR, D_ALL);
+ MMIO_D(PCH_PP_STATUS, D_ALL);
+ MMIO_D(PCH_LVDS, D_ALL);
+ MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
+ MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
+ MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
+ MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
+ MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
+ MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
+ MMIO_D(PCH_DREF_CONTROL, D_ALL);
+ MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
+ MMIO_D(PCH_DPLL_SEL, D_ALL);
+
+ MMIO_D(_MMIO(0x61208), D_ALL);
+ MMIO_D(_MMIO(0x6120c), D_ALL);
+ MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
+ MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
+
+ MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
+ MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
+ MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
+ MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
+ MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
+ MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
+
+ MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
+ PORTA_HOTPLUG_STATUS_MASK
+ | PORTB_HOTPLUG_STATUS_MASK
+ | PORTC_HOTPLUG_STATUS_MASK
+ | PORTD_HOTPLUG_STATUS_MASK,
+ NULL, NULL);
+
+ MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
+ MMIO_D(FUSE_STRAP, D_ALL);
+ MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
+
+ MMIO_D(DISP_ARB_CTL, D_ALL);
+ MMIO_D(DISP_ARB_CTL2, D_ALL);
+
+ MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
+ MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
+ MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
+
+ MMIO_D(SOUTH_CHICKEN1, D_ALL);
+ MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
+ MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
+ MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
+ MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
+ MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
+ MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
+
+ MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
+ MMIO_D(ILK_DPFC_CONTROL, D_ALL);
+ MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
+ MMIO_D(ILK_DPFC_STATUS, D_ALL);
+ MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
+ MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
+ MMIO_D(ILK_FBC_RT_BASE, D_ALL);
+
+ MMIO_D(IPS_CTL, D_ALL);
+
+ MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
+
+ MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
+
+ MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
+ MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
+
+ MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
+ MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
+ MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
+ MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
+ MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
+ MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
+ MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(_MMIO(0x60110), D_ALL);
+ MMIO_D(_MMIO(0x61110), D_ALL);
+ MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+ MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+ MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+ MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+ MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+ MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
+
+ MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
+ MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
+ MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
+ MMIO_D(SPLL_CTL, D_ALL);
+ MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
+ MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
+ MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
+ MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
+ MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
+ MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
+ MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
+ MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
+ MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
+ MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
+
+ MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
+ MMIO_D(_MMIO(0x46508), D_ALL);
+
+ MMIO_D(_MMIO(0x49080), D_ALL);
+ MMIO_D(_MMIO(0x49180), D_ALL);
+ MMIO_D(_MMIO(0x49280), D_ALL);
+
+ MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
+ MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
+ MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
+
+ MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
+ MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
+ MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
+
+ MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
+ MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
+ MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
+
+ MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
+ MMIO_D(SBI_ADDR, D_ALL);
+ MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
+ MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
+ MMIO_D(PIXCLK_GATE, D_ALL);
+
+ MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
+ dp_aux_ch_ctl_mmio_write);
+
+ MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+ MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
+
+ MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
+ MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
+ MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
+ MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
+ MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
+
+ MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
+ MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
+ MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
+ MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
+ MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
+
+ MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
+ MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
+ MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
+
+ MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
+ MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
+ MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
+ MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
+
+ MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
+ MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
+ MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
+ MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
+
+ MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
+ MMIO_D(FORCEWAKE_ACK, D_ALL);
+ MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
+ MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
+ MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
+ MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
+ MMIO_D(ECOBUS, D_ALL);
+ MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
+ MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
+ MMIO_D(GEN6_RPNSWREQ, D_ALL);
+ MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
+ MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
+ MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
+ MMIO_D(GEN6_RPSTAT1, D_ALL);
+ MMIO_D(GEN6_RP_CONTROL, D_ALL);
+ MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
+ MMIO_D(GEN6_RP_CUR_UP, D_ALL);
+ MMIO_D(GEN6_RP_PREV_UP, D_ALL);
+ MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
+ MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
+ MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
+ MMIO_D(GEN6_RP_UP_EI, D_ALL);
+ MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
+ MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
+ MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
+ MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
+ MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
+ MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
+ MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
+ MMIO_D(GEN6_RC_SLEEP, D_ALL);
+ MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
+ MMIO_D(GEN6_PMINTRMSK, D_ALL);
+ MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
+
+ MMIO_D(RSTDBYCTL, D_ALL);
+
+ MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
+ MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
+ MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
+
+ MMIO_D(TILECTL, D_ALL);
+
+ MMIO_D(GEN6_UCGCTL1, D_ALL);
+ MMIO_D(GEN6_UCGCTL2, D_ALL);
+
+ MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_D(GEN6_PCODE_DATA, D_ALL);
+ MMIO_D(_MMIO(0x13812c), D_ALL);
+ MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
+ MMIO_D(HSW_EDRAM_CAP, D_ALL);
+ MMIO_D(HSW_IDICR, D_ALL);
+ MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
+
+ MMIO_D(_MMIO(0x3c), D_ALL);
+ MMIO_D(_MMIO(0x860), D_ALL);
+ MMIO_D(ECOSKPD, D_ALL);
+ MMIO_D(_MMIO(0x121d0), D_ALL);
+ MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
+ MMIO_D(_MMIO(0x41d0), D_ALL);
+ MMIO_D(GAC_ECO_BITS, D_ALL);
+ MMIO_D(_MMIO(0x6200), D_ALL);
+ MMIO_D(_MMIO(0x6204), D_ALL);
+ MMIO_D(_MMIO(0x6208), D_ALL);
+ MMIO_D(_MMIO(0x7118), D_ALL);
+ MMIO_D(_MMIO(0x7180), D_ALL);
+ MMIO_D(_MMIO(0x7408), D_ALL);
+ MMIO_D(_MMIO(0x7c00), D_ALL);
+ MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
+ MMIO_D(_MMIO(0x911c), D_ALL);
+ MMIO_D(_MMIO(0x9120), D_ALL);
+ MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_D(GAB_CTL, D_ALL);
+ MMIO_D(_MMIO(0x48800), D_ALL);
+ MMIO_D(_MMIO(0xce044), D_ALL);
+ MMIO_D(_MMIO(0xe6500), D_ALL);
+ MMIO_D(_MMIO(0xe6504), D_ALL);
+ MMIO_D(_MMIO(0xe6600), D_ALL);
+ MMIO_D(_MMIO(0xe6604), D_ALL);
+ MMIO_D(_MMIO(0xe6700), D_ALL);
+ MMIO_D(_MMIO(0xe6704), D_ALL);
+ MMIO_D(_MMIO(0xe6800), D_ALL);
+ MMIO_D(_MMIO(0xe6804), D_ALL);
+ MMIO_D(PCH_GMBUS4, D_ALL);
+ MMIO_D(PCH_GMBUS5, D_ALL);
+
+ MMIO_D(_MMIO(0x902c), D_ALL);
+ MMIO_D(_MMIO(0xec008), D_ALL);
+ MMIO_D(_MMIO(0xec00c), D_ALL);
+ MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
+ MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
+ MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
+ MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
+ MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
+ MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
+ MMIO_D(_MMIO(0xec408), D_ALL);
+ MMIO_D(_MMIO(0xec40c), D_ALL);
+ MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
+ MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
+ MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
+ MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
+ MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
+ MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
+ MMIO_D(_MMIO(0xfc810), D_ALL);
+ MMIO_D(_MMIO(0xfc81c), D_ALL);
+ MMIO_D(_MMIO(0xfc828), D_ALL);
+ MMIO_D(_MMIO(0xfc834), D_ALL);
+ MMIO_D(_MMIO(0xfcc00), D_ALL);
+ MMIO_D(_MMIO(0xfcc0c), D_ALL);
+ MMIO_D(_MMIO(0xfcc18), D_ALL);
+ MMIO_D(_MMIO(0xfcc24), D_ALL);
+ MMIO_D(_MMIO(0xfd000), D_ALL);
+ MMIO_D(_MMIO(0xfd00c), D_ALL);
+ MMIO_D(_MMIO(0xfd018), D_ALL);
+ MMIO_D(_MMIO(0xfd024), D_ALL);
+ MMIO_D(_MMIO(0xfd034), D_ALL);
+
+ MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
+ MMIO_D(_MMIO(0x2054), D_ALL);
+ MMIO_D(_MMIO(0x12054), D_ALL);
+ MMIO_D(_MMIO(0x22054), D_ALL);
+ MMIO_D(_MMIO(0x1a054), D_ALL);
+
+ MMIO_D(_MMIO(0x44070), D_ALL);
+ MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
+ MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
+ MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+
+ MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
+ MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
+ MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
+ MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
+ MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
+ MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
+ MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
+ MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
+ MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
+
+ return 0;
+}
+
+static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
+{
+ struct drm_i915_private *dev_priv = gvt->gt->i915;
+ int ret;
+
+ MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
+ intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
+
+ MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
+
+ MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
+
+ MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
+ MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
+ MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
+ MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
+
+ MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
+ intel_vgpu_reg_master_irq_handler);
+
+ MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
+ mmio_read_from_hw, NULL);
+
+#define RING_REG(base) _MMIO((base) + 0xd0)
+ MMIO_RING_F(RING_REG, 4, F_RO, 0,
+ ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
+ ring_reset_ctl_write);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x230)
+ MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x234)
+ MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
+ NULL, NULL);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x244)
+ MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x370)
+ MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
+#undef RING_REG
+
+#define RING_REG(base) _MMIO((base) + 0x3a0)
+ MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
+#undef RING_REG
+
+ MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
+ MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
+ MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
+ MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
+ MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
+ MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
+
+ MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
+
+ MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
+ MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
+
+ MMIO_D(GAMTARBMODE, D_BDW_PLUS);
+
+#define RING_REG(base) _MMIO((base) + 0x270)
+ MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
+#undef RING_REG
+
+ MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
+
+ MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
+ MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
+ MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
+
+ MMIO_D(WM_MISC, D_BDW);
+ MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
+
+ MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
+
+ MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
+
+ MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
+ MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
+ MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
+
+ MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
+ MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
+ MMIO_D(_MMIO(0xb110), D_BDW);
+ MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
+
+ MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
+ D_BDW_PLUS, NULL, force_nonpriv_write);
+
+ MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
+
+ MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
+ MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
+
+ MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
+
+ MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
+
+ MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
+ MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
+
+ MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ return 0;
+}
+
+static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
+{
+ struct drm_i915_private *dev_priv = gvt->gt->i915;
+ int ret;
+
+ MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
+ MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
+ MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
+ MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
+
+ MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
+ dp_aux_ch_ctl_mmio_write);
+ MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
+ dp_aux_ch_ctl_mmio_write);
+ MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
+ dp_aux_ch_ctl_mmio_write);
+
+ MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
+ MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
+
+ MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
+
+ MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
+ MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
+ MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
+ MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
+ MMIO_D(DC_STATE_EN, D_SKL_PLUS);
+ MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
+ MMIO_D(CDCLK_CTL, D_SKL_PLUS);
+ MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
+ MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
+ MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
+ MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
+ MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
+ MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
+ MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
+ MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
+ MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
+ MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
+ MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
+
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
+
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
+
+ MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
+ MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
+
+ MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+
+ MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+
+ MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+
+ MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+ MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
+
+ MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
+
+ MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
+ MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
+ MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
+
+ MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_D(SKL_DFSM, D_SKL_PLUS);
+ MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
+
+ MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
+ NULL, NULL);
+ MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
+ NULL, NULL);
+
+ MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
+ MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
+ MMIO_D(RC6_LOCATION, D_SKL_PLUS);
+ MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
+ F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+
+ /* TRTT */
+ MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
+ NULL, gen9_trtte_write);
+ MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
+ NULL, gen9_trtt_chicken_write);
+
+ MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
+
+ MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
+
+ MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
+ MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
+
+ MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
+ MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
+ MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
+
+ MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
+ MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
+
+ MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
+ MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
+
+ MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
+#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
+ MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, csfe_chicken1_mmio_write);
+#undef CSFE_CHICKEN1_REG
+ MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+ MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
+
+ MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
+ MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
+
+ return 0;
+}
+
+static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
+{
+ struct drm_i915_private *dev_priv = gvt->gt->i915;
+ int ret;
+
+ MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
+
+ MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
+ MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
+ MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
+ MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
+ MMIO_D(ERROR_GEN6, D_BXT);
+ MMIO_D(DONE_REG, D_BXT);
+ MMIO_D(EIR, D_BXT);
+ MMIO_D(PGTBL_ER, D_BXT);
+ MMIO_D(_MMIO(0x4194), D_BXT);
+ MMIO_D(_MMIO(0x4294), D_BXT);
+ MMIO_D(_MMIO(0x4494), D_BXT);
+
+ MMIO_RING_D(RING_PSMI_CTL, D_BXT);
+ MMIO_RING_D(RING_DMA_FADD, D_BXT);
+ MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
+ MMIO_RING_D(RING_IPEHR, D_BXT);
+ MMIO_RING_D(RING_INSTPS, D_BXT);
+ MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
+ MMIO_RING_D(RING_BBSTATE, D_BXT);
+ MMIO_RING_D(RING_IPEIR, D_BXT);
+
+ MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
+
+ MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
+ MMIO_D(BXT_RP_STATE_CAP, D_BXT);
+ MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
+ NULL, bxt_phy_ctl_family_write);
+ MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
+ NULL, bxt_phy_ctl_family_write);
+ MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
+ MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
+ MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
+ MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
+ NULL, bxt_port_pll_enable_write);
+ MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
+ NULL, bxt_port_pll_enable_write);
+ MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
+ bxt_port_pll_enable_write);
+
+ MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
+
+ MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
+ MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
+
+ MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
+ NULL, bxt_pcs_dw12_grp_write);
+ MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
+ bxt_port_tx_dw3_read, NULL);
+ MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
+
+ MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
+ NULL, bxt_pcs_dw12_grp_write);
+ MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
+ bxt_port_tx_dw3_read, NULL);
+ MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
+
+ MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
+ NULL, bxt_pcs_dw12_grp_write);
+ MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
+ bxt_port_tx_dw3_read, NULL);
+ MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
+ MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
+ MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
+
+ MMIO_D(BXT_DE_PLL_CTL, D_BXT);
+ MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
+ MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
+ MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
+
+ MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
+ MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
+
+ MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
+ MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
+ MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
+
+ MMIO_D(RC6_CTX_BASE, D_BXT);
+
+ MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
+ MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
+ MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
+ MMIO_D(GEN6_GFXPAUSE, D_BXT);
+ MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
+ MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+ 0, 0, D_BXT, NULL, NULL);
+ MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+ 0, 0, D_BXT, NULL, NULL);
+ MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+ 0, 0, D_BXT, NULL, NULL);
+ MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+ 0, 0, D_BXT, NULL, NULL);
+
+ MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
+
+ MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
+
+ return 0;
+}
+
+static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
+{
+ struct drm_i915_private *i915 = gvt->gt->i915;
+ int ret;
+
+ ret = intel_gvt_init_generic_mmio_info(gvt);
+ if (ret)
+ return ret;
+
+ if (IS_BROADWELL(i915)) {
+ ret = intel_gvt_init_bdw_mmio_info(gvt);
+ if (ret)
+ return ret;
+ } else if (IS_SKYLAKE(i915) ||
+ IS_KABYLAKE(i915) ||
+ IS_COFFEELAKE(i915) ||
+ IS_COMETLAKE(i915)) {
+ ret = intel_gvt_init_bdw_mmio_info(gvt);
+ if (ret)
+ return ret;
+ ret = intel_gvt_init_skl_mmio_info(gvt);
+ if (ret)
+ return ret;
+ } else if (IS_BROXTON(i915)) {
+ ret = intel_gvt_init_bdw_mmio_info(gvt);
+ if (ret)
+ return ret;
+ ret = intel_gvt_init_skl_mmio_info(gvt);
+ if (ret)
+ return ret;
+ ret = intel_gvt_init_bxt_mmio_info(gvt);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index 244cc7320b54..05bd2f8e9d94 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -133,6 +133,12 @@
#define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
#define VF_GUARDBAND _MMIO(0x83a4)
+/* XXX FIXME i915 has changed PP_XXX definition */
+#define PCH_PP_STATUS _MMIO(0xc7200)
+#define PCH_PP_CONTROL _MMIO(0xc7204)
+#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
+#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
+#define PCH_PP_DIVISOR _MMIO(0xc7210)
#define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
#endif
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index 4e70c1a9ef2e..64846d9bff0b 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
dev_priv->params.enable_gvt = 0;
}
+#define GENERATE_MMIO_TABLE_IN_I915
+static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
+{
+ return 0;
+}
+
+#include "gvt/reg.h"
+#include "gvt/mmio_table.h"
+#undef GENERATE_MMIO_TABLE_IN_I915
+
+
/**
* intel_gvt_init - initialize GVT components
* @dev_priv: drm i915 private data
--
2.25.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 2/3] i915/gvt: save the initial HW state snapshot in i915.
2021-11-08 21:27 ` [Intel-gfx] " Zhi Wang
@ 2021-11-08 21:27 ` Zhi Wang
-1 siblings, 0 replies; 35+ messages in thread
From: Zhi Wang @ 2021-11-08 21:27 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, zhenyuw, zhi.a.wang,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
Cc: Zhi Wang
From: Zhi Wang <zhi.wang.linux@gmail.com>
Save the inital HW state snapshot in i915 so that the rest code of GVT-g
can be moved into a dedicated module while it can still get a clean
initial HW state saved at the correct time during the initialization of
i915. The futhrer vGPU created by GVT-g will use this HW state as the
initial HW state.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
---
drivers/gpu/drm/i915/gvt/gvt.c | 31 +------------
drivers/gpu/drm/i915/gvt/gvt.h | 6 +++
drivers/gpu/drm/i915/intel_gvt.c | 75 ++++++++++++++++++++++++++++++--
3 files changed, 80 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index cbac409f6c8a..4b3b47892453 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -63,23 +63,6 @@ static const struct intel_gvt_ops intel_gvt_ops = {
.emulate_hotplug = intel_vgpu_emulate_hotplug,
};
-static void init_device_info(struct intel_gvt *gvt)
-{
- struct intel_gvt_device_info *info = &gvt->device_info;
- struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev);
-
- info->max_support_vgpus = 8;
- info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE;
- info->mmio_size = 2 * 1024 * 1024;
- info->mmio_bar = 0;
- info->gtt_start_offset = 8 * 1024 * 1024;
- info->gtt_entry_size = 8;
- info->gtt_entry_size_shift = 3;
- info->gmadr_bytes_in_cmd = 8;
- info->max_surface_size = 36 * 1024 * 1024;
- info->msi_cap_offset = pdev->msi_cap;
-}
-
static void intel_gvt_test_and_emulate_vblank(struct intel_gvt *gvt)
{
struct intel_vgpu *vgpu;
@@ -188,27 +171,19 @@ void intel_gvt_clean_device(struct drm_i915_private *i915)
*/
int intel_gvt_init_device(struct drm_i915_private *i915)
{
- struct intel_gvt *gvt;
+ struct intel_gvt *gvt = i915->gvt;
struct intel_vgpu *vgpu;
int ret;
- if (drm_WARN_ON(&i915->drm, i915->gvt))
+ if (drm_WARN_ON(&i915->drm, !i915->gvt))
return -EEXIST;
- gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL);
- if (!gvt)
- return -ENOMEM;
-
gvt_dbg_core("init gvt device\n");
idr_init_base(&gvt->vgpu_idr, 1);
spin_lock_init(&gvt->scheduler.mmio_context_lock);
mutex_init(&gvt->lock);
mutex_init(&gvt->sched_lock);
- gvt->gt = &i915->gt;
- i915->gvt = gvt;
-
- init_device_info(gvt);
ret = intel_gvt_setup_mmio_info(gvt);
if (ret)
@@ -281,8 +256,6 @@ int intel_gvt_init_device(struct drm_i915_private *i915)
intel_gvt_clean_mmio_info(gvt);
out_clean_idr:
idr_destroy(&gvt->vgpu_idr);
- kfree(gvt);
- i915->gvt = NULL;
return ret;
}
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 0c0615602343..1defee730cf3 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -296,6 +296,11 @@ struct intel_vgpu_type {
enum intel_vgpu_edid resolution;
};
+struct intel_gvt_hw_state {
+ void *cfg_space;
+ void *mmio;
+};
+
struct intel_gvt {
/* GVT scope lock, protect GVT itself, and all resource currently
* not yet protected by special locks(vgpu and scheduler lock).
@@ -311,6 +316,7 @@ struct intel_gvt {
struct intel_gvt_gm gm;
struct intel_gvt_fence fence;
struct intel_gvt_mmio mmio;
+ struct intel_gvt_hw_state hw_state;
struct intel_gvt_firmware firmware;
struct intel_gvt_irq irq;
struct intel_gvt_gtt gtt;
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index 64846d9bff0b..4fd51974bd35 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -87,8 +87,12 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
}
#define GENERATE_MMIO_TABLE_IN_I915
-static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
+static int new_mmio_info(struct intel_gvt *gvt, u32 offset)
{
+ void *mmio = gvt->hw_state.mmio;
+
+ *(u32 *)(mmio + offset) = intel_uncore_read_notrace(gvt->gt->uncore,
+ _MMIO(offset));
return 0;
}
@@ -96,6 +100,22 @@ static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
#include "gvt/mmio_table.h"
#undef GENERATE_MMIO_TABLE_IN_I915
+static void init_device_info(struct intel_gvt *gvt)
+{
+ struct intel_gvt_device_info *info = &gvt->device_info;
+ struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev);
+
+ info->max_support_vgpus = 8;
+ info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE;
+ info->mmio_size = 2 * 1024 * 1024;
+ info->mmio_bar = 0;
+ info->gtt_start_offset = 8 * 1024 * 1024;
+ info->gtt_entry_size = 8;
+ info->gtt_entry_size_shift = 3;
+ info->gmadr_bytes_in_cmd = 8;
+ info->max_surface_size = 36 * 1024 * 1024;
+ info->msi_cap_offset = pdev->msi_cap;
+}
/**
* intel_gvt_init - initialize GVT components
@@ -109,7 +129,13 @@ static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
*/
int intel_gvt_init(struct drm_i915_private *dev_priv)
{
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct intel_gvt *gvt = NULL;
+ struct intel_gvt_hw_state *hw_state;
+ struct intel_gvt_device_info *info;
+ void *mem;
int ret;
+ int i;
if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
@@ -123,17 +149,54 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
if (intel_uc_wants_guc_submission(&dev_priv->gt.uc)) {
drm_err(&dev_priv->drm,
"i915 GVT-g loading failed due to Graphics virtualization is not yet supported with GuC submission\n");
- return -EIO;
+ goto bail;
}
+ gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL);
+ if (!gvt)
+ goto bail;
+
+ gvt->gt = &dev_priv->gt;
+ hw_state = &gvt->hw_state;
+ info = &gvt->device_info;
+
+ init_device_info(gvt);
+
+ mem = kmalloc(info->cfg_space_size, GFP_KERNEL);
+ if (!mem)
+ goto err_cfg_space;
+
+ hw_state->cfg_space = mem;
+
+ mem = vmalloc(info->mmio_size);
+ if (!mem)
+ goto err_mmio;
+
+ hw_state->mmio = mem;
+
+ for (i = 0; i < PCI_CFG_SPACE_EXP_SIZE; i += 4)
+ pci_read_config_dword(pdev, i, hw_state->cfg_space + i);
+
+ ret = intel_gvt_init_mmio_info(gvt);
+ if (ret)
+ goto err_mmio_info;
+
+ dev_priv->gvt = gvt;
+
ret = intel_gvt_init_device(dev_priv);
if (ret) {
drm_dbg(&dev_priv->drm, "Fail to init GVT device\n");
- goto bail;
+ goto err_mmio_info;
}
return 0;
+err_mmio_info:
+ vfree(hw_state->mmio);
+err_mmio:
+ kfree(hw_state->cfg_space);
+err_cfg_space:
+ kfree(gvt);
bail:
dev_priv->params.enable_gvt = 0;
return 0;
@@ -154,10 +217,16 @@ static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
*/
void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)
{
+ struct intel_gvt *gvt = dev_priv->gvt;
+
if (!intel_gvt_active(dev_priv))
return;
+ kfree(gvt->hw_state.cfg_space);
+ vfree(gvt->hw_state.mmio);
intel_gvt_clean_device(dev_priv);
+ kfree(gvt);
+ dev_priv->gvt = NULL;
}
/**
--
2.25.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 2/3] i915/gvt: save the initial HW state snapshot in i915.
@ 2021-11-08 21:27 ` Zhi Wang
0 siblings, 0 replies; 35+ messages in thread
From: Zhi Wang @ 2021-11-08 21:27 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, zhenyuw, zhi.a.wang,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
Cc: Zhi Wang
From: Zhi Wang <zhi.wang.linux@gmail.com>
Save the inital HW state snapshot in i915 so that the rest code of GVT-g
can be moved into a dedicated module while it can still get a clean
initial HW state saved at the correct time during the initialization of
i915. The futhrer vGPU created by GVT-g will use this HW state as the
initial HW state.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
---
drivers/gpu/drm/i915/gvt/gvt.c | 31 +------------
drivers/gpu/drm/i915/gvt/gvt.h | 6 +++
drivers/gpu/drm/i915/intel_gvt.c | 75 ++++++++++++++++++++++++++++++--
3 files changed, 80 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index cbac409f6c8a..4b3b47892453 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -63,23 +63,6 @@ static const struct intel_gvt_ops intel_gvt_ops = {
.emulate_hotplug = intel_vgpu_emulate_hotplug,
};
-static void init_device_info(struct intel_gvt *gvt)
-{
- struct intel_gvt_device_info *info = &gvt->device_info;
- struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev);
-
- info->max_support_vgpus = 8;
- info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE;
- info->mmio_size = 2 * 1024 * 1024;
- info->mmio_bar = 0;
- info->gtt_start_offset = 8 * 1024 * 1024;
- info->gtt_entry_size = 8;
- info->gtt_entry_size_shift = 3;
- info->gmadr_bytes_in_cmd = 8;
- info->max_surface_size = 36 * 1024 * 1024;
- info->msi_cap_offset = pdev->msi_cap;
-}
-
static void intel_gvt_test_and_emulate_vblank(struct intel_gvt *gvt)
{
struct intel_vgpu *vgpu;
@@ -188,27 +171,19 @@ void intel_gvt_clean_device(struct drm_i915_private *i915)
*/
int intel_gvt_init_device(struct drm_i915_private *i915)
{
- struct intel_gvt *gvt;
+ struct intel_gvt *gvt = i915->gvt;
struct intel_vgpu *vgpu;
int ret;
- if (drm_WARN_ON(&i915->drm, i915->gvt))
+ if (drm_WARN_ON(&i915->drm, !i915->gvt))
return -EEXIST;
- gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL);
- if (!gvt)
- return -ENOMEM;
-
gvt_dbg_core("init gvt device\n");
idr_init_base(&gvt->vgpu_idr, 1);
spin_lock_init(&gvt->scheduler.mmio_context_lock);
mutex_init(&gvt->lock);
mutex_init(&gvt->sched_lock);
- gvt->gt = &i915->gt;
- i915->gvt = gvt;
-
- init_device_info(gvt);
ret = intel_gvt_setup_mmio_info(gvt);
if (ret)
@@ -281,8 +256,6 @@ int intel_gvt_init_device(struct drm_i915_private *i915)
intel_gvt_clean_mmio_info(gvt);
out_clean_idr:
idr_destroy(&gvt->vgpu_idr);
- kfree(gvt);
- i915->gvt = NULL;
return ret;
}
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 0c0615602343..1defee730cf3 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -296,6 +296,11 @@ struct intel_vgpu_type {
enum intel_vgpu_edid resolution;
};
+struct intel_gvt_hw_state {
+ void *cfg_space;
+ void *mmio;
+};
+
struct intel_gvt {
/* GVT scope lock, protect GVT itself, and all resource currently
* not yet protected by special locks(vgpu and scheduler lock).
@@ -311,6 +316,7 @@ struct intel_gvt {
struct intel_gvt_gm gm;
struct intel_gvt_fence fence;
struct intel_gvt_mmio mmio;
+ struct intel_gvt_hw_state hw_state;
struct intel_gvt_firmware firmware;
struct intel_gvt_irq irq;
struct intel_gvt_gtt gtt;
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index 64846d9bff0b..4fd51974bd35 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -87,8 +87,12 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
}
#define GENERATE_MMIO_TABLE_IN_I915
-static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
+static int new_mmio_info(struct intel_gvt *gvt, u32 offset)
{
+ void *mmio = gvt->hw_state.mmio;
+
+ *(u32 *)(mmio + offset) = intel_uncore_read_notrace(gvt->gt->uncore,
+ _MMIO(offset));
return 0;
}
@@ -96,6 +100,22 @@ static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
#include "gvt/mmio_table.h"
#undef GENERATE_MMIO_TABLE_IN_I915
+static void init_device_info(struct intel_gvt *gvt)
+{
+ struct intel_gvt_device_info *info = &gvt->device_info;
+ struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev);
+
+ info->max_support_vgpus = 8;
+ info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE;
+ info->mmio_size = 2 * 1024 * 1024;
+ info->mmio_bar = 0;
+ info->gtt_start_offset = 8 * 1024 * 1024;
+ info->gtt_entry_size = 8;
+ info->gtt_entry_size_shift = 3;
+ info->gmadr_bytes_in_cmd = 8;
+ info->max_surface_size = 36 * 1024 * 1024;
+ info->msi_cap_offset = pdev->msi_cap;
+}
/**
* intel_gvt_init - initialize GVT components
@@ -109,7 +129,13 @@ static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
*/
int intel_gvt_init(struct drm_i915_private *dev_priv)
{
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct intel_gvt *gvt = NULL;
+ struct intel_gvt_hw_state *hw_state;
+ struct intel_gvt_device_info *info;
+ void *mem;
int ret;
+ int i;
if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
@@ -123,17 +149,54 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
if (intel_uc_wants_guc_submission(&dev_priv->gt.uc)) {
drm_err(&dev_priv->drm,
"i915 GVT-g loading failed due to Graphics virtualization is not yet supported with GuC submission\n");
- return -EIO;
+ goto bail;
}
+ gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL);
+ if (!gvt)
+ goto bail;
+
+ gvt->gt = &dev_priv->gt;
+ hw_state = &gvt->hw_state;
+ info = &gvt->device_info;
+
+ init_device_info(gvt);
+
+ mem = kmalloc(info->cfg_space_size, GFP_KERNEL);
+ if (!mem)
+ goto err_cfg_space;
+
+ hw_state->cfg_space = mem;
+
+ mem = vmalloc(info->mmio_size);
+ if (!mem)
+ goto err_mmio;
+
+ hw_state->mmio = mem;
+
+ for (i = 0; i < PCI_CFG_SPACE_EXP_SIZE; i += 4)
+ pci_read_config_dword(pdev, i, hw_state->cfg_space + i);
+
+ ret = intel_gvt_init_mmio_info(gvt);
+ if (ret)
+ goto err_mmio_info;
+
+ dev_priv->gvt = gvt;
+
ret = intel_gvt_init_device(dev_priv);
if (ret) {
drm_dbg(&dev_priv->drm, "Fail to init GVT device\n");
- goto bail;
+ goto err_mmio_info;
}
return 0;
+err_mmio_info:
+ vfree(hw_state->mmio);
+err_mmio:
+ kfree(hw_state->cfg_space);
+err_cfg_space:
+ kfree(gvt);
bail:
dev_priv->params.enable_gvt = 0;
return 0;
@@ -154,10 +217,16 @@ static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
*/
void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)
{
+ struct intel_gvt *gvt = dev_priv->gvt;
+
if (!intel_gvt_active(dev_priv))
return;
+ kfree(gvt->hw_state.cfg_space);
+ vfree(gvt->hw_state.mmio);
intel_gvt_clean_device(dev_priv);
+ kfree(gvt);
+ dev_priv->gvt = NULL;
}
/**
--
2.25.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 3/3] i915/gvt: Use the initial HW state snapshot saved in i915
2021-11-08 21:27 ` [Intel-gfx] " Zhi Wang
@ 2021-11-08 21:27 ` Zhi Wang
-1 siblings, 0 replies; 35+ messages in thread
From: Zhi Wang @ 2021-11-08 21:27 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, zhenyuw, zhi.a.wang,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
Cc: Zhi Wang
From: Zhi Wang <zhi.wang.linux@gmail.com>
The code of saving initial HW state snapshot has been moved into i915.
Let the GVT-g core logic use that snapshot.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
---
drivers/gpu/drm/i915/gvt/cfg_space.c | 2 +-
drivers/gpu/drm/i915/gvt/firmware.c | 45 ++++------------------------
drivers/gpu/drm/i915/gvt/gvt.h | 2 --
drivers/gpu/drm/i915/gvt/mmio.c | 2 +-
4 files changed, 7 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c
index b490e3db2e38..51588ca95113 100644
--- a/drivers/gpu/drm/i915/gvt/cfg_space.c
+++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
@@ -379,7 +379,7 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
u16 *gmch_ctl;
u8 next;
- memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
+ memcpy(vgpu_cfg_space(vgpu), gvt->hw_state.cfg_space,
info->cfg_space_size);
if (!primary) {
diff --git a/drivers/gpu/drm/i915/gvt/firmware.c b/drivers/gpu/drm/i915/gvt/firmware.c
index 1a8274a3f4b1..a98af544abca 100644
--- a/drivers/gpu/drm/i915/gvt/firmware.c
+++ b/drivers/gpu/drm/i915/gvt/firmware.c
@@ -66,13 +66,6 @@ static struct bin_attribute firmware_attr = {
.mmap = NULL,
};
-static int mmio_snapshot_handler(struct intel_gvt *gvt, u32 offset, void *data)
-{
- *(u32 *)(data + offset) = intel_uncore_read_notrace(gvt->gt->uncore,
- _MMIO(offset));
- return 0;
-}
-
static int expose_firmware_sysfs(struct intel_gvt *gvt)
{
struct intel_gvt_device_info *info = &gvt->device_info;
@@ -81,7 +74,7 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt)
void *firmware;
void *p;
unsigned long size, crc32_start;
- int i, ret;
+ int ret;
size = sizeof(*h) + info->mmio_size + info->cfg_space_size;
firmware = vzalloc(size);
@@ -99,17 +92,11 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt)
p = firmware + h->cfg_space_offset;
- for (i = 0; i < h->cfg_space_size; i += 4)
- pci_read_config_dword(pdev, i, p + i);
-
- memcpy(gvt->firmware.cfg_space, p, info->cfg_space_size);
+ memcpy(gvt->hw_state.cfg_space, p, info->cfg_space_size);
p = firmware + h->mmio_offset;
- /* Take a snapshot of hw mmio registers. */
- intel_gvt_for_each_tracked_mmio(gvt, mmio_snapshot_handler, p);
-
- memcpy(gvt->firmware.mmio, p, info->mmio_size);
+ memcpy(gvt->hw_state.mmio, p, info->mmio_size);
crc32_start = offsetof(struct gvt_firmware_header, crc32) + 4;
h->crc32 = crc32_le(0, firmware + crc32_start, size - crc32_start);
@@ -142,9 +129,6 @@ void intel_gvt_free_firmware(struct intel_gvt *gvt)
{
if (!gvt->firmware.firmware_loaded)
clean_firmware_sysfs(gvt);
-
- kfree(gvt->firmware.cfg_space);
- vfree(gvt->firmware.mmio);
}
static int verify_firmware(struct intel_gvt *gvt,
@@ -204,36 +188,17 @@ static int verify_firmware(struct intel_gvt *gvt,
*/
int intel_gvt_load_firmware(struct intel_gvt *gvt)
{
- struct intel_gvt_device_info *info = &gvt->device_info;
struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev);
struct intel_gvt_firmware *firmware = &gvt->firmware;
struct gvt_firmware_header *h;
const struct firmware *fw;
char *path;
- void *mem;
int ret;
path = kmalloc(PATH_MAX, GFP_KERNEL);
if (!path)
return -ENOMEM;
- mem = kmalloc(info->cfg_space_size, GFP_KERNEL);
- if (!mem) {
- kfree(path);
- return -ENOMEM;
- }
-
- firmware->cfg_space = mem;
-
- mem = vmalloc(info->mmio_size);
- if (!mem) {
- kfree(path);
- kfree(firmware->cfg_space);
- return -ENOMEM;
- }
-
- firmware->mmio = mem;
-
sprintf(path, "%s/vid_0x%04x_did_0x%04x_rid_0x%02x.golden_hw_state",
GVT_FIRMWARE_PATH, pdev->vendor, pdev->device,
pdev->revision);
@@ -256,9 +221,9 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt)
h = (struct gvt_firmware_header *)fw->data;
- memcpy(firmware->cfg_space, fw->data + h->cfg_space_offset,
+ memcpy(gvt->hw_state.cfg_space, fw->data + h->cfg_space_offset,
h->cfg_space_size);
- memcpy(firmware->mmio, fw->data + h->mmio_offset,
+ memcpy(gvt->hw_state.mmio, fw->data + h->mmio_offset,
h->mmio_size);
release_firmware(fw);
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 1defee730cf3..4e2fd564abea 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -280,8 +280,6 @@ struct intel_gvt_mmio {
};
struct intel_gvt_firmware {
- void *cfg_space;
- void *mmio;
bool firmware_loaded;
};
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 24210b1eaec5..63f806113560 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -241,7 +241,7 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
{
struct intel_gvt *gvt = vgpu->gvt;
const struct intel_gvt_device_info *info = &gvt->device_info;
- void *mmio = gvt->firmware.mmio;
+ void *mmio = gvt->hw_state.mmio;
if (dmlr) {
memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
--
2.25.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-gfx] [PATCH 3/3] i915/gvt: Use the initial HW state snapshot saved in i915
@ 2021-11-08 21:27 ` Zhi Wang
0 siblings, 0 replies; 35+ messages in thread
From: Zhi Wang @ 2021-11-08 21:27 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, zhenyuw, zhi.a.wang,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
Cc: Zhi Wang
From: Zhi Wang <zhi.wang.linux@gmail.com>
The code of saving initial HW state snapshot has been moved into i915.
Let the GVT-g core logic use that snapshot.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
---
drivers/gpu/drm/i915/gvt/cfg_space.c | 2 +-
drivers/gpu/drm/i915/gvt/firmware.c | 45 ++++------------------------
drivers/gpu/drm/i915/gvt/gvt.h | 2 --
drivers/gpu/drm/i915/gvt/mmio.c | 2 +-
4 files changed, 7 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c
index b490e3db2e38..51588ca95113 100644
--- a/drivers/gpu/drm/i915/gvt/cfg_space.c
+++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
@@ -379,7 +379,7 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
u16 *gmch_ctl;
u8 next;
- memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
+ memcpy(vgpu_cfg_space(vgpu), gvt->hw_state.cfg_space,
info->cfg_space_size);
if (!primary) {
diff --git a/drivers/gpu/drm/i915/gvt/firmware.c b/drivers/gpu/drm/i915/gvt/firmware.c
index 1a8274a3f4b1..a98af544abca 100644
--- a/drivers/gpu/drm/i915/gvt/firmware.c
+++ b/drivers/gpu/drm/i915/gvt/firmware.c
@@ -66,13 +66,6 @@ static struct bin_attribute firmware_attr = {
.mmap = NULL,
};
-static int mmio_snapshot_handler(struct intel_gvt *gvt, u32 offset, void *data)
-{
- *(u32 *)(data + offset) = intel_uncore_read_notrace(gvt->gt->uncore,
- _MMIO(offset));
- return 0;
-}
-
static int expose_firmware_sysfs(struct intel_gvt *gvt)
{
struct intel_gvt_device_info *info = &gvt->device_info;
@@ -81,7 +74,7 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt)
void *firmware;
void *p;
unsigned long size, crc32_start;
- int i, ret;
+ int ret;
size = sizeof(*h) + info->mmio_size + info->cfg_space_size;
firmware = vzalloc(size);
@@ -99,17 +92,11 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt)
p = firmware + h->cfg_space_offset;
- for (i = 0; i < h->cfg_space_size; i += 4)
- pci_read_config_dword(pdev, i, p + i);
-
- memcpy(gvt->firmware.cfg_space, p, info->cfg_space_size);
+ memcpy(gvt->hw_state.cfg_space, p, info->cfg_space_size);
p = firmware + h->mmio_offset;
- /* Take a snapshot of hw mmio registers. */
- intel_gvt_for_each_tracked_mmio(gvt, mmio_snapshot_handler, p);
-
- memcpy(gvt->firmware.mmio, p, info->mmio_size);
+ memcpy(gvt->hw_state.mmio, p, info->mmio_size);
crc32_start = offsetof(struct gvt_firmware_header, crc32) + 4;
h->crc32 = crc32_le(0, firmware + crc32_start, size - crc32_start);
@@ -142,9 +129,6 @@ void intel_gvt_free_firmware(struct intel_gvt *gvt)
{
if (!gvt->firmware.firmware_loaded)
clean_firmware_sysfs(gvt);
-
- kfree(gvt->firmware.cfg_space);
- vfree(gvt->firmware.mmio);
}
static int verify_firmware(struct intel_gvt *gvt,
@@ -204,36 +188,17 @@ static int verify_firmware(struct intel_gvt *gvt,
*/
int intel_gvt_load_firmware(struct intel_gvt *gvt)
{
- struct intel_gvt_device_info *info = &gvt->device_info;
struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev);
struct intel_gvt_firmware *firmware = &gvt->firmware;
struct gvt_firmware_header *h;
const struct firmware *fw;
char *path;
- void *mem;
int ret;
path = kmalloc(PATH_MAX, GFP_KERNEL);
if (!path)
return -ENOMEM;
- mem = kmalloc(info->cfg_space_size, GFP_KERNEL);
- if (!mem) {
- kfree(path);
- return -ENOMEM;
- }
-
- firmware->cfg_space = mem;
-
- mem = vmalloc(info->mmio_size);
- if (!mem) {
- kfree(path);
- kfree(firmware->cfg_space);
- return -ENOMEM;
- }
-
- firmware->mmio = mem;
-
sprintf(path, "%s/vid_0x%04x_did_0x%04x_rid_0x%02x.golden_hw_state",
GVT_FIRMWARE_PATH, pdev->vendor, pdev->device,
pdev->revision);
@@ -256,9 +221,9 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt)
h = (struct gvt_firmware_header *)fw->data;
- memcpy(firmware->cfg_space, fw->data + h->cfg_space_offset,
+ memcpy(gvt->hw_state.cfg_space, fw->data + h->cfg_space_offset,
h->cfg_space_size);
- memcpy(firmware->mmio, fw->data + h->mmio_offset,
+ memcpy(gvt->hw_state.mmio, fw->data + h->mmio_offset,
h->mmio_size);
release_firmware(fw);
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 1defee730cf3..4e2fd564abea 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -280,8 +280,6 @@ struct intel_gvt_mmio {
};
struct intel_gvt_firmware {
- void *cfg_space;
- void *mmio;
bool firmware_loaded;
};
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 24210b1eaec5..63f806113560 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -241,7 +241,7 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
{
struct intel_gvt *gvt = vgpu->gvt;
const struct intel_gvt_device_info *info = &gvt->device_info;
- void *mmio = gvt->firmware.mmio;
+ void *mmio = gvt->hw_state.mmio;
if (dmlr) {
memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
--
2.25.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-08 21:27 ` [Intel-gfx] " Zhi Wang
@ 2021-11-09 7:00 ` Jani Nikula
-1 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2021-11-09 7:00 UTC (permalink / raw)
To: Zhi Wang, joonas.lahtinen, rodrigo.vivi, zhenyuw, zhi.a.wang,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
Cc: Zhi Wang
On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
> From: Zhi Wang <zhi.wang.linux@gmail.com>
>
> To support the new mdev interfaces and the re-factor patches from
> Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
> MMIO snapshot still needs to be saved in i915 so that the inital clean HW
> state can be used for the further vGPU. Seperate the tracked MMIO table
> from GVT-g, so that GVT-g and i915 can both use it.
Do you really have to both put code in a header and then include that in
multiple places?
I think you may need to rethink the whole approach, maybe make them
actual tables instead of code.
BR,
Jani.
>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: Zhi Wang <zhi.a.wang@intel.com>
> Cc: Christoph Hellwig <hch@lst.de>
> Cc: Jason Gunthorpe <jgg@nvidia.com>
> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
> drivers/gpu/drm/i915/gvt/reg.h | 6 +
> drivers/gpu/drm/i915/intel_gvt.c | 11 +
> 4 files changed, 1592 insertions(+), 1534 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index cde0a477fb49..6a08d362bf66 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -41,13 +41,6 @@
> #include "i915_pvinfo.h"
> #include "display/intel_display_types.h"
>
> -/* XXX FIXME i915 has changed PP_XXX definition */
> -#define PCH_PP_STATUS _MMIO(0xc7200)
> -#define PCH_PP_CONTROL _MMIO(0xc7204)
> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
> -
> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
> {
> struct drm_i915_private *i915 = gvt->gt->i915;
> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
> return 0;
> }
>
> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
> - f, s, am, rm, d, r, w); \
> - if (ret) \
> - return ret; \
> -} while (0)
> -
> -#define MMIO_D(reg, d) \
> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
> -
> -#define MMIO_DH(reg, d, r, w) \
> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
> -
> -#define MMIO_DFH(reg, d, f, r, w) \
> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
> -
> -#define MMIO_GM(reg, d, r, w) \
> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
> -
> -#define MMIO_GM_RDR(reg, d, r, w) \
> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
> -
> -#define MMIO_RO(reg, d, f, rm, r, w) \
> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
> -
> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> - if (HAS_ENGINE(gvt->gt, VCS1)) \
> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
> -} while (0)
> -
> -#define MMIO_RING_D(prefix, d) \
> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
> -
> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
> -
> -#define MMIO_RING_GM(prefix, d, r, w) \
> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
> -
> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
> -
> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
> -
> -static int init_generic_mmio_info(struct intel_gvt *gvt)
> -{
> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> - int ret;
> -
> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
> - intel_vgpu_reg_imr_handler);
> -
> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(SDEISR, D_ALL);
> -
> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
> -
> -
> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
> - gamw_echo_dev_rw_ia_write);
> -
> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> -
> -#define RING_REG(base) _MMIO((base) + 0x28)
> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x134)
> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x6c)
> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
> -#undef RING_REG
> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
> -
> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
> -
> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
> -
> - /* RING MODE */
> -#define RING_REG(base) _MMIO((base) + 0x29c)
> - MMIO_RING_DFH(RING_REG, D_ALL,
> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
> - ring_mode_mmio_write);
> -#undef RING_REG
> -
> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
> - mmio_read_from_hw, NULL);
> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
> - mmio_read_from_hw, NULL);
> -
> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> -
> - /* display */
> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_D(_MMIO(0x602a0), D_ALL);
> -
> - MMIO_D(_MMIO(0x65050), D_ALL);
> - MMIO_D(_MMIO(0x650b4), D_ALL);
> -
> - MMIO_D(_MMIO(0xc4040), D_ALL);
> - MMIO_D(DERRMR, D_ALL);
> -
> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
> -
> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
> -
> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
> -
> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
> -
> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
> -
> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
> -
> - MMIO_D(CURPOS(PIPE_A), D_ALL);
> - MMIO_D(CURPOS(PIPE_B), D_ALL);
> - MMIO_D(CURPOS(PIPE_C), D_ALL);
> -
> - MMIO_D(CURBASE(PIPE_A), D_ALL);
> - MMIO_D(CURBASE(PIPE_B), D_ALL);
> - MMIO_D(CURBASE(PIPE_C), D_ALL);
> -
> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
> -
> - MMIO_D(_MMIO(0x700ac), D_ALL);
> - MMIO_D(_MMIO(0x710ac), D_ALL);
> - MMIO_D(_MMIO(0x720ac), D_ALL);
> -
> - MMIO_D(_MMIO(0x70090), D_ALL);
> - MMIO_D(_MMIO(0x70094), D_ALL);
> - MMIO_D(_MMIO(0x70098), D_ALL);
> - MMIO_D(_MMIO(0x7009c), D_ALL);
> -
> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
> -
> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
> -
> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
> -
> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
> -
> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
> -
> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
> -
> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
> -
> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
> -
> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
> -
> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
> -
> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
> -
> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
> - MMIO_D(WM1_LP_ILK, D_ALL);
> - MMIO_D(WM2_LP_ILK, D_ALL);
> - MMIO_D(WM3_LP_ILK, D_ALL);
> - MMIO_D(WM1S_LP_ILK, D_ALL);
> - MMIO_D(WM2S_LP_IVB, D_ALL);
> - MMIO_D(WM3S_LP_IVB, D_ALL);
> -
> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
> -
> - MMIO_D(_MMIO(0x48268), D_ALL);
> -
> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> - gmbus_mmio_write);
> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> - dp_aux_ch_ctl_mmio_write);
> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> - dp_aux_ch_ctl_mmio_write);
> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> - dp_aux_ch_ctl_mmio_write);
> -
> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
> -
> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
> -
> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> -
> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
> -
> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
> -
> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
> -
> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
> -
> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
> -
> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
> -
> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
> -
> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
> -
> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
> - MMIO_D(PCH_PP_STATUS, D_ALL);
> - MMIO_D(PCH_LVDS, D_ALL);
> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
> - MMIO_D(PCH_DPLL_SEL, D_ALL);
> -
> - MMIO_D(_MMIO(0x61208), D_ALL);
> - MMIO_D(_MMIO(0x6120c), D_ALL);
> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
> -
> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
> -
> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
> - PORTA_HOTPLUG_STATUS_MASK
> - | PORTB_HOTPLUG_STATUS_MASK
> - | PORTC_HOTPLUG_STATUS_MASK
> - | PORTD_HOTPLUG_STATUS_MASK,
> - NULL, NULL);
> -
> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
> - MMIO_D(FUSE_STRAP, D_ALL);
> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
> -
> - MMIO_D(DISP_ARB_CTL, D_ALL);
> - MMIO_D(DISP_ARB_CTL2, D_ALL);
> -
> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
> -
> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
> -
> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
> -
> - MMIO_D(IPS_CTL, D_ALL);
> -
> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
> -
> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
> -
> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
> -
> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(_MMIO(0x60110), D_ALL);
> - MMIO_D(_MMIO(0x61110), D_ALL);
> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> -
> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
> - MMIO_D(SPLL_CTL, D_ALL);
> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
> -
> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
> - MMIO_D(_MMIO(0x46508), D_ALL);
> -
> - MMIO_D(_MMIO(0x49080), D_ALL);
> - MMIO_D(_MMIO(0x49180), D_ALL);
> - MMIO_D(_MMIO(0x49280), D_ALL);
> -
> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
> -
> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
> -
> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
> -
> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
> - MMIO_D(SBI_ADDR, D_ALL);
> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
> - MMIO_D(PIXCLK_GATE, D_ALL);
> -
> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
> - dp_aux_ch_ctl_mmio_write);
> -
> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> -
> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
> -
> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
> -
> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
> -
> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
> -
> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
> -
> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
> - MMIO_D(FORCEWAKE_ACK, D_ALL);
> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
> - MMIO_D(ECOBUS, D_ALL);
> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
> - MMIO_D(GEN6_RPSTAT1, D_ALL);
> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
> -
> - MMIO_D(RSTDBYCTL, D_ALL);
> -
> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
> -
> - MMIO_D(TILECTL, D_ALL);
> -
> - MMIO_D(GEN6_UCGCTL1, D_ALL);
> - MMIO_D(GEN6_UCGCTL2, D_ALL);
> -
> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
> - MMIO_D(_MMIO(0x13812c), D_ALL);
> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
> - MMIO_D(HSW_IDICR, D_ALL);
> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
> -
> - MMIO_D(_MMIO(0x3c), D_ALL);
> - MMIO_D(_MMIO(0x860), D_ALL);
> - MMIO_D(ECOSKPD, D_ALL);
> - MMIO_D(_MMIO(0x121d0), D_ALL);
> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
> - MMIO_D(_MMIO(0x41d0), D_ALL);
> - MMIO_D(GAC_ECO_BITS, D_ALL);
> - MMIO_D(_MMIO(0x6200), D_ALL);
> - MMIO_D(_MMIO(0x6204), D_ALL);
> - MMIO_D(_MMIO(0x6208), D_ALL);
> - MMIO_D(_MMIO(0x7118), D_ALL);
> - MMIO_D(_MMIO(0x7180), D_ALL);
> - MMIO_D(_MMIO(0x7408), D_ALL);
> - MMIO_D(_MMIO(0x7c00), D_ALL);
> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
> - MMIO_D(_MMIO(0x911c), D_ALL);
> - MMIO_D(_MMIO(0x9120), D_ALL);
> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_D(GAB_CTL, D_ALL);
> - MMIO_D(_MMIO(0x48800), D_ALL);
> - MMIO_D(_MMIO(0xce044), D_ALL);
> - MMIO_D(_MMIO(0xe6500), D_ALL);
> - MMIO_D(_MMIO(0xe6504), D_ALL);
> - MMIO_D(_MMIO(0xe6600), D_ALL);
> - MMIO_D(_MMIO(0xe6604), D_ALL);
> - MMIO_D(_MMIO(0xe6700), D_ALL);
> - MMIO_D(_MMIO(0xe6704), D_ALL);
> - MMIO_D(_MMIO(0xe6800), D_ALL);
> - MMIO_D(_MMIO(0xe6804), D_ALL);
> - MMIO_D(PCH_GMBUS4, D_ALL);
> - MMIO_D(PCH_GMBUS5, D_ALL);
> -
> - MMIO_D(_MMIO(0x902c), D_ALL);
> - MMIO_D(_MMIO(0xec008), D_ALL);
> - MMIO_D(_MMIO(0xec00c), D_ALL);
> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
> - MMIO_D(_MMIO(0xec408), D_ALL);
> - MMIO_D(_MMIO(0xec40c), D_ALL);
> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
> - MMIO_D(_MMIO(0xfc810), D_ALL);
> - MMIO_D(_MMIO(0xfc81c), D_ALL);
> - MMIO_D(_MMIO(0xfc828), D_ALL);
> - MMIO_D(_MMIO(0xfc834), D_ALL);
> - MMIO_D(_MMIO(0xfcc00), D_ALL);
> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
> - MMIO_D(_MMIO(0xfcc18), D_ALL);
> - MMIO_D(_MMIO(0xfcc24), D_ALL);
> - MMIO_D(_MMIO(0xfd000), D_ALL);
> - MMIO_D(_MMIO(0xfd00c), D_ALL);
> - MMIO_D(_MMIO(0xfd018), D_ALL);
> - MMIO_D(_MMIO(0xfd024), D_ALL);
> - MMIO_D(_MMIO(0xfd034), D_ALL);
> -
> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
> - MMIO_D(_MMIO(0x2054), D_ALL);
> - MMIO_D(_MMIO(0x12054), D_ALL);
> - MMIO_D(_MMIO(0x22054), D_ALL);
> - MMIO_D(_MMIO(0x1a054), D_ALL);
> -
> - MMIO_D(_MMIO(0x44070), D_ALL);
> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
> -
> - return 0;
> -}
> -
> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
> -{
> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> - int ret;
> -
> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
> - intel_vgpu_reg_master_irq_handler);
> -
> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
> - mmio_read_from_hw, NULL);
> -
> -#define RING_REG(base) _MMIO((base) + 0xd0)
> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
> - ring_reset_ctl_write);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x230)
> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x234)
> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
> - NULL, NULL);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x244)
> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x370)
> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x3a0)
> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
> -#undef RING_REG
> -
> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
> -
> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
> -
> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
> -
> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
> -
> -#define RING_REG(base) _MMIO((base) + 0x270)
> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> -#undef RING_REG
> -
> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
> -
> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
> -
> - MMIO_D(WM_MISC, D_BDW);
> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
> -
> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
> -
> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
> -
> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
> -
> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
> - MMIO_D(_MMIO(0xb110), D_BDW);
> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
> -
> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
> - D_BDW_PLUS, NULL, force_nonpriv_write);
> -
> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
> -
> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
> -
> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
> -
> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
> -
> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
> -
> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - return 0;
> -}
> -
> -static int init_skl_mmio_info(struct intel_gvt *gvt)
> -{
> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> - int ret;
> -
> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> - dp_aux_ch_ctl_mmio_write);
> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> - dp_aux_ch_ctl_mmio_write);
> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> - dp_aux_ch_ctl_mmio_write);
> -
> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
> -
> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
> -
> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
> -
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> -
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> -
> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> -
> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
> -
> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
> -
> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
> -
> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> - NULL, NULL);
> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> - NULL, NULL);
> -
> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> -
> - /* TRTT */
> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
> - NULL, gen9_trtte_write);
> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
> - NULL, gen9_trtt_chicken_write);
> -
> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
> -
> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
> -
> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
> -
> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
> -
> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
> -
> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
> -
> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, csfe_chicken1_mmio_write);
> -#undef CSFE_CHICKEN1_REG
> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> -
> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
> -
> - return 0;
> -}
> -
> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
> -{
> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> - int ret;
> -
> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
> -
> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
> - MMIO_D(ERROR_GEN6, D_BXT);
> - MMIO_D(DONE_REG, D_BXT);
> - MMIO_D(EIR, D_BXT);
> - MMIO_D(PGTBL_ER, D_BXT);
> - MMIO_D(_MMIO(0x4194), D_BXT);
> - MMIO_D(_MMIO(0x4294), D_BXT);
> - MMIO_D(_MMIO(0x4494), D_BXT);
> -
> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
> - MMIO_RING_D(RING_IPEHR, D_BXT);
> - MMIO_RING_D(RING_INSTPS, D_BXT);
> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
> - MMIO_RING_D(RING_BBSTATE, D_BXT);
> - MMIO_RING_D(RING_IPEIR, D_BXT);
> -
> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
> -
> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
> - NULL, bxt_phy_ctl_family_write);
> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
> - NULL, bxt_phy_ctl_family_write);
> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
> - NULL, bxt_port_pll_enable_write);
> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
> - NULL, bxt_port_pll_enable_write);
> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
> - bxt_port_pll_enable_write);
> -
> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
> -
> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
> -
> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
> - NULL, bxt_pcs_dw12_grp_write);
> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
> - bxt_port_tx_dw3_read, NULL);
> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
> -
> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
> - NULL, bxt_pcs_dw12_grp_write);
> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
> - bxt_port_tx_dw3_read, NULL);
> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
> -
> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
> - NULL, bxt_pcs_dw12_grp_write);
> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
> - bxt_port_tx_dw3_read, NULL);
> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
> -
> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
> -
> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
> -
> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
> -
> - MMIO_D(RC6_CTX_BASE, D_BXT);
> -
> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> - 0, 0, D_BXT, NULL, NULL);
> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> - 0, 0, D_BXT, NULL, NULL);
> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> - 0, 0, D_BXT, NULL, NULL);
> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> - 0, 0, D_BXT, NULL, NULL);
> -
> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
> -
> - return 0;
> -}
> +#include "mmio_table.h"
>
> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
> unsigned int offset)
> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
> {
> struct intel_gvt_device_info *info = &gvt->device_info;
> - struct drm_i915_private *i915 = gvt->gt->i915;
> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
> int ret;
>
> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
> if (!gvt->mmio.mmio_attribute)
> return -ENOMEM;
>
> - ret = init_generic_mmio_info(gvt);
> - if (ret)
> - goto err;
> -
> - if (IS_BROADWELL(i915)) {
> - ret = init_bdw_mmio_info(gvt);
> - if (ret)
> - goto err;
> - } else if (IS_SKYLAKE(i915) ||
> - IS_KABYLAKE(i915) ||
> - IS_COFFEELAKE(i915) ||
> - IS_COMETLAKE(i915)) {
> - ret = init_bdw_mmio_info(gvt);
> - if (ret)
> - goto err;
> - ret = init_skl_mmio_info(gvt);
> - if (ret)
> - goto err;
> - } else if (IS_BROXTON(i915)) {
> - ret = init_bdw_mmio_info(gvt);
> - if (ret)
> - goto err;
> - ret = init_skl_mmio_info(gvt);
> - if (ret)
> - goto err;
> - ret = init_bxt_mmio_info(gvt);
> - if (ret)
> - goto err;
> + ret = intel_gvt_init_mmio_info(gvt);
> + if (ret) {
> + intel_gvt_clean_mmio_info(gvt);
> + return ret;
> }
>
> gvt->mmio.mmio_block = mmio_blocks;
> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
>
> return 0;
> -err:
> - intel_gvt_clean_mmio_info(gvt);
> - return ret;
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
> new file mode 100644
> index 000000000000..39a4cb59695a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
> @@ -0,0 +1,1570 @@
> +/*
> + * Copyright © 2021 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef _GVT_MMIO_TABLE_H_
> +#define _GVT_MMIO_TABLE_H_
> +
> +#ifdef GENERATE_MMIO_TABLE_IN_I915
> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
> + if (ret) \
> + return ret; \
> +} while (0)
> +#else
> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
> + f, s, am, rm, d, r, w); \
> + if (ret) \
> + return ret; \
> +} while (0)
> +#endif
> +
> +#define MMIO_D(reg, d) \
> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
> +
> +#define MMIO_DH(reg, d, r, w) \
> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
> +
> +#define MMIO_DFH(reg, d, f, r, w) \
> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
> +
> +#define MMIO_GM(reg, d, r, w) \
> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
> +
> +#define MMIO_GM_RDR(reg, d, r, w) \
> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
> +
> +#define MMIO_RO(reg, d, f, rm, r, w) \
> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
> +
> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> + if (HAS_ENGINE(gvt->gt, VCS1)) \
> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
> +} while (0)
> +
> +#define MMIO_RING_D(prefix, d) \
> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
> +
> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
> +
> +#define MMIO_RING_GM(prefix, d, r, w) \
> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
> +
> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
> +
> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
> +
> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
> +{
> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> +
> + int ret;
> +
> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
> + intel_vgpu_reg_imr_handler);
> +
> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(SDEISR, D_ALL);
> +
> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
> +
> +
> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
> + gamw_echo_dev_rw_ia_write);
> +
> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> +
> +#define RING_REG(base) _MMIO((base) + 0x28)
> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x134)
> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x6c)
> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
> +#undef RING_REG
> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
> +
> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
> +
> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
> +
> + /* RING MODE */
> +#define RING_REG(base) _MMIO((base) + 0x29c)
> + MMIO_RING_DFH(RING_REG, D_ALL,
> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
> + ring_mode_mmio_write);
> +#undef RING_REG
> +
> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
> + mmio_read_from_hw, NULL);
> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
> + mmio_read_from_hw, NULL);
> +
> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> +
> + /* display */
> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_D(_MMIO(0x602a0), D_ALL);
> +
> + MMIO_D(_MMIO(0x65050), D_ALL);
> + MMIO_D(_MMIO(0x650b4), D_ALL);
> +
> + MMIO_D(_MMIO(0xc4040), D_ALL);
> + MMIO_D(DERRMR, D_ALL);
> +
> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
> +
> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
> +
> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
> +
> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
> +
> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
> +
> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
> +
> + MMIO_D(CURPOS(PIPE_A), D_ALL);
> + MMIO_D(CURPOS(PIPE_B), D_ALL);
> + MMIO_D(CURPOS(PIPE_C), D_ALL);
> +
> + MMIO_D(CURBASE(PIPE_A), D_ALL);
> + MMIO_D(CURBASE(PIPE_B), D_ALL);
> + MMIO_D(CURBASE(PIPE_C), D_ALL);
> +
> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
> +
> + MMIO_D(_MMIO(0x700ac), D_ALL);
> + MMIO_D(_MMIO(0x710ac), D_ALL);
> + MMIO_D(_MMIO(0x720ac), D_ALL);
> +
> + MMIO_D(_MMIO(0x70090), D_ALL);
> + MMIO_D(_MMIO(0x70094), D_ALL);
> + MMIO_D(_MMIO(0x70098), D_ALL);
> + MMIO_D(_MMIO(0x7009c), D_ALL);
> +
> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
> +
> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
> +
> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
> +
> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
> +
> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
> +
> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
> +
> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
> +
> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
> +
> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
> +
> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
> +
> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
> +
> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
> + MMIO_D(WM1_LP_ILK, D_ALL);
> + MMIO_D(WM2_LP_ILK, D_ALL);
> + MMIO_D(WM3_LP_ILK, D_ALL);
> + MMIO_D(WM1S_LP_ILK, D_ALL);
> + MMIO_D(WM2S_LP_IVB, D_ALL);
> + MMIO_D(WM3S_LP_IVB, D_ALL);
> +
> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
> +
> + MMIO_D(_MMIO(0x48268), D_ALL);
> +
> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> + gmbus_mmio_write);
> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> + dp_aux_ch_ctl_mmio_write);
> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> + dp_aux_ch_ctl_mmio_write);
> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> + dp_aux_ch_ctl_mmio_write);
> +
> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
> +
> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
> +
> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> +
> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
> +
> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
> +
> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
> +
> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
> +
> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
> +
> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
> +
> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
> +
> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
> +
> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
> + MMIO_D(PCH_PP_STATUS, D_ALL);
> + MMIO_D(PCH_LVDS, D_ALL);
> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
> + MMIO_D(PCH_DPLL_SEL, D_ALL);
> +
> + MMIO_D(_MMIO(0x61208), D_ALL);
> + MMIO_D(_MMIO(0x6120c), D_ALL);
> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
> +
> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
> +
> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
> + PORTA_HOTPLUG_STATUS_MASK
> + | PORTB_HOTPLUG_STATUS_MASK
> + | PORTC_HOTPLUG_STATUS_MASK
> + | PORTD_HOTPLUG_STATUS_MASK,
> + NULL, NULL);
> +
> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
> + MMIO_D(FUSE_STRAP, D_ALL);
> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
> +
> + MMIO_D(DISP_ARB_CTL, D_ALL);
> + MMIO_D(DISP_ARB_CTL2, D_ALL);
> +
> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
> +
> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
> +
> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
> +
> + MMIO_D(IPS_CTL, D_ALL);
> +
> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
> +
> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
> +
> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
> +
> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(_MMIO(0x60110), D_ALL);
> + MMIO_D(_MMIO(0x61110), D_ALL);
> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> +
> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
> + MMIO_D(SPLL_CTL, D_ALL);
> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
> +
> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
> + MMIO_D(_MMIO(0x46508), D_ALL);
> +
> + MMIO_D(_MMIO(0x49080), D_ALL);
> + MMIO_D(_MMIO(0x49180), D_ALL);
> + MMIO_D(_MMIO(0x49280), D_ALL);
> +
> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
> +
> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
> +
> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
> +
> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
> + MMIO_D(SBI_ADDR, D_ALL);
> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
> + MMIO_D(PIXCLK_GATE, D_ALL);
> +
> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
> + dp_aux_ch_ctl_mmio_write);
> +
> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> +
> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
> +
> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
> +
> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
> +
> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
> +
> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
> +
> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
> + MMIO_D(FORCEWAKE_ACK, D_ALL);
> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
> + MMIO_D(ECOBUS, D_ALL);
> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
> + MMIO_D(GEN6_RPSTAT1, D_ALL);
> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
> +
> + MMIO_D(RSTDBYCTL, D_ALL);
> +
> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
> +
> + MMIO_D(TILECTL, D_ALL);
> +
> + MMIO_D(GEN6_UCGCTL1, D_ALL);
> + MMIO_D(GEN6_UCGCTL2, D_ALL);
> +
> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
> + MMIO_D(_MMIO(0x13812c), D_ALL);
> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
> + MMIO_D(HSW_IDICR, D_ALL);
> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
> +
> + MMIO_D(_MMIO(0x3c), D_ALL);
> + MMIO_D(_MMIO(0x860), D_ALL);
> + MMIO_D(ECOSKPD, D_ALL);
> + MMIO_D(_MMIO(0x121d0), D_ALL);
> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
> + MMIO_D(_MMIO(0x41d0), D_ALL);
> + MMIO_D(GAC_ECO_BITS, D_ALL);
> + MMIO_D(_MMIO(0x6200), D_ALL);
> + MMIO_D(_MMIO(0x6204), D_ALL);
> + MMIO_D(_MMIO(0x6208), D_ALL);
> + MMIO_D(_MMIO(0x7118), D_ALL);
> + MMIO_D(_MMIO(0x7180), D_ALL);
> + MMIO_D(_MMIO(0x7408), D_ALL);
> + MMIO_D(_MMIO(0x7c00), D_ALL);
> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
> + MMIO_D(_MMIO(0x911c), D_ALL);
> + MMIO_D(_MMIO(0x9120), D_ALL);
> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_D(GAB_CTL, D_ALL);
> + MMIO_D(_MMIO(0x48800), D_ALL);
> + MMIO_D(_MMIO(0xce044), D_ALL);
> + MMIO_D(_MMIO(0xe6500), D_ALL);
> + MMIO_D(_MMIO(0xe6504), D_ALL);
> + MMIO_D(_MMIO(0xe6600), D_ALL);
> + MMIO_D(_MMIO(0xe6604), D_ALL);
> + MMIO_D(_MMIO(0xe6700), D_ALL);
> + MMIO_D(_MMIO(0xe6704), D_ALL);
> + MMIO_D(_MMIO(0xe6800), D_ALL);
> + MMIO_D(_MMIO(0xe6804), D_ALL);
> + MMIO_D(PCH_GMBUS4, D_ALL);
> + MMIO_D(PCH_GMBUS5, D_ALL);
> +
> + MMIO_D(_MMIO(0x902c), D_ALL);
> + MMIO_D(_MMIO(0xec008), D_ALL);
> + MMIO_D(_MMIO(0xec00c), D_ALL);
> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
> + MMIO_D(_MMIO(0xec408), D_ALL);
> + MMIO_D(_MMIO(0xec40c), D_ALL);
> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
> + MMIO_D(_MMIO(0xfc810), D_ALL);
> + MMIO_D(_MMIO(0xfc81c), D_ALL);
> + MMIO_D(_MMIO(0xfc828), D_ALL);
> + MMIO_D(_MMIO(0xfc834), D_ALL);
> + MMIO_D(_MMIO(0xfcc00), D_ALL);
> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
> + MMIO_D(_MMIO(0xfcc18), D_ALL);
> + MMIO_D(_MMIO(0xfcc24), D_ALL);
> + MMIO_D(_MMIO(0xfd000), D_ALL);
> + MMIO_D(_MMIO(0xfd00c), D_ALL);
> + MMIO_D(_MMIO(0xfd018), D_ALL);
> + MMIO_D(_MMIO(0xfd024), D_ALL);
> + MMIO_D(_MMIO(0xfd034), D_ALL);
> +
> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
> + MMIO_D(_MMIO(0x2054), D_ALL);
> + MMIO_D(_MMIO(0x12054), D_ALL);
> + MMIO_D(_MMIO(0x22054), D_ALL);
> + MMIO_D(_MMIO(0x1a054), D_ALL);
> +
> + MMIO_D(_MMIO(0x44070), D_ALL);
> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
> +
> + return 0;
> +}
> +
> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
> +{
> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> + int ret;
> +
> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
> + intel_vgpu_reg_master_irq_handler);
> +
> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
> + mmio_read_from_hw, NULL);
> +
> +#define RING_REG(base) _MMIO((base) + 0xd0)
> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
> + ring_reset_ctl_write);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x230)
> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x234)
> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
> + NULL, NULL);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x244)
> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x370)
> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x3a0)
> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
> +#undef RING_REG
> +
> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
> +
> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
> +
> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
> +
> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
> +
> +#define RING_REG(base) _MMIO((base) + 0x270)
> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> +#undef RING_REG
> +
> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
> +
> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
> +
> + MMIO_D(WM_MISC, D_BDW);
> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
> +
> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
> +
> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
> +
> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
> +
> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
> + MMIO_D(_MMIO(0xb110), D_BDW);
> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
> +
> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
> + D_BDW_PLUS, NULL, force_nonpriv_write);
> +
> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
> +
> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
> +
> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
> +
> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
> +
> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
> +
> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + return 0;
> +}
> +
> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
> +{
> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> + int ret;
> +
> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> + dp_aux_ch_ctl_mmio_write);
> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> + dp_aux_ch_ctl_mmio_write);
> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> + dp_aux_ch_ctl_mmio_write);
> +
> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
> +
> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
> +
> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
> +
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> +
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> +
> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> +
> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
> +
> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
> +
> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
> +
> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> + NULL, NULL);
> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> + NULL, NULL);
> +
> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> +
> + /* TRTT */
> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
> + NULL, gen9_trtte_write);
> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
> + NULL, gen9_trtt_chicken_write);
> +
> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
> +
> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
> +
> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
> +
> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
> +
> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
> +
> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
> +
> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, csfe_chicken1_mmio_write);
> +#undef CSFE_CHICKEN1_REG
> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> +
> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
> +
> + return 0;
> +}
> +
> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
> +{
> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> + int ret;
> +
> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
> +
> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
> + MMIO_D(ERROR_GEN6, D_BXT);
> + MMIO_D(DONE_REG, D_BXT);
> + MMIO_D(EIR, D_BXT);
> + MMIO_D(PGTBL_ER, D_BXT);
> + MMIO_D(_MMIO(0x4194), D_BXT);
> + MMIO_D(_MMIO(0x4294), D_BXT);
> + MMIO_D(_MMIO(0x4494), D_BXT);
> +
> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
> + MMIO_RING_D(RING_IPEHR, D_BXT);
> + MMIO_RING_D(RING_INSTPS, D_BXT);
> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
> + MMIO_RING_D(RING_BBSTATE, D_BXT);
> + MMIO_RING_D(RING_IPEIR, D_BXT);
> +
> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
> +
> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
> + NULL, bxt_phy_ctl_family_write);
> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
> + NULL, bxt_phy_ctl_family_write);
> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
> + NULL, bxt_port_pll_enable_write);
> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
> + NULL, bxt_port_pll_enable_write);
> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
> + bxt_port_pll_enable_write);
> +
> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
> +
> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
> +
> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
> + NULL, bxt_pcs_dw12_grp_write);
> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
> + bxt_port_tx_dw3_read, NULL);
> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
> +
> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
> + NULL, bxt_pcs_dw12_grp_write);
> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
> + bxt_port_tx_dw3_read, NULL);
> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
> +
> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
> + NULL, bxt_pcs_dw12_grp_write);
> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
> + bxt_port_tx_dw3_read, NULL);
> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
> +
> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
> +
> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
> +
> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
> +
> + MMIO_D(RC6_CTX_BASE, D_BXT);
> +
> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> + 0, 0, D_BXT, NULL, NULL);
> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> + 0, 0, D_BXT, NULL, NULL);
> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> + 0, 0, D_BXT, NULL, NULL);
> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> + 0, 0, D_BXT, NULL, NULL);
> +
> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
> +
> + return 0;
> +}
> +
> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
> +{
> + struct drm_i915_private *i915 = gvt->gt->i915;
> + int ret;
> +
> + ret = intel_gvt_init_generic_mmio_info(gvt);
> + if (ret)
> + return ret;
> +
> + if (IS_BROADWELL(i915)) {
> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> + if (ret)
> + return ret;
> + } else if (IS_SKYLAKE(i915) ||
> + IS_KABYLAKE(i915) ||
> + IS_COFFEELAKE(i915) ||
> + IS_COMETLAKE(i915)) {
> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> + if (ret)
> + return ret;
> + ret = intel_gvt_init_skl_mmio_info(gvt);
> + if (ret)
> + return ret;
> + } else if (IS_BROXTON(i915)) {
> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> + if (ret)
> + return ret;
> + ret = intel_gvt_init_skl_mmio_info(gvt);
> + if (ret)
> + return ret;
> + ret = intel_gvt_init_bxt_mmio_info(gvt);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +#endif
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index 244cc7320b54..05bd2f8e9d94 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -133,6 +133,12 @@
> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
> #define VF_GUARDBAND _MMIO(0x83a4)
>
> +/* XXX FIXME i915 has changed PP_XXX definition */
> +#define PCH_PP_STATUS _MMIO(0xc7200)
> +#define PCH_PP_CONTROL _MMIO(0xc7204)
> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
>
> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
> index 4e70c1a9ef2e..64846d9bff0b 100644
> --- a/drivers/gpu/drm/i915/intel_gvt.c
> +++ b/drivers/gpu/drm/i915/intel_gvt.c
> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
> dev_priv->params.enable_gvt = 0;
> }
>
> +#define GENERATE_MMIO_TABLE_IN_I915
> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
> +{
> + return 0;
> +}
> +
> +#include "gvt/reg.h"
> +#include "gvt/mmio_table.h"
> +#undef GENERATE_MMIO_TABLE_IN_I915
> +
> +
> /**
> * intel_gvt_init - initialize GVT components
> * @dev_priv: drm i915 private data
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 7:00 ` Jani Nikula
0 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2021-11-09 7:00 UTC (permalink / raw)
To: Zhi Wang, joonas.lahtinen, rodrigo.vivi, zhenyuw, zhi.a.wang,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
Cc: Zhi Wang
On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
> From: Zhi Wang <zhi.wang.linux@gmail.com>
>
> To support the new mdev interfaces and the re-factor patches from
> Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
> MMIO snapshot still needs to be saved in i915 so that the inital clean HW
> state can be used for the further vGPU. Seperate the tracked MMIO table
> from GVT-g, so that GVT-g and i915 can both use it.
Do you really have to both put code in a header and then include that in
multiple places?
I think you may need to rethink the whole approach, maybe make them
actual tables instead of code.
BR,
Jani.
>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: Zhi Wang <zhi.a.wang@intel.com>
> Cc: Christoph Hellwig <hch@lst.de>
> Cc: Jason Gunthorpe <jgg@nvidia.com>
> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
> drivers/gpu/drm/i915/gvt/reg.h | 6 +
> drivers/gpu/drm/i915/intel_gvt.c | 11 +
> 4 files changed, 1592 insertions(+), 1534 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index cde0a477fb49..6a08d362bf66 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -41,13 +41,6 @@
> #include "i915_pvinfo.h"
> #include "display/intel_display_types.h"
>
> -/* XXX FIXME i915 has changed PP_XXX definition */
> -#define PCH_PP_STATUS _MMIO(0xc7200)
> -#define PCH_PP_CONTROL _MMIO(0xc7204)
> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
> -
> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
> {
> struct drm_i915_private *i915 = gvt->gt->i915;
> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
> return 0;
> }
>
> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
> - f, s, am, rm, d, r, w); \
> - if (ret) \
> - return ret; \
> -} while (0)
> -
> -#define MMIO_D(reg, d) \
> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
> -
> -#define MMIO_DH(reg, d, r, w) \
> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
> -
> -#define MMIO_DFH(reg, d, f, r, w) \
> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
> -
> -#define MMIO_GM(reg, d, r, w) \
> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
> -
> -#define MMIO_GM_RDR(reg, d, r, w) \
> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
> -
> -#define MMIO_RO(reg, d, f, rm, r, w) \
> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
> -
> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> - if (HAS_ENGINE(gvt->gt, VCS1)) \
> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
> -} while (0)
> -
> -#define MMIO_RING_D(prefix, d) \
> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
> -
> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
> -
> -#define MMIO_RING_GM(prefix, d, r, w) \
> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
> -
> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
> -
> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
> -
> -static int init_generic_mmio_info(struct intel_gvt *gvt)
> -{
> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> - int ret;
> -
> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
> - intel_vgpu_reg_imr_handler);
> -
> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(SDEISR, D_ALL);
> -
> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
> -
> -
> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
> - gamw_echo_dev_rw_ia_write);
> -
> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> -
> -#define RING_REG(base) _MMIO((base) + 0x28)
> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x134)
> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x6c)
> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
> -#undef RING_REG
> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
> -
> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
> -
> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
> -
> - /* RING MODE */
> -#define RING_REG(base) _MMIO((base) + 0x29c)
> - MMIO_RING_DFH(RING_REG, D_ALL,
> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
> - ring_mode_mmio_write);
> -#undef RING_REG
> -
> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
> - mmio_read_from_hw, NULL);
> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
> - mmio_read_from_hw, NULL);
> -
> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> -
> - /* display */
> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_D(_MMIO(0x602a0), D_ALL);
> -
> - MMIO_D(_MMIO(0x65050), D_ALL);
> - MMIO_D(_MMIO(0x650b4), D_ALL);
> -
> - MMIO_D(_MMIO(0xc4040), D_ALL);
> - MMIO_D(DERRMR, D_ALL);
> -
> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
> -
> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
> -
> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
> -
> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
> -
> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
> -
> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
> -
> - MMIO_D(CURPOS(PIPE_A), D_ALL);
> - MMIO_D(CURPOS(PIPE_B), D_ALL);
> - MMIO_D(CURPOS(PIPE_C), D_ALL);
> -
> - MMIO_D(CURBASE(PIPE_A), D_ALL);
> - MMIO_D(CURBASE(PIPE_B), D_ALL);
> - MMIO_D(CURBASE(PIPE_C), D_ALL);
> -
> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
> -
> - MMIO_D(_MMIO(0x700ac), D_ALL);
> - MMIO_D(_MMIO(0x710ac), D_ALL);
> - MMIO_D(_MMIO(0x720ac), D_ALL);
> -
> - MMIO_D(_MMIO(0x70090), D_ALL);
> - MMIO_D(_MMIO(0x70094), D_ALL);
> - MMIO_D(_MMIO(0x70098), D_ALL);
> - MMIO_D(_MMIO(0x7009c), D_ALL);
> -
> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
> - reg50080_mmio_write);
> -
> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
> -
> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
> -
> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
> -
> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
> -
> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
> -
> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
> -
> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
> -
> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
> -
> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
> -
> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
> -
> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
> -
> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
> - MMIO_D(WM1_LP_ILK, D_ALL);
> - MMIO_D(WM2_LP_ILK, D_ALL);
> - MMIO_D(WM3_LP_ILK, D_ALL);
> - MMIO_D(WM1S_LP_ILK, D_ALL);
> - MMIO_D(WM2S_LP_IVB, D_ALL);
> - MMIO_D(WM3S_LP_IVB, D_ALL);
> -
> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
> -
> - MMIO_D(_MMIO(0x48268), D_ALL);
> -
> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> - gmbus_mmio_write);
> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> - dp_aux_ch_ctl_mmio_write);
> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> - dp_aux_ch_ctl_mmio_write);
> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> - dp_aux_ch_ctl_mmio_write);
> -
> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
> -
> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
> -
> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> -
> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
> -
> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
> -
> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
> -
> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
> -
> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
> -
> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
> -
> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
> -
> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
> -
> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
> - MMIO_D(PCH_PP_STATUS, D_ALL);
> - MMIO_D(PCH_LVDS, D_ALL);
> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
> - MMIO_D(PCH_DPLL_SEL, D_ALL);
> -
> - MMIO_D(_MMIO(0x61208), D_ALL);
> - MMIO_D(_MMIO(0x6120c), D_ALL);
> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
> -
> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
> -
> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
> - PORTA_HOTPLUG_STATUS_MASK
> - | PORTB_HOTPLUG_STATUS_MASK
> - | PORTC_HOTPLUG_STATUS_MASK
> - | PORTD_HOTPLUG_STATUS_MASK,
> - NULL, NULL);
> -
> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
> - MMIO_D(FUSE_STRAP, D_ALL);
> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
> -
> - MMIO_D(DISP_ARB_CTL, D_ALL);
> - MMIO_D(DISP_ARB_CTL2, D_ALL);
> -
> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
> -
> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
> -
> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
> -
> - MMIO_D(IPS_CTL, D_ALL);
> -
> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
> -
> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
> -
> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
> -
> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(_MMIO(0x60110), D_ALL);
> - MMIO_D(_MMIO(0x61110), D_ALL);
> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> -
> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
> - MMIO_D(SPLL_CTL, D_ALL);
> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
> -
> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
> - MMIO_D(_MMIO(0x46508), D_ALL);
> -
> - MMIO_D(_MMIO(0x49080), D_ALL);
> - MMIO_D(_MMIO(0x49180), D_ALL);
> - MMIO_D(_MMIO(0x49280), D_ALL);
> -
> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
> -
> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
> -
> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
> -
> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
> - MMIO_D(SBI_ADDR, D_ALL);
> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
> - MMIO_D(PIXCLK_GATE, D_ALL);
> -
> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
> - dp_aux_ch_ctl_mmio_write);
> -
> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> -
> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
> -
> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
> -
> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
> -
> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
> -
> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
> -
> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
> - MMIO_D(FORCEWAKE_ACK, D_ALL);
> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
> - MMIO_D(ECOBUS, D_ALL);
> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
> - MMIO_D(GEN6_RPSTAT1, D_ALL);
> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
> -
> - MMIO_D(RSTDBYCTL, D_ALL);
> -
> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
> -
> - MMIO_D(TILECTL, D_ALL);
> -
> - MMIO_D(GEN6_UCGCTL1, D_ALL);
> - MMIO_D(GEN6_UCGCTL2, D_ALL);
> -
> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
> - MMIO_D(_MMIO(0x13812c), D_ALL);
> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
> - MMIO_D(HSW_IDICR, D_ALL);
> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
> -
> - MMIO_D(_MMIO(0x3c), D_ALL);
> - MMIO_D(_MMIO(0x860), D_ALL);
> - MMIO_D(ECOSKPD, D_ALL);
> - MMIO_D(_MMIO(0x121d0), D_ALL);
> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
> - MMIO_D(_MMIO(0x41d0), D_ALL);
> - MMIO_D(GAC_ECO_BITS, D_ALL);
> - MMIO_D(_MMIO(0x6200), D_ALL);
> - MMIO_D(_MMIO(0x6204), D_ALL);
> - MMIO_D(_MMIO(0x6208), D_ALL);
> - MMIO_D(_MMIO(0x7118), D_ALL);
> - MMIO_D(_MMIO(0x7180), D_ALL);
> - MMIO_D(_MMIO(0x7408), D_ALL);
> - MMIO_D(_MMIO(0x7c00), D_ALL);
> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
> - MMIO_D(_MMIO(0x911c), D_ALL);
> - MMIO_D(_MMIO(0x9120), D_ALL);
> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_D(GAB_CTL, D_ALL);
> - MMIO_D(_MMIO(0x48800), D_ALL);
> - MMIO_D(_MMIO(0xce044), D_ALL);
> - MMIO_D(_MMIO(0xe6500), D_ALL);
> - MMIO_D(_MMIO(0xe6504), D_ALL);
> - MMIO_D(_MMIO(0xe6600), D_ALL);
> - MMIO_D(_MMIO(0xe6604), D_ALL);
> - MMIO_D(_MMIO(0xe6700), D_ALL);
> - MMIO_D(_MMIO(0xe6704), D_ALL);
> - MMIO_D(_MMIO(0xe6800), D_ALL);
> - MMIO_D(_MMIO(0xe6804), D_ALL);
> - MMIO_D(PCH_GMBUS4, D_ALL);
> - MMIO_D(PCH_GMBUS5, D_ALL);
> -
> - MMIO_D(_MMIO(0x902c), D_ALL);
> - MMIO_D(_MMIO(0xec008), D_ALL);
> - MMIO_D(_MMIO(0xec00c), D_ALL);
> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
> - MMIO_D(_MMIO(0xec408), D_ALL);
> - MMIO_D(_MMIO(0xec40c), D_ALL);
> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
> - MMIO_D(_MMIO(0xfc810), D_ALL);
> - MMIO_D(_MMIO(0xfc81c), D_ALL);
> - MMIO_D(_MMIO(0xfc828), D_ALL);
> - MMIO_D(_MMIO(0xfc834), D_ALL);
> - MMIO_D(_MMIO(0xfcc00), D_ALL);
> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
> - MMIO_D(_MMIO(0xfcc18), D_ALL);
> - MMIO_D(_MMIO(0xfcc24), D_ALL);
> - MMIO_D(_MMIO(0xfd000), D_ALL);
> - MMIO_D(_MMIO(0xfd00c), D_ALL);
> - MMIO_D(_MMIO(0xfd018), D_ALL);
> - MMIO_D(_MMIO(0xfd024), D_ALL);
> - MMIO_D(_MMIO(0xfd034), D_ALL);
> -
> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
> - MMIO_D(_MMIO(0x2054), D_ALL);
> - MMIO_D(_MMIO(0x12054), D_ALL);
> - MMIO_D(_MMIO(0x22054), D_ALL);
> - MMIO_D(_MMIO(0x1a054), D_ALL);
> -
> - MMIO_D(_MMIO(0x44070), D_ALL);
> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> -
> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
> -
> - return 0;
> -}
> -
> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
> -{
> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> - int ret;
> -
> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
> - intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
> -
> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
> - intel_vgpu_reg_master_irq_handler);
> -
> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
> - mmio_read_from_hw, NULL);
> -
> -#define RING_REG(base) _MMIO((base) + 0xd0)
> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
> - ring_reset_ctl_write);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x230)
> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x234)
> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
> - NULL, NULL);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x244)
> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x370)
> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
> -#undef RING_REG
> -
> -#define RING_REG(base) _MMIO((base) + 0x3a0)
> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
> -#undef RING_REG
> -
> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
> -
> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
> -
> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
> -
> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
> -
> -#define RING_REG(base) _MMIO((base) + 0x270)
> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> -#undef RING_REG
> -
> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
> -
> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
> -
> - MMIO_D(WM_MISC, D_BDW);
> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
> -
> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
> -
> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
> -
> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
> -
> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
> - MMIO_D(_MMIO(0xb110), D_BDW);
> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
> -
> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
> - D_BDW_PLUS, NULL, force_nonpriv_write);
> -
> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
> -
> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
> -
> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
> -
> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
> -
> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
> -
> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> - return 0;
> -}
> -
> -static int init_skl_mmio_info(struct intel_gvt *gvt)
> -{
> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> - int ret;
> -
> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> - dp_aux_ch_ctl_mmio_write);
> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> - dp_aux_ch_ctl_mmio_write);
> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> - dp_aux_ch_ctl_mmio_write);
> -
> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
> -
> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
> -
> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
> -
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> -
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> -
> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> -
> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> -
> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
> -
> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
> -
> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
> -
> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> - NULL, NULL);
> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> - NULL, NULL);
> -
> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> -
> - /* TRTT */
> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
> - NULL, gen9_trtte_write);
> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
> - NULL, gen9_trtt_chicken_write);
> -
> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
> -
> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
> -
> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
> -
> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
> -
> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
> -
> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
> -
> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, csfe_chicken1_mmio_write);
> -#undef CSFE_CHICKEN1_REG
> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> - NULL, NULL);
> -
> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
> -
> - return 0;
> -}
> -
> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
> -{
> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> - int ret;
> -
> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
> -
> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
> - MMIO_D(ERROR_GEN6, D_BXT);
> - MMIO_D(DONE_REG, D_BXT);
> - MMIO_D(EIR, D_BXT);
> - MMIO_D(PGTBL_ER, D_BXT);
> - MMIO_D(_MMIO(0x4194), D_BXT);
> - MMIO_D(_MMIO(0x4294), D_BXT);
> - MMIO_D(_MMIO(0x4494), D_BXT);
> -
> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
> - MMIO_RING_D(RING_IPEHR, D_BXT);
> - MMIO_RING_D(RING_INSTPS, D_BXT);
> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
> - MMIO_RING_D(RING_BBSTATE, D_BXT);
> - MMIO_RING_D(RING_IPEIR, D_BXT);
> -
> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
> -
> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
> - NULL, bxt_phy_ctl_family_write);
> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
> - NULL, bxt_phy_ctl_family_write);
> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
> - NULL, bxt_port_pll_enable_write);
> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
> - NULL, bxt_port_pll_enable_write);
> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
> - bxt_port_pll_enable_write);
> -
> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
> -
> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
> -
> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
> - NULL, bxt_pcs_dw12_grp_write);
> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
> - bxt_port_tx_dw3_read, NULL);
> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
> -
> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
> - NULL, bxt_pcs_dw12_grp_write);
> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
> - bxt_port_tx_dw3_read, NULL);
> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
> -
> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
> - NULL, bxt_pcs_dw12_grp_write);
> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
> - bxt_port_tx_dw3_read, NULL);
> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
> -
> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
> -
> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
> -
> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
> -
> - MMIO_D(RC6_CTX_BASE, D_BXT);
> -
> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> - 0, 0, D_BXT, NULL, NULL);
> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> - 0, 0, D_BXT, NULL, NULL);
> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> - 0, 0, D_BXT, NULL, NULL);
> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> - 0, 0, D_BXT, NULL, NULL);
> -
> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> -
> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
> -
> - return 0;
> -}
> +#include "mmio_table.h"
>
> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
> unsigned int offset)
> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
> {
> struct intel_gvt_device_info *info = &gvt->device_info;
> - struct drm_i915_private *i915 = gvt->gt->i915;
> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
> int ret;
>
> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
> if (!gvt->mmio.mmio_attribute)
> return -ENOMEM;
>
> - ret = init_generic_mmio_info(gvt);
> - if (ret)
> - goto err;
> -
> - if (IS_BROADWELL(i915)) {
> - ret = init_bdw_mmio_info(gvt);
> - if (ret)
> - goto err;
> - } else if (IS_SKYLAKE(i915) ||
> - IS_KABYLAKE(i915) ||
> - IS_COFFEELAKE(i915) ||
> - IS_COMETLAKE(i915)) {
> - ret = init_bdw_mmio_info(gvt);
> - if (ret)
> - goto err;
> - ret = init_skl_mmio_info(gvt);
> - if (ret)
> - goto err;
> - } else if (IS_BROXTON(i915)) {
> - ret = init_bdw_mmio_info(gvt);
> - if (ret)
> - goto err;
> - ret = init_skl_mmio_info(gvt);
> - if (ret)
> - goto err;
> - ret = init_bxt_mmio_info(gvt);
> - if (ret)
> - goto err;
> + ret = intel_gvt_init_mmio_info(gvt);
> + if (ret) {
> + intel_gvt_clean_mmio_info(gvt);
> + return ret;
> }
>
> gvt->mmio.mmio_block = mmio_blocks;
> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
>
> return 0;
> -err:
> - intel_gvt_clean_mmio_info(gvt);
> - return ret;
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
> new file mode 100644
> index 000000000000..39a4cb59695a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
> @@ -0,0 +1,1570 @@
> +/*
> + * Copyright © 2021 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef _GVT_MMIO_TABLE_H_
> +#define _GVT_MMIO_TABLE_H_
> +
> +#ifdef GENERATE_MMIO_TABLE_IN_I915
> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
> + if (ret) \
> + return ret; \
> +} while (0)
> +#else
> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
> + f, s, am, rm, d, r, w); \
> + if (ret) \
> + return ret; \
> +} while (0)
> +#endif
> +
> +#define MMIO_D(reg, d) \
> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
> +
> +#define MMIO_DH(reg, d, r, w) \
> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
> +
> +#define MMIO_DFH(reg, d, f, r, w) \
> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
> +
> +#define MMIO_GM(reg, d, r, w) \
> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
> +
> +#define MMIO_GM_RDR(reg, d, r, w) \
> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
> +
> +#define MMIO_RO(reg, d, f, rm, r, w) \
> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
> +
> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> + if (HAS_ENGINE(gvt->gt, VCS1)) \
> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
> +} while (0)
> +
> +#define MMIO_RING_D(prefix, d) \
> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
> +
> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
> +
> +#define MMIO_RING_GM(prefix, d, r, w) \
> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
> +
> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
> +
> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
> +
> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
> +{
> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> +
> + int ret;
> +
> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
> + intel_vgpu_reg_imr_handler);
> +
> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(SDEISR, D_ALL);
> +
> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
> +
> +
> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
> + gamw_echo_dev_rw_ia_write);
> +
> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> +
> +#define RING_REG(base) _MMIO((base) + 0x28)
> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x134)
> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x6c)
> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
> +#undef RING_REG
> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
> +
> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
> +
> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
> +
> + /* RING MODE */
> +#define RING_REG(base) _MMIO((base) + 0x29c)
> + MMIO_RING_DFH(RING_REG, D_ALL,
> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
> + ring_mode_mmio_write);
> +#undef RING_REG
> +
> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
> + mmio_read_from_hw, NULL);
> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
> + mmio_read_from_hw, NULL);
> +
> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> +
> + /* display */
> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_D(_MMIO(0x602a0), D_ALL);
> +
> + MMIO_D(_MMIO(0x65050), D_ALL);
> + MMIO_D(_MMIO(0x650b4), D_ALL);
> +
> + MMIO_D(_MMIO(0xc4040), D_ALL);
> + MMIO_D(DERRMR, D_ALL);
> +
> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
> +
> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
> +
> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
> +
> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
> +
> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
> +
> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
> +
> + MMIO_D(CURPOS(PIPE_A), D_ALL);
> + MMIO_D(CURPOS(PIPE_B), D_ALL);
> + MMIO_D(CURPOS(PIPE_C), D_ALL);
> +
> + MMIO_D(CURBASE(PIPE_A), D_ALL);
> + MMIO_D(CURBASE(PIPE_B), D_ALL);
> + MMIO_D(CURBASE(PIPE_C), D_ALL);
> +
> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
> +
> + MMIO_D(_MMIO(0x700ac), D_ALL);
> + MMIO_D(_MMIO(0x710ac), D_ALL);
> + MMIO_D(_MMIO(0x720ac), D_ALL);
> +
> + MMIO_D(_MMIO(0x70090), D_ALL);
> + MMIO_D(_MMIO(0x70094), D_ALL);
> + MMIO_D(_MMIO(0x70098), D_ALL);
> + MMIO_D(_MMIO(0x7009c), D_ALL);
> +
> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
> + reg50080_mmio_write);
> +
> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
> +
> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
> +
> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
> +
> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
> +
> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
> +
> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
> +
> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
> +
> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
> +
> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
> +
> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
> +
> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
> +
> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
> + MMIO_D(WM1_LP_ILK, D_ALL);
> + MMIO_D(WM2_LP_ILK, D_ALL);
> + MMIO_D(WM3_LP_ILK, D_ALL);
> + MMIO_D(WM1S_LP_ILK, D_ALL);
> + MMIO_D(WM2S_LP_IVB, D_ALL);
> + MMIO_D(WM3S_LP_IVB, D_ALL);
> +
> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
> +
> + MMIO_D(_MMIO(0x48268), D_ALL);
> +
> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> + gmbus_mmio_write);
> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> + dp_aux_ch_ctl_mmio_write);
> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> + dp_aux_ch_ctl_mmio_write);
> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> + dp_aux_ch_ctl_mmio_write);
> +
> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
> +
> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
> +
> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> +
> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
> +
> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
> +
> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
> +
> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
> +
> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
> +
> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
> +
> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
> +
> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
> +
> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
> + MMIO_D(PCH_PP_STATUS, D_ALL);
> + MMIO_D(PCH_LVDS, D_ALL);
> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
> + MMIO_D(PCH_DPLL_SEL, D_ALL);
> +
> + MMIO_D(_MMIO(0x61208), D_ALL);
> + MMIO_D(_MMIO(0x6120c), D_ALL);
> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
> +
> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
> +
> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
> + PORTA_HOTPLUG_STATUS_MASK
> + | PORTB_HOTPLUG_STATUS_MASK
> + | PORTC_HOTPLUG_STATUS_MASK
> + | PORTD_HOTPLUG_STATUS_MASK,
> + NULL, NULL);
> +
> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
> + MMIO_D(FUSE_STRAP, D_ALL);
> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
> +
> + MMIO_D(DISP_ARB_CTL, D_ALL);
> + MMIO_D(DISP_ARB_CTL2, D_ALL);
> +
> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
> +
> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
> +
> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
> +
> + MMIO_D(IPS_CTL, D_ALL);
> +
> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
> +
> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
> +
> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
> +
> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(_MMIO(0x60110), D_ALL);
> + MMIO_D(_MMIO(0x61110), D_ALL);
> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> +
> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
> + MMIO_D(SPLL_CTL, D_ALL);
> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
> +
> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
> + MMIO_D(_MMIO(0x46508), D_ALL);
> +
> + MMIO_D(_MMIO(0x49080), D_ALL);
> + MMIO_D(_MMIO(0x49180), D_ALL);
> + MMIO_D(_MMIO(0x49280), D_ALL);
> +
> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
> +
> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
> +
> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
> +
> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
> + MMIO_D(SBI_ADDR, D_ALL);
> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
> + MMIO_D(PIXCLK_GATE, D_ALL);
> +
> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
> + dp_aux_ch_ctl_mmio_write);
> +
> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> +
> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
> +
> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
> +
> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
> +
> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
> +
> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
> +
> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
> + MMIO_D(FORCEWAKE_ACK, D_ALL);
> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
> + MMIO_D(ECOBUS, D_ALL);
> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
> + MMIO_D(GEN6_RPSTAT1, D_ALL);
> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
> +
> + MMIO_D(RSTDBYCTL, D_ALL);
> +
> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
> +
> + MMIO_D(TILECTL, D_ALL);
> +
> + MMIO_D(GEN6_UCGCTL1, D_ALL);
> + MMIO_D(GEN6_UCGCTL2, D_ALL);
> +
> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
> + MMIO_D(_MMIO(0x13812c), D_ALL);
> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
> + MMIO_D(HSW_IDICR, D_ALL);
> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
> +
> + MMIO_D(_MMIO(0x3c), D_ALL);
> + MMIO_D(_MMIO(0x860), D_ALL);
> + MMIO_D(ECOSKPD, D_ALL);
> + MMIO_D(_MMIO(0x121d0), D_ALL);
> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
> + MMIO_D(_MMIO(0x41d0), D_ALL);
> + MMIO_D(GAC_ECO_BITS, D_ALL);
> + MMIO_D(_MMIO(0x6200), D_ALL);
> + MMIO_D(_MMIO(0x6204), D_ALL);
> + MMIO_D(_MMIO(0x6208), D_ALL);
> + MMIO_D(_MMIO(0x7118), D_ALL);
> + MMIO_D(_MMIO(0x7180), D_ALL);
> + MMIO_D(_MMIO(0x7408), D_ALL);
> + MMIO_D(_MMIO(0x7c00), D_ALL);
> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
> + MMIO_D(_MMIO(0x911c), D_ALL);
> + MMIO_D(_MMIO(0x9120), D_ALL);
> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_D(GAB_CTL, D_ALL);
> + MMIO_D(_MMIO(0x48800), D_ALL);
> + MMIO_D(_MMIO(0xce044), D_ALL);
> + MMIO_D(_MMIO(0xe6500), D_ALL);
> + MMIO_D(_MMIO(0xe6504), D_ALL);
> + MMIO_D(_MMIO(0xe6600), D_ALL);
> + MMIO_D(_MMIO(0xe6604), D_ALL);
> + MMIO_D(_MMIO(0xe6700), D_ALL);
> + MMIO_D(_MMIO(0xe6704), D_ALL);
> + MMIO_D(_MMIO(0xe6800), D_ALL);
> + MMIO_D(_MMIO(0xe6804), D_ALL);
> + MMIO_D(PCH_GMBUS4, D_ALL);
> + MMIO_D(PCH_GMBUS5, D_ALL);
> +
> + MMIO_D(_MMIO(0x902c), D_ALL);
> + MMIO_D(_MMIO(0xec008), D_ALL);
> + MMIO_D(_MMIO(0xec00c), D_ALL);
> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
> + MMIO_D(_MMIO(0xec408), D_ALL);
> + MMIO_D(_MMIO(0xec40c), D_ALL);
> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
> + MMIO_D(_MMIO(0xfc810), D_ALL);
> + MMIO_D(_MMIO(0xfc81c), D_ALL);
> + MMIO_D(_MMIO(0xfc828), D_ALL);
> + MMIO_D(_MMIO(0xfc834), D_ALL);
> + MMIO_D(_MMIO(0xfcc00), D_ALL);
> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
> + MMIO_D(_MMIO(0xfcc18), D_ALL);
> + MMIO_D(_MMIO(0xfcc24), D_ALL);
> + MMIO_D(_MMIO(0xfd000), D_ALL);
> + MMIO_D(_MMIO(0xfd00c), D_ALL);
> + MMIO_D(_MMIO(0xfd018), D_ALL);
> + MMIO_D(_MMIO(0xfd024), D_ALL);
> + MMIO_D(_MMIO(0xfd034), D_ALL);
> +
> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
> + MMIO_D(_MMIO(0x2054), D_ALL);
> + MMIO_D(_MMIO(0x12054), D_ALL);
> + MMIO_D(_MMIO(0x22054), D_ALL);
> + MMIO_D(_MMIO(0x1a054), D_ALL);
> +
> + MMIO_D(_MMIO(0x44070), D_ALL);
> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> +
> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
> +
> + return 0;
> +}
> +
> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
> +{
> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> + int ret;
> +
> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
> + intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
> +
> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
> + intel_vgpu_reg_master_irq_handler);
> +
> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
> + mmio_read_from_hw, NULL);
> +
> +#define RING_REG(base) _MMIO((base) + 0xd0)
> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
> + ring_reset_ctl_write);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x230)
> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x234)
> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
> + NULL, NULL);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x244)
> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x370)
> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
> +#undef RING_REG
> +
> +#define RING_REG(base) _MMIO((base) + 0x3a0)
> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
> +#undef RING_REG
> +
> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
> +
> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
> +
> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
> +
> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
> +
> +#define RING_REG(base) _MMIO((base) + 0x270)
> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> +#undef RING_REG
> +
> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
> +
> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
> +
> + MMIO_D(WM_MISC, D_BDW);
> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
> +
> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
> +
> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
> +
> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
> +
> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
> + MMIO_D(_MMIO(0xb110), D_BDW);
> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
> +
> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
> + D_BDW_PLUS, NULL, force_nonpriv_write);
> +
> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
> +
> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
> +
> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
> +
> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
> +
> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
> +
> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> + return 0;
> +}
> +
> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
> +{
> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> + int ret;
> +
> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> + dp_aux_ch_ctl_mmio_write);
> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> + dp_aux_ch_ctl_mmio_write);
> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> + dp_aux_ch_ctl_mmio_write);
> +
> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
> +
> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
> +
> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
> +
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> +
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> +
> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> +
> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> +
> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
> +
> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
> +
> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
> +
> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> + NULL, NULL);
> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> + NULL, NULL);
> +
> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> +
> + /* TRTT */
> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
> + NULL, gen9_trtte_write);
> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
> + NULL, gen9_trtt_chicken_write);
> +
> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
> +
> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
> +
> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
> +
> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
> +
> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
> +
> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
> +
> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, csfe_chicken1_mmio_write);
> +#undef CSFE_CHICKEN1_REG
> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> + NULL, NULL);
> +
> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
> +
> + return 0;
> +}
> +
> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
> +{
> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> + int ret;
> +
> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
> +
> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
> + MMIO_D(ERROR_GEN6, D_BXT);
> + MMIO_D(DONE_REG, D_BXT);
> + MMIO_D(EIR, D_BXT);
> + MMIO_D(PGTBL_ER, D_BXT);
> + MMIO_D(_MMIO(0x4194), D_BXT);
> + MMIO_D(_MMIO(0x4294), D_BXT);
> + MMIO_D(_MMIO(0x4494), D_BXT);
> +
> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
> + MMIO_RING_D(RING_IPEHR, D_BXT);
> + MMIO_RING_D(RING_INSTPS, D_BXT);
> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
> + MMIO_RING_D(RING_BBSTATE, D_BXT);
> + MMIO_RING_D(RING_IPEIR, D_BXT);
> +
> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
> +
> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
> + NULL, bxt_phy_ctl_family_write);
> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
> + NULL, bxt_phy_ctl_family_write);
> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
> + NULL, bxt_port_pll_enable_write);
> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
> + NULL, bxt_port_pll_enable_write);
> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
> + bxt_port_pll_enable_write);
> +
> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
> +
> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
> +
> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
> + NULL, bxt_pcs_dw12_grp_write);
> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
> + bxt_port_tx_dw3_read, NULL);
> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
> +
> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
> + NULL, bxt_pcs_dw12_grp_write);
> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
> + bxt_port_tx_dw3_read, NULL);
> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
> +
> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
> + NULL, bxt_pcs_dw12_grp_write);
> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
> + bxt_port_tx_dw3_read, NULL);
> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
> +
> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
> +
> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
> +
> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
> +
> + MMIO_D(RC6_CTX_BASE, D_BXT);
> +
> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> + 0, 0, D_BXT, NULL, NULL);
> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> + 0, 0, D_BXT, NULL, NULL);
> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> + 0, 0, D_BXT, NULL, NULL);
> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> + 0, 0, D_BXT, NULL, NULL);
> +
> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> +
> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
> +
> + return 0;
> +}
> +
> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
> +{
> + struct drm_i915_private *i915 = gvt->gt->i915;
> + int ret;
> +
> + ret = intel_gvt_init_generic_mmio_info(gvt);
> + if (ret)
> + return ret;
> +
> + if (IS_BROADWELL(i915)) {
> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> + if (ret)
> + return ret;
> + } else if (IS_SKYLAKE(i915) ||
> + IS_KABYLAKE(i915) ||
> + IS_COFFEELAKE(i915) ||
> + IS_COMETLAKE(i915)) {
> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> + if (ret)
> + return ret;
> + ret = intel_gvt_init_skl_mmio_info(gvt);
> + if (ret)
> + return ret;
> + } else if (IS_BROXTON(i915)) {
> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> + if (ret)
> + return ret;
> + ret = intel_gvt_init_skl_mmio_info(gvt);
> + if (ret)
> + return ret;
> + ret = intel_gvt_init_bxt_mmio_info(gvt);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +#endif
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index 244cc7320b54..05bd2f8e9d94 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -133,6 +133,12 @@
> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
> #define VF_GUARDBAND _MMIO(0x83a4)
>
> +/* XXX FIXME i915 has changed PP_XXX definition */
> +#define PCH_PP_STATUS _MMIO(0xc7200)
> +#define PCH_PP_CONTROL _MMIO(0xc7204)
> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
>
> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
> index 4e70c1a9ef2e..64846d9bff0b 100644
> --- a/drivers/gpu/drm/i915/intel_gvt.c
> +++ b/drivers/gpu/drm/i915/intel_gvt.c
> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
> dev_priv->params.enable_gvt = 0;
> }
>
> +#define GENERATE_MMIO_TABLE_IN_I915
> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
> +{
> + return 0;
> +}
> +
> +#include "gvt/reg.h"
> +#include "gvt/mmio_table.h"
> +#undef GENERATE_MMIO_TABLE_IN_I915
> +
> +
> /**
> * intel_gvt_init - initialize GVT components
> * @dev_priv: drm i915 private data
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-09 7:00 ` [Intel-gfx] " Jani Nikula
@ 2021-11-09 7:51 ` Christoph Hellwig
-1 siblings, 0 replies; 35+ messages in thread
From: Christoph Hellwig @ 2021-11-09 7:51 UTC (permalink / raw)
To: Jani Nikula
Cc: Zhi Wang, joonas.lahtinen, rodrigo.vivi, zhenyuw, zhi.a.wang,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
On Tue, Nov 09, 2021 at 09:00:39AM +0200, Jani Nikula wrote:
> On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
> > From: Zhi Wang <zhi.wang.linux@gmail.com>
> >
> > To support the new mdev interfaces and the re-factor patches from
> > Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
> > MMIO snapshot still needs to be saved in i915 so that the inital clean HW
> > state can be used for the further vGPU. Seperate the tracked MMIO table
> > from GVT-g, so that GVT-g and i915 can both use it.
>
> Do you really have to both put code in a header and then include that in
> multiple places?
>
> I think you may need to rethink the whole approach, maybe make them
> actual tables instead of code.
Without understanding this code too well: an approach that makes in
actual table and uses an accessor seems more useful to me as well.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 7:51 ` Christoph Hellwig
0 siblings, 0 replies; 35+ messages in thread
From: Christoph Hellwig @ 2021-11-09 7:51 UTC (permalink / raw)
To: Jani Nikula
Cc: Zhi Wang, intel-gfx, linux-kernel, dri-devel, jgg, intel-gvt-dev, hch
On Tue, Nov 09, 2021 at 09:00:39AM +0200, Jani Nikula wrote:
> On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
> > From: Zhi Wang <zhi.wang.linux@gmail.com>
> >
> > To support the new mdev interfaces and the re-factor patches from
> > Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
> > MMIO snapshot still needs to be saved in i915 so that the inital clean HW
> > state can be used for the further vGPU. Seperate the tracked MMIO table
> > from GVT-g, so that GVT-g and i915 can both use it.
>
> Do you really have to both put code in a header and then include that in
> multiple places?
>
> I think you may need to rethink the whole approach, maybe make them
> actual tables instead of code.
Without understanding this code too well: an approach that makes in
actual table and uses an accessor seems more useful to me as well.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-09 7:00 ` [Intel-gfx] " Jani Nikula
@ 2021-11-09 8:41 ` Wang, Zhi A
-1 siblings, 0 replies; 35+ messages in thread
From: Wang, Zhi A @ 2021-11-09 8:41 UTC (permalink / raw)
To: Jani Nikula, Zhi Wang, joonas.lahtinen, Vivi, Rodrigo, zhenyuw,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
On 11/9/2021 9:00 AM, Jani Nikula wrote:
> On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
>> From: Zhi Wang <zhi.wang.linux@gmail.com>
>>
>> To support the new mdev interfaces and the re-factor patches from
>> Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
>> MMIO snapshot still needs to be saved in i915 so that the inital clean HW
>> state can be used for the further vGPU. Seperate the tracked MMIO table
>> from GVT-g, so that GVT-g and i915 can both use it.
> Do you really have to both put code in a header and then include that in
> multiple places?
>
> I think you may need to rethink the whole approach, maybe make them
> actual tables instead of code.
>
Hi Jani:
Sadly we can't not use a static-defined struct for a MMIO table. (That's
actually how the code was before) Because:
1) We use the register defininations from i915.
2) Every MMIO register definiation in i915 is not a number. It's a macro
_MMIO(r), which can't be put in the static-defined struct. That's how
the code has been modified like this when it was merged upstream. The
MMIO table has to be created dynamically.
The MMIO table in the current GVT-g contains handlers in GVT-g code,
which shouldn't be built into i915 after it was moved into a dedicated
module. That's the reason I think putting it in a common header would be
better.
It would be nice to have some better ideas. Currently what in my mind
is: 1) Start a new .c file in gvt which contains the code to build MMIO
table and let it be used both by i915 and gvt. 2) i915 builds the table
and only use it for HW state saving. GVT-g builds a superior table and
attach the handlers. Does that sounds better?
Thanks,
Zhi.
> BR,
> Jani.
>
>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
>> Cc: Zhi Wang <zhi.a.wang@intel.com>
>> Cc: Christoph Hellwig <hch@lst.de>
>> Cc: Jason Gunthorpe <jgg@nvidia.com>
>> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
>> ---
>> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
>> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
>> drivers/gpu/drm/i915/gvt/reg.h | 6 +
>> drivers/gpu/drm/i915/intel_gvt.c | 11 +
>> 4 files changed, 1592 insertions(+), 1534 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
>>
>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>> index cde0a477fb49..6a08d362bf66 100644
>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>> @@ -41,13 +41,6 @@
>> #include "i915_pvinfo.h"
>> #include "display/intel_display_types.h"
>>
>> -/* XXX FIXME i915 has changed PP_XXX definition */
>> -#define PCH_PP_STATUS _MMIO(0xc7200)
>> -#define PCH_PP_CONTROL _MMIO(0xc7204)
>> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
>> -
>> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
>> {
>> struct drm_i915_private *i915 = gvt->gt->i915;
>> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
>> return 0;
>> }
>>
>> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>> - f, s, am, rm, d, r, w); \
>> - if (ret) \
>> - return ret; \
>> -} while (0)
>> -
>> -#define MMIO_D(reg, d) \
>> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>> -
>> -#define MMIO_DH(reg, d, r, w) \
>> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>> -
>> -#define MMIO_DFH(reg, d, f, r, w) \
>> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
>> -
>> -#define MMIO_GM(reg, d, r, w) \
>> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>> -
>> -#define MMIO_GM_RDR(reg, d, r, w) \
>> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>> -
>> -#define MMIO_RO(reg, d, f, rm, r, w) \
>> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>> -
>> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>> - if (HAS_ENGINE(gvt->gt, VCS1)) \
>> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>> -} while (0)
>> -
>> -#define MMIO_RING_D(prefix, d) \
>> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>> -
>> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
>> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>> -
>> -#define MMIO_RING_GM(prefix, d, r, w) \
>> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>> -
>> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>> -
>> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>> -
>> -static int init_generic_mmio_info(struct intel_gvt *gvt)
>> -{
>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>> - int ret;
>> -
>> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>> - intel_vgpu_reg_imr_handler);
>> -
>> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(SDEISR, D_ALL);
>> -
>> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>> -
>> -
>> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>> - gamw_echo_dev_rw_ia_write);
>> -
>> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x28)
>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x134)
>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x6c)
>> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>> -#undef RING_REG
>> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>> -
>> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
>> -
>> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>> -
>> - /* RING MODE */
>> -#define RING_REG(base) _MMIO((base) + 0x29c)
>> - MMIO_RING_DFH(RING_REG, D_ALL,
>> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>> - ring_mode_mmio_write);
>> -#undef RING_REG
>> -
>> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>> - mmio_read_from_hw, NULL);
>> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>> - mmio_read_from_hw, NULL);
>> -
>> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> -
>> - /* display */
>> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_D(_MMIO(0x602a0), D_ALL);
>> -
>> - MMIO_D(_MMIO(0x65050), D_ALL);
>> - MMIO_D(_MMIO(0x650b4), D_ALL);
>> -
>> - MMIO_D(_MMIO(0xc4040), D_ALL);
>> - MMIO_D(DERRMR, D_ALL);
>> -
>> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>> -
>> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>> -
>> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>> -
>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>> -
>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>> -
>> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
>> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
>> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
>> -
>> - MMIO_D(CURPOS(PIPE_A), D_ALL);
>> - MMIO_D(CURPOS(PIPE_B), D_ALL);
>> - MMIO_D(CURPOS(PIPE_C), D_ALL);
>> -
>> - MMIO_D(CURBASE(PIPE_A), D_ALL);
>> - MMIO_D(CURBASE(PIPE_B), D_ALL);
>> - MMIO_D(CURBASE(PIPE_C), D_ALL);
>> -
>> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>> -
>> - MMIO_D(_MMIO(0x700ac), D_ALL);
>> - MMIO_D(_MMIO(0x710ac), D_ALL);
>> - MMIO_D(_MMIO(0x720ac), D_ALL);
>> -
>> - MMIO_D(_MMIO(0x70090), D_ALL);
>> - MMIO_D(_MMIO(0x70094), D_ALL);
>> - MMIO_D(_MMIO(0x70098), D_ALL);
>> - MMIO_D(_MMIO(0x7009c), D_ALL);
>> -
>> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
>> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
>> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
>> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
>> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
>> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
>> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
>> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
>> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
>> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
>> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
>> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
>> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>> -
>> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>> -
>> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>> -
>> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>> -
>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>> -
>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>> -
>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>> -
>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>> -
>> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
>> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>> -
>> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
>> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>> -
>> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
>> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>> -
>> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>> - MMIO_D(WM1_LP_ILK, D_ALL);
>> - MMIO_D(WM2_LP_ILK, D_ALL);
>> - MMIO_D(WM3_LP_ILK, D_ALL);
>> - MMIO_D(WM1S_LP_ILK, D_ALL);
>> - MMIO_D(WM2S_LP_IVB, D_ALL);
>> - MMIO_D(WM3S_LP_IVB, D_ALL);
>> -
>> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>> -
>> - MMIO_D(_MMIO(0x48268), D_ALL);
>> -
>> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>> - gmbus_mmio_write);
>> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> -
>> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>> -
>> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>> -
>> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>> -
>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>> -
>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>> -
>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>> -
>> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>> -
>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>> -
>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>> -
>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>> -
>> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>> -
>> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
>> - MMIO_D(PCH_PP_STATUS, D_ALL);
>> - MMIO_D(PCH_LVDS, D_ALL);
>> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
>> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>> - MMIO_D(PCH_DPLL_SEL, D_ALL);
>> -
>> - MMIO_D(_MMIO(0x61208), D_ALL);
>> - MMIO_D(_MMIO(0x6120c), D_ALL);
>> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>> -
>> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>> -
>> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>> - PORTA_HOTPLUG_STATUS_MASK
>> - | PORTB_HOTPLUG_STATUS_MASK
>> - | PORTC_HOTPLUG_STATUS_MASK
>> - | PORTD_HOTPLUG_STATUS_MASK,
>> - NULL, NULL);
>> -
>> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>> - MMIO_D(FUSE_STRAP, D_ALL);
>> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>> -
>> - MMIO_D(DISP_ARB_CTL, D_ALL);
>> - MMIO_D(DISP_ARB_CTL2, D_ALL);
>> -
>> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>> -
>> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
>> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>> -
>> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
>> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>> -
>> - MMIO_D(IPS_CTL, D_ALL);
>> -
>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>> -
>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>> -
>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>> -
>> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(_MMIO(0x60110), D_ALL);
>> - MMIO_D(_MMIO(0x61110), D_ALL);
>> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> -
>> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>> - MMIO_D(SPLL_CTL, D_ALL);
>> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>> -
>> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>> - MMIO_D(_MMIO(0x46508), D_ALL);
>> -
>> - MMIO_D(_MMIO(0x49080), D_ALL);
>> - MMIO_D(_MMIO(0x49180), D_ALL);
>> - MMIO_D(_MMIO(0x49280), D_ALL);
>> -
>> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>> -
>> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>> -
>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>> -
>> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>> - MMIO_D(SBI_ADDR, D_ALL);
>> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>> - MMIO_D(PIXCLK_GATE, D_ALL);
>> -
>> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> -
>> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> -
>> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> -
>> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>> -
>> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>> -
>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>> -
>> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>> -
>> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>> - MMIO_D(FORCEWAKE_ACK, D_ALL);
>> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>> - MMIO_D(ECOBUS, D_ALL);
>> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
>> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>> - MMIO_D(GEN6_RPSTAT1, D_ALL);
>> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
>> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
>> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
>> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
>> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>> -
>> - MMIO_D(RSTDBYCTL, D_ALL);
>> -
>> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>> -
>> - MMIO_D(TILECTL, D_ALL);
>> -
>> - MMIO_D(GEN6_UCGCTL1, D_ALL);
>> - MMIO_D(GEN6_UCGCTL2, D_ALL);
>> -
>> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
>> - MMIO_D(_MMIO(0x13812c), D_ALL);
>> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
>> - MMIO_D(HSW_IDICR, D_ALL);
>> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(_MMIO(0x3c), D_ALL);
>> - MMIO_D(_MMIO(0x860), D_ALL);
>> - MMIO_D(ECOSKPD, D_ALL);
>> - MMIO_D(_MMIO(0x121d0), D_ALL);
>> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>> - MMIO_D(_MMIO(0x41d0), D_ALL);
>> - MMIO_D(GAC_ECO_BITS, D_ALL);
>> - MMIO_D(_MMIO(0x6200), D_ALL);
>> - MMIO_D(_MMIO(0x6204), D_ALL);
>> - MMIO_D(_MMIO(0x6208), D_ALL);
>> - MMIO_D(_MMIO(0x7118), D_ALL);
>> - MMIO_D(_MMIO(0x7180), D_ALL);
>> - MMIO_D(_MMIO(0x7408), D_ALL);
>> - MMIO_D(_MMIO(0x7c00), D_ALL);
>> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>> - MMIO_D(_MMIO(0x911c), D_ALL);
>> - MMIO_D(_MMIO(0x9120), D_ALL);
>> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_D(GAB_CTL, D_ALL);
>> - MMIO_D(_MMIO(0x48800), D_ALL);
>> - MMIO_D(_MMIO(0xce044), D_ALL);
>> - MMIO_D(_MMIO(0xe6500), D_ALL);
>> - MMIO_D(_MMIO(0xe6504), D_ALL);
>> - MMIO_D(_MMIO(0xe6600), D_ALL);
>> - MMIO_D(_MMIO(0xe6604), D_ALL);
>> - MMIO_D(_MMIO(0xe6700), D_ALL);
>> - MMIO_D(_MMIO(0xe6704), D_ALL);
>> - MMIO_D(_MMIO(0xe6800), D_ALL);
>> - MMIO_D(_MMIO(0xe6804), D_ALL);
>> - MMIO_D(PCH_GMBUS4, D_ALL);
>> - MMIO_D(PCH_GMBUS5, D_ALL);
>> -
>> - MMIO_D(_MMIO(0x902c), D_ALL);
>> - MMIO_D(_MMIO(0xec008), D_ALL);
>> - MMIO_D(_MMIO(0xec00c), D_ALL);
>> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>> - MMIO_D(_MMIO(0xec408), D_ALL);
>> - MMIO_D(_MMIO(0xec40c), D_ALL);
>> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>> - MMIO_D(_MMIO(0xfc810), D_ALL);
>> - MMIO_D(_MMIO(0xfc81c), D_ALL);
>> - MMIO_D(_MMIO(0xfc828), D_ALL);
>> - MMIO_D(_MMIO(0xfc834), D_ALL);
>> - MMIO_D(_MMIO(0xfcc00), D_ALL);
>> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
>> - MMIO_D(_MMIO(0xfcc18), D_ALL);
>> - MMIO_D(_MMIO(0xfcc24), D_ALL);
>> - MMIO_D(_MMIO(0xfd000), D_ALL);
>> - MMIO_D(_MMIO(0xfd00c), D_ALL);
>> - MMIO_D(_MMIO(0xfd018), D_ALL);
>> - MMIO_D(_MMIO(0xfd024), D_ALL);
>> - MMIO_D(_MMIO(0xfd034), D_ALL);
>> -
>> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>> - MMIO_D(_MMIO(0x2054), D_ALL);
>> - MMIO_D(_MMIO(0x12054), D_ALL);
>> - MMIO_D(_MMIO(0x22054), D_ALL);
>> - MMIO_D(_MMIO(0x1a054), D_ALL);
>> -
>> - MMIO_D(_MMIO(0x44070), D_ALL);
>> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>> -
>> - return 0;
>> -}
>> -
>> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
>> -{
>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>> - int ret;
>> -
>> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_master_irq_handler);
>> -
>> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>> - mmio_read_from_hw, NULL);
>> -
>> -#define RING_REG(base) _MMIO((base) + 0xd0)
>> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
>> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>> - ring_reset_ctl_write);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x230)
>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x234)
>> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>> - NULL, NULL);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x244)
>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x370)
>> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x3a0)
>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>> -#undef RING_REG
>> -
>> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>> -
>> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>> -
>> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x270)
>> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>> -#undef RING_REG
>> -
>> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>> -
>> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>> -
>> - MMIO_D(WM_MISC, D_BDW);
>> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>> -
>> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>> -
>> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>> -
>> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>> -
>> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_D(_MMIO(0xb110), D_BDW);
>> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>> -
>> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>> - D_BDW_PLUS, NULL, force_nonpriv_write);
>> -
>> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>> -
>> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>> -
>> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>> -
>> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>> -
>> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>> -
>> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - return 0;
>> -}
>> -
>> -static int init_skl_mmio_info(struct intel_gvt *gvt)
>> -{
>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>> - int ret;
>> -
>> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> -
>> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>> -
>> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>> -
>> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>> -
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> -
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> -
>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> -
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>> -
>> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>> -
>> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
>> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>> -
>> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>> - NULL, NULL);
>> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>> - NULL, NULL);
>> -
>> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> -
>> - /* TRTT */
>> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>> - NULL, gen9_trtte_write);
>> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>> - NULL, gen9_trtt_chicken_write);
>> -
>> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>> -
>> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>> -
>> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>> -
>> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>> -
>> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>> -
>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>> -
>> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, csfe_chicken1_mmio_write);
>> -#undef CSFE_CHICKEN1_REG
>> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> -
>> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>> -
>> - return 0;
>> -}
>> -
>> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
>> -{
>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>> - int ret;
>> -
>> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>> -
>> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>> - MMIO_D(ERROR_GEN6, D_BXT);
>> - MMIO_D(DONE_REG, D_BXT);
>> - MMIO_D(EIR, D_BXT);
>> - MMIO_D(PGTBL_ER, D_BXT);
>> - MMIO_D(_MMIO(0x4194), D_BXT);
>> - MMIO_D(_MMIO(0x4294), D_BXT);
>> - MMIO_D(_MMIO(0x4494), D_BXT);
>> -
>> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
>> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>> - MMIO_RING_D(RING_IPEHR, D_BXT);
>> - MMIO_RING_D(RING_INSTPS, D_BXT);
>> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>> - MMIO_RING_D(RING_BBSTATE, D_BXT);
>> - MMIO_RING_D(RING_IPEIR, D_BXT);
>> -
>> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>> -
>> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>> - NULL, bxt_phy_ctl_family_write);
>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>> - NULL, bxt_phy_ctl_family_write);
>> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>> - NULL, bxt_port_pll_enable_write);
>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>> - NULL, bxt_port_pll_enable_write);
>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>> - bxt_port_pll_enable_write);
>> -
>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>> -
>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>> -
>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>> - NULL, bxt_pcs_dw12_grp_write);
>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>> - bxt_port_tx_dw3_read, NULL);
>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>> -
>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>> - NULL, bxt_pcs_dw12_grp_write);
>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>> - bxt_port_tx_dw3_read, NULL);
>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>> -
>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>> - NULL, bxt_pcs_dw12_grp_write);
>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>> - bxt_port_tx_dw3_read, NULL);
>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>> -
>> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>> -
>> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>> -
>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>> -
>> - MMIO_D(RC6_CTX_BASE, D_BXT);
>> -
>> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
>> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> - 0, 0, D_BXT, NULL, NULL);
>> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> - 0, 0, D_BXT, NULL, NULL);
>> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> - 0, 0, D_BXT, NULL, NULL);
>> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> - 0, 0, D_BXT, NULL, NULL);
>> -
>> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>> -
>> - return 0;
>> -}
>> +#include "mmio_table.h"
>>
>> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
>> unsigned int offset)
>> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
>> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>> {
>> struct intel_gvt_device_info *info = &gvt->device_info;
>> - struct drm_i915_private *i915 = gvt->gt->i915;
>> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
>> int ret;
>>
>> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>> if (!gvt->mmio.mmio_attribute)
>> return -ENOMEM;
>>
>> - ret = init_generic_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> -
>> - if (IS_BROADWELL(i915)) {
>> - ret = init_bdw_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> - } else if (IS_SKYLAKE(i915) ||
>> - IS_KABYLAKE(i915) ||
>> - IS_COFFEELAKE(i915) ||
>> - IS_COMETLAKE(i915)) {
>> - ret = init_bdw_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> - ret = init_skl_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> - } else if (IS_BROXTON(i915)) {
>> - ret = init_bdw_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> - ret = init_skl_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> - ret = init_bxt_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> + ret = intel_gvt_init_mmio_info(gvt);
>> + if (ret) {
>> + intel_gvt_clean_mmio_info(gvt);
>> + return ret;
>> }
>>
>> gvt->mmio.mmio_block = mmio_blocks;
>> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
>>
>> return 0;
>> -err:
>> - intel_gvt_clean_mmio_info(gvt);
>> - return ret;
>> }
>>
>> /**
>> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
>> new file mode 100644
>> index 000000000000..39a4cb59695a
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
>> @@ -0,0 +1,1570 @@
>> +/*
>> + * Copyright © 2021 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */
>> +
>> +#ifndef _GVT_MMIO_TABLE_H_
>> +#define _GVT_MMIO_TABLE_H_
>> +
>> +#ifdef GENERATE_MMIO_TABLE_IN_I915
>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
>> + if (ret) \
>> + return ret; \
>> +} while (0)
>> +#else
>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>> + f, s, am, rm, d, r, w); \
>> + if (ret) \
>> + return ret; \
>> +} while (0)
>> +#endif
>> +
>> +#define MMIO_D(reg, d) \
>> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>> +
>> +#define MMIO_DH(reg, d, r, w) \
>> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>> +
>> +#define MMIO_DFH(reg, d, f, r, w) \
>> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
>> +
>> +#define MMIO_GM(reg, d, r, w) \
>> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>> +
>> +#define MMIO_GM_RDR(reg, d, r, w) \
>> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>> +
>> +#define MMIO_RO(reg, d, f, rm, r, w) \
>> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>> +
>> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>> + if (HAS_ENGINE(gvt->gt, VCS1)) \
>> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>> +} while (0)
>> +
>> +#define MMIO_RING_D(prefix, d) \
>> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>> +
>> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
>> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>> +
>> +#define MMIO_RING_GM(prefix, d, r, w) \
>> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>> +
>> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>> +
>> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>> +
>> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
>> +{
>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>> +
>> + int ret;
>> +
>> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>> + intel_vgpu_reg_imr_handler);
>> +
>> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(SDEISR, D_ALL);
>> +
>> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>> +
>> +
>> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>> + gamw_echo_dev_rw_ia_write);
>> +
>> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x28)
>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x134)
>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x6c)
>> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>> +#undef RING_REG
>> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>> +
>> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
>> +
>> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>> +
>> + /* RING MODE */
>> +#define RING_REG(base) _MMIO((base) + 0x29c)
>> + MMIO_RING_DFH(RING_REG, D_ALL,
>> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>> + ring_mode_mmio_write);
>> +#undef RING_REG
>> +
>> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>> + mmio_read_from_hw, NULL);
>> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>> + mmio_read_from_hw, NULL);
>> +
>> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> +
>> + /* display */
>> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_D(_MMIO(0x602a0), D_ALL);
>> +
>> + MMIO_D(_MMIO(0x65050), D_ALL);
>> + MMIO_D(_MMIO(0x650b4), D_ALL);
>> +
>> + MMIO_D(_MMIO(0xc4040), D_ALL);
>> + MMIO_D(DERRMR, D_ALL);
>> +
>> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>> +
>> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>> +
>> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>> +
>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>> +
>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>> +
>> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
>> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
>> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
>> +
>> + MMIO_D(CURPOS(PIPE_A), D_ALL);
>> + MMIO_D(CURPOS(PIPE_B), D_ALL);
>> + MMIO_D(CURPOS(PIPE_C), D_ALL);
>> +
>> + MMIO_D(CURBASE(PIPE_A), D_ALL);
>> + MMIO_D(CURBASE(PIPE_B), D_ALL);
>> + MMIO_D(CURBASE(PIPE_C), D_ALL);
>> +
>> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>> +
>> + MMIO_D(_MMIO(0x700ac), D_ALL);
>> + MMIO_D(_MMIO(0x710ac), D_ALL);
>> + MMIO_D(_MMIO(0x720ac), D_ALL);
>> +
>> + MMIO_D(_MMIO(0x70090), D_ALL);
>> + MMIO_D(_MMIO(0x70094), D_ALL);
>> + MMIO_D(_MMIO(0x70098), D_ALL);
>> + MMIO_D(_MMIO(0x7009c), D_ALL);
>> +
>> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
>> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
>> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
>> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
>> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
>> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
>> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
>> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
>> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
>> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
>> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
>> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
>> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>> +
>> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>> +
>> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>> +
>> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>> +
>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>> +
>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>> +
>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>> +
>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>> +
>> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
>> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>> +
>> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
>> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>> +
>> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
>> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>> +
>> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>> + MMIO_D(WM1_LP_ILK, D_ALL);
>> + MMIO_D(WM2_LP_ILK, D_ALL);
>> + MMIO_D(WM3_LP_ILK, D_ALL);
>> + MMIO_D(WM1S_LP_ILK, D_ALL);
>> + MMIO_D(WM2S_LP_IVB, D_ALL);
>> + MMIO_D(WM3S_LP_IVB, D_ALL);
>> +
>> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>> +
>> + MMIO_D(_MMIO(0x48268), D_ALL);
>> +
>> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>> + gmbus_mmio_write);
>> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> +
>> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>> +
>> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>> +
>> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>> +
>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>> +
>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>> +
>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>> +
>> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>> +
>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>> +
>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>> +
>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>> +
>> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>> +
>> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
>> + MMIO_D(PCH_PP_STATUS, D_ALL);
>> + MMIO_D(PCH_LVDS, D_ALL);
>> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
>> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>> + MMIO_D(PCH_DPLL_SEL, D_ALL);
>> +
>> + MMIO_D(_MMIO(0x61208), D_ALL);
>> + MMIO_D(_MMIO(0x6120c), D_ALL);
>> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>> +
>> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>> +
>> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>> + PORTA_HOTPLUG_STATUS_MASK
>> + | PORTB_HOTPLUG_STATUS_MASK
>> + | PORTC_HOTPLUG_STATUS_MASK
>> + | PORTD_HOTPLUG_STATUS_MASK,
>> + NULL, NULL);
>> +
>> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>> + MMIO_D(FUSE_STRAP, D_ALL);
>> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>> +
>> + MMIO_D(DISP_ARB_CTL, D_ALL);
>> + MMIO_D(DISP_ARB_CTL2, D_ALL);
>> +
>> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>> +
>> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
>> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>> +
>> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
>> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>> +
>> + MMIO_D(IPS_CTL, D_ALL);
>> +
>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>> +
>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>> +
>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>> +
>> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(_MMIO(0x60110), D_ALL);
>> + MMIO_D(_MMIO(0x61110), D_ALL);
>> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> +
>> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>> + MMIO_D(SPLL_CTL, D_ALL);
>> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>> +
>> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>> + MMIO_D(_MMIO(0x46508), D_ALL);
>> +
>> + MMIO_D(_MMIO(0x49080), D_ALL);
>> + MMIO_D(_MMIO(0x49180), D_ALL);
>> + MMIO_D(_MMIO(0x49280), D_ALL);
>> +
>> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>> +
>> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>> +
>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>> +
>> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>> + MMIO_D(SBI_ADDR, D_ALL);
>> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>> + MMIO_D(PIXCLK_GATE, D_ALL);
>> +
>> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> +
>> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> +
>> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> +
>> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>> +
>> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>> +
>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>> +
>> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>> +
>> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>> + MMIO_D(FORCEWAKE_ACK, D_ALL);
>> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>> + MMIO_D(ECOBUS, D_ALL);
>> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
>> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>> + MMIO_D(GEN6_RPSTAT1, D_ALL);
>> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
>> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
>> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
>> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
>> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>> +
>> + MMIO_D(RSTDBYCTL, D_ALL);
>> +
>> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>> +
>> + MMIO_D(TILECTL, D_ALL);
>> +
>> + MMIO_D(GEN6_UCGCTL1, D_ALL);
>> + MMIO_D(GEN6_UCGCTL2, D_ALL);
>> +
>> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
>> + MMIO_D(_MMIO(0x13812c), D_ALL);
>> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
>> + MMIO_D(HSW_IDICR, D_ALL);
>> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(_MMIO(0x3c), D_ALL);
>> + MMIO_D(_MMIO(0x860), D_ALL);
>> + MMIO_D(ECOSKPD, D_ALL);
>> + MMIO_D(_MMIO(0x121d0), D_ALL);
>> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>> + MMIO_D(_MMIO(0x41d0), D_ALL);
>> + MMIO_D(GAC_ECO_BITS, D_ALL);
>> + MMIO_D(_MMIO(0x6200), D_ALL);
>> + MMIO_D(_MMIO(0x6204), D_ALL);
>> + MMIO_D(_MMIO(0x6208), D_ALL);
>> + MMIO_D(_MMIO(0x7118), D_ALL);
>> + MMIO_D(_MMIO(0x7180), D_ALL);
>> + MMIO_D(_MMIO(0x7408), D_ALL);
>> + MMIO_D(_MMIO(0x7c00), D_ALL);
>> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>> + MMIO_D(_MMIO(0x911c), D_ALL);
>> + MMIO_D(_MMIO(0x9120), D_ALL);
>> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_D(GAB_CTL, D_ALL);
>> + MMIO_D(_MMIO(0x48800), D_ALL);
>> + MMIO_D(_MMIO(0xce044), D_ALL);
>> + MMIO_D(_MMIO(0xe6500), D_ALL);
>> + MMIO_D(_MMIO(0xe6504), D_ALL);
>> + MMIO_D(_MMIO(0xe6600), D_ALL);
>> + MMIO_D(_MMIO(0xe6604), D_ALL);
>> + MMIO_D(_MMIO(0xe6700), D_ALL);
>> + MMIO_D(_MMIO(0xe6704), D_ALL);
>> + MMIO_D(_MMIO(0xe6800), D_ALL);
>> + MMIO_D(_MMIO(0xe6804), D_ALL);
>> + MMIO_D(PCH_GMBUS4, D_ALL);
>> + MMIO_D(PCH_GMBUS5, D_ALL);
>> +
>> + MMIO_D(_MMIO(0x902c), D_ALL);
>> + MMIO_D(_MMIO(0xec008), D_ALL);
>> + MMIO_D(_MMIO(0xec00c), D_ALL);
>> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>> + MMIO_D(_MMIO(0xec408), D_ALL);
>> + MMIO_D(_MMIO(0xec40c), D_ALL);
>> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>> + MMIO_D(_MMIO(0xfc810), D_ALL);
>> + MMIO_D(_MMIO(0xfc81c), D_ALL);
>> + MMIO_D(_MMIO(0xfc828), D_ALL);
>> + MMIO_D(_MMIO(0xfc834), D_ALL);
>> + MMIO_D(_MMIO(0xfcc00), D_ALL);
>> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
>> + MMIO_D(_MMIO(0xfcc18), D_ALL);
>> + MMIO_D(_MMIO(0xfcc24), D_ALL);
>> + MMIO_D(_MMIO(0xfd000), D_ALL);
>> + MMIO_D(_MMIO(0xfd00c), D_ALL);
>> + MMIO_D(_MMIO(0xfd018), D_ALL);
>> + MMIO_D(_MMIO(0xfd024), D_ALL);
>> + MMIO_D(_MMIO(0xfd034), D_ALL);
>> +
>> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>> + MMIO_D(_MMIO(0x2054), D_ALL);
>> + MMIO_D(_MMIO(0x12054), D_ALL);
>> + MMIO_D(_MMIO(0x22054), D_ALL);
>> + MMIO_D(_MMIO(0x1a054), D_ALL);
>> +
>> + MMIO_D(_MMIO(0x44070), D_ALL);
>> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>> +
>> + return 0;
>> +}
>> +
>> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
>> +{
>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>> + int ret;
>> +
>> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_master_irq_handler);
>> +
>> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>> + mmio_read_from_hw, NULL);
>> +
>> +#define RING_REG(base) _MMIO((base) + 0xd0)
>> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
>> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>> + ring_reset_ctl_write);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x230)
>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x234)
>> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>> + NULL, NULL);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x244)
>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x370)
>> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x3a0)
>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>> +#undef RING_REG
>> +
>> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>> +
>> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>> +
>> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x270)
>> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>> +#undef RING_REG
>> +
>> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>> +
>> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>> +
>> + MMIO_D(WM_MISC, D_BDW);
>> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>> +
>> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>> +
>> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>> +
>> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>> +
>> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_D(_MMIO(0xb110), D_BDW);
>> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>> +
>> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>> + D_BDW_PLUS, NULL, force_nonpriv_write);
>> +
>> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>> +
>> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>> +
>> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>> +
>> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>> +
>> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>> +
>> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + return 0;
>> +}
>> +
>> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
>> +{
>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>> + int ret;
>> +
>> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> +
>> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>> +
>> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>> +
>> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>> +
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> +
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> +
>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> +
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>> +
>> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>> +
>> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
>> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>> +
>> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>> + NULL, NULL);
>> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>> + NULL, NULL);
>> +
>> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> +
>> + /* TRTT */
>> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>> + NULL, gen9_trtte_write);
>> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>> + NULL, gen9_trtt_chicken_write);
>> +
>> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>> +
>> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>> +
>> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>> +
>> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>> +
>> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>> +
>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>> +
>> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, csfe_chicken1_mmio_write);
>> +#undef CSFE_CHICKEN1_REG
>> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> +
>> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>> +
>> + return 0;
>> +}
>> +
>> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
>> +{
>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>> + int ret;
>> +
>> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>> +
>> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>> + MMIO_D(ERROR_GEN6, D_BXT);
>> + MMIO_D(DONE_REG, D_BXT);
>> + MMIO_D(EIR, D_BXT);
>> + MMIO_D(PGTBL_ER, D_BXT);
>> + MMIO_D(_MMIO(0x4194), D_BXT);
>> + MMIO_D(_MMIO(0x4294), D_BXT);
>> + MMIO_D(_MMIO(0x4494), D_BXT);
>> +
>> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
>> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>> + MMIO_RING_D(RING_IPEHR, D_BXT);
>> + MMIO_RING_D(RING_INSTPS, D_BXT);
>> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>> + MMIO_RING_D(RING_BBSTATE, D_BXT);
>> + MMIO_RING_D(RING_IPEIR, D_BXT);
>> +
>> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>> +
>> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>> + NULL, bxt_phy_ctl_family_write);
>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>> + NULL, bxt_phy_ctl_family_write);
>> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>> + NULL, bxt_port_pll_enable_write);
>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>> + NULL, bxt_port_pll_enable_write);
>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>> + bxt_port_pll_enable_write);
>> +
>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>> +
>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>> +
>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>> + NULL, bxt_pcs_dw12_grp_write);
>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>> + bxt_port_tx_dw3_read, NULL);
>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>> +
>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>> + NULL, bxt_pcs_dw12_grp_write);
>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>> + bxt_port_tx_dw3_read, NULL);
>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>> +
>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>> + NULL, bxt_pcs_dw12_grp_write);
>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>> + bxt_port_tx_dw3_read, NULL);
>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>> +
>> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>> +
>> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>> +
>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>> +
>> + MMIO_D(RC6_CTX_BASE, D_BXT);
>> +
>> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
>> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> + 0, 0, D_BXT, NULL, NULL);
>> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> + 0, 0, D_BXT, NULL, NULL);
>> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> + 0, 0, D_BXT, NULL, NULL);
>> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> + 0, 0, D_BXT, NULL, NULL);
>> +
>> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>> +
>> + return 0;
>> +}
>> +
>> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
>> +{
>> + struct drm_i915_private *i915 = gvt->gt->i915;
>> + int ret;
>> +
>> + ret = intel_gvt_init_generic_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> +
>> + if (IS_BROADWELL(i915)) {
>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + } else if (IS_SKYLAKE(i915) ||
>> + IS_KABYLAKE(i915) ||
>> + IS_COFFEELAKE(i915) ||
>> + IS_COMETLAKE(i915)) {
>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + } else if (IS_BROXTON(i915)) {
>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + ret = intel_gvt_init_bxt_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +#endif
>> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
>> index 244cc7320b54..05bd2f8e9d94 100644
>> --- a/drivers/gpu/drm/i915/gvt/reg.h
>> +++ b/drivers/gpu/drm/i915/gvt/reg.h
>> @@ -133,6 +133,12 @@
>> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
>> #define VF_GUARDBAND _MMIO(0x83a4)
>>
>> +/* XXX FIXME i915 has changed PP_XXX definition */
>> +#define PCH_PP_STATUS _MMIO(0xc7200)
>> +#define PCH_PP_CONTROL _MMIO(0xc7204)
>> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>
>> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
>> #endif
>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
>> index 4e70c1a9ef2e..64846d9bff0b 100644
>> --- a/drivers/gpu/drm/i915/intel_gvt.c
>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
>> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>> dev_priv->params.enable_gvt = 0;
>> }
>>
>> +#define GENERATE_MMIO_TABLE_IN_I915
>> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
>> +{
>> + return 0;
>> +}
>> +
>> +#include "gvt/reg.h"
>> +#include "gvt/mmio_table.h"
>> +#undef GENERATE_MMIO_TABLE_IN_I915
>> +
>> +
>> /**
>> * intel_gvt_init - initialize GVT components
>> * @dev_priv: drm i915 private data
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 8:41 ` Wang, Zhi A
0 siblings, 0 replies; 35+ messages in thread
From: Wang, Zhi A @ 2021-11-09 8:41 UTC (permalink / raw)
To: Jani Nikula, Zhi Wang, joonas.lahtinen, Vivi, Rodrigo, zhenyuw,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
On 11/9/2021 9:00 AM, Jani Nikula wrote:
> On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
>> From: Zhi Wang <zhi.wang.linux@gmail.com>
>>
>> To support the new mdev interfaces and the re-factor patches from
>> Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
>> MMIO snapshot still needs to be saved in i915 so that the inital clean HW
>> state can be used for the further vGPU. Seperate the tracked MMIO table
>> from GVT-g, so that GVT-g and i915 can both use it.
> Do you really have to both put code in a header and then include that in
> multiple places?
>
> I think you may need to rethink the whole approach, maybe make them
> actual tables instead of code.
>
Hi Jani:
Sadly we can't not use a static-defined struct for a MMIO table. (That's
actually how the code was before) Because:
1) We use the register defininations from i915.
2) Every MMIO register definiation in i915 is not a number. It's a macro
_MMIO(r), which can't be put in the static-defined struct. That's how
the code has been modified like this when it was merged upstream. The
MMIO table has to be created dynamically.
The MMIO table in the current GVT-g contains handlers in GVT-g code,
which shouldn't be built into i915 after it was moved into a dedicated
module. That's the reason I think putting it in a common header would be
better.
It would be nice to have some better ideas. Currently what in my mind
is: 1) Start a new .c file in gvt which contains the code to build MMIO
table and let it be used both by i915 and gvt. 2) i915 builds the table
and only use it for HW state saving. GVT-g builds a superior table and
attach the handlers. Does that sounds better?
Thanks,
Zhi.
> BR,
> Jani.
>
>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
>> Cc: Zhi Wang <zhi.a.wang@intel.com>
>> Cc: Christoph Hellwig <hch@lst.de>
>> Cc: Jason Gunthorpe <jgg@nvidia.com>
>> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
>> ---
>> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
>> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
>> drivers/gpu/drm/i915/gvt/reg.h | 6 +
>> drivers/gpu/drm/i915/intel_gvt.c | 11 +
>> 4 files changed, 1592 insertions(+), 1534 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
>>
>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>> index cde0a477fb49..6a08d362bf66 100644
>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>> @@ -41,13 +41,6 @@
>> #include "i915_pvinfo.h"
>> #include "display/intel_display_types.h"
>>
>> -/* XXX FIXME i915 has changed PP_XXX definition */
>> -#define PCH_PP_STATUS _MMIO(0xc7200)
>> -#define PCH_PP_CONTROL _MMIO(0xc7204)
>> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
>> -
>> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
>> {
>> struct drm_i915_private *i915 = gvt->gt->i915;
>> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
>> return 0;
>> }
>>
>> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>> - f, s, am, rm, d, r, w); \
>> - if (ret) \
>> - return ret; \
>> -} while (0)
>> -
>> -#define MMIO_D(reg, d) \
>> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>> -
>> -#define MMIO_DH(reg, d, r, w) \
>> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>> -
>> -#define MMIO_DFH(reg, d, f, r, w) \
>> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
>> -
>> -#define MMIO_GM(reg, d, r, w) \
>> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>> -
>> -#define MMIO_GM_RDR(reg, d, r, w) \
>> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>> -
>> -#define MMIO_RO(reg, d, f, rm, r, w) \
>> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>> -
>> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>> - if (HAS_ENGINE(gvt->gt, VCS1)) \
>> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>> -} while (0)
>> -
>> -#define MMIO_RING_D(prefix, d) \
>> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>> -
>> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
>> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>> -
>> -#define MMIO_RING_GM(prefix, d, r, w) \
>> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>> -
>> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>> -
>> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>> -
>> -static int init_generic_mmio_info(struct intel_gvt *gvt)
>> -{
>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>> - int ret;
>> -
>> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>> - intel_vgpu_reg_imr_handler);
>> -
>> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(SDEISR, D_ALL);
>> -
>> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>> -
>> -
>> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>> - gamw_echo_dev_rw_ia_write);
>> -
>> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x28)
>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x134)
>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x6c)
>> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>> -#undef RING_REG
>> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>> -
>> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
>> -
>> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>> -
>> - /* RING MODE */
>> -#define RING_REG(base) _MMIO((base) + 0x29c)
>> - MMIO_RING_DFH(RING_REG, D_ALL,
>> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>> - ring_mode_mmio_write);
>> -#undef RING_REG
>> -
>> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>> - mmio_read_from_hw, NULL);
>> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>> - mmio_read_from_hw, NULL);
>> -
>> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> -
>> - /* display */
>> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_D(_MMIO(0x602a0), D_ALL);
>> -
>> - MMIO_D(_MMIO(0x65050), D_ALL);
>> - MMIO_D(_MMIO(0x650b4), D_ALL);
>> -
>> - MMIO_D(_MMIO(0xc4040), D_ALL);
>> - MMIO_D(DERRMR, D_ALL);
>> -
>> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>> -
>> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>> -
>> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>> -
>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>> -
>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>> -
>> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
>> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
>> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
>> -
>> - MMIO_D(CURPOS(PIPE_A), D_ALL);
>> - MMIO_D(CURPOS(PIPE_B), D_ALL);
>> - MMIO_D(CURPOS(PIPE_C), D_ALL);
>> -
>> - MMIO_D(CURBASE(PIPE_A), D_ALL);
>> - MMIO_D(CURBASE(PIPE_B), D_ALL);
>> - MMIO_D(CURBASE(PIPE_C), D_ALL);
>> -
>> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>> -
>> - MMIO_D(_MMIO(0x700ac), D_ALL);
>> - MMIO_D(_MMIO(0x710ac), D_ALL);
>> - MMIO_D(_MMIO(0x720ac), D_ALL);
>> -
>> - MMIO_D(_MMIO(0x70090), D_ALL);
>> - MMIO_D(_MMIO(0x70094), D_ALL);
>> - MMIO_D(_MMIO(0x70098), D_ALL);
>> - MMIO_D(_MMIO(0x7009c), D_ALL);
>> -
>> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
>> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
>> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
>> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
>> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
>> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
>> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
>> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
>> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
>> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
>> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
>> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
>> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>> - reg50080_mmio_write);
>> -
>> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>> -
>> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>> -
>> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>> -
>> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>> -
>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>> -
>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>> -
>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>> -
>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>> -
>> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
>> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>> -
>> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
>> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>> -
>> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
>> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>> -
>> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>> - MMIO_D(WM1_LP_ILK, D_ALL);
>> - MMIO_D(WM2_LP_ILK, D_ALL);
>> - MMIO_D(WM3_LP_ILK, D_ALL);
>> - MMIO_D(WM1S_LP_ILK, D_ALL);
>> - MMIO_D(WM2S_LP_IVB, D_ALL);
>> - MMIO_D(WM3S_LP_IVB, D_ALL);
>> -
>> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>> -
>> - MMIO_D(_MMIO(0x48268), D_ALL);
>> -
>> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>> - gmbus_mmio_write);
>> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> -
>> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>> -
>> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>> -
>> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>> -
>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>> -
>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>> -
>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>> -
>> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>> -
>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>> -
>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>> -
>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>> -
>> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>> -
>> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
>> - MMIO_D(PCH_PP_STATUS, D_ALL);
>> - MMIO_D(PCH_LVDS, D_ALL);
>> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
>> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>> - MMIO_D(PCH_DPLL_SEL, D_ALL);
>> -
>> - MMIO_D(_MMIO(0x61208), D_ALL);
>> - MMIO_D(_MMIO(0x6120c), D_ALL);
>> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>> -
>> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>> -
>> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>> - PORTA_HOTPLUG_STATUS_MASK
>> - | PORTB_HOTPLUG_STATUS_MASK
>> - | PORTC_HOTPLUG_STATUS_MASK
>> - | PORTD_HOTPLUG_STATUS_MASK,
>> - NULL, NULL);
>> -
>> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>> - MMIO_D(FUSE_STRAP, D_ALL);
>> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>> -
>> - MMIO_D(DISP_ARB_CTL, D_ALL);
>> - MMIO_D(DISP_ARB_CTL2, D_ALL);
>> -
>> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>> -
>> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
>> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>> -
>> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
>> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>> -
>> - MMIO_D(IPS_CTL, D_ALL);
>> -
>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>> -
>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>> -
>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>> -
>> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(_MMIO(0x60110), D_ALL);
>> - MMIO_D(_MMIO(0x61110), D_ALL);
>> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> -
>> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>> - MMIO_D(SPLL_CTL, D_ALL);
>> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>> -
>> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>> - MMIO_D(_MMIO(0x46508), D_ALL);
>> -
>> - MMIO_D(_MMIO(0x49080), D_ALL);
>> - MMIO_D(_MMIO(0x49180), D_ALL);
>> - MMIO_D(_MMIO(0x49280), D_ALL);
>> -
>> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>> -
>> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>> -
>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>> -
>> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>> - MMIO_D(SBI_ADDR, D_ALL);
>> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>> - MMIO_D(PIXCLK_GATE, D_ALL);
>> -
>> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> -
>> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> -
>> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> -
>> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>> -
>> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>> -
>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>> -
>> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>> -
>> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>> - MMIO_D(FORCEWAKE_ACK, D_ALL);
>> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>> - MMIO_D(ECOBUS, D_ALL);
>> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
>> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>> - MMIO_D(GEN6_RPSTAT1, D_ALL);
>> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
>> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
>> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
>> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
>> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>> -
>> - MMIO_D(RSTDBYCTL, D_ALL);
>> -
>> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>> -
>> - MMIO_D(TILECTL, D_ALL);
>> -
>> - MMIO_D(GEN6_UCGCTL1, D_ALL);
>> - MMIO_D(GEN6_UCGCTL2, D_ALL);
>> -
>> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
>> - MMIO_D(_MMIO(0x13812c), D_ALL);
>> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
>> - MMIO_D(HSW_IDICR, D_ALL);
>> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>> -
>> - MMIO_D(_MMIO(0x3c), D_ALL);
>> - MMIO_D(_MMIO(0x860), D_ALL);
>> - MMIO_D(ECOSKPD, D_ALL);
>> - MMIO_D(_MMIO(0x121d0), D_ALL);
>> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>> - MMIO_D(_MMIO(0x41d0), D_ALL);
>> - MMIO_D(GAC_ECO_BITS, D_ALL);
>> - MMIO_D(_MMIO(0x6200), D_ALL);
>> - MMIO_D(_MMIO(0x6204), D_ALL);
>> - MMIO_D(_MMIO(0x6208), D_ALL);
>> - MMIO_D(_MMIO(0x7118), D_ALL);
>> - MMIO_D(_MMIO(0x7180), D_ALL);
>> - MMIO_D(_MMIO(0x7408), D_ALL);
>> - MMIO_D(_MMIO(0x7c00), D_ALL);
>> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>> - MMIO_D(_MMIO(0x911c), D_ALL);
>> - MMIO_D(_MMIO(0x9120), D_ALL);
>> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_D(GAB_CTL, D_ALL);
>> - MMIO_D(_MMIO(0x48800), D_ALL);
>> - MMIO_D(_MMIO(0xce044), D_ALL);
>> - MMIO_D(_MMIO(0xe6500), D_ALL);
>> - MMIO_D(_MMIO(0xe6504), D_ALL);
>> - MMIO_D(_MMIO(0xe6600), D_ALL);
>> - MMIO_D(_MMIO(0xe6604), D_ALL);
>> - MMIO_D(_MMIO(0xe6700), D_ALL);
>> - MMIO_D(_MMIO(0xe6704), D_ALL);
>> - MMIO_D(_MMIO(0xe6800), D_ALL);
>> - MMIO_D(_MMIO(0xe6804), D_ALL);
>> - MMIO_D(PCH_GMBUS4, D_ALL);
>> - MMIO_D(PCH_GMBUS5, D_ALL);
>> -
>> - MMIO_D(_MMIO(0x902c), D_ALL);
>> - MMIO_D(_MMIO(0xec008), D_ALL);
>> - MMIO_D(_MMIO(0xec00c), D_ALL);
>> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>> - MMIO_D(_MMIO(0xec408), D_ALL);
>> - MMIO_D(_MMIO(0xec40c), D_ALL);
>> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>> - MMIO_D(_MMIO(0xfc810), D_ALL);
>> - MMIO_D(_MMIO(0xfc81c), D_ALL);
>> - MMIO_D(_MMIO(0xfc828), D_ALL);
>> - MMIO_D(_MMIO(0xfc834), D_ALL);
>> - MMIO_D(_MMIO(0xfcc00), D_ALL);
>> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
>> - MMIO_D(_MMIO(0xfcc18), D_ALL);
>> - MMIO_D(_MMIO(0xfcc24), D_ALL);
>> - MMIO_D(_MMIO(0xfd000), D_ALL);
>> - MMIO_D(_MMIO(0xfd00c), D_ALL);
>> - MMIO_D(_MMIO(0xfd018), D_ALL);
>> - MMIO_D(_MMIO(0xfd024), D_ALL);
>> - MMIO_D(_MMIO(0xfd034), D_ALL);
>> -
>> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>> - MMIO_D(_MMIO(0x2054), D_ALL);
>> - MMIO_D(_MMIO(0x12054), D_ALL);
>> - MMIO_D(_MMIO(0x22054), D_ALL);
>> - MMIO_D(_MMIO(0x1a054), D_ALL);
>> -
>> - MMIO_D(_MMIO(0x44070), D_ALL);
>> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> -
>> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>> -
>> - return 0;
>> -}
>> -
>> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
>> -{
>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>> - int ret;
>> -
>> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>> - intel_vgpu_reg_master_irq_handler);
>> -
>> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>> - mmio_read_from_hw, NULL);
>> -
>> -#define RING_REG(base) _MMIO((base) + 0xd0)
>> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
>> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>> - ring_reset_ctl_write);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x230)
>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x234)
>> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>> - NULL, NULL);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x244)
>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x370)
>> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>> -#undef RING_REG
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x3a0)
>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>> -#undef RING_REG
>> -
>> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>> -
>> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>> -
>> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>> -
>> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>> -
>> -#define RING_REG(base) _MMIO((base) + 0x270)
>> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>> -#undef RING_REG
>> -
>> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>> -
>> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>> -
>> - MMIO_D(WM_MISC, D_BDW);
>> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>> -
>> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>> -
>> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>> -
>> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>> -
>> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_D(_MMIO(0xb110), D_BDW);
>> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>> -
>> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>> - D_BDW_PLUS, NULL, force_nonpriv_write);
>> -
>> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>> -
>> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>> -
>> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>> -
>> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>> -
>> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>> -
>> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - return 0;
>> -}
>> -
>> -static int init_skl_mmio_info(struct intel_gvt *gvt)
>> -{
>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>> - int ret;
>> -
>> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> - dp_aux_ch_ctl_mmio_write);
>> -
>> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>> -
>> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>> -
>> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>> -
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> -
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> -
>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> -
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>> -
>> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>> -
>> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>> -
>> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
>> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>> -
>> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>> - NULL, NULL);
>> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>> - NULL, NULL);
>> -
>> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> -
>> - /* TRTT */
>> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>> - NULL, gen9_trtte_write);
>> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>> - NULL, gen9_trtt_chicken_write);
>> -
>> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>> -
>> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>> -
>> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>> -
>> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>> -
>> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>> -
>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>> -
>> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, csfe_chicken1_mmio_write);
>> -#undef CSFE_CHICKEN1_REG
>> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> - NULL, NULL);
>> -
>> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>> -
>> - return 0;
>> -}
>> -
>> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
>> -{
>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>> - int ret;
>> -
>> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>> -
>> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>> - MMIO_D(ERROR_GEN6, D_BXT);
>> - MMIO_D(DONE_REG, D_BXT);
>> - MMIO_D(EIR, D_BXT);
>> - MMIO_D(PGTBL_ER, D_BXT);
>> - MMIO_D(_MMIO(0x4194), D_BXT);
>> - MMIO_D(_MMIO(0x4294), D_BXT);
>> - MMIO_D(_MMIO(0x4494), D_BXT);
>> -
>> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
>> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>> - MMIO_RING_D(RING_IPEHR, D_BXT);
>> - MMIO_RING_D(RING_INSTPS, D_BXT);
>> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>> - MMIO_RING_D(RING_BBSTATE, D_BXT);
>> - MMIO_RING_D(RING_IPEIR, D_BXT);
>> -
>> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>> -
>> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>> - NULL, bxt_phy_ctl_family_write);
>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>> - NULL, bxt_phy_ctl_family_write);
>> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>> - NULL, bxt_port_pll_enable_write);
>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>> - NULL, bxt_port_pll_enable_write);
>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>> - bxt_port_pll_enable_write);
>> -
>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>> -
>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>> -
>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>> - NULL, bxt_pcs_dw12_grp_write);
>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>> - bxt_port_tx_dw3_read, NULL);
>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>> -
>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>> - NULL, bxt_pcs_dw12_grp_write);
>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>> - bxt_port_tx_dw3_read, NULL);
>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>> -
>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>> - NULL, bxt_pcs_dw12_grp_write);
>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>> - bxt_port_tx_dw3_read, NULL);
>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>> -
>> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>> -
>> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>> -
>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>> -
>> - MMIO_D(RC6_CTX_BASE, D_BXT);
>> -
>> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
>> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> - 0, 0, D_BXT, NULL, NULL);
>> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> - 0, 0, D_BXT, NULL, NULL);
>> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> - 0, 0, D_BXT, NULL, NULL);
>> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> - 0, 0, D_BXT, NULL, NULL);
>> -
>> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> -
>> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>> -
>> - return 0;
>> -}
>> +#include "mmio_table.h"
>>
>> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
>> unsigned int offset)
>> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
>> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>> {
>> struct intel_gvt_device_info *info = &gvt->device_info;
>> - struct drm_i915_private *i915 = gvt->gt->i915;
>> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
>> int ret;
>>
>> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>> if (!gvt->mmio.mmio_attribute)
>> return -ENOMEM;
>>
>> - ret = init_generic_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> -
>> - if (IS_BROADWELL(i915)) {
>> - ret = init_bdw_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> - } else if (IS_SKYLAKE(i915) ||
>> - IS_KABYLAKE(i915) ||
>> - IS_COFFEELAKE(i915) ||
>> - IS_COMETLAKE(i915)) {
>> - ret = init_bdw_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> - ret = init_skl_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> - } else if (IS_BROXTON(i915)) {
>> - ret = init_bdw_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> - ret = init_skl_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> - ret = init_bxt_mmio_info(gvt);
>> - if (ret)
>> - goto err;
>> + ret = intel_gvt_init_mmio_info(gvt);
>> + if (ret) {
>> + intel_gvt_clean_mmio_info(gvt);
>> + return ret;
>> }
>>
>> gvt->mmio.mmio_block = mmio_blocks;
>> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
>>
>> return 0;
>> -err:
>> - intel_gvt_clean_mmio_info(gvt);
>> - return ret;
>> }
>>
>> /**
>> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
>> new file mode 100644
>> index 000000000000..39a4cb59695a
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
>> @@ -0,0 +1,1570 @@
>> +/*
>> + * Copyright © 2021 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */
>> +
>> +#ifndef _GVT_MMIO_TABLE_H_
>> +#define _GVT_MMIO_TABLE_H_
>> +
>> +#ifdef GENERATE_MMIO_TABLE_IN_I915
>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
>> + if (ret) \
>> + return ret; \
>> +} while (0)
>> +#else
>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>> + f, s, am, rm, d, r, w); \
>> + if (ret) \
>> + return ret; \
>> +} while (0)
>> +#endif
>> +
>> +#define MMIO_D(reg, d) \
>> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>> +
>> +#define MMIO_DH(reg, d, r, w) \
>> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>> +
>> +#define MMIO_DFH(reg, d, f, r, w) \
>> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
>> +
>> +#define MMIO_GM(reg, d, r, w) \
>> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>> +
>> +#define MMIO_GM_RDR(reg, d, r, w) \
>> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>> +
>> +#define MMIO_RO(reg, d, f, rm, r, w) \
>> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>> +
>> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>> + if (HAS_ENGINE(gvt->gt, VCS1)) \
>> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>> +} while (0)
>> +
>> +#define MMIO_RING_D(prefix, d) \
>> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>> +
>> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
>> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>> +
>> +#define MMIO_RING_GM(prefix, d, r, w) \
>> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>> +
>> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>> +
>> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>> +
>> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
>> +{
>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>> +
>> + int ret;
>> +
>> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>> + intel_vgpu_reg_imr_handler);
>> +
>> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(SDEISR, D_ALL);
>> +
>> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>> +
>> +
>> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>> + gamw_echo_dev_rw_ia_write);
>> +
>> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x28)
>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x134)
>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x6c)
>> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>> +#undef RING_REG
>> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>> +
>> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
>> +
>> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>> +
>> + /* RING MODE */
>> +#define RING_REG(base) _MMIO((base) + 0x29c)
>> + MMIO_RING_DFH(RING_REG, D_ALL,
>> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>> + ring_mode_mmio_write);
>> +#undef RING_REG
>> +
>> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>> + mmio_read_from_hw, NULL);
>> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>> + mmio_read_from_hw, NULL);
>> +
>> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> +
>> + /* display */
>> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_D(_MMIO(0x602a0), D_ALL);
>> +
>> + MMIO_D(_MMIO(0x65050), D_ALL);
>> + MMIO_D(_MMIO(0x650b4), D_ALL);
>> +
>> + MMIO_D(_MMIO(0xc4040), D_ALL);
>> + MMIO_D(DERRMR, D_ALL);
>> +
>> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>> +
>> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>> +
>> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>> +
>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>> +
>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>> +
>> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
>> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
>> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
>> +
>> + MMIO_D(CURPOS(PIPE_A), D_ALL);
>> + MMIO_D(CURPOS(PIPE_B), D_ALL);
>> + MMIO_D(CURPOS(PIPE_C), D_ALL);
>> +
>> + MMIO_D(CURBASE(PIPE_A), D_ALL);
>> + MMIO_D(CURBASE(PIPE_B), D_ALL);
>> + MMIO_D(CURBASE(PIPE_C), D_ALL);
>> +
>> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>> +
>> + MMIO_D(_MMIO(0x700ac), D_ALL);
>> + MMIO_D(_MMIO(0x710ac), D_ALL);
>> + MMIO_D(_MMIO(0x720ac), D_ALL);
>> +
>> + MMIO_D(_MMIO(0x70090), D_ALL);
>> + MMIO_D(_MMIO(0x70094), D_ALL);
>> + MMIO_D(_MMIO(0x70098), D_ALL);
>> + MMIO_D(_MMIO(0x7009c), D_ALL);
>> +
>> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
>> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
>> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
>> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
>> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
>> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
>> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
>> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
>> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
>> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
>> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
>> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
>> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>> + reg50080_mmio_write);
>> +
>> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>> +
>> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>> +
>> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>> +
>> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>> +
>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>> +
>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>> +
>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>> +
>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>> +
>> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
>> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>> +
>> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
>> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>> +
>> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
>> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>> +
>> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>> + MMIO_D(WM1_LP_ILK, D_ALL);
>> + MMIO_D(WM2_LP_ILK, D_ALL);
>> + MMIO_D(WM3_LP_ILK, D_ALL);
>> + MMIO_D(WM1S_LP_ILK, D_ALL);
>> + MMIO_D(WM2S_LP_IVB, D_ALL);
>> + MMIO_D(WM3S_LP_IVB, D_ALL);
>> +
>> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>> +
>> + MMIO_D(_MMIO(0x48268), D_ALL);
>> +
>> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>> + gmbus_mmio_write);
>> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> +
>> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>> +
>> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>> +
>> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>> +
>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>> +
>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>> +
>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>> +
>> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>> +
>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>> +
>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>> +
>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>> +
>> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>> +
>> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
>> + MMIO_D(PCH_PP_STATUS, D_ALL);
>> + MMIO_D(PCH_LVDS, D_ALL);
>> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
>> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>> + MMIO_D(PCH_DPLL_SEL, D_ALL);
>> +
>> + MMIO_D(_MMIO(0x61208), D_ALL);
>> + MMIO_D(_MMIO(0x6120c), D_ALL);
>> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>> +
>> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>> +
>> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>> + PORTA_HOTPLUG_STATUS_MASK
>> + | PORTB_HOTPLUG_STATUS_MASK
>> + | PORTC_HOTPLUG_STATUS_MASK
>> + | PORTD_HOTPLUG_STATUS_MASK,
>> + NULL, NULL);
>> +
>> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>> + MMIO_D(FUSE_STRAP, D_ALL);
>> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>> +
>> + MMIO_D(DISP_ARB_CTL, D_ALL);
>> + MMIO_D(DISP_ARB_CTL2, D_ALL);
>> +
>> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>> +
>> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
>> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>> +
>> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
>> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>> +
>> + MMIO_D(IPS_CTL, D_ALL);
>> +
>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>> +
>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>> +
>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>> +
>> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(_MMIO(0x60110), D_ALL);
>> + MMIO_D(_MMIO(0x61110), D_ALL);
>> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>> +
>> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>> + MMIO_D(SPLL_CTL, D_ALL);
>> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>> +
>> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>> + MMIO_D(_MMIO(0x46508), D_ALL);
>> +
>> + MMIO_D(_MMIO(0x49080), D_ALL);
>> + MMIO_D(_MMIO(0x49180), D_ALL);
>> + MMIO_D(_MMIO(0x49280), D_ALL);
>> +
>> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>> +
>> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>> +
>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>> +
>> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>> + MMIO_D(SBI_ADDR, D_ALL);
>> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>> + MMIO_D(PIXCLK_GATE, D_ALL);
>> +
>> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> +
>> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>> +
>> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>> +
>> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>> +
>> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>> +
>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>> +
>> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>> +
>> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>> + MMIO_D(FORCEWAKE_ACK, D_ALL);
>> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>> + MMIO_D(ECOBUS, D_ALL);
>> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
>> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>> + MMIO_D(GEN6_RPSTAT1, D_ALL);
>> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
>> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
>> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
>> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
>> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>> +
>> + MMIO_D(RSTDBYCTL, D_ALL);
>> +
>> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>> +
>> + MMIO_D(TILECTL, D_ALL);
>> +
>> + MMIO_D(GEN6_UCGCTL1, D_ALL);
>> + MMIO_D(GEN6_UCGCTL2, D_ALL);
>> +
>> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
>> + MMIO_D(_MMIO(0x13812c), D_ALL);
>> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
>> + MMIO_D(HSW_IDICR, D_ALL);
>> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>> +
>> + MMIO_D(_MMIO(0x3c), D_ALL);
>> + MMIO_D(_MMIO(0x860), D_ALL);
>> + MMIO_D(ECOSKPD, D_ALL);
>> + MMIO_D(_MMIO(0x121d0), D_ALL);
>> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>> + MMIO_D(_MMIO(0x41d0), D_ALL);
>> + MMIO_D(GAC_ECO_BITS, D_ALL);
>> + MMIO_D(_MMIO(0x6200), D_ALL);
>> + MMIO_D(_MMIO(0x6204), D_ALL);
>> + MMIO_D(_MMIO(0x6208), D_ALL);
>> + MMIO_D(_MMIO(0x7118), D_ALL);
>> + MMIO_D(_MMIO(0x7180), D_ALL);
>> + MMIO_D(_MMIO(0x7408), D_ALL);
>> + MMIO_D(_MMIO(0x7c00), D_ALL);
>> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>> + MMIO_D(_MMIO(0x911c), D_ALL);
>> + MMIO_D(_MMIO(0x9120), D_ALL);
>> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_D(GAB_CTL, D_ALL);
>> + MMIO_D(_MMIO(0x48800), D_ALL);
>> + MMIO_D(_MMIO(0xce044), D_ALL);
>> + MMIO_D(_MMIO(0xe6500), D_ALL);
>> + MMIO_D(_MMIO(0xe6504), D_ALL);
>> + MMIO_D(_MMIO(0xe6600), D_ALL);
>> + MMIO_D(_MMIO(0xe6604), D_ALL);
>> + MMIO_D(_MMIO(0xe6700), D_ALL);
>> + MMIO_D(_MMIO(0xe6704), D_ALL);
>> + MMIO_D(_MMIO(0xe6800), D_ALL);
>> + MMIO_D(_MMIO(0xe6804), D_ALL);
>> + MMIO_D(PCH_GMBUS4, D_ALL);
>> + MMIO_D(PCH_GMBUS5, D_ALL);
>> +
>> + MMIO_D(_MMIO(0x902c), D_ALL);
>> + MMIO_D(_MMIO(0xec008), D_ALL);
>> + MMIO_D(_MMIO(0xec00c), D_ALL);
>> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>> + MMIO_D(_MMIO(0xec408), D_ALL);
>> + MMIO_D(_MMIO(0xec40c), D_ALL);
>> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>> + MMIO_D(_MMIO(0xfc810), D_ALL);
>> + MMIO_D(_MMIO(0xfc81c), D_ALL);
>> + MMIO_D(_MMIO(0xfc828), D_ALL);
>> + MMIO_D(_MMIO(0xfc834), D_ALL);
>> + MMIO_D(_MMIO(0xfcc00), D_ALL);
>> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
>> + MMIO_D(_MMIO(0xfcc18), D_ALL);
>> + MMIO_D(_MMIO(0xfcc24), D_ALL);
>> + MMIO_D(_MMIO(0xfd000), D_ALL);
>> + MMIO_D(_MMIO(0xfd00c), D_ALL);
>> + MMIO_D(_MMIO(0xfd018), D_ALL);
>> + MMIO_D(_MMIO(0xfd024), D_ALL);
>> + MMIO_D(_MMIO(0xfd034), D_ALL);
>> +
>> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>> + MMIO_D(_MMIO(0x2054), D_ALL);
>> + MMIO_D(_MMIO(0x12054), D_ALL);
>> + MMIO_D(_MMIO(0x22054), D_ALL);
>> + MMIO_D(_MMIO(0x1a054), D_ALL);
>> +
>> + MMIO_D(_MMIO(0x44070), D_ALL);
>> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> +
>> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>> +
>> + return 0;
>> +}
>> +
>> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
>> +{
>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>> + int ret;
>> +
>> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>> + intel_vgpu_reg_master_irq_handler);
>> +
>> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>> + mmio_read_from_hw, NULL);
>> +
>> +#define RING_REG(base) _MMIO((base) + 0xd0)
>> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
>> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>> + ring_reset_ctl_write);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x230)
>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x234)
>> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>> + NULL, NULL);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x244)
>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x370)
>> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>> +#undef RING_REG
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x3a0)
>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>> +#undef RING_REG
>> +
>> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>> +
>> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>> +
>> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>> +
>> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>> +
>> +#define RING_REG(base) _MMIO((base) + 0x270)
>> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>> +#undef RING_REG
>> +
>> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>> +
>> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>> +
>> + MMIO_D(WM_MISC, D_BDW);
>> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>> +
>> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>> +
>> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>> +
>> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>> +
>> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_D(_MMIO(0xb110), D_BDW);
>> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>> +
>> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>> + D_BDW_PLUS, NULL, force_nonpriv_write);
>> +
>> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>> +
>> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>> +
>> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>> +
>> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>> +
>> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>> +
>> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + return 0;
>> +}
>> +
>> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
>> +{
>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>> + int ret;
>> +
>> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>> + dp_aux_ch_ctl_mmio_write);
>> +
>> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>> +
>> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>> +
>> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>> +
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> +
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> +
>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>> +
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>> +
>> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>> +
>> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>> +
>> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
>> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>> +
>> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>> + NULL, NULL);
>> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>> + NULL, NULL);
>> +
>> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> +
>> + /* TRTT */
>> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>> + NULL, gen9_trtte_write);
>> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>> + NULL, gen9_trtt_chicken_write);
>> +
>> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>> +
>> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>> +
>> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>> +
>> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>> +
>> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>> +
>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>> +
>> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, csfe_chicken1_mmio_write);
>> +#undef CSFE_CHICKEN1_REG
>> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>> + NULL, NULL);
>> +
>> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>> +
>> + return 0;
>> +}
>> +
>> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
>> +{
>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>> + int ret;
>> +
>> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>> +
>> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>> + MMIO_D(ERROR_GEN6, D_BXT);
>> + MMIO_D(DONE_REG, D_BXT);
>> + MMIO_D(EIR, D_BXT);
>> + MMIO_D(PGTBL_ER, D_BXT);
>> + MMIO_D(_MMIO(0x4194), D_BXT);
>> + MMIO_D(_MMIO(0x4294), D_BXT);
>> + MMIO_D(_MMIO(0x4494), D_BXT);
>> +
>> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
>> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>> + MMIO_RING_D(RING_IPEHR, D_BXT);
>> + MMIO_RING_D(RING_INSTPS, D_BXT);
>> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>> + MMIO_RING_D(RING_BBSTATE, D_BXT);
>> + MMIO_RING_D(RING_IPEIR, D_BXT);
>> +
>> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>> +
>> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>> + NULL, bxt_phy_ctl_family_write);
>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>> + NULL, bxt_phy_ctl_family_write);
>> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>> + NULL, bxt_port_pll_enable_write);
>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>> + NULL, bxt_port_pll_enable_write);
>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>> + bxt_port_pll_enable_write);
>> +
>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>> +
>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>> +
>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>> + NULL, bxt_pcs_dw12_grp_write);
>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>> + bxt_port_tx_dw3_read, NULL);
>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>> +
>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>> + NULL, bxt_pcs_dw12_grp_write);
>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>> + bxt_port_tx_dw3_read, NULL);
>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>> +
>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>> + NULL, bxt_pcs_dw12_grp_write);
>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>> + bxt_port_tx_dw3_read, NULL);
>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>> +
>> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>> +
>> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>> +
>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>> +
>> + MMIO_D(RC6_CTX_BASE, D_BXT);
>> +
>> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
>> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> + 0, 0, D_BXT, NULL, NULL);
>> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> + 0, 0, D_BXT, NULL, NULL);
>> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> + 0, 0, D_BXT, NULL, NULL);
>> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>> + 0, 0, D_BXT, NULL, NULL);
>> +
>> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>> +
>> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>> +
>> + return 0;
>> +}
>> +
>> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
>> +{
>> + struct drm_i915_private *i915 = gvt->gt->i915;
>> + int ret;
>> +
>> + ret = intel_gvt_init_generic_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> +
>> + if (IS_BROADWELL(i915)) {
>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + } else if (IS_SKYLAKE(i915) ||
>> + IS_KABYLAKE(i915) ||
>> + IS_COFFEELAKE(i915) ||
>> + IS_COMETLAKE(i915)) {
>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + } else if (IS_BROXTON(i915)) {
>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + ret = intel_gvt_init_bxt_mmio_info(gvt);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +#endif
>> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
>> index 244cc7320b54..05bd2f8e9d94 100644
>> --- a/drivers/gpu/drm/i915/gvt/reg.h
>> +++ b/drivers/gpu/drm/i915/gvt/reg.h
>> @@ -133,6 +133,12 @@
>> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
>> #define VF_GUARDBAND _MMIO(0x83a4)
>>
>> +/* XXX FIXME i915 has changed PP_XXX definition */
>> +#define PCH_PP_STATUS _MMIO(0xc7200)
>> +#define PCH_PP_CONTROL _MMIO(0xc7204)
>> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>
>> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
>> #endif
>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
>> index 4e70c1a9ef2e..64846d9bff0b 100644
>> --- a/drivers/gpu/drm/i915/intel_gvt.c
>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
>> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>> dev_priv->params.enable_gvt = 0;
>> }
>>
>> +#define GENERATE_MMIO_TABLE_IN_I915
>> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
>> +{
>> + return 0;
>> +}
>> +
>> +#include "gvt/reg.h"
>> +#include "gvt/mmio_table.h"
>> +#undef GENERATE_MMIO_TABLE_IN_I915
>> +
>> +
>> /**
>> * intel_gvt_init - initialize GVT components
>> * @dev_priv: drm i915 private data
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-09 7:00 ` [Intel-gfx] " Jani Nikula
@ 2021-11-09 9:44 ` Christoph Hellwig
-1 siblings, 0 replies; 35+ messages in thread
From: Christoph Hellwig @ 2021-11-09 9:44 UTC (permalink / raw)
To: Jani Nikula
Cc: Zhi Wang, joonas.lahtinen, rodrigo.vivi, zhenyuw, zhi.a.wang,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
On Tue, Nov 09, 2021 at 09:00:39AM +0200, Jani Nikula wrote:
> On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
> > From: Zhi Wang <zhi.wang.linux@gmail.com>
> >
> > To support the new mdev interfaces and the re-factor patches from
> > Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
> > MMIO snapshot still needs to be saved in i915 so that the inital clean HW
> > state can be used for the further vGPU. Seperate the tracked MMIO table
> > from GVT-g, so that GVT-g and i915 can both use it.
>
> Do you really have to both put code in a header and then include that in
> multiple places?
>
> I think you may need to rethink the whole approach, maybe make them
> actual tables instead of code.
I played around with this a bit and I can't think of anyting better,
especially given that a function (i915_mmio_reg_offset) is used to
get the offset. So except for the cosmetic cleanup below I think this
is the best we can do for now:
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 4e2fd564abea1..c1f5f3b8abb2c 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -295,8 +295,8 @@ struct intel_vgpu_type {
};
struct intel_gvt_hw_state {
- void *cfg_space;
- void *mmio;
+ u32 *cfg_space;
+ u32 *mmio;
};
struct intel_gvt {
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6a08d362bf664..41d1bb80aba40 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2124,6 +2124,17 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
return 0;
}
+/*
+ * Generate the MMIO handler hash table.
+ */
+#define MMIO_F(reg, s, f, am, rm, d, r, w) \
+do { \
+ int ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
+ f, s, am, rm, d, r, w); \
+ if (ret) \
+ return ret; \
+} while (0)
+
#include "mmio_table.h"
static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
index 39a4cb59695ae..2a17f7162224d 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_table.h
+++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
@@ -25,20 +25,7 @@
#ifndef _GVT_MMIO_TABLE_H_
#define _GVT_MMIO_TABLE_H_
-#ifdef GENERATE_MMIO_TABLE_IN_I915
-#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
- ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
- if (ret) \
- return ret; \
-} while (0)
-#else
-#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
- ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
- f, s, am, rm, d, r, w); \
- if (ret) \
- return ret; \
-} while (0)
-#endif
+#include "gvt/reg.h"
#define MMIO_D(reg, d) \
MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
@@ -86,8 +73,6 @@ static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
{
struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
-
MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
intel_vgpu_reg_imr_handler);
@@ -905,7 +890,6 @@ static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
{
struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
@@ -1095,7 +1079,6 @@ static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
{
struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
@@ -1346,7 +1329,6 @@ static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
{
struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index 4fd51974bd359..fa9d79815af26 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -86,19 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
dev_priv->params.enable_gvt = 0;
}
-#define GENERATE_MMIO_TABLE_IN_I915
-static int new_mmio_info(struct intel_gvt *gvt, u32 offset)
-{
- void *mmio = gvt->hw_state.mmio;
-
- *(u32 *)(mmio + offset) = intel_uncore_read_notrace(gvt->gt->uncore,
- _MMIO(offset));
- return 0;
-}
-
-#include "gvt/reg.h"
+/*
+ * Generates the MMIO golden state table.
+ */
+#define MMIO_F(reg, s, f, am, rm, d, r, w) \
+do { \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ \
+ (gvt)->hw_state.mmio[offset] = \
+ intel_uncore_read_notrace((gvt)->gt->uncore, _MMIO(offset)); \
+} while (0)
#include "gvt/mmio_table.h"
-#undef GENERATE_MMIO_TABLE_IN_I915
static void init_device_info(struct intel_gvt *gvt)
{
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 9:44 ` Christoph Hellwig
0 siblings, 0 replies; 35+ messages in thread
From: Christoph Hellwig @ 2021-11-09 9:44 UTC (permalink / raw)
To: Jani Nikula
Cc: Zhi Wang, intel-gfx, linux-kernel, dri-devel, jgg, intel-gvt-dev, hch
On Tue, Nov 09, 2021 at 09:00:39AM +0200, Jani Nikula wrote:
> On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
> > From: Zhi Wang <zhi.wang.linux@gmail.com>
> >
> > To support the new mdev interfaces and the re-factor patches from
> > Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
> > MMIO snapshot still needs to be saved in i915 so that the inital clean HW
> > state can be used for the further vGPU. Seperate the tracked MMIO table
> > from GVT-g, so that GVT-g and i915 can both use it.
>
> Do you really have to both put code in a header and then include that in
> multiple places?
>
> I think you may need to rethink the whole approach, maybe make them
> actual tables instead of code.
I played around with this a bit and I can't think of anyting better,
especially given that a function (i915_mmio_reg_offset) is used to
get the offset. So except for the cosmetic cleanup below I think this
is the best we can do for now:
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 4e2fd564abea1..c1f5f3b8abb2c 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -295,8 +295,8 @@ struct intel_vgpu_type {
};
struct intel_gvt_hw_state {
- void *cfg_space;
- void *mmio;
+ u32 *cfg_space;
+ u32 *mmio;
};
struct intel_gvt {
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6a08d362bf664..41d1bb80aba40 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2124,6 +2124,17 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
return 0;
}
+/*
+ * Generate the MMIO handler hash table.
+ */
+#define MMIO_F(reg, s, f, am, rm, d, r, w) \
+do { \
+ int ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
+ f, s, am, rm, d, r, w); \
+ if (ret) \
+ return ret; \
+} while (0)
+
#include "mmio_table.h"
static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
index 39a4cb59695ae..2a17f7162224d 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_table.h
+++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
@@ -25,20 +25,7 @@
#ifndef _GVT_MMIO_TABLE_H_
#define _GVT_MMIO_TABLE_H_
-#ifdef GENERATE_MMIO_TABLE_IN_I915
-#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
- ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
- if (ret) \
- return ret; \
-} while (0)
-#else
-#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
- ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
- f, s, am, rm, d, r, w); \
- if (ret) \
- return ret; \
-} while (0)
-#endif
+#include "gvt/reg.h"
#define MMIO_D(reg, d) \
MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
@@ -86,8 +73,6 @@ static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
{
struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
-
MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
intel_vgpu_reg_imr_handler);
@@ -905,7 +890,6 @@ static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
{
struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
@@ -1095,7 +1079,6 @@ static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
{
struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
@@ -1346,7 +1329,6 @@ static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
{
struct drm_i915_private *dev_priv = gvt->gt->i915;
- int ret;
MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index 4fd51974bd359..fa9d79815af26 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -86,19 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
dev_priv->params.enable_gvt = 0;
}
-#define GENERATE_MMIO_TABLE_IN_I915
-static int new_mmio_info(struct intel_gvt *gvt, u32 offset)
-{
- void *mmio = gvt->hw_state.mmio;
-
- *(u32 *)(mmio + offset) = intel_uncore_read_notrace(gvt->gt->uncore,
- _MMIO(offset));
- return 0;
-}
-
-#include "gvt/reg.h"
+/*
+ * Generates the MMIO golden state table.
+ */
+#define MMIO_F(reg, s, f, am, rm, d, r, w) \
+do { \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ \
+ (gvt)->hw_state.mmio[offset] = \
+ intel_uncore_read_notrace((gvt)->gt->uncore, _MMIO(offset)); \
+} while (0)
#include "gvt/mmio_table.h"
-#undef GENERATE_MMIO_TABLE_IN_I915
static void init_device_info(struct intel_gvt *gvt)
{
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-09 8:41 ` [Intel-gfx] " Wang, Zhi A
@ 2021-11-09 10:20 ` Jani Nikula
-1 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2021-11-09 10:20 UTC (permalink / raw)
To: Wang, Zhi A, Zhi Wang, joonas.lahtinen, Vivi, Rodrigo, zhenyuw,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
On Tue, 09 Nov 2021, "Wang, Zhi A" <zhi.a.wang@intel.com> wrote:
> On 11/9/2021 9:00 AM, Jani Nikula wrote:
>> On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
>>> From: Zhi Wang <zhi.wang.linux@gmail.com>
>>>
>>> To support the new mdev interfaces and the re-factor patches from
>>> Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
>>> MMIO snapshot still needs to be saved in i915 so that the inital clean HW
>>> state can be used for the further vGPU. Seperate the tracked MMIO table
>>> from GVT-g, so that GVT-g and i915 can both use it.
>> Do you really have to both put code in a header and then include that in
>> multiple places?
>>
>> I think you may need to rethink the whole approach, maybe make them
>> actual tables instead of code.
>>
> Hi Jani:
>
> Sadly we can't not use a static-defined struct for a MMIO table. (That's
> actually how the code was before) Because:
>
> 1) We use the register defininations from i915.
>
> 2) Every MMIO register definiation in i915 is not a number. It's a macro
> _MMIO(r), which can't be put in the static-defined struct. That's how
> the code has been modified like this when it was merged upstream. The
> MMIO table has to be created dynamically.
Right.
> The MMIO table in the current GVT-g contains handlers in GVT-g code,
> which shouldn't be built into i915 after it was moved into a dedicated
> module. That's the reason I think putting it in a common header would be
> better.
>
> It would be nice to have some better ideas. Currently what in my mind
> is: 1) Start a new .c file in gvt which contains the code to build MMIO
> table and let it be used both by i915 and gvt. 2) i915 builds the table
> and only use it for HW state saving. GVT-g builds a superior table and
> attach the handlers. Does that sounds better?
Having the functions defined in a single .c file and called (perhaps via
just one or two entry points) sounds much better than including code.
Perhaps you could pass in the function to call (new_mmio_info) as a
parameter in different situations instead of macro magic, to make the
code more readable?
Basically I want more clarity in the interfaces between the compilation
units everywhere in i915.
BR,
Jani.
>
> Thanks,
>
> Zhi.
>
>> BR,
>> Jani.
>>
>>
>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
>>> Cc: Zhi Wang <zhi.a.wang@intel.com>
>>> Cc: Christoph Hellwig <hch@lst.de>
>>> Cc: Jason Gunthorpe <jgg@nvidia.com>
>>> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
>>> ---
>>> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
>>> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
>>> drivers/gpu/drm/i915/gvt/reg.h | 6 +
>>> drivers/gpu/drm/i915/intel_gvt.c | 11 +
>>> 4 files changed, 1592 insertions(+), 1534 deletions(-)
>>> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
>>>
>>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>>> index cde0a477fb49..6a08d362bf66 100644
>>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>>> @@ -41,13 +41,6 @@
>>> #include "i915_pvinfo.h"
>>> #include "display/intel_display_types.h"
>>>
>>> -/* XXX FIXME i915 has changed PP_XXX definition */
>>> -#define PCH_PP_STATUS _MMIO(0xc7200)
>>> -#define PCH_PP_CONTROL _MMIO(0xc7204)
>>> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>> -
>>> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
>>> {
>>> struct drm_i915_private *i915 = gvt->gt->i915;
>>> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
>>> return 0;
>>> }
>>>
>>> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>> - f, s, am, rm, d, r, w); \
>>> - if (ret) \
>>> - return ret; \
>>> -} while (0)
>>> -
>>> -#define MMIO_D(reg, d) \
>>> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>> -
>>> -#define MMIO_DH(reg, d, r, w) \
>>> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>> -
>>> -#define MMIO_DFH(reg, d, f, r, w) \
>>> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>> -
>>> -#define MMIO_GM(reg, d, r, w) \
>>> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>> -
>>> -#define MMIO_GM_RDR(reg, d, r, w) \
>>> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>> -
>>> -#define MMIO_RO(reg, d, f, rm, r, w) \
>>> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>> -
>>> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>> - if (HAS_ENGINE(gvt->gt, VCS1)) \
>>> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>> -} while (0)
>>> -
>>> -#define MMIO_RING_D(prefix, d) \
>>> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>> -
>>> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>> -
>>> -#define MMIO_RING_GM(prefix, d, r, w) \
>>> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>> -
>>> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>> -
>>> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>> -
>>> -static int init_generic_mmio_info(struct intel_gvt *gvt)
>>> -{
>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> - int ret;
>>> -
>>> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>> - intel_vgpu_reg_imr_handler);
>>> -
>>> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(SDEISR, D_ALL);
>>> -
>>> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>> -
>>> -
>>> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>> - gamw_echo_dev_rw_ia_write);
>>> -
>>> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x28)
>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x134)
>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x6c)
>>> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>> -#undef RING_REG
>>> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>> -
>>> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>> -
>>> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>> -
>>> - /* RING MODE */
>>> -#define RING_REG(base) _MMIO((base) + 0x29c)
>>> - MMIO_RING_DFH(RING_REG, D_ALL,
>>> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>> - ring_mode_mmio_write);
>>> -#undef RING_REG
>>> -
>>> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>> - mmio_read_from_hw, NULL);
>>> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>> - mmio_read_from_hw, NULL);
>>> -
>>> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - /* display */
>>> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_D(_MMIO(0x602a0), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x65050), D_ALL);
>>> - MMIO_D(_MMIO(0x650b4), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0xc4040), D_ALL);
>>> - MMIO_D(DERRMR, D_ALL);
>>> -
>>> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>> -
>>> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>> -
>>> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>> -
>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>> -
>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>> -
>>> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(CURPOS(PIPE_A), D_ALL);
>>> - MMIO_D(CURPOS(PIPE_B), D_ALL);
>>> - MMIO_D(CURPOS(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(CURBASE(PIPE_A), D_ALL);
>>> - MMIO_D(CURBASE(PIPE_B), D_ALL);
>>> - MMIO_D(CURBASE(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x700ac), D_ALL);
>>> - MMIO_D(_MMIO(0x710ac), D_ALL);
>>> - MMIO_D(_MMIO(0x720ac), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x70090), D_ALL);
>>> - MMIO_D(_MMIO(0x70094), D_ALL);
>>> - MMIO_D(_MMIO(0x70098), D_ALL);
>>> - MMIO_D(_MMIO(0x7009c), D_ALL);
>>> -
>>> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>> -
>>> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>> -
>>> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>> -
>>> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>> -
>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>> -
>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>> -
>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>> -
>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>> -
>>> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>> -
>>> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>> -
>>> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>> - MMIO_D(WM1_LP_ILK, D_ALL);
>>> - MMIO_D(WM2_LP_ILK, D_ALL);
>>> - MMIO_D(WM3_LP_ILK, D_ALL);
>>> - MMIO_D(WM1S_LP_ILK, D_ALL);
>>> - MMIO_D(WM2S_LP_IVB, D_ALL);
>>> - MMIO_D(WM3S_LP_IVB, D_ALL);
>>> -
>>> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x48268), D_ALL);
>>> -
>>> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>> - gmbus_mmio_write);
>>> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> -
>>> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>> -
>>> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>> -
>>> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>> -
>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>> -
>>> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>> -
>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>> -
>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>> -
>>> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>> - MMIO_D(PCH_PP_STATUS, D_ALL);
>>> - MMIO_D(PCH_LVDS, D_ALL);
>>> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>> - MMIO_D(PCH_DPLL_SEL, D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x61208), D_ALL);
>>> - MMIO_D(_MMIO(0x6120c), D_ALL);
>>> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>> -
>>> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>> -
>>> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>> - PORTA_HOTPLUG_STATUS_MASK
>>> - | PORTB_HOTPLUG_STATUS_MASK
>>> - | PORTC_HOTPLUG_STATUS_MASK
>>> - | PORTD_HOTPLUG_STATUS_MASK,
>>> - NULL, NULL);
>>> -
>>> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>> - MMIO_D(FUSE_STRAP, D_ALL);
>>> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>> -
>>> - MMIO_D(DISP_ARB_CTL, D_ALL);
>>> - MMIO_D(DISP_ARB_CTL2, D_ALL);
>>> -
>>> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>> -
>>> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>> -
>>> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>> -
>>> - MMIO_D(IPS_CTL, D_ALL);
>>> -
>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>> -
>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>> -
>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(_MMIO(0x60110), D_ALL);
>>> - MMIO_D(_MMIO(0x61110), D_ALL);
>>> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> -
>>> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>> - MMIO_D(SPLL_CTL, D_ALL);
>>> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>> -
>>> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>> - MMIO_D(_MMIO(0x46508), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x49080), D_ALL);
>>> - MMIO_D(_MMIO(0x49180), D_ALL);
>>> - MMIO_D(_MMIO(0x49280), D_ALL);
>>> -
>>> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>> -
>>> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>> - MMIO_D(SBI_ADDR, D_ALL);
>>> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>> - MMIO_D(PIXCLK_GATE, D_ALL);
>>> -
>>> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> -
>>> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> -
>>> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> -
>>> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>> -
>>> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>> -
>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>> -
>>> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>> - MMIO_D(FORCEWAKE_ACK, D_ALL);
>>> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>> - MMIO_D(ECOBUS, D_ALL);
>>> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>> - MMIO_D(GEN6_RPSTAT1, D_ALL);
>>> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>> -
>>> - MMIO_D(RSTDBYCTL, D_ALL);
>>> -
>>> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>> -
>>> - MMIO_D(TILECTL, D_ALL);
>>> -
>>> - MMIO_D(GEN6_UCGCTL1, D_ALL);
>>> - MMIO_D(GEN6_UCGCTL2, D_ALL);
>>> -
>>> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>> - MMIO_D(_MMIO(0x13812c), D_ALL);
>>> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>> - MMIO_D(HSW_IDICR, D_ALL);
>>> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(_MMIO(0x3c), D_ALL);
>>> - MMIO_D(_MMIO(0x860), D_ALL);
>>> - MMIO_D(ECOSKPD, D_ALL);
>>> - MMIO_D(_MMIO(0x121d0), D_ALL);
>>> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>> - MMIO_D(_MMIO(0x41d0), D_ALL);
>>> - MMIO_D(GAC_ECO_BITS, D_ALL);
>>> - MMIO_D(_MMIO(0x6200), D_ALL);
>>> - MMIO_D(_MMIO(0x6204), D_ALL);
>>> - MMIO_D(_MMIO(0x6208), D_ALL);
>>> - MMIO_D(_MMIO(0x7118), D_ALL);
>>> - MMIO_D(_MMIO(0x7180), D_ALL);
>>> - MMIO_D(_MMIO(0x7408), D_ALL);
>>> - MMIO_D(_MMIO(0x7c00), D_ALL);
>>> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>> - MMIO_D(_MMIO(0x911c), D_ALL);
>>> - MMIO_D(_MMIO(0x9120), D_ALL);
>>> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_D(GAB_CTL, D_ALL);
>>> - MMIO_D(_MMIO(0x48800), D_ALL);
>>> - MMIO_D(_MMIO(0xce044), D_ALL);
>>> - MMIO_D(_MMIO(0xe6500), D_ALL);
>>> - MMIO_D(_MMIO(0xe6504), D_ALL);
>>> - MMIO_D(_MMIO(0xe6600), D_ALL);
>>> - MMIO_D(_MMIO(0xe6604), D_ALL);
>>> - MMIO_D(_MMIO(0xe6700), D_ALL);
>>> - MMIO_D(_MMIO(0xe6704), D_ALL);
>>> - MMIO_D(_MMIO(0xe6800), D_ALL);
>>> - MMIO_D(_MMIO(0xe6804), D_ALL);
>>> - MMIO_D(PCH_GMBUS4, D_ALL);
>>> - MMIO_D(PCH_GMBUS5, D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x902c), D_ALL);
>>> - MMIO_D(_MMIO(0xec008), D_ALL);
>>> - MMIO_D(_MMIO(0xec00c), D_ALL);
>>> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>> - MMIO_D(_MMIO(0xec408), D_ALL);
>>> - MMIO_D(_MMIO(0xec40c), D_ALL);
>>> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>> - MMIO_D(_MMIO(0xfc810), D_ALL);
>>> - MMIO_D(_MMIO(0xfc81c), D_ALL);
>>> - MMIO_D(_MMIO(0xfc828), D_ALL);
>>> - MMIO_D(_MMIO(0xfc834), D_ALL);
>>> - MMIO_D(_MMIO(0xfcc00), D_ALL);
>>> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>> - MMIO_D(_MMIO(0xfcc18), D_ALL);
>>> - MMIO_D(_MMIO(0xfcc24), D_ALL);
>>> - MMIO_D(_MMIO(0xfd000), D_ALL);
>>> - MMIO_D(_MMIO(0xfd00c), D_ALL);
>>> - MMIO_D(_MMIO(0xfd018), D_ALL);
>>> - MMIO_D(_MMIO(0xfd024), D_ALL);
>>> - MMIO_D(_MMIO(0xfd034), D_ALL);
>>> -
>>> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>> - MMIO_D(_MMIO(0x2054), D_ALL);
>>> - MMIO_D(_MMIO(0x12054), D_ALL);
>>> - MMIO_D(_MMIO(0x22054), D_ALL);
>>> - MMIO_D(_MMIO(0x1a054), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x44070), D_ALL);
>>> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
>>> -{
>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> - int ret;
>>> -
>>> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_master_irq_handler);
>>> -
>>> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>> - mmio_read_from_hw, NULL);
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0xd0)
>>> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>> - ring_reset_ctl_write);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x230)
>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x234)
>>> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>> - NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x244)
>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x370)
>>> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x3a0)
>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>> -
>>> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>> -
>>> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x270)
>>> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>> -
>>> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>> -
>>> - MMIO_D(WM_MISC, D_BDW);
>>> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>> -
>>> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>> -
>>> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>> -
>>> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_D(_MMIO(0xb110), D_BDW);
>>> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>> -
>>> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>> - D_BDW_PLUS, NULL, force_nonpriv_write);
>>> -
>>> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>> -
>>> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>> -
>>> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>> -
>>> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - return 0;
>>> -}
>>> -
>>> -static int init_skl_mmio_info(struct intel_gvt *gvt)
>>> -{
>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> - int ret;
>>> -
>>> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> -
>>> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>> -
>>> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>> -
>>> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>> -
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> -
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> -
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> -
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>> -
>>> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>> -
>>> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>> -
>>> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>> - NULL, NULL);
>>> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>> - NULL, NULL);
>>> -
>>> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> -
>>> - /* TRTT */
>>> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>> - NULL, gen9_trtte_write);
>>> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>> - NULL, gen9_trtt_chicken_write);
>>> -
>>> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>> -
>>> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>> -
>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, csfe_chicken1_mmio_write);
>>> -#undef CSFE_CHICKEN1_REG
>>> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> -
>>> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
>>> -{
>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> - int ret;
>>> -
>>> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>> -
>>> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>> - MMIO_D(ERROR_GEN6, D_BXT);
>>> - MMIO_D(DONE_REG, D_BXT);
>>> - MMIO_D(EIR, D_BXT);
>>> - MMIO_D(PGTBL_ER, D_BXT);
>>> - MMIO_D(_MMIO(0x4194), D_BXT);
>>> - MMIO_D(_MMIO(0x4294), D_BXT);
>>> - MMIO_D(_MMIO(0x4494), D_BXT);
>>> -
>>> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>> - MMIO_RING_D(RING_IPEHR, D_BXT);
>>> - MMIO_RING_D(RING_INSTPS, D_BXT);
>>> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>> - MMIO_RING_D(RING_BBSTATE, D_BXT);
>>> - MMIO_RING_D(RING_IPEIR, D_BXT);
>>> -
>>> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>> -
>>> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>> - NULL, bxt_phy_ctl_family_write);
>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>> - NULL, bxt_phy_ctl_family_write);
>>> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>> - NULL, bxt_port_pll_enable_write);
>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>> - NULL, bxt_port_pll_enable_write);
>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>> - bxt_port_pll_enable_write);
>>> -
>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>> -
>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>> -
>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>> - NULL, bxt_pcs_dw12_grp_write);
>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>> - bxt_port_tx_dw3_read, NULL);
>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>> -
>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>> - NULL, bxt_pcs_dw12_grp_write);
>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>> - bxt_port_tx_dw3_read, NULL);
>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>> -
>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>> - NULL, bxt_pcs_dw12_grp_write);
>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>> - bxt_port_tx_dw3_read, NULL);
>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>> -
>>> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>> -
>>> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>> -
>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>> -
>>> - MMIO_D(RC6_CTX_BASE, D_BXT);
>>> -
>>> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> - 0, 0, D_BXT, NULL, NULL);
>>> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> - 0, 0, D_BXT, NULL, NULL);
>>> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> - 0, 0, D_BXT, NULL, NULL);
>>> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> - 0, 0, D_BXT, NULL, NULL);
>>> -
>>> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>> -
>>> - return 0;
>>> -}
>>> +#include "mmio_table.h"
>>>
>>> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
>>> unsigned int offset)
>>> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
>>> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>> {
>>> struct intel_gvt_device_info *info = &gvt->device_info;
>>> - struct drm_i915_private *i915 = gvt->gt->i915;
>>> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
>>> int ret;
>>>
>>> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>> if (!gvt->mmio.mmio_attribute)
>>> return -ENOMEM;
>>>
>>> - ret = init_generic_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> -
>>> - if (IS_BROADWELL(i915)) {
>>> - ret = init_bdw_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> - } else if (IS_SKYLAKE(i915) ||
>>> - IS_KABYLAKE(i915) ||
>>> - IS_COFFEELAKE(i915) ||
>>> - IS_COMETLAKE(i915)) {
>>> - ret = init_bdw_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> - ret = init_skl_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> - } else if (IS_BROXTON(i915)) {
>>> - ret = init_bdw_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> - ret = init_skl_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> - ret = init_bxt_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> + ret = intel_gvt_init_mmio_info(gvt);
>>> + if (ret) {
>>> + intel_gvt_clean_mmio_info(gvt);
>>> + return ret;
>>> }
>>>
>>> gvt->mmio.mmio_block = mmio_blocks;
>>> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
>>>
>>> return 0;
>>> -err:
>>> - intel_gvt_clean_mmio_info(gvt);
>>> - return ret;
>>> }
>>>
>>> /**
>>> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>> new file mode 100644
>>> index 000000000000..39a4cb59695a
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>> @@ -0,0 +1,1570 @@
>>> +/*
>>> + * Copyright © 2021 Intel Corporation
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>> + * copy of this software and associated documentation files (the "Software"),
>>> + * to deal in the Software without restriction, including without limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice (including the next
>>> + * paragraph) shall be included in all copies or substantial portions of the
>>> + * Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>> + * IN THE SOFTWARE.
>>> + *
>>> + */
>>> +
>>> +#ifndef _GVT_MMIO_TABLE_H_
>>> +#define _GVT_MMIO_TABLE_H_
>>> +
>>> +#ifdef GENERATE_MMIO_TABLE_IN_I915
>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
>>> + if (ret) \
>>> + return ret; \
>>> +} while (0)
>>> +#else
>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>> + f, s, am, rm, d, r, w); \
>>> + if (ret) \
>>> + return ret; \
>>> +} while (0)
>>> +#endif
>>> +
>>> +#define MMIO_D(reg, d) \
>>> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>> +
>>> +#define MMIO_DH(reg, d, r, w) \
>>> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>> +
>>> +#define MMIO_DFH(reg, d, f, r, w) \
>>> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>> +
>>> +#define MMIO_GM(reg, d, r, w) \
>>> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>> +
>>> +#define MMIO_GM_RDR(reg, d, r, w) \
>>> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>> +
>>> +#define MMIO_RO(reg, d, f, rm, r, w) \
>>> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>> +
>>> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>> + if (HAS_ENGINE(gvt->gt, VCS1)) \
>>> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>> +} while (0)
>>> +
>>> +#define MMIO_RING_D(prefix, d) \
>>> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>> +
>>> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>> +
>>> +#define MMIO_RING_GM(prefix, d, r, w) \
>>> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>> +
>>> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>> +
>>> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>> +
>>> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
>>> +{
>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> +
>>> + int ret;
>>> +
>>> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>> + intel_vgpu_reg_imr_handler);
>>> +
>>> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(SDEISR, D_ALL);
>>> +
>>> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>> +
>>> +
>>> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>> + gamw_echo_dev_rw_ia_write);
>>> +
>>> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x28)
>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x134)
>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x6c)
>>> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>> +#undef RING_REG
>>> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>> +
>>> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>> +
>>> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>> +
>>> + /* RING MODE */
>>> +#define RING_REG(base) _MMIO((base) + 0x29c)
>>> + MMIO_RING_DFH(RING_REG, D_ALL,
>>> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>> + ring_mode_mmio_write);
>>> +#undef RING_REG
>>> +
>>> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>> + mmio_read_from_hw, NULL);
>>> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>> + mmio_read_from_hw, NULL);
>>> +
>>> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + /* display */
>>> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_D(_MMIO(0x602a0), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x65050), D_ALL);
>>> + MMIO_D(_MMIO(0x650b4), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0xc4040), D_ALL);
>>> + MMIO_D(DERRMR, D_ALL);
>>> +
>>> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>> +
>>> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>> +
>>> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>> +
>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>> +
>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>> +
>>> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(CURPOS(PIPE_A), D_ALL);
>>> + MMIO_D(CURPOS(PIPE_B), D_ALL);
>>> + MMIO_D(CURPOS(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(CURBASE(PIPE_A), D_ALL);
>>> + MMIO_D(CURBASE(PIPE_B), D_ALL);
>>> + MMIO_D(CURBASE(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x700ac), D_ALL);
>>> + MMIO_D(_MMIO(0x710ac), D_ALL);
>>> + MMIO_D(_MMIO(0x720ac), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x70090), D_ALL);
>>> + MMIO_D(_MMIO(0x70094), D_ALL);
>>> + MMIO_D(_MMIO(0x70098), D_ALL);
>>> + MMIO_D(_MMIO(0x7009c), D_ALL);
>>> +
>>> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>> +
>>> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>> +
>>> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>> +
>>> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>> +
>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>> +
>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>> +
>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>> +
>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>> +
>>> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>> +
>>> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>> +
>>> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>> + MMIO_D(WM1_LP_ILK, D_ALL);
>>> + MMIO_D(WM2_LP_ILK, D_ALL);
>>> + MMIO_D(WM3_LP_ILK, D_ALL);
>>> + MMIO_D(WM1S_LP_ILK, D_ALL);
>>> + MMIO_D(WM2S_LP_IVB, D_ALL);
>>> + MMIO_D(WM3S_LP_IVB, D_ALL);
>>> +
>>> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x48268), D_ALL);
>>> +
>>> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>> + gmbus_mmio_write);
>>> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> +
>>> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>> +
>>> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>> +
>>> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>> +
>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>> +
>>> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>> +
>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>> +
>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>> +
>>> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>> + MMIO_D(PCH_PP_STATUS, D_ALL);
>>> + MMIO_D(PCH_LVDS, D_ALL);
>>> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>> + MMIO_D(PCH_DPLL_SEL, D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x61208), D_ALL);
>>> + MMIO_D(_MMIO(0x6120c), D_ALL);
>>> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>> +
>>> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>> +
>>> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>> + PORTA_HOTPLUG_STATUS_MASK
>>> + | PORTB_HOTPLUG_STATUS_MASK
>>> + | PORTC_HOTPLUG_STATUS_MASK
>>> + | PORTD_HOTPLUG_STATUS_MASK,
>>> + NULL, NULL);
>>> +
>>> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>> + MMIO_D(FUSE_STRAP, D_ALL);
>>> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>> +
>>> + MMIO_D(DISP_ARB_CTL, D_ALL);
>>> + MMIO_D(DISP_ARB_CTL2, D_ALL);
>>> +
>>> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>> +
>>> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>> +
>>> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>> +
>>> + MMIO_D(IPS_CTL, D_ALL);
>>> +
>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>> +
>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>> +
>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(_MMIO(0x60110), D_ALL);
>>> + MMIO_D(_MMIO(0x61110), D_ALL);
>>> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> +
>>> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>> + MMIO_D(SPLL_CTL, D_ALL);
>>> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>> +
>>> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>> + MMIO_D(_MMIO(0x46508), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x49080), D_ALL);
>>> + MMIO_D(_MMIO(0x49180), D_ALL);
>>> + MMIO_D(_MMIO(0x49280), D_ALL);
>>> +
>>> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>> +
>>> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>> + MMIO_D(SBI_ADDR, D_ALL);
>>> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>> + MMIO_D(PIXCLK_GATE, D_ALL);
>>> +
>>> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> +
>>> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> +
>>> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> +
>>> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>> +
>>> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>> +
>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>> +
>>> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>> + MMIO_D(FORCEWAKE_ACK, D_ALL);
>>> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>> + MMIO_D(ECOBUS, D_ALL);
>>> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>> + MMIO_D(GEN6_RPSTAT1, D_ALL);
>>> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>> +
>>> + MMIO_D(RSTDBYCTL, D_ALL);
>>> +
>>> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>> +
>>> + MMIO_D(TILECTL, D_ALL);
>>> +
>>> + MMIO_D(GEN6_UCGCTL1, D_ALL);
>>> + MMIO_D(GEN6_UCGCTL2, D_ALL);
>>> +
>>> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>> + MMIO_D(_MMIO(0x13812c), D_ALL);
>>> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>> + MMIO_D(HSW_IDICR, D_ALL);
>>> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(_MMIO(0x3c), D_ALL);
>>> + MMIO_D(_MMIO(0x860), D_ALL);
>>> + MMIO_D(ECOSKPD, D_ALL);
>>> + MMIO_D(_MMIO(0x121d0), D_ALL);
>>> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>> + MMIO_D(_MMIO(0x41d0), D_ALL);
>>> + MMIO_D(GAC_ECO_BITS, D_ALL);
>>> + MMIO_D(_MMIO(0x6200), D_ALL);
>>> + MMIO_D(_MMIO(0x6204), D_ALL);
>>> + MMIO_D(_MMIO(0x6208), D_ALL);
>>> + MMIO_D(_MMIO(0x7118), D_ALL);
>>> + MMIO_D(_MMIO(0x7180), D_ALL);
>>> + MMIO_D(_MMIO(0x7408), D_ALL);
>>> + MMIO_D(_MMIO(0x7c00), D_ALL);
>>> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>> + MMIO_D(_MMIO(0x911c), D_ALL);
>>> + MMIO_D(_MMIO(0x9120), D_ALL);
>>> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_D(GAB_CTL, D_ALL);
>>> + MMIO_D(_MMIO(0x48800), D_ALL);
>>> + MMIO_D(_MMIO(0xce044), D_ALL);
>>> + MMIO_D(_MMIO(0xe6500), D_ALL);
>>> + MMIO_D(_MMIO(0xe6504), D_ALL);
>>> + MMIO_D(_MMIO(0xe6600), D_ALL);
>>> + MMIO_D(_MMIO(0xe6604), D_ALL);
>>> + MMIO_D(_MMIO(0xe6700), D_ALL);
>>> + MMIO_D(_MMIO(0xe6704), D_ALL);
>>> + MMIO_D(_MMIO(0xe6800), D_ALL);
>>> + MMIO_D(_MMIO(0xe6804), D_ALL);
>>> + MMIO_D(PCH_GMBUS4, D_ALL);
>>> + MMIO_D(PCH_GMBUS5, D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x902c), D_ALL);
>>> + MMIO_D(_MMIO(0xec008), D_ALL);
>>> + MMIO_D(_MMIO(0xec00c), D_ALL);
>>> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>> + MMIO_D(_MMIO(0xec408), D_ALL);
>>> + MMIO_D(_MMIO(0xec40c), D_ALL);
>>> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>> + MMIO_D(_MMIO(0xfc810), D_ALL);
>>> + MMIO_D(_MMIO(0xfc81c), D_ALL);
>>> + MMIO_D(_MMIO(0xfc828), D_ALL);
>>> + MMIO_D(_MMIO(0xfc834), D_ALL);
>>> + MMIO_D(_MMIO(0xfcc00), D_ALL);
>>> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>> + MMIO_D(_MMIO(0xfcc18), D_ALL);
>>> + MMIO_D(_MMIO(0xfcc24), D_ALL);
>>> + MMIO_D(_MMIO(0xfd000), D_ALL);
>>> + MMIO_D(_MMIO(0xfd00c), D_ALL);
>>> + MMIO_D(_MMIO(0xfd018), D_ALL);
>>> + MMIO_D(_MMIO(0xfd024), D_ALL);
>>> + MMIO_D(_MMIO(0xfd034), D_ALL);
>>> +
>>> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>> + MMIO_D(_MMIO(0x2054), D_ALL);
>>> + MMIO_D(_MMIO(0x12054), D_ALL);
>>> + MMIO_D(_MMIO(0x22054), D_ALL);
>>> + MMIO_D(_MMIO(0x1a054), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x44070), D_ALL);
>>> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
>>> +{
>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> + int ret;
>>> +
>>> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_master_irq_handler);
>>> +
>>> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>> + mmio_read_from_hw, NULL);
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0xd0)
>>> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>> + ring_reset_ctl_write);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x230)
>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x234)
>>> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>> + NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x244)
>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x370)
>>> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x3a0)
>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>> +
>>> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>> +
>>> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x270)
>>> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>> +
>>> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>> +
>>> + MMIO_D(WM_MISC, D_BDW);
>>> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>> +
>>> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>> +
>>> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>> +
>>> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_D(_MMIO(0xb110), D_BDW);
>>> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>> +
>>> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>> + D_BDW_PLUS, NULL, force_nonpriv_write);
>>> +
>>> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>> +
>>> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>> +
>>> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>> +
>>> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + return 0;
>>> +}
>>> +
>>> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
>>> +{
>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> + int ret;
>>> +
>>> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> +
>>> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>> +
>>> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>> +
>>> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>> +
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> +
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> +
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> +
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>> +
>>> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>> +
>>> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>> +
>>> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>> + NULL, NULL);
>>> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>> + NULL, NULL);
>>> +
>>> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> +
>>> + /* TRTT */
>>> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>> + NULL, gen9_trtte_write);
>>> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>> + NULL, gen9_trtt_chicken_write);
>>> +
>>> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>> +
>>> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>> +
>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, csfe_chicken1_mmio_write);
>>> +#undef CSFE_CHICKEN1_REG
>>> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> +
>>> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
>>> +{
>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> + int ret;
>>> +
>>> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>> +
>>> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>> + MMIO_D(ERROR_GEN6, D_BXT);
>>> + MMIO_D(DONE_REG, D_BXT);
>>> + MMIO_D(EIR, D_BXT);
>>> + MMIO_D(PGTBL_ER, D_BXT);
>>> + MMIO_D(_MMIO(0x4194), D_BXT);
>>> + MMIO_D(_MMIO(0x4294), D_BXT);
>>> + MMIO_D(_MMIO(0x4494), D_BXT);
>>> +
>>> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>> + MMIO_RING_D(RING_IPEHR, D_BXT);
>>> + MMIO_RING_D(RING_INSTPS, D_BXT);
>>> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>> + MMIO_RING_D(RING_BBSTATE, D_BXT);
>>> + MMIO_RING_D(RING_IPEIR, D_BXT);
>>> +
>>> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>> +
>>> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>> + NULL, bxt_phy_ctl_family_write);
>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>> + NULL, bxt_phy_ctl_family_write);
>>> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>> + NULL, bxt_port_pll_enable_write);
>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>> + NULL, bxt_port_pll_enable_write);
>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>> + bxt_port_pll_enable_write);
>>> +
>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>> +
>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>> +
>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>> + NULL, bxt_pcs_dw12_grp_write);
>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>> + bxt_port_tx_dw3_read, NULL);
>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>> +
>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>> + NULL, bxt_pcs_dw12_grp_write);
>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>> + bxt_port_tx_dw3_read, NULL);
>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>> +
>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>> + NULL, bxt_pcs_dw12_grp_write);
>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>> + bxt_port_tx_dw3_read, NULL);
>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>> +
>>> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>> +
>>> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>> +
>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>> +
>>> + MMIO_D(RC6_CTX_BASE, D_BXT);
>>> +
>>> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> + 0, 0, D_BXT, NULL, NULL);
>>> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> + 0, 0, D_BXT, NULL, NULL);
>>> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> + 0, 0, D_BXT, NULL, NULL);
>>> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> + 0, 0, D_BXT, NULL, NULL);
>>> +
>>> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
>>> +{
>>> + struct drm_i915_private *i915 = gvt->gt->i915;
>>> + int ret;
>>> +
>>> + ret = intel_gvt_init_generic_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + if (IS_BROADWELL(i915)) {
>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + } else if (IS_SKYLAKE(i915) ||
>>> + IS_KABYLAKE(i915) ||
>>> + IS_COFFEELAKE(i915) ||
>>> + IS_COMETLAKE(i915)) {
>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + } else if (IS_BROXTON(i915)) {
>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + ret = intel_gvt_init_bxt_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +#endif
>>> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
>>> index 244cc7320b54..05bd2f8e9d94 100644
>>> --- a/drivers/gpu/drm/i915/gvt/reg.h
>>> +++ b/drivers/gpu/drm/i915/gvt/reg.h
>>> @@ -133,6 +133,12 @@
>>> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
>>> #define VF_GUARDBAND _MMIO(0x83a4)
>>>
>>> +/* XXX FIXME i915 has changed PP_XXX definition */
>>> +#define PCH_PP_STATUS _MMIO(0xc7200)
>>> +#define PCH_PP_CONTROL _MMIO(0xc7204)
>>> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>
>>> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
>>> #endif
>>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
>>> index 4e70c1a9ef2e..64846d9bff0b 100644
>>> --- a/drivers/gpu/drm/i915/intel_gvt.c
>>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
>>> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>>> dev_priv->params.enable_gvt = 0;
>>> }
>>>
>>> +#define GENERATE_MMIO_TABLE_IN_I915
>>> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
>>> +{
>>> + return 0;
>>> +}
>>> +
>>> +#include "gvt/reg.h"
>>> +#include "gvt/mmio_table.h"
>>> +#undef GENERATE_MMIO_TABLE_IN_I915
>>> +
>>> +
>>> /**
>>> * intel_gvt_init - initialize GVT components
>>> * @dev_priv: drm i915 private data
>
>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 10:20 ` Jani Nikula
0 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2021-11-09 10:20 UTC (permalink / raw)
To: Wang, Zhi A, Zhi Wang, joonas.lahtinen, Vivi, Rodrigo, zhenyuw,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
On Tue, 09 Nov 2021, "Wang, Zhi A" <zhi.a.wang@intel.com> wrote:
> On 11/9/2021 9:00 AM, Jani Nikula wrote:
>> On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
>>> From: Zhi Wang <zhi.wang.linux@gmail.com>
>>>
>>> To support the new mdev interfaces and the re-factor patches from
>>> Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
>>> MMIO snapshot still needs to be saved in i915 so that the inital clean HW
>>> state can be used for the further vGPU. Seperate the tracked MMIO table
>>> from GVT-g, so that GVT-g and i915 can both use it.
>> Do you really have to both put code in a header and then include that in
>> multiple places?
>>
>> I think you may need to rethink the whole approach, maybe make them
>> actual tables instead of code.
>>
> Hi Jani:
>
> Sadly we can't not use a static-defined struct for a MMIO table. (That's
> actually how the code was before) Because:
>
> 1) We use the register defininations from i915.
>
> 2) Every MMIO register definiation in i915 is not a number. It's a macro
> _MMIO(r), which can't be put in the static-defined struct. That's how
> the code has been modified like this when it was merged upstream. The
> MMIO table has to be created dynamically.
Right.
> The MMIO table in the current GVT-g contains handlers in GVT-g code,
> which shouldn't be built into i915 after it was moved into a dedicated
> module. That's the reason I think putting it in a common header would be
> better.
>
> It would be nice to have some better ideas. Currently what in my mind
> is: 1) Start a new .c file in gvt which contains the code to build MMIO
> table and let it be used both by i915 and gvt. 2) i915 builds the table
> and only use it for HW state saving. GVT-g builds a superior table and
> attach the handlers. Does that sounds better?
Having the functions defined in a single .c file and called (perhaps via
just one or two entry points) sounds much better than including code.
Perhaps you could pass in the function to call (new_mmio_info) as a
parameter in different situations instead of macro magic, to make the
code more readable?
Basically I want more clarity in the interfaces between the compilation
units everywhere in i915.
BR,
Jani.
>
> Thanks,
>
> Zhi.
>
>> BR,
>> Jani.
>>
>>
>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
>>> Cc: Zhi Wang <zhi.a.wang@intel.com>
>>> Cc: Christoph Hellwig <hch@lst.de>
>>> Cc: Jason Gunthorpe <jgg@nvidia.com>
>>> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
>>> ---
>>> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
>>> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
>>> drivers/gpu/drm/i915/gvt/reg.h | 6 +
>>> drivers/gpu/drm/i915/intel_gvt.c | 11 +
>>> 4 files changed, 1592 insertions(+), 1534 deletions(-)
>>> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
>>>
>>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>>> index cde0a477fb49..6a08d362bf66 100644
>>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>>> @@ -41,13 +41,6 @@
>>> #include "i915_pvinfo.h"
>>> #include "display/intel_display_types.h"
>>>
>>> -/* XXX FIXME i915 has changed PP_XXX definition */
>>> -#define PCH_PP_STATUS _MMIO(0xc7200)
>>> -#define PCH_PP_CONTROL _MMIO(0xc7204)
>>> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>> -
>>> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
>>> {
>>> struct drm_i915_private *i915 = gvt->gt->i915;
>>> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
>>> return 0;
>>> }
>>>
>>> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>> - f, s, am, rm, d, r, w); \
>>> - if (ret) \
>>> - return ret; \
>>> -} while (0)
>>> -
>>> -#define MMIO_D(reg, d) \
>>> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>> -
>>> -#define MMIO_DH(reg, d, r, w) \
>>> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>> -
>>> -#define MMIO_DFH(reg, d, f, r, w) \
>>> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>> -
>>> -#define MMIO_GM(reg, d, r, w) \
>>> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>> -
>>> -#define MMIO_GM_RDR(reg, d, r, w) \
>>> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>> -
>>> -#define MMIO_RO(reg, d, f, rm, r, w) \
>>> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>> -
>>> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>> - if (HAS_ENGINE(gvt->gt, VCS1)) \
>>> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>> -} while (0)
>>> -
>>> -#define MMIO_RING_D(prefix, d) \
>>> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>> -
>>> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>> -
>>> -#define MMIO_RING_GM(prefix, d, r, w) \
>>> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>> -
>>> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>> -
>>> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>> -
>>> -static int init_generic_mmio_info(struct intel_gvt *gvt)
>>> -{
>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> - int ret;
>>> -
>>> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>> - intel_vgpu_reg_imr_handler);
>>> -
>>> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(SDEISR, D_ALL);
>>> -
>>> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>> -
>>> -
>>> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>> - gamw_echo_dev_rw_ia_write);
>>> -
>>> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x28)
>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x134)
>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x6c)
>>> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>> -#undef RING_REG
>>> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>> -
>>> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>> -
>>> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>> -
>>> - /* RING MODE */
>>> -#define RING_REG(base) _MMIO((base) + 0x29c)
>>> - MMIO_RING_DFH(RING_REG, D_ALL,
>>> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>> - ring_mode_mmio_write);
>>> -#undef RING_REG
>>> -
>>> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>> - mmio_read_from_hw, NULL);
>>> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>> - mmio_read_from_hw, NULL);
>>> -
>>> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - /* display */
>>> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_D(_MMIO(0x602a0), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x65050), D_ALL);
>>> - MMIO_D(_MMIO(0x650b4), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0xc4040), D_ALL);
>>> - MMIO_D(DERRMR, D_ALL);
>>> -
>>> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>> -
>>> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>> -
>>> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>> -
>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>> -
>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>> -
>>> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(CURPOS(PIPE_A), D_ALL);
>>> - MMIO_D(CURPOS(PIPE_B), D_ALL);
>>> - MMIO_D(CURPOS(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(CURBASE(PIPE_A), D_ALL);
>>> - MMIO_D(CURBASE(PIPE_B), D_ALL);
>>> - MMIO_D(CURBASE(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x700ac), D_ALL);
>>> - MMIO_D(_MMIO(0x710ac), D_ALL);
>>> - MMIO_D(_MMIO(0x720ac), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x70090), D_ALL);
>>> - MMIO_D(_MMIO(0x70094), D_ALL);
>>> - MMIO_D(_MMIO(0x70098), D_ALL);
>>> - MMIO_D(_MMIO(0x7009c), D_ALL);
>>> -
>>> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>> - reg50080_mmio_write);
>>> -
>>> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>> -
>>> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>> -
>>> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>> -
>>> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>> -
>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>> -
>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>> -
>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>> -
>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>> -
>>> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>> -
>>> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>> -
>>> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>> - MMIO_D(WM1_LP_ILK, D_ALL);
>>> - MMIO_D(WM2_LP_ILK, D_ALL);
>>> - MMIO_D(WM3_LP_ILK, D_ALL);
>>> - MMIO_D(WM1S_LP_ILK, D_ALL);
>>> - MMIO_D(WM2S_LP_IVB, D_ALL);
>>> - MMIO_D(WM3S_LP_IVB, D_ALL);
>>> -
>>> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x48268), D_ALL);
>>> -
>>> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>> - gmbus_mmio_write);
>>> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> -
>>> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>> -
>>> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>> -
>>> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>> -
>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>> -
>>> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>> -
>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>> -
>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>> -
>>> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>> - MMIO_D(PCH_PP_STATUS, D_ALL);
>>> - MMIO_D(PCH_LVDS, D_ALL);
>>> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>> - MMIO_D(PCH_DPLL_SEL, D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x61208), D_ALL);
>>> - MMIO_D(_MMIO(0x6120c), D_ALL);
>>> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>> -
>>> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>> -
>>> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>> - PORTA_HOTPLUG_STATUS_MASK
>>> - | PORTB_HOTPLUG_STATUS_MASK
>>> - | PORTC_HOTPLUG_STATUS_MASK
>>> - | PORTD_HOTPLUG_STATUS_MASK,
>>> - NULL, NULL);
>>> -
>>> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>> - MMIO_D(FUSE_STRAP, D_ALL);
>>> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>> -
>>> - MMIO_D(DISP_ARB_CTL, D_ALL);
>>> - MMIO_D(DISP_ARB_CTL2, D_ALL);
>>> -
>>> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>> -
>>> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>> -
>>> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>> -
>>> - MMIO_D(IPS_CTL, D_ALL);
>>> -
>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>> -
>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>> -
>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(_MMIO(0x60110), D_ALL);
>>> - MMIO_D(_MMIO(0x61110), D_ALL);
>>> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> -
>>> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>> - MMIO_D(SPLL_CTL, D_ALL);
>>> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>> -
>>> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>> - MMIO_D(_MMIO(0x46508), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x49080), D_ALL);
>>> - MMIO_D(_MMIO(0x49180), D_ALL);
>>> - MMIO_D(_MMIO(0x49280), D_ALL);
>>> -
>>> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>> -
>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>> -
>>> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>> - MMIO_D(SBI_ADDR, D_ALL);
>>> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>> - MMIO_D(PIXCLK_GATE, D_ALL);
>>> -
>>> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> -
>>> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> -
>>> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> -
>>> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>> -
>>> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>> -
>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>> -
>>> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>> - MMIO_D(FORCEWAKE_ACK, D_ALL);
>>> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>> - MMIO_D(ECOBUS, D_ALL);
>>> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>> - MMIO_D(GEN6_RPSTAT1, D_ALL);
>>> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>> -
>>> - MMIO_D(RSTDBYCTL, D_ALL);
>>> -
>>> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>> -
>>> - MMIO_D(TILECTL, D_ALL);
>>> -
>>> - MMIO_D(GEN6_UCGCTL1, D_ALL);
>>> - MMIO_D(GEN6_UCGCTL2, D_ALL);
>>> -
>>> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>> - MMIO_D(_MMIO(0x13812c), D_ALL);
>>> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>> - MMIO_D(HSW_IDICR, D_ALL);
>>> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_D(_MMIO(0x3c), D_ALL);
>>> - MMIO_D(_MMIO(0x860), D_ALL);
>>> - MMIO_D(ECOSKPD, D_ALL);
>>> - MMIO_D(_MMIO(0x121d0), D_ALL);
>>> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>> - MMIO_D(_MMIO(0x41d0), D_ALL);
>>> - MMIO_D(GAC_ECO_BITS, D_ALL);
>>> - MMIO_D(_MMIO(0x6200), D_ALL);
>>> - MMIO_D(_MMIO(0x6204), D_ALL);
>>> - MMIO_D(_MMIO(0x6208), D_ALL);
>>> - MMIO_D(_MMIO(0x7118), D_ALL);
>>> - MMIO_D(_MMIO(0x7180), D_ALL);
>>> - MMIO_D(_MMIO(0x7408), D_ALL);
>>> - MMIO_D(_MMIO(0x7c00), D_ALL);
>>> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>> - MMIO_D(_MMIO(0x911c), D_ALL);
>>> - MMIO_D(_MMIO(0x9120), D_ALL);
>>> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_D(GAB_CTL, D_ALL);
>>> - MMIO_D(_MMIO(0x48800), D_ALL);
>>> - MMIO_D(_MMIO(0xce044), D_ALL);
>>> - MMIO_D(_MMIO(0xe6500), D_ALL);
>>> - MMIO_D(_MMIO(0xe6504), D_ALL);
>>> - MMIO_D(_MMIO(0xe6600), D_ALL);
>>> - MMIO_D(_MMIO(0xe6604), D_ALL);
>>> - MMIO_D(_MMIO(0xe6700), D_ALL);
>>> - MMIO_D(_MMIO(0xe6704), D_ALL);
>>> - MMIO_D(_MMIO(0xe6800), D_ALL);
>>> - MMIO_D(_MMIO(0xe6804), D_ALL);
>>> - MMIO_D(PCH_GMBUS4, D_ALL);
>>> - MMIO_D(PCH_GMBUS5, D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x902c), D_ALL);
>>> - MMIO_D(_MMIO(0xec008), D_ALL);
>>> - MMIO_D(_MMIO(0xec00c), D_ALL);
>>> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>> - MMIO_D(_MMIO(0xec408), D_ALL);
>>> - MMIO_D(_MMIO(0xec40c), D_ALL);
>>> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>> - MMIO_D(_MMIO(0xfc810), D_ALL);
>>> - MMIO_D(_MMIO(0xfc81c), D_ALL);
>>> - MMIO_D(_MMIO(0xfc828), D_ALL);
>>> - MMIO_D(_MMIO(0xfc834), D_ALL);
>>> - MMIO_D(_MMIO(0xfcc00), D_ALL);
>>> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>> - MMIO_D(_MMIO(0xfcc18), D_ALL);
>>> - MMIO_D(_MMIO(0xfcc24), D_ALL);
>>> - MMIO_D(_MMIO(0xfd000), D_ALL);
>>> - MMIO_D(_MMIO(0xfd00c), D_ALL);
>>> - MMIO_D(_MMIO(0xfd018), D_ALL);
>>> - MMIO_D(_MMIO(0xfd024), D_ALL);
>>> - MMIO_D(_MMIO(0xfd034), D_ALL);
>>> -
>>> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>> - MMIO_D(_MMIO(0x2054), D_ALL);
>>> - MMIO_D(_MMIO(0x12054), D_ALL);
>>> - MMIO_D(_MMIO(0x22054), D_ALL);
>>> - MMIO_D(_MMIO(0x1a054), D_ALL);
>>> -
>>> - MMIO_D(_MMIO(0x44070), D_ALL);
>>> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> -
>>> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
>>> -{
>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> - int ret;
>>> -
>>> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>> - intel_vgpu_reg_master_irq_handler);
>>> -
>>> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>> - mmio_read_from_hw, NULL);
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0xd0)
>>> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>> - ring_reset_ctl_write);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x230)
>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x234)
>>> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>> - NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x244)
>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x370)
>>> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x3a0)
>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>> -
>>> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>> -
>>> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>> -
>>> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>> -
>>> -#define RING_REG(base) _MMIO((base) + 0x270)
>>> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>> -#undef RING_REG
>>> -
>>> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>> -
>>> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>> -
>>> - MMIO_D(WM_MISC, D_BDW);
>>> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>> -
>>> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>> -
>>> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>> -
>>> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_D(_MMIO(0xb110), D_BDW);
>>> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>> -
>>> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>> - D_BDW_PLUS, NULL, force_nonpriv_write);
>>> -
>>> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>> -
>>> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>> -
>>> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>> -
>>> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - return 0;
>>> -}
>>> -
>>> -static int init_skl_mmio_info(struct intel_gvt *gvt)
>>> -{
>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> - int ret;
>>> -
>>> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> - dp_aux_ch_ctl_mmio_write);
>>> -
>>> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>> -
>>> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>> -
>>> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>> -
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> -
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> -
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> -
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>> -
>>> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>> -
>>> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>> -
>>> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>> -
>>> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>> - NULL, NULL);
>>> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>> - NULL, NULL);
>>> -
>>> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> -
>>> - /* TRTT */
>>> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>> - NULL, gen9_trtte_write);
>>> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>> - NULL, gen9_trtt_chicken_write);
>>> -
>>> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>> -
>>> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>> -
>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>> -
>>> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, csfe_chicken1_mmio_write);
>>> -#undef CSFE_CHICKEN1_REG
>>> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> - NULL, NULL);
>>> -
>>> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
>>> -{
>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> - int ret;
>>> -
>>> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>> -
>>> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>> - MMIO_D(ERROR_GEN6, D_BXT);
>>> - MMIO_D(DONE_REG, D_BXT);
>>> - MMIO_D(EIR, D_BXT);
>>> - MMIO_D(PGTBL_ER, D_BXT);
>>> - MMIO_D(_MMIO(0x4194), D_BXT);
>>> - MMIO_D(_MMIO(0x4294), D_BXT);
>>> - MMIO_D(_MMIO(0x4494), D_BXT);
>>> -
>>> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>> - MMIO_RING_D(RING_IPEHR, D_BXT);
>>> - MMIO_RING_D(RING_INSTPS, D_BXT);
>>> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>> - MMIO_RING_D(RING_BBSTATE, D_BXT);
>>> - MMIO_RING_D(RING_IPEIR, D_BXT);
>>> -
>>> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>> -
>>> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>> - NULL, bxt_phy_ctl_family_write);
>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>> - NULL, bxt_phy_ctl_family_write);
>>> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>> - NULL, bxt_port_pll_enable_write);
>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>> - NULL, bxt_port_pll_enable_write);
>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>> - bxt_port_pll_enable_write);
>>> -
>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>> -
>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>> -
>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>> - NULL, bxt_pcs_dw12_grp_write);
>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>> - bxt_port_tx_dw3_read, NULL);
>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>> -
>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>> - NULL, bxt_pcs_dw12_grp_write);
>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>> - bxt_port_tx_dw3_read, NULL);
>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>> -
>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>> - NULL, bxt_pcs_dw12_grp_write);
>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>> - bxt_port_tx_dw3_read, NULL);
>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>> -
>>> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>> -
>>> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>> -
>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>> -
>>> - MMIO_D(RC6_CTX_BASE, D_BXT);
>>> -
>>> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> - 0, 0, D_BXT, NULL, NULL);
>>> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> - 0, 0, D_BXT, NULL, NULL);
>>> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> - 0, 0, D_BXT, NULL, NULL);
>>> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> - 0, 0, D_BXT, NULL, NULL);
>>> -
>>> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> -
>>> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>> -
>>> - return 0;
>>> -}
>>> +#include "mmio_table.h"
>>>
>>> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
>>> unsigned int offset)
>>> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
>>> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>> {
>>> struct intel_gvt_device_info *info = &gvt->device_info;
>>> - struct drm_i915_private *i915 = gvt->gt->i915;
>>> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
>>> int ret;
>>>
>>> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>> if (!gvt->mmio.mmio_attribute)
>>> return -ENOMEM;
>>>
>>> - ret = init_generic_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> -
>>> - if (IS_BROADWELL(i915)) {
>>> - ret = init_bdw_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> - } else if (IS_SKYLAKE(i915) ||
>>> - IS_KABYLAKE(i915) ||
>>> - IS_COFFEELAKE(i915) ||
>>> - IS_COMETLAKE(i915)) {
>>> - ret = init_bdw_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> - ret = init_skl_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> - } else if (IS_BROXTON(i915)) {
>>> - ret = init_bdw_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> - ret = init_skl_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> - ret = init_bxt_mmio_info(gvt);
>>> - if (ret)
>>> - goto err;
>>> + ret = intel_gvt_init_mmio_info(gvt);
>>> + if (ret) {
>>> + intel_gvt_clean_mmio_info(gvt);
>>> + return ret;
>>> }
>>>
>>> gvt->mmio.mmio_block = mmio_blocks;
>>> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
>>>
>>> return 0;
>>> -err:
>>> - intel_gvt_clean_mmio_info(gvt);
>>> - return ret;
>>> }
>>>
>>> /**
>>> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>> new file mode 100644
>>> index 000000000000..39a4cb59695a
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>> @@ -0,0 +1,1570 @@
>>> +/*
>>> + * Copyright © 2021 Intel Corporation
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>> + * copy of this software and associated documentation files (the "Software"),
>>> + * to deal in the Software without restriction, including without limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice (including the next
>>> + * paragraph) shall be included in all copies or substantial portions of the
>>> + * Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>> + * IN THE SOFTWARE.
>>> + *
>>> + */
>>> +
>>> +#ifndef _GVT_MMIO_TABLE_H_
>>> +#define _GVT_MMIO_TABLE_H_
>>> +
>>> +#ifdef GENERATE_MMIO_TABLE_IN_I915
>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
>>> + if (ret) \
>>> + return ret; \
>>> +} while (0)
>>> +#else
>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>> + f, s, am, rm, d, r, w); \
>>> + if (ret) \
>>> + return ret; \
>>> +} while (0)
>>> +#endif
>>> +
>>> +#define MMIO_D(reg, d) \
>>> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>> +
>>> +#define MMIO_DH(reg, d, r, w) \
>>> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>> +
>>> +#define MMIO_DFH(reg, d, f, r, w) \
>>> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>> +
>>> +#define MMIO_GM(reg, d, r, w) \
>>> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>> +
>>> +#define MMIO_GM_RDR(reg, d, r, w) \
>>> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>> +
>>> +#define MMIO_RO(reg, d, f, rm, r, w) \
>>> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>> +
>>> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>> + if (HAS_ENGINE(gvt->gt, VCS1)) \
>>> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>> +} while (0)
>>> +
>>> +#define MMIO_RING_D(prefix, d) \
>>> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>> +
>>> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>> +
>>> +#define MMIO_RING_GM(prefix, d, r, w) \
>>> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>> +
>>> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>> +
>>> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>> +
>>> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
>>> +{
>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> +
>>> + int ret;
>>> +
>>> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>> + intel_vgpu_reg_imr_handler);
>>> +
>>> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(SDEISR, D_ALL);
>>> +
>>> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>> +
>>> +
>>> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>> + gamw_echo_dev_rw_ia_write);
>>> +
>>> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x28)
>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x134)
>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x6c)
>>> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>> +#undef RING_REG
>>> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>> +
>>> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>> +
>>> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>> +
>>> + /* RING MODE */
>>> +#define RING_REG(base) _MMIO((base) + 0x29c)
>>> + MMIO_RING_DFH(RING_REG, D_ALL,
>>> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>> + ring_mode_mmio_write);
>>> +#undef RING_REG
>>> +
>>> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>> + mmio_read_from_hw, NULL);
>>> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>> + mmio_read_from_hw, NULL);
>>> +
>>> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + /* display */
>>> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_D(_MMIO(0x602a0), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x65050), D_ALL);
>>> + MMIO_D(_MMIO(0x650b4), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0xc4040), D_ALL);
>>> + MMIO_D(DERRMR, D_ALL);
>>> +
>>> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>> +
>>> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>> +
>>> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>> +
>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>> +
>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>> +
>>> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(CURPOS(PIPE_A), D_ALL);
>>> + MMIO_D(CURPOS(PIPE_B), D_ALL);
>>> + MMIO_D(CURPOS(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(CURBASE(PIPE_A), D_ALL);
>>> + MMIO_D(CURBASE(PIPE_B), D_ALL);
>>> + MMIO_D(CURBASE(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x700ac), D_ALL);
>>> + MMIO_D(_MMIO(0x710ac), D_ALL);
>>> + MMIO_D(_MMIO(0x720ac), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x70090), D_ALL);
>>> + MMIO_D(_MMIO(0x70094), D_ALL);
>>> + MMIO_D(_MMIO(0x70098), D_ALL);
>>> + MMIO_D(_MMIO(0x7009c), D_ALL);
>>> +
>>> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>> + reg50080_mmio_write);
>>> +
>>> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>> +
>>> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>> +
>>> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>> +
>>> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>> +
>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>> +
>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>> +
>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>> +
>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>> +
>>> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>> +
>>> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>> +
>>> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>> + MMIO_D(WM1_LP_ILK, D_ALL);
>>> + MMIO_D(WM2_LP_ILK, D_ALL);
>>> + MMIO_D(WM3_LP_ILK, D_ALL);
>>> + MMIO_D(WM1S_LP_ILK, D_ALL);
>>> + MMIO_D(WM2S_LP_IVB, D_ALL);
>>> + MMIO_D(WM3S_LP_IVB, D_ALL);
>>> +
>>> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x48268), D_ALL);
>>> +
>>> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>> + gmbus_mmio_write);
>>> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> +
>>> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>> +
>>> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>> +
>>> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>> +
>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>> +
>>> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>> +
>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>> +
>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>> +
>>> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>> + MMIO_D(PCH_PP_STATUS, D_ALL);
>>> + MMIO_D(PCH_LVDS, D_ALL);
>>> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>> + MMIO_D(PCH_DPLL_SEL, D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x61208), D_ALL);
>>> + MMIO_D(_MMIO(0x6120c), D_ALL);
>>> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>> +
>>> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>> +
>>> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>> + PORTA_HOTPLUG_STATUS_MASK
>>> + | PORTB_HOTPLUG_STATUS_MASK
>>> + | PORTC_HOTPLUG_STATUS_MASK
>>> + | PORTD_HOTPLUG_STATUS_MASK,
>>> + NULL, NULL);
>>> +
>>> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>> + MMIO_D(FUSE_STRAP, D_ALL);
>>> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>> +
>>> + MMIO_D(DISP_ARB_CTL, D_ALL);
>>> + MMIO_D(DISP_ARB_CTL2, D_ALL);
>>> +
>>> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>> +
>>> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>> +
>>> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>> +
>>> + MMIO_D(IPS_CTL, D_ALL);
>>> +
>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>> +
>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>> +
>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(_MMIO(0x60110), D_ALL);
>>> + MMIO_D(_MMIO(0x61110), D_ALL);
>>> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>> +
>>> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>> + MMIO_D(SPLL_CTL, D_ALL);
>>> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>> +
>>> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>> + MMIO_D(_MMIO(0x46508), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x49080), D_ALL);
>>> + MMIO_D(_MMIO(0x49180), D_ALL);
>>> + MMIO_D(_MMIO(0x49280), D_ALL);
>>> +
>>> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>> +
>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>> +
>>> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>> + MMIO_D(SBI_ADDR, D_ALL);
>>> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>> + MMIO_D(PIXCLK_GATE, D_ALL);
>>> +
>>> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> +
>>> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>> +
>>> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>> +
>>> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>> +
>>> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>> +
>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>> +
>>> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>> + MMIO_D(FORCEWAKE_ACK, D_ALL);
>>> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>> + MMIO_D(ECOBUS, D_ALL);
>>> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>> + MMIO_D(GEN6_RPSTAT1, D_ALL);
>>> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>> +
>>> + MMIO_D(RSTDBYCTL, D_ALL);
>>> +
>>> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>> +
>>> + MMIO_D(TILECTL, D_ALL);
>>> +
>>> + MMIO_D(GEN6_UCGCTL1, D_ALL);
>>> + MMIO_D(GEN6_UCGCTL2, D_ALL);
>>> +
>>> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>> + MMIO_D(_MMIO(0x13812c), D_ALL);
>>> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>> + MMIO_D(HSW_IDICR, D_ALL);
>>> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_D(_MMIO(0x3c), D_ALL);
>>> + MMIO_D(_MMIO(0x860), D_ALL);
>>> + MMIO_D(ECOSKPD, D_ALL);
>>> + MMIO_D(_MMIO(0x121d0), D_ALL);
>>> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>> + MMIO_D(_MMIO(0x41d0), D_ALL);
>>> + MMIO_D(GAC_ECO_BITS, D_ALL);
>>> + MMIO_D(_MMIO(0x6200), D_ALL);
>>> + MMIO_D(_MMIO(0x6204), D_ALL);
>>> + MMIO_D(_MMIO(0x6208), D_ALL);
>>> + MMIO_D(_MMIO(0x7118), D_ALL);
>>> + MMIO_D(_MMIO(0x7180), D_ALL);
>>> + MMIO_D(_MMIO(0x7408), D_ALL);
>>> + MMIO_D(_MMIO(0x7c00), D_ALL);
>>> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>> + MMIO_D(_MMIO(0x911c), D_ALL);
>>> + MMIO_D(_MMIO(0x9120), D_ALL);
>>> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_D(GAB_CTL, D_ALL);
>>> + MMIO_D(_MMIO(0x48800), D_ALL);
>>> + MMIO_D(_MMIO(0xce044), D_ALL);
>>> + MMIO_D(_MMIO(0xe6500), D_ALL);
>>> + MMIO_D(_MMIO(0xe6504), D_ALL);
>>> + MMIO_D(_MMIO(0xe6600), D_ALL);
>>> + MMIO_D(_MMIO(0xe6604), D_ALL);
>>> + MMIO_D(_MMIO(0xe6700), D_ALL);
>>> + MMIO_D(_MMIO(0xe6704), D_ALL);
>>> + MMIO_D(_MMIO(0xe6800), D_ALL);
>>> + MMIO_D(_MMIO(0xe6804), D_ALL);
>>> + MMIO_D(PCH_GMBUS4, D_ALL);
>>> + MMIO_D(PCH_GMBUS5, D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x902c), D_ALL);
>>> + MMIO_D(_MMIO(0xec008), D_ALL);
>>> + MMIO_D(_MMIO(0xec00c), D_ALL);
>>> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>> + MMIO_D(_MMIO(0xec408), D_ALL);
>>> + MMIO_D(_MMIO(0xec40c), D_ALL);
>>> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>> + MMIO_D(_MMIO(0xfc810), D_ALL);
>>> + MMIO_D(_MMIO(0xfc81c), D_ALL);
>>> + MMIO_D(_MMIO(0xfc828), D_ALL);
>>> + MMIO_D(_MMIO(0xfc834), D_ALL);
>>> + MMIO_D(_MMIO(0xfcc00), D_ALL);
>>> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>> + MMIO_D(_MMIO(0xfcc18), D_ALL);
>>> + MMIO_D(_MMIO(0xfcc24), D_ALL);
>>> + MMIO_D(_MMIO(0xfd000), D_ALL);
>>> + MMIO_D(_MMIO(0xfd00c), D_ALL);
>>> + MMIO_D(_MMIO(0xfd018), D_ALL);
>>> + MMIO_D(_MMIO(0xfd024), D_ALL);
>>> + MMIO_D(_MMIO(0xfd034), D_ALL);
>>> +
>>> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>> + MMIO_D(_MMIO(0x2054), D_ALL);
>>> + MMIO_D(_MMIO(0x12054), D_ALL);
>>> + MMIO_D(_MMIO(0x22054), D_ALL);
>>> + MMIO_D(_MMIO(0x1a054), D_ALL);
>>> +
>>> + MMIO_D(_MMIO(0x44070), D_ALL);
>>> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> +
>>> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
>>> +{
>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> + int ret;
>>> +
>>> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>> + intel_vgpu_reg_master_irq_handler);
>>> +
>>> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>> + mmio_read_from_hw, NULL);
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0xd0)
>>> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>> + ring_reset_ctl_write);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x230)
>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x234)
>>> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>> + NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x244)
>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x370)
>>> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x3a0)
>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>> +
>>> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>> +
>>> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>> +
>>> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>> +
>>> +#define RING_REG(base) _MMIO((base) + 0x270)
>>> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>> +#undef RING_REG
>>> +
>>> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>> +
>>> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>> +
>>> + MMIO_D(WM_MISC, D_BDW);
>>> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>> +
>>> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>> +
>>> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>> +
>>> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_D(_MMIO(0xb110), D_BDW);
>>> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>> +
>>> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>> + D_BDW_PLUS, NULL, force_nonpriv_write);
>>> +
>>> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>> +
>>> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>> +
>>> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>> +
>>> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + return 0;
>>> +}
>>> +
>>> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
>>> +{
>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> + int ret;
>>> +
>>> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>> + dp_aux_ch_ctl_mmio_write);
>>> +
>>> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>> +
>>> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>> +
>>> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>> +
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> +
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> +
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>> +
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>> +
>>> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>> +
>>> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>> +
>>> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>> +
>>> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>> + NULL, NULL);
>>> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>> + NULL, NULL);
>>> +
>>> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> +
>>> + /* TRTT */
>>> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>> + NULL, gen9_trtte_write);
>>> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>> + NULL, gen9_trtt_chicken_write);
>>> +
>>> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>> +
>>> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>> +
>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>> +
>>> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, csfe_chicken1_mmio_write);
>>> +#undef CSFE_CHICKEN1_REG
>>> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>> + NULL, NULL);
>>> +
>>> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
>>> +{
>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>> + int ret;
>>> +
>>> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>> +
>>> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>> + MMIO_D(ERROR_GEN6, D_BXT);
>>> + MMIO_D(DONE_REG, D_BXT);
>>> + MMIO_D(EIR, D_BXT);
>>> + MMIO_D(PGTBL_ER, D_BXT);
>>> + MMIO_D(_MMIO(0x4194), D_BXT);
>>> + MMIO_D(_MMIO(0x4294), D_BXT);
>>> + MMIO_D(_MMIO(0x4494), D_BXT);
>>> +
>>> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>> + MMIO_RING_D(RING_IPEHR, D_BXT);
>>> + MMIO_RING_D(RING_INSTPS, D_BXT);
>>> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>> + MMIO_RING_D(RING_BBSTATE, D_BXT);
>>> + MMIO_RING_D(RING_IPEIR, D_BXT);
>>> +
>>> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>> +
>>> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>> + NULL, bxt_phy_ctl_family_write);
>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>> + NULL, bxt_phy_ctl_family_write);
>>> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>> + NULL, bxt_port_pll_enable_write);
>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>> + NULL, bxt_port_pll_enable_write);
>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>> + bxt_port_pll_enable_write);
>>> +
>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>> +
>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>> +
>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>> + NULL, bxt_pcs_dw12_grp_write);
>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>> + bxt_port_tx_dw3_read, NULL);
>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>> +
>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>> + NULL, bxt_pcs_dw12_grp_write);
>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>> + bxt_port_tx_dw3_read, NULL);
>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>> +
>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>> + NULL, bxt_pcs_dw12_grp_write);
>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>> + bxt_port_tx_dw3_read, NULL);
>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>> +
>>> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>> +
>>> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>> +
>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>> +
>>> + MMIO_D(RC6_CTX_BASE, D_BXT);
>>> +
>>> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> + 0, 0, D_BXT, NULL, NULL);
>>> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> + 0, 0, D_BXT, NULL, NULL);
>>> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> + 0, 0, D_BXT, NULL, NULL);
>>> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>> + 0, 0, D_BXT, NULL, NULL);
>>> +
>>> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>> +
>>> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
>>> +{
>>> + struct drm_i915_private *i915 = gvt->gt->i915;
>>> + int ret;
>>> +
>>> + ret = intel_gvt_init_generic_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + if (IS_BROADWELL(i915)) {
>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + } else if (IS_SKYLAKE(i915) ||
>>> + IS_KABYLAKE(i915) ||
>>> + IS_COFFEELAKE(i915) ||
>>> + IS_COMETLAKE(i915)) {
>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + } else if (IS_BROXTON(i915)) {
>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + ret = intel_gvt_init_bxt_mmio_info(gvt);
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +#endif
>>> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
>>> index 244cc7320b54..05bd2f8e9d94 100644
>>> --- a/drivers/gpu/drm/i915/gvt/reg.h
>>> +++ b/drivers/gpu/drm/i915/gvt/reg.h
>>> @@ -133,6 +133,12 @@
>>> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
>>> #define VF_GUARDBAND _MMIO(0x83a4)
>>>
>>> +/* XXX FIXME i915 has changed PP_XXX definition */
>>> +#define PCH_PP_STATUS _MMIO(0xc7200)
>>> +#define PCH_PP_CONTROL _MMIO(0xc7204)
>>> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>
>>> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
>>> #endif
>>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
>>> index 4e70c1a9ef2e..64846d9bff0b 100644
>>> --- a/drivers/gpu/drm/i915/intel_gvt.c
>>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
>>> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>>> dev_priv->params.enable_gvt = 0;
>>> }
>>>
>>> +#define GENERATE_MMIO_TABLE_IN_I915
>>> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
>>> +{
>>> + return 0;
>>> +}
>>> +
>>> +#include "gvt/reg.h"
>>> +#include "gvt/mmio_table.h"
>>> +#undef GENERATE_MMIO_TABLE_IN_I915
>>> +
>>> +
>>> /**
>>> * intel_gvt_init - initialize GVT components
>>> * @dev_priv: drm i915 private data
>
>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-09 10:20 ` [Intel-gfx] " Jani Nikula
@ 2021-11-09 10:36 ` hch
-1 siblings, 0 replies; 35+ messages in thread
From: hch @ 2021-11-09 10:36 UTC (permalink / raw)
To: Jani Nikula
Cc: Wang, Zhi A, Zhi Wang, joonas.lahtinen, Vivi, Rodrigo, zhenyuw,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
On Tue, Nov 09, 2021 at 12:20:24PM +0200, Jani Nikula wrote:
> Having the functions defined in a single .c file and called (perhaps via
> just one or two entry points) sounds much better than including code.
>
> Perhaps you could pass in the function to call (new_mmio_info) as a
> parameter in different situations instead of macro magic, to make the
> code more readable?
>
> Basically I want more clarity in the interfaces between the compilation
> units everywhere in i915.
So as far as a I can tell the table is used for a few things:
1) to store the golden state, this is a plain array of u32
2) to attach special write (and sometimes read) handlers, and have
a mask for read-only fields even for writable registers
3) to show the difference between the real and virtual registers in
debugfs
4) to restore some registers on pm resume
Can we somehow handle 3 and 4 with the table built for 1?
In that case we only need special handling in the GVT for the registers
that are overriden, which is a tiny subset and this avoids the giant
duplication.
Btw, the mmio_info_table hash is only used to iterate over all entries,
which is a strange use for a hash. It might make sense to replace it
with a more suitable data structure and/or actually make use of the
hash in intel_gvt_find_mmio_info.
>
>
> BR,
> Jani.
>
>
> >
> > Thanks,
> >
> > Zhi.
> >
> >> BR,
> >> Jani.
> >>
> >>
> >>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> >>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> >>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> >>> Cc: Zhi Wang <zhi.a.wang@intel.com>
> >>> Cc: Christoph Hellwig <hch@lst.de>
> >>> Cc: Jason Gunthorpe <jgg@nvidia.com>
> >>> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
> >>> ---
> >>> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
> >>> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
> >>> drivers/gpu/drm/i915/gvt/reg.h | 6 +
> >>> drivers/gpu/drm/i915/intel_gvt.c | 11 +
> >>> 4 files changed, 1592 insertions(+), 1534 deletions(-)
> >>> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> >>> index cde0a477fb49..6a08d362bf66 100644
> >>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> >>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> >>> @@ -41,13 +41,6 @@
> >>> #include "i915_pvinfo.h"
> >>> #include "display/intel_display_types.h"
> >>>
> >>> -/* XXX FIXME i915 has changed PP_XXX definition */
> >>> -#define PCH_PP_STATUS _MMIO(0xc7200)
> >>> -#define PCH_PP_CONTROL _MMIO(0xc7204)
> >>> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
> >>> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
> >>> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
> >>> -
> >>> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
> >>> {
> >>> struct drm_i915_private *i915 = gvt->gt->i915;
> >>> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
> >>> return 0;
> >>> }
> >>>
> >>> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> >>> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
> >>> - f, s, am, rm, d, r, w); \
> >>> - if (ret) \
> >>> - return ret; \
> >>> -} while (0)
> >>> -
> >>> -#define MMIO_D(reg, d) \
> >>> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
> >>> -
> >>> -#define MMIO_DH(reg, d, r, w) \
> >>> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
> >>> -
> >>> -#define MMIO_DFH(reg, d, f, r, w) \
> >>> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
> >>> -
> >>> -#define MMIO_GM(reg, d, r, w) \
> >>> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
> >>> -
> >>> -#define MMIO_GM_RDR(reg, d, r, w) \
> >>> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
> >>> -
> >>> -#define MMIO_RO(reg, d, f, rm, r, w) \
> >>> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
> >>> -
> >>> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
> >>> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
> >>> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> >>> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> >>> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> >>> - if (HAS_ENGINE(gvt->gt, VCS1)) \
> >>> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
> >>> -} while (0)
> >>> -
> >>> -#define MMIO_RING_D(prefix, d) \
> >>> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
> >>> -
> >>> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
> >>> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
> >>> -
> >>> -#define MMIO_RING_GM(prefix, d, r, w) \
> >>> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
> >>> -
> >>> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
> >>> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
> >>> -
> >>> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
> >>> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
> >>> -
> >>> -static int init_generic_mmio_info(struct intel_gvt *gvt)
> >>> -{
> >>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> - int ret;
> >>> -
> >>> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
> >>> - intel_vgpu_reg_imr_handler);
> >>> -
> >>> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(SDEISR, D_ALL);
> >>> -
> >>> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
> >>> -
> >>> -
> >>> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
> >>> - gamw_echo_dev_rw_ia_write);
> >>> -
> >>> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x28)
> >>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x134)
> >>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x6c)
> >>> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
> >>> -#undef RING_REG
> >>> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
> >>> -
> >>> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
> >>> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
> >>> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
> >>> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
> >>> -
> >>> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
> >>> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
> >>> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
> >>> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
> >>> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
> >>> -
> >>> - /* RING MODE */
> >>> -#define RING_REG(base) _MMIO((base) + 0x29c)
> >>> - MMIO_RING_DFH(RING_REG, D_ALL,
> >>> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
> >>> - ring_mode_mmio_write);
> >>> -#undef RING_REG
> >>> -
> >>> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
> >>> - mmio_read_from_hw, NULL);
> >>> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
> >>> - mmio_read_from_hw, NULL);
> >>> -
> >>> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
> >>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - /* display */
> >>> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_D(_MMIO(0x602a0), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x65050), D_ALL);
> >>> - MMIO_D(_MMIO(0x650b4), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0xc4040), D_ALL);
> >>> - MMIO_D(DERRMR, D_ALL);
> >>> -
> >>> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
> >>> -
> >>> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
> >>> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
> >>> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
> >>> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
> >>> -
> >>> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
> >>> -
> >>> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
> >>> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
> >>> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(CURPOS(PIPE_A), D_ALL);
> >>> - MMIO_D(CURPOS(PIPE_B), D_ALL);
> >>> - MMIO_D(CURPOS(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(CURBASE(PIPE_A), D_ALL);
> >>> - MMIO_D(CURBASE(PIPE_B), D_ALL);
> >>> - MMIO_D(CURBASE(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
> >>> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
> >>> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x700ac), D_ALL);
> >>> - MMIO_D(_MMIO(0x710ac), D_ALL);
> >>> - MMIO_D(_MMIO(0x720ac), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x70090), D_ALL);
> >>> - MMIO_D(_MMIO(0x70094), D_ALL);
> >>> - MMIO_D(_MMIO(0x70098), D_ALL);
> >>> - MMIO_D(_MMIO(0x7009c), D_ALL);
> >>> -
> >>> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
> >>> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
> >>> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
> >>> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
> >>> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
> >>> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> >>> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
> >>> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
> >>> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
> >>> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
> >>> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
> >>> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
> >>> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
> >>> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
> >>> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
> >>> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
> >>> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
> >>> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
> >>> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
> >>> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
> >>> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
> >>> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
> >>> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
> >>> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
> >>> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
> >>> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
> >>> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
> >>> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
> >>> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
> >>> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
> >>> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
> >>> -
> >>> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
> >>> -
> >>> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
> >>> -
> >>> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
> >>> -
> >>> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
> >>> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
> >>> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
> >>> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
> >>> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
> >>> -
> >>> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
> >>> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
> >>> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
> >>> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
> >>> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
> >>> -
> >>> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
> >>> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
> >>> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
> >>> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
> >>> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
> >>> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
> >>> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
> >>> - MMIO_D(WM1_LP_ILK, D_ALL);
> >>> - MMIO_D(WM2_LP_ILK, D_ALL);
> >>> - MMIO_D(WM3_LP_ILK, D_ALL);
> >>> - MMIO_D(WM1S_LP_ILK, D_ALL);
> >>> - MMIO_D(WM2S_LP_IVB, D_ALL);
> >>> - MMIO_D(WM3S_LP_IVB, D_ALL);
> >>> -
> >>> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
> >>> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
> >>> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
> >>> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x48268), D_ALL);
> >>> -
> >>> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> >>> - gmbus_mmio_write);
> >>> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> -
> >>> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
> >>> -
> >>> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
> >>> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
> >>> -
> >>> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> -
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
> >>> -
> >>> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
> >>> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
> >>> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
> >>> -
> >>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
> >>> -
> >>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
> >>> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
> >>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
> >>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
> >>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
> >>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
> >>> -
> >>> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
> >>> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
> >>> - MMIO_D(PCH_PP_STATUS, D_ALL);
> >>> - MMIO_D(PCH_LVDS, D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
> >>> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
> >>> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
> >>> - MMIO_D(PCH_DPLL_SEL, D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x61208), D_ALL);
> >>> - MMIO_D(_MMIO(0x6120c), D_ALL);
> >>> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
> >>> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
> >>> -
> >>> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
> >>> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> -
> >>> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
> >>> - PORTA_HOTPLUG_STATUS_MASK
> >>> - | PORTB_HOTPLUG_STATUS_MASK
> >>> - | PORTC_HOTPLUG_STATUS_MASK
> >>> - | PORTD_HOTPLUG_STATUS_MASK,
> >>> - NULL, NULL);
> >>> -
> >>> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
> >>> - MMIO_D(FUSE_STRAP, D_ALL);
> >>> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
> >>> -
> >>> - MMIO_D(DISP_ARB_CTL, D_ALL);
> >>> - MMIO_D(DISP_ARB_CTL2, D_ALL);
> >>> -
> >>> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
> >>> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
> >>> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
> >>> -
> >>> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
> >>> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
> >>> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
> >>> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
> >>> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
> >>> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
> >>> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
> >>> -
> >>> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
> >>> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
> >>> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
> >>> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
> >>> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
> >>> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
> >>> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
> >>> -
> >>> - MMIO_D(IPS_CTL, D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
> >>> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
> >>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
> >>> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
> >>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
> >>> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
> >>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(_MMIO(0x60110), D_ALL);
> >>> - MMIO_D(_MMIO(0x61110), D_ALL);
> >>> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> -
> >>> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
> >>> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
> >>> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
> >>> - MMIO_D(SPLL_CTL, D_ALL);
> >>> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
> >>> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
> >>> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
> >>> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
> >>> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
> >>> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
> >>> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
> >>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
> >>> -
> >>> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
> >>> - MMIO_D(_MMIO(0x46508), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x49080), D_ALL);
> >>> - MMIO_D(_MMIO(0x49180), D_ALL);
> >>> - MMIO_D(_MMIO(0x49280), D_ALL);
> >>> -
> >>> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
> >>> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
> >>> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
> >>> -
> >>> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
> >>> - MMIO_D(SBI_ADDR, D_ALL);
> >>> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
> >>> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
> >>> - MMIO_D(PIXCLK_GATE, D_ALL);
> >>> -
> >>> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> -
> >>> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> -
> >>> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> -
> >>> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
> >>> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
> >>> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
> >>> -
> >>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
> >>> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
> >>> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
> >>> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
> >>> -
> >>> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
> >>> - MMIO_D(FORCEWAKE_ACK, D_ALL);
> >>> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
> >>> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
> >>> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
> >>> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
> >>> - MMIO_D(ECOBUS, D_ALL);
> >>> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
> >>> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
> >>> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
> >>> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
> >>> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
> >>> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
> >>> - MMIO_D(GEN6_RPSTAT1, D_ALL);
> >>> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
> >>> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
> >>> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
> >>> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
> >>> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
> >>> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
> >>> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
> >>> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
> >>> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
> >>> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
> >>> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
> >>> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
> >>> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
> >>> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
> >>> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
> >>> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
> >>> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> -
> >>> - MMIO_D(RSTDBYCTL, D_ALL);
> >>> -
> >>> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
> >>> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
> >>> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
> >>> -
> >>> - MMIO_D(TILECTL, D_ALL);
> >>> -
> >>> - MMIO_D(GEN6_UCGCTL1, D_ALL);
> >>> - MMIO_D(GEN6_UCGCTL2, D_ALL);
> >>> -
> >>> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
> >>> - MMIO_D(_MMIO(0x13812c), D_ALL);
> >>> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
> >>> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
> >>> - MMIO_D(HSW_IDICR, D_ALL);
> >>> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(_MMIO(0x3c), D_ALL);
> >>> - MMIO_D(_MMIO(0x860), D_ALL);
> >>> - MMIO_D(ECOSKPD, D_ALL);
> >>> - MMIO_D(_MMIO(0x121d0), D_ALL);
> >>> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
> >>> - MMIO_D(_MMIO(0x41d0), D_ALL);
> >>> - MMIO_D(GAC_ECO_BITS, D_ALL);
> >>> - MMIO_D(_MMIO(0x6200), D_ALL);
> >>> - MMIO_D(_MMIO(0x6204), D_ALL);
> >>> - MMIO_D(_MMIO(0x6208), D_ALL);
> >>> - MMIO_D(_MMIO(0x7118), D_ALL);
> >>> - MMIO_D(_MMIO(0x7180), D_ALL);
> >>> - MMIO_D(_MMIO(0x7408), D_ALL);
> >>> - MMIO_D(_MMIO(0x7c00), D_ALL);
> >>> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
> >>> - MMIO_D(_MMIO(0x911c), D_ALL);
> >>> - MMIO_D(_MMIO(0x9120), D_ALL);
> >>> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_D(GAB_CTL, D_ALL);
> >>> - MMIO_D(_MMIO(0x48800), D_ALL);
> >>> - MMIO_D(_MMIO(0xce044), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6500), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6504), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6600), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6604), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6700), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6704), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6800), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6804), D_ALL);
> >>> - MMIO_D(PCH_GMBUS4, D_ALL);
> >>> - MMIO_D(PCH_GMBUS5, D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x902c), D_ALL);
> >>> - MMIO_D(_MMIO(0xec008), D_ALL);
> >>> - MMIO_D(_MMIO(0xec00c), D_ALL);
> >>> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
> >>> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
> >>> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
> >>> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
> >>> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
> >>> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
> >>> - MMIO_D(_MMIO(0xec408), D_ALL);
> >>> - MMIO_D(_MMIO(0xec40c), D_ALL);
> >>> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
> >>> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
> >>> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
> >>> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
> >>> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
> >>> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
> >>> - MMIO_D(_MMIO(0xfc810), D_ALL);
> >>> - MMIO_D(_MMIO(0xfc81c), D_ALL);
> >>> - MMIO_D(_MMIO(0xfc828), D_ALL);
> >>> - MMIO_D(_MMIO(0xfc834), D_ALL);
> >>> - MMIO_D(_MMIO(0xfcc00), D_ALL);
> >>> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
> >>> - MMIO_D(_MMIO(0xfcc18), D_ALL);
> >>> - MMIO_D(_MMIO(0xfcc24), D_ALL);
> >>> - MMIO_D(_MMIO(0xfd000), D_ALL);
> >>> - MMIO_D(_MMIO(0xfd00c), D_ALL);
> >>> - MMIO_D(_MMIO(0xfd018), D_ALL);
> >>> - MMIO_D(_MMIO(0xfd024), D_ALL);
> >>> - MMIO_D(_MMIO(0xfd034), D_ALL);
> >>> -
> >>> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
> >>> - MMIO_D(_MMIO(0x2054), D_ALL);
> >>> - MMIO_D(_MMIO(0x12054), D_ALL);
> >>> - MMIO_D(_MMIO(0x22054), D_ALL);
> >>> - MMIO_D(_MMIO(0x1a054), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x44070), D_ALL);
> >>> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> >>> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
> >>> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> >>> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> >>> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
> >>> -
> >>> - return 0;
> >>> -}
> >>> -
> >>> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
> >>> -{
> >>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> - int ret;
> >>> -
> >>> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_master_irq_handler);
> >>> -
> >>> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
> >>> - mmio_read_from_hw, NULL);
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0xd0)
> >>> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
> >>> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
> >>> - ring_reset_ctl_write);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x230)
> >>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x234)
> >>> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
> >>> - NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x244)
> >>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x370)
> >>> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x3a0)
> >>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
> >>> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
> >>> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
> >>> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
> >>> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
> >>> -
> >>> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
> >>> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x270)
> >>> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
> >>> -
> >>> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
> >>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
> >>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(WM_MISC, D_BDW);
> >>> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
> >>> -
> >>> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
> >>> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
> >>> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
> >>> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_D(_MMIO(0xb110), D_BDW);
> >>> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
> >>> -
> >>> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
> >>> - D_BDW_PLUS, NULL, force_nonpriv_write);
> >>> -
> >>> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
> >>> -
> >>> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - return 0;
> >>> -}
> >>> -
> >>> -static int init_skl_mmio_info(struct intel_gvt *gvt)
> >>> -{
> >>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> - int ret;
> >>> -
> >>> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> -
> >>> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
> >>> -
> >>> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
> >>> -
> >>> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
> >>> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> >>> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> >>> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
> >>> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
> >>> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
> >>> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> >>> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> >>> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
> >>> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
> >>> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
> >>> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
> >>> -
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> -
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> -
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> -
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
> >>> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
> >>> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
> >>> -
> >>> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
> >>> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
> >>> -
> >>> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> >>> - NULL, NULL);
> >>> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> >>> - NULL, NULL);
> >>> -
> >>> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
> >>> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
> >>> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
> >>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> -
> >>> - /* TRTT */
> >>> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
> >>> - NULL, gen9_trtte_write);
> >>> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
> >>> - NULL, gen9_trtt_chicken_write);
> >>> -
> >>> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
> >>> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
> >>> -
> >>> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
> >>> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
> >>> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
> >>> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, csfe_chicken1_mmio_write);
> >>> -#undef CSFE_CHICKEN1_REG
> >>> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> -
> >>> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
> >>> -
> >>> - return 0;
> >>> -}
> >>> -
> >>> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
> >>> -{
> >>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> - int ret;
> >>> -
> >>> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
> >>> -
> >>> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
> >>> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
> >>> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
> >>> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
> >>> - MMIO_D(ERROR_GEN6, D_BXT);
> >>> - MMIO_D(DONE_REG, D_BXT);
> >>> - MMIO_D(EIR, D_BXT);
> >>> - MMIO_D(PGTBL_ER, D_BXT);
> >>> - MMIO_D(_MMIO(0x4194), D_BXT);
> >>> - MMIO_D(_MMIO(0x4294), D_BXT);
> >>> - MMIO_D(_MMIO(0x4494), D_BXT);
> >>> -
> >>> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
> >>> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
> >>> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
> >>> - MMIO_RING_D(RING_IPEHR, D_BXT);
> >>> - MMIO_RING_D(RING_INSTPS, D_BXT);
> >>> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
> >>> - MMIO_RING_D(RING_BBSTATE, D_BXT);
> >>> - MMIO_RING_D(RING_IPEIR, D_BXT);
> >>> -
> >>> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
> >>> -
> >>> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
> >>> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
> >>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
> >>> - NULL, bxt_phy_ctl_family_write);
> >>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
> >>> - NULL, bxt_phy_ctl_family_write);
> >>> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
> >>> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
> >>> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
> >>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
> >>> - NULL, bxt_port_pll_enable_write);
> >>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
> >>> - NULL, bxt_port_pll_enable_write);
> >>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
> >>> - bxt_port_pll_enable_write);
> >>> -
> >>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
> >>> -
> >>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
> >>> -
> >>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
> >>> - NULL, bxt_pcs_dw12_grp_write);
> >>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
> >>> - bxt_port_tx_dw3_read, NULL);
> >>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
> >>> -
> >>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
> >>> - NULL, bxt_pcs_dw12_grp_write);
> >>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
> >>> - bxt_port_tx_dw3_read, NULL);
> >>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
> >>> -
> >>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
> >>> - NULL, bxt_pcs_dw12_grp_write);
> >>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
> >>> - bxt_port_tx_dw3_read, NULL);
> >>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
> >>> -
> >>> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
> >>> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
> >>> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
> >>> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
> >>> -
> >>> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
> >>> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
> >>> -
> >>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
> >>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
> >>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
> >>> -
> >>> - MMIO_D(RC6_CTX_BASE, D_BXT);
> >>> -
> >>> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
> >>> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
> >>> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
> >>> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
> >>> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> - 0, 0, D_BXT, NULL, NULL);
> >>> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> - 0, 0, D_BXT, NULL, NULL);
> >>> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> - 0, 0, D_BXT, NULL, NULL);
> >>> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> - 0, 0, D_BXT, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
> >>> -
> >>> - return 0;
> >>> -}
> >>> +#include "mmio_table.h"
> >>>
> >>> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
> >>> unsigned int offset)
> >>> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
> >>> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
> >>> {
> >>> struct intel_gvt_device_info *info = &gvt->device_info;
> >>> - struct drm_i915_private *i915 = gvt->gt->i915;
> >>> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
> >>> int ret;
> >>>
> >>> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
> >>> if (!gvt->mmio.mmio_attribute)
> >>> return -ENOMEM;
> >>>
> >>> - ret = init_generic_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> -
> >>> - if (IS_BROADWELL(i915)) {
> >>> - ret = init_bdw_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> - } else if (IS_SKYLAKE(i915) ||
> >>> - IS_KABYLAKE(i915) ||
> >>> - IS_COFFEELAKE(i915) ||
> >>> - IS_COMETLAKE(i915)) {
> >>> - ret = init_bdw_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> - ret = init_skl_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> - } else if (IS_BROXTON(i915)) {
> >>> - ret = init_bdw_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> - ret = init_skl_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> - ret = init_bxt_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> + ret = intel_gvt_init_mmio_info(gvt);
> >>> + if (ret) {
> >>> + intel_gvt_clean_mmio_info(gvt);
> >>> + return ret;
> >>> }
> >>>
> >>> gvt->mmio.mmio_block = mmio_blocks;
> >>> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
> >>>
> >>> return 0;
> >>> -err:
> >>> - intel_gvt_clean_mmio_info(gvt);
> >>> - return ret;
> >>> }
> >>>
> >>> /**
> >>> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
> >>> new file mode 100644
> >>> index 000000000000..39a4cb59695a
> >>> --- /dev/null
> >>> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
> >>> @@ -0,0 +1,1570 @@
> >>> +/*
> >>> + * Copyright © 2021 Intel Corporation
> >>> + *
> >>> + * Permission is hereby granted, free of charge, to any person obtaining a
> >>> + * copy of this software and associated documentation files (the "Software"),
> >>> + * to deal in the Software without restriction, including without limitation
> >>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> >>> + * and/or sell copies of the Software, and to permit persons to whom the
> >>> + * Software is furnished to do so, subject to the following conditions:
> >>> + *
> >>> + * The above copyright notice and this permission notice (including the next
> >>> + * paragraph) shall be included in all copies or substantial portions of the
> >>> + * Software.
> >>> + *
> >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> >>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> >>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> >>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> >>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> >>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> >>> + * IN THE SOFTWARE.
> >>> + *
> >>> + */
> >>> +
> >>> +#ifndef _GVT_MMIO_TABLE_H_
> >>> +#define _GVT_MMIO_TABLE_H_
> >>> +
> >>> +#ifdef GENERATE_MMIO_TABLE_IN_I915
> >>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> >>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
> >>> + if (ret) \
> >>> + return ret; \
> >>> +} while (0)
> >>> +#else
> >>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> >>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
> >>> + f, s, am, rm, d, r, w); \
> >>> + if (ret) \
> >>> + return ret; \
> >>> +} while (0)
> >>> +#endif
> >>> +
> >>> +#define MMIO_D(reg, d) \
> >>> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
> >>> +
> >>> +#define MMIO_DH(reg, d, r, w) \
> >>> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
> >>> +
> >>> +#define MMIO_DFH(reg, d, f, r, w) \
> >>> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
> >>> +
> >>> +#define MMIO_GM(reg, d, r, w) \
> >>> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
> >>> +
> >>> +#define MMIO_GM_RDR(reg, d, r, w) \
> >>> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
> >>> +
> >>> +#define MMIO_RO(reg, d, f, rm, r, w) \
> >>> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
> >>> +
> >>> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
> >>> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
> >>> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> >>> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> >>> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> >>> + if (HAS_ENGINE(gvt->gt, VCS1)) \
> >>> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
> >>> +} while (0)
> >>> +
> >>> +#define MMIO_RING_D(prefix, d) \
> >>> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
> >>> +
> >>> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
> >>> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
> >>> +
> >>> +#define MMIO_RING_GM(prefix, d, r, w) \
> >>> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
> >>> +
> >>> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
> >>> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
> >>> +
> >>> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
> >>> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
> >>> +
> >>> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
> >>> +{
> >>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> +
> >>> + int ret;
> >>> +
> >>> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
> >>> + intel_vgpu_reg_imr_handler);
> >>> +
> >>> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(SDEISR, D_ALL);
> >>> +
> >>> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
> >>> +
> >>> +
> >>> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
> >>> + gamw_echo_dev_rw_ia_write);
> >>> +
> >>> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x28)
> >>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x134)
> >>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x6c)
> >>> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
> >>> +#undef RING_REG
> >>> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
> >>> +
> >>> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
> >>> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
> >>> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
> >>> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
> >>> +
> >>> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
> >>> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
> >>> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
> >>> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
> >>> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
> >>> +
> >>> + /* RING MODE */
> >>> +#define RING_REG(base) _MMIO((base) + 0x29c)
> >>> + MMIO_RING_DFH(RING_REG, D_ALL,
> >>> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
> >>> + ring_mode_mmio_write);
> >>> +#undef RING_REG
> >>> +
> >>> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
> >>> + mmio_read_from_hw, NULL);
> >>> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
> >>> + mmio_read_from_hw, NULL);
> >>> +
> >>> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
> >>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + /* display */
> >>> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_D(_MMIO(0x602a0), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x65050), D_ALL);
> >>> + MMIO_D(_MMIO(0x650b4), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0xc4040), D_ALL);
> >>> + MMIO_D(DERRMR, D_ALL);
> >>> +
> >>> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
> >>> +
> >>> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
> >>> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
> >>> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
> >>> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
> >>> +
> >>> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
> >>> +
> >>> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
> >>> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
> >>> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(CURPOS(PIPE_A), D_ALL);
> >>> + MMIO_D(CURPOS(PIPE_B), D_ALL);
> >>> + MMIO_D(CURPOS(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(CURBASE(PIPE_A), D_ALL);
> >>> + MMIO_D(CURBASE(PIPE_B), D_ALL);
> >>> + MMIO_D(CURBASE(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
> >>> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
> >>> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x700ac), D_ALL);
> >>> + MMIO_D(_MMIO(0x710ac), D_ALL);
> >>> + MMIO_D(_MMIO(0x720ac), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x70090), D_ALL);
> >>> + MMIO_D(_MMIO(0x70094), D_ALL);
> >>> + MMIO_D(_MMIO(0x70098), D_ALL);
> >>> + MMIO_D(_MMIO(0x7009c), D_ALL);
> >>> +
> >>> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
> >>> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
> >>> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
> >>> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
> >>> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
> >>> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> >>> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
> >>> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
> >>> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
> >>> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
> >>> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
> >>> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
> >>> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
> >>> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
> >>> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
> >>> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
> >>> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
> >>> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
> >>> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
> >>> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
> >>> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
> >>> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
> >>> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
> >>> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
> >>> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
> >>> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
> >>> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
> >>> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
> >>> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
> >>> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
> >>> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
> >>> +
> >>> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
> >>> +
> >>> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
> >>> +
> >>> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
> >>> +
> >>> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
> >>> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
> >>> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
> >>> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
> >>> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
> >>> +
> >>> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
> >>> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
> >>> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
> >>> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
> >>> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
> >>> +
> >>> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
> >>> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
> >>> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
> >>> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
> >>> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
> >>> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
> >>> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
> >>> + MMIO_D(WM1_LP_ILK, D_ALL);
> >>> + MMIO_D(WM2_LP_ILK, D_ALL);
> >>> + MMIO_D(WM3_LP_ILK, D_ALL);
> >>> + MMIO_D(WM1S_LP_ILK, D_ALL);
> >>> + MMIO_D(WM2S_LP_IVB, D_ALL);
> >>> + MMIO_D(WM3S_LP_IVB, D_ALL);
> >>> +
> >>> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
> >>> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
> >>> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
> >>> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x48268), D_ALL);
> >>> +
> >>> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> >>> + gmbus_mmio_write);
> >>> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> +
> >>> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
> >>> +
> >>> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
> >>> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
> >>> +
> >>> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> +
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
> >>> +
> >>> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
> >>> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
> >>> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
> >>> +
> >>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
> >>> +
> >>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
> >>> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
> >>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
> >>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
> >>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
> >>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
> >>> +
> >>> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
> >>> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
> >>> + MMIO_D(PCH_PP_STATUS, D_ALL);
> >>> + MMIO_D(PCH_LVDS, D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
> >>> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
> >>> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
> >>> + MMIO_D(PCH_DPLL_SEL, D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x61208), D_ALL);
> >>> + MMIO_D(_MMIO(0x6120c), D_ALL);
> >>> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
> >>> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
> >>> +
> >>> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
> >>> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> +
> >>> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
> >>> + PORTA_HOTPLUG_STATUS_MASK
> >>> + | PORTB_HOTPLUG_STATUS_MASK
> >>> + | PORTC_HOTPLUG_STATUS_MASK
> >>> + | PORTD_HOTPLUG_STATUS_MASK,
> >>> + NULL, NULL);
> >>> +
> >>> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
> >>> + MMIO_D(FUSE_STRAP, D_ALL);
> >>> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
> >>> +
> >>> + MMIO_D(DISP_ARB_CTL, D_ALL);
> >>> + MMIO_D(DISP_ARB_CTL2, D_ALL);
> >>> +
> >>> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
> >>> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
> >>> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
> >>> +
> >>> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
> >>> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
> >>> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
> >>> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
> >>> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
> >>> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
> >>> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
> >>> +
> >>> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
> >>> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
> >>> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
> >>> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
> >>> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
> >>> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
> >>> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
> >>> +
> >>> + MMIO_D(IPS_CTL, D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
> >>> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
> >>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
> >>> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
> >>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
> >>> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
> >>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(_MMIO(0x60110), D_ALL);
> >>> + MMIO_D(_MMIO(0x61110), D_ALL);
> >>> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> +
> >>> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
> >>> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
> >>> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
> >>> + MMIO_D(SPLL_CTL, D_ALL);
> >>> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
> >>> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
> >>> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
> >>> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
> >>> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
> >>> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
> >>> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
> >>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
> >>> +
> >>> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
> >>> + MMIO_D(_MMIO(0x46508), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x49080), D_ALL);
> >>> + MMIO_D(_MMIO(0x49180), D_ALL);
> >>> + MMIO_D(_MMIO(0x49280), D_ALL);
> >>> +
> >>> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
> >>> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
> >>> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
> >>> +
> >>> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
> >>> + MMIO_D(SBI_ADDR, D_ALL);
> >>> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
> >>> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
> >>> + MMIO_D(PIXCLK_GATE, D_ALL);
> >>> +
> >>> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> +
> >>> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> +
> >>> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> +
> >>> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
> >>> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
> >>> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
> >>> +
> >>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
> >>> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
> >>> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
> >>> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
> >>> +
> >>> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
> >>> + MMIO_D(FORCEWAKE_ACK, D_ALL);
> >>> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
> >>> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
> >>> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
> >>> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
> >>> + MMIO_D(ECOBUS, D_ALL);
> >>> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
> >>> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
> >>> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
> >>> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
> >>> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
> >>> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
> >>> + MMIO_D(GEN6_RPSTAT1, D_ALL);
> >>> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
> >>> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
> >>> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
> >>> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
> >>> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
> >>> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
> >>> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
> >>> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
> >>> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
> >>> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
> >>> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
> >>> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
> >>> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
> >>> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
> >>> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
> >>> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
> >>> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> +
> >>> + MMIO_D(RSTDBYCTL, D_ALL);
> >>> +
> >>> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
> >>> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
> >>> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
> >>> +
> >>> + MMIO_D(TILECTL, D_ALL);
> >>> +
> >>> + MMIO_D(GEN6_UCGCTL1, D_ALL);
> >>> + MMIO_D(GEN6_UCGCTL2, D_ALL);
> >>> +
> >>> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
> >>> + MMIO_D(_MMIO(0x13812c), D_ALL);
> >>> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
> >>> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
> >>> + MMIO_D(HSW_IDICR, D_ALL);
> >>> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(_MMIO(0x3c), D_ALL);
> >>> + MMIO_D(_MMIO(0x860), D_ALL);
> >>> + MMIO_D(ECOSKPD, D_ALL);
> >>> + MMIO_D(_MMIO(0x121d0), D_ALL);
> >>> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
> >>> + MMIO_D(_MMIO(0x41d0), D_ALL);
> >>> + MMIO_D(GAC_ECO_BITS, D_ALL);
> >>> + MMIO_D(_MMIO(0x6200), D_ALL);
> >>> + MMIO_D(_MMIO(0x6204), D_ALL);
> >>> + MMIO_D(_MMIO(0x6208), D_ALL);
> >>> + MMIO_D(_MMIO(0x7118), D_ALL);
> >>> + MMIO_D(_MMIO(0x7180), D_ALL);
> >>> + MMIO_D(_MMIO(0x7408), D_ALL);
> >>> + MMIO_D(_MMIO(0x7c00), D_ALL);
> >>> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
> >>> + MMIO_D(_MMIO(0x911c), D_ALL);
> >>> + MMIO_D(_MMIO(0x9120), D_ALL);
> >>> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_D(GAB_CTL, D_ALL);
> >>> + MMIO_D(_MMIO(0x48800), D_ALL);
> >>> + MMIO_D(_MMIO(0xce044), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6500), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6504), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6600), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6604), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6700), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6704), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6800), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6804), D_ALL);
> >>> + MMIO_D(PCH_GMBUS4, D_ALL);
> >>> + MMIO_D(PCH_GMBUS5, D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x902c), D_ALL);
> >>> + MMIO_D(_MMIO(0xec008), D_ALL);
> >>> + MMIO_D(_MMIO(0xec00c), D_ALL);
> >>> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
> >>> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
> >>> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
> >>> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
> >>> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
> >>> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
> >>> + MMIO_D(_MMIO(0xec408), D_ALL);
> >>> + MMIO_D(_MMIO(0xec40c), D_ALL);
> >>> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
> >>> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
> >>> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
> >>> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
> >>> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
> >>> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
> >>> + MMIO_D(_MMIO(0xfc810), D_ALL);
> >>> + MMIO_D(_MMIO(0xfc81c), D_ALL);
> >>> + MMIO_D(_MMIO(0xfc828), D_ALL);
> >>> + MMIO_D(_MMIO(0xfc834), D_ALL);
> >>> + MMIO_D(_MMIO(0xfcc00), D_ALL);
> >>> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
> >>> + MMIO_D(_MMIO(0xfcc18), D_ALL);
> >>> + MMIO_D(_MMIO(0xfcc24), D_ALL);
> >>> + MMIO_D(_MMIO(0xfd000), D_ALL);
> >>> + MMIO_D(_MMIO(0xfd00c), D_ALL);
> >>> + MMIO_D(_MMIO(0xfd018), D_ALL);
> >>> + MMIO_D(_MMIO(0xfd024), D_ALL);
> >>> + MMIO_D(_MMIO(0xfd034), D_ALL);
> >>> +
> >>> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
> >>> + MMIO_D(_MMIO(0x2054), D_ALL);
> >>> + MMIO_D(_MMIO(0x12054), D_ALL);
> >>> + MMIO_D(_MMIO(0x22054), D_ALL);
> >>> + MMIO_D(_MMIO(0x1a054), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x44070), D_ALL);
> >>> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> >>> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
> >>> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> >>> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> >>> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
> >>> +{
> >>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> + int ret;
> >>> +
> >>> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_master_irq_handler);
> >>> +
> >>> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
> >>> + mmio_read_from_hw, NULL);
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0xd0)
> >>> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
> >>> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
> >>> + ring_reset_ctl_write);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x230)
> >>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x234)
> >>> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
> >>> + NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x244)
> >>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x370)
> >>> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x3a0)
> >>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
> >>> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
> >>> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
> >>> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
> >>> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
> >>> +
> >>> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
> >>> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x270)
> >>> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
> >>> +
> >>> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
> >>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
> >>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(WM_MISC, D_BDW);
> >>> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
> >>> +
> >>> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
> >>> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
> >>> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
> >>> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_D(_MMIO(0xb110), D_BDW);
> >>> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
> >>> +
> >>> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
> >>> + D_BDW_PLUS, NULL, force_nonpriv_write);
> >>> +
> >>> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
> >>> +
> >>> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
> >>> +{
> >>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> + int ret;
> >>> +
> >>> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> +
> >>> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
> >>> +
> >>> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
> >>> +
> >>> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
> >>> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> >>> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> >>> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
> >>> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
> >>> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
> >>> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> >>> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> >>> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
> >>> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
> >>> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
> >>> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
> >>> +
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> +
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> +
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> +
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
> >>> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
> >>> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
> >>> +
> >>> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
> >>> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
> >>> +
> >>> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> >>> + NULL, NULL);
> >>> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> >>> + NULL, NULL);
> >>> +
> >>> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
> >>> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
> >>> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
> >>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> +
> >>> + /* TRTT */
> >>> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
> >>> + NULL, gen9_trtte_write);
> >>> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
> >>> + NULL, gen9_trtt_chicken_write);
> >>> +
> >>> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
> >>> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
> >>> +
> >>> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
> >>> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
> >>> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
> >>> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, csfe_chicken1_mmio_write);
> >>> +#undef CSFE_CHICKEN1_REG
> >>> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> +
> >>> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
> >>> +{
> >>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> + int ret;
> >>> +
> >>> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
> >>> +
> >>> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
> >>> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
> >>> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
> >>> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
> >>> + MMIO_D(ERROR_GEN6, D_BXT);
> >>> + MMIO_D(DONE_REG, D_BXT);
> >>> + MMIO_D(EIR, D_BXT);
> >>> + MMIO_D(PGTBL_ER, D_BXT);
> >>> + MMIO_D(_MMIO(0x4194), D_BXT);
> >>> + MMIO_D(_MMIO(0x4294), D_BXT);
> >>> + MMIO_D(_MMIO(0x4494), D_BXT);
> >>> +
> >>> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
> >>> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
> >>> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
> >>> + MMIO_RING_D(RING_IPEHR, D_BXT);
> >>> + MMIO_RING_D(RING_INSTPS, D_BXT);
> >>> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
> >>> + MMIO_RING_D(RING_BBSTATE, D_BXT);
> >>> + MMIO_RING_D(RING_IPEIR, D_BXT);
> >>> +
> >>> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
> >>> +
> >>> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
> >>> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
> >>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
> >>> + NULL, bxt_phy_ctl_family_write);
> >>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
> >>> + NULL, bxt_phy_ctl_family_write);
> >>> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
> >>> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
> >>> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
> >>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
> >>> + NULL, bxt_port_pll_enable_write);
> >>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
> >>> + NULL, bxt_port_pll_enable_write);
> >>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
> >>> + bxt_port_pll_enable_write);
> >>> +
> >>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
> >>> +
> >>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
> >>> +
> >>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
> >>> + NULL, bxt_pcs_dw12_grp_write);
> >>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
> >>> + bxt_port_tx_dw3_read, NULL);
> >>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
> >>> +
> >>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
> >>> + NULL, bxt_pcs_dw12_grp_write);
> >>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
> >>> + bxt_port_tx_dw3_read, NULL);
> >>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
> >>> +
> >>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
> >>> + NULL, bxt_pcs_dw12_grp_write);
> >>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
> >>> + bxt_port_tx_dw3_read, NULL);
> >>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
> >>> +
> >>> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
> >>> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
> >>> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
> >>> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
> >>> +
> >>> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
> >>> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
> >>> +
> >>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
> >>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
> >>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
> >>> +
> >>> + MMIO_D(RC6_CTX_BASE, D_BXT);
> >>> +
> >>> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
> >>> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
> >>> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
> >>> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
> >>> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> + 0, 0, D_BXT, NULL, NULL);
> >>> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> + 0, 0, D_BXT, NULL, NULL);
> >>> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> + 0, 0, D_BXT, NULL, NULL);
> >>> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> + 0, 0, D_BXT, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
> >>> +{
> >>> + struct drm_i915_private *i915 = gvt->gt->i915;
> >>> + int ret;
> >>> +
> >>> + ret = intel_gvt_init_generic_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + if (IS_BROADWELL(i915)) {
> >>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + } else if (IS_SKYLAKE(i915) ||
> >>> + IS_KABYLAKE(i915) ||
> >>> + IS_COFFEELAKE(i915) ||
> >>> + IS_COMETLAKE(i915)) {
> >>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + ret = intel_gvt_init_skl_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + } else if (IS_BROXTON(i915)) {
> >>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + ret = intel_gvt_init_skl_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + ret = intel_gvt_init_bxt_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + }
> >>> +
> >>> + return 0;
> >>> +}
> >>> +#endif
> >>> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> >>> index 244cc7320b54..05bd2f8e9d94 100644
> >>> --- a/drivers/gpu/drm/i915/gvt/reg.h
> >>> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> >>> @@ -133,6 +133,12 @@
> >>> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
> >>> #define VF_GUARDBAND _MMIO(0x83a4)
> >>>
> >>> +/* XXX FIXME i915 has changed PP_XXX definition */
> >>> +#define PCH_PP_STATUS _MMIO(0xc7200)
> >>> +#define PCH_PP_CONTROL _MMIO(0xc7204)
> >>> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
> >>> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
> >>> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
> >>>
> >>> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
> >>> #endif
> >>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
> >>> index 4e70c1a9ef2e..64846d9bff0b 100644
> >>> --- a/drivers/gpu/drm/i915/intel_gvt.c
> >>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
> >>> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
> >>> dev_priv->params.enable_gvt = 0;
> >>> }
> >>>
> >>> +#define GENERATE_MMIO_TABLE_IN_I915
> >>> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
> >>> +{
> >>> + return 0;
> >>> +}
> >>> +
> >>> +#include "gvt/reg.h"
> >>> +#include "gvt/mmio_table.h"
> >>> +#undef GENERATE_MMIO_TABLE_IN_I915
> >>> +
> >>> +
> >>> /**
> >>> * intel_gvt_init - initialize GVT components
> >>> * @dev_priv: drm i915 private data
> >
> >
>
> --
> Jani Nikula, Intel Open Source Graphics Center
---end quoted text---
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 10:36 ` hch
0 siblings, 0 replies; 35+ messages in thread
From: hch @ 2021-11-09 10:36 UTC (permalink / raw)
To: Jani Nikula
Cc: Zhi Wang, intel-gfx, linux-kernel, dri-devel, jgg, intel-gvt-dev, hch
On Tue, Nov 09, 2021 at 12:20:24PM +0200, Jani Nikula wrote:
> Having the functions defined in a single .c file and called (perhaps via
> just one or two entry points) sounds much better than including code.
>
> Perhaps you could pass in the function to call (new_mmio_info) as a
> parameter in different situations instead of macro magic, to make the
> code more readable?
>
> Basically I want more clarity in the interfaces between the compilation
> units everywhere in i915.
So as far as a I can tell the table is used for a few things:
1) to store the golden state, this is a plain array of u32
2) to attach special write (and sometimes read) handlers, and have
a mask for read-only fields even for writable registers
3) to show the difference between the real and virtual registers in
debugfs
4) to restore some registers on pm resume
Can we somehow handle 3 and 4 with the table built for 1?
In that case we only need special handling in the GVT for the registers
that are overriden, which is a tiny subset and this avoids the giant
duplication.
Btw, the mmio_info_table hash is only used to iterate over all entries,
which is a strange use for a hash. It might make sense to replace it
with a more suitable data structure and/or actually make use of the
hash in intel_gvt_find_mmio_info.
>
>
> BR,
> Jani.
>
>
> >
> > Thanks,
> >
> > Zhi.
> >
> >> BR,
> >> Jani.
> >>
> >>
> >>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> >>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> >>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> >>> Cc: Zhi Wang <zhi.a.wang@intel.com>
> >>> Cc: Christoph Hellwig <hch@lst.de>
> >>> Cc: Jason Gunthorpe <jgg@nvidia.com>
> >>> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
> >>> ---
> >>> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
> >>> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
> >>> drivers/gpu/drm/i915/gvt/reg.h | 6 +
> >>> drivers/gpu/drm/i915/intel_gvt.c | 11 +
> >>> 4 files changed, 1592 insertions(+), 1534 deletions(-)
> >>> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> >>> index cde0a477fb49..6a08d362bf66 100644
> >>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> >>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> >>> @@ -41,13 +41,6 @@
> >>> #include "i915_pvinfo.h"
> >>> #include "display/intel_display_types.h"
> >>>
> >>> -/* XXX FIXME i915 has changed PP_XXX definition */
> >>> -#define PCH_PP_STATUS _MMIO(0xc7200)
> >>> -#define PCH_PP_CONTROL _MMIO(0xc7204)
> >>> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
> >>> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
> >>> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
> >>> -
> >>> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
> >>> {
> >>> struct drm_i915_private *i915 = gvt->gt->i915;
> >>> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
> >>> return 0;
> >>> }
> >>>
> >>> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> >>> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
> >>> - f, s, am, rm, d, r, w); \
> >>> - if (ret) \
> >>> - return ret; \
> >>> -} while (0)
> >>> -
> >>> -#define MMIO_D(reg, d) \
> >>> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
> >>> -
> >>> -#define MMIO_DH(reg, d, r, w) \
> >>> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
> >>> -
> >>> -#define MMIO_DFH(reg, d, f, r, w) \
> >>> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
> >>> -
> >>> -#define MMIO_GM(reg, d, r, w) \
> >>> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
> >>> -
> >>> -#define MMIO_GM_RDR(reg, d, r, w) \
> >>> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
> >>> -
> >>> -#define MMIO_RO(reg, d, f, rm, r, w) \
> >>> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
> >>> -
> >>> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
> >>> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
> >>> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> >>> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> >>> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> >>> - if (HAS_ENGINE(gvt->gt, VCS1)) \
> >>> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
> >>> -} while (0)
> >>> -
> >>> -#define MMIO_RING_D(prefix, d) \
> >>> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
> >>> -
> >>> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
> >>> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
> >>> -
> >>> -#define MMIO_RING_GM(prefix, d, r, w) \
> >>> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
> >>> -
> >>> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
> >>> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
> >>> -
> >>> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
> >>> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
> >>> -
> >>> -static int init_generic_mmio_info(struct intel_gvt *gvt)
> >>> -{
> >>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> - int ret;
> >>> -
> >>> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
> >>> - intel_vgpu_reg_imr_handler);
> >>> -
> >>> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(SDEISR, D_ALL);
> >>> -
> >>> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
> >>> -
> >>> -
> >>> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
> >>> - gamw_echo_dev_rw_ia_write);
> >>> -
> >>> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x28)
> >>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x134)
> >>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x6c)
> >>> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
> >>> -#undef RING_REG
> >>> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
> >>> -
> >>> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
> >>> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
> >>> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
> >>> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
> >>> -
> >>> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
> >>> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
> >>> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
> >>> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
> >>> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
> >>> -
> >>> - /* RING MODE */
> >>> -#define RING_REG(base) _MMIO((base) + 0x29c)
> >>> - MMIO_RING_DFH(RING_REG, D_ALL,
> >>> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
> >>> - ring_mode_mmio_write);
> >>> -#undef RING_REG
> >>> -
> >>> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
> >>> - mmio_read_from_hw, NULL);
> >>> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
> >>> - mmio_read_from_hw, NULL);
> >>> -
> >>> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
> >>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - /* display */
> >>> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_D(_MMIO(0x602a0), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x65050), D_ALL);
> >>> - MMIO_D(_MMIO(0x650b4), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0xc4040), D_ALL);
> >>> - MMIO_D(DERRMR, D_ALL);
> >>> -
> >>> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
> >>> -
> >>> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
> >>> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
> >>> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
> >>> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
> >>> -
> >>> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
> >>> -
> >>> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
> >>> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
> >>> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(CURPOS(PIPE_A), D_ALL);
> >>> - MMIO_D(CURPOS(PIPE_B), D_ALL);
> >>> - MMIO_D(CURPOS(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(CURBASE(PIPE_A), D_ALL);
> >>> - MMIO_D(CURBASE(PIPE_B), D_ALL);
> >>> - MMIO_D(CURBASE(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
> >>> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
> >>> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x700ac), D_ALL);
> >>> - MMIO_D(_MMIO(0x710ac), D_ALL);
> >>> - MMIO_D(_MMIO(0x720ac), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x70090), D_ALL);
> >>> - MMIO_D(_MMIO(0x70094), D_ALL);
> >>> - MMIO_D(_MMIO(0x70098), D_ALL);
> >>> - MMIO_D(_MMIO(0x7009c), D_ALL);
> >>> -
> >>> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
> >>> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
> >>> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
> >>> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
> >>> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
> >>> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> >>> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
> >>> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
> >>> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
> >>> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
> >>> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
> >>> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
> >>> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
> >>> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
> >>> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
> >>> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
> >>> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
> >>> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
> >>> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
> >>> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
> >>> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
> >>> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
> >>> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
> >>> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
> >>> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
> >>> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
> >>> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
> >>> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
> >>> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
> >>> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
> >>> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
> >>> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
> >>> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
> >>> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
> >>> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
> >>> - reg50080_mmio_write);
> >>> -
> >>> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
> >>> -
> >>> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
> >>> -
> >>> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
> >>> -
> >>> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
> >>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
> >>> -
> >>> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
> >>> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
> >>> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
> >>> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
> >>> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
> >>> -
> >>> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
> >>> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
> >>> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
> >>> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
> >>> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
> >>> -
> >>> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
> >>> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
> >>> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
> >>> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
> >>> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
> >>> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
> >>> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
> >>> - MMIO_D(WM1_LP_ILK, D_ALL);
> >>> - MMIO_D(WM2_LP_ILK, D_ALL);
> >>> - MMIO_D(WM3_LP_ILK, D_ALL);
> >>> - MMIO_D(WM1S_LP_ILK, D_ALL);
> >>> - MMIO_D(WM2S_LP_IVB, D_ALL);
> >>> - MMIO_D(WM3S_LP_IVB, D_ALL);
> >>> -
> >>> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
> >>> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
> >>> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
> >>> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x48268), D_ALL);
> >>> -
> >>> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> >>> - gmbus_mmio_write);
> >>> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> -
> >>> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
> >>> -
> >>> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
> >>> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
> >>> -
> >>> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> -
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
> >>> -
> >>> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
> >>> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
> >>> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
> >>> -
> >>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
> >>> -
> >>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
> >>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
> >>> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
> >>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
> >>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
> >>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
> >>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
> >>> -
> >>> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
> >>> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
> >>> - MMIO_D(PCH_PP_STATUS, D_ALL);
> >>> - MMIO_D(PCH_LVDS, D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
> >>> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
> >>> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
> >>> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
> >>> - MMIO_D(PCH_DPLL_SEL, D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x61208), D_ALL);
> >>> - MMIO_D(_MMIO(0x6120c), D_ALL);
> >>> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
> >>> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
> >>> -
> >>> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
> >>> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> -
> >>> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
> >>> - PORTA_HOTPLUG_STATUS_MASK
> >>> - | PORTB_HOTPLUG_STATUS_MASK
> >>> - | PORTC_HOTPLUG_STATUS_MASK
> >>> - | PORTD_HOTPLUG_STATUS_MASK,
> >>> - NULL, NULL);
> >>> -
> >>> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
> >>> - MMIO_D(FUSE_STRAP, D_ALL);
> >>> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
> >>> -
> >>> - MMIO_D(DISP_ARB_CTL, D_ALL);
> >>> - MMIO_D(DISP_ARB_CTL2, D_ALL);
> >>> -
> >>> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
> >>> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
> >>> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
> >>> -
> >>> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
> >>> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
> >>> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
> >>> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
> >>> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
> >>> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
> >>> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
> >>> -
> >>> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
> >>> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
> >>> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
> >>> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
> >>> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
> >>> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
> >>> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
> >>> -
> >>> - MMIO_D(IPS_CTL, D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
> >>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
> >>> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
> >>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
> >>> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
> >>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
> >>> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
> >>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(_MMIO(0x60110), D_ALL);
> >>> - MMIO_D(_MMIO(0x61110), D_ALL);
> >>> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> -
> >>> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
> >>> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
> >>> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
> >>> - MMIO_D(SPLL_CTL, D_ALL);
> >>> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
> >>> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
> >>> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
> >>> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
> >>> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
> >>> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
> >>> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
> >>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
> >>> -
> >>> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
> >>> - MMIO_D(_MMIO(0x46508), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x49080), D_ALL);
> >>> - MMIO_D(_MMIO(0x49180), D_ALL);
> >>> - MMIO_D(_MMIO(0x49280), D_ALL);
> >>> -
> >>> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
> >>> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
> >>> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
> >>> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
> >>> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
> >>> -
> >>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
> >>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
> >>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
> >>> -
> >>> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
> >>> - MMIO_D(SBI_ADDR, D_ALL);
> >>> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
> >>> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
> >>> - MMIO_D(PIXCLK_GATE, D_ALL);
> >>> -
> >>> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> -
> >>> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> -
> >>> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> -
> >>> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
> >>> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
> >>> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
> >>> -
> >>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
> >>> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
> >>> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
> >>> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
> >>> -
> >>> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
> >>> - MMIO_D(FORCEWAKE_ACK, D_ALL);
> >>> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
> >>> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
> >>> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
> >>> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
> >>> - MMIO_D(ECOBUS, D_ALL);
> >>> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
> >>> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
> >>> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
> >>> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
> >>> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
> >>> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
> >>> - MMIO_D(GEN6_RPSTAT1, D_ALL);
> >>> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
> >>> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
> >>> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
> >>> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
> >>> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
> >>> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
> >>> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
> >>> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
> >>> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
> >>> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
> >>> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
> >>> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
> >>> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
> >>> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
> >>> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
> >>> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
> >>> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
> >>> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> -
> >>> - MMIO_D(RSTDBYCTL, D_ALL);
> >>> -
> >>> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
> >>> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
> >>> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
> >>> -
> >>> - MMIO_D(TILECTL, D_ALL);
> >>> -
> >>> - MMIO_D(GEN6_UCGCTL1, D_ALL);
> >>> - MMIO_D(GEN6_UCGCTL2, D_ALL);
> >>> -
> >>> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
> >>> - MMIO_D(_MMIO(0x13812c), D_ALL);
> >>> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
> >>> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
> >>> - MMIO_D(HSW_IDICR, D_ALL);
> >>> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_D(_MMIO(0x3c), D_ALL);
> >>> - MMIO_D(_MMIO(0x860), D_ALL);
> >>> - MMIO_D(ECOSKPD, D_ALL);
> >>> - MMIO_D(_MMIO(0x121d0), D_ALL);
> >>> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
> >>> - MMIO_D(_MMIO(0x41d0), D_ALL);
> >>> - MMIO_D(GAC_ECO_BITS, D_ALL);
> >>> - MMIO_D(_MMIO(0x6200), D_ALL);
> >>> - MMIO_D(_MMIO(0x6204), D_ALL);
> >>> - MMIO_D(_MMIO(0x6208), D_ALL);
> >>> - MMIO_D(_MMIO(0x7118), D_ALL);
> >>> - MMIO_D(_MMIO(0x7180), D_ALL);
> >>> - MMIO_D(_MMIO(0x7408), D_ALL);
> >>> - MMIO_D(_MMIO(0x7c00), D_ALL);
> >>> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
> >>> - MMIO_D(_MMIO(0x911c), D_ALL);
> >>> - MMIO_D(_MMIO(0x9120), D_ALL);
> >>> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_D(GAB_CTL, D_ALL);
> >>> - MMIO_D(_MMIO(0x48800), D_ALL);
> >>> - MMIO_D(_MMIO(0xce044), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6500), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6504), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6600), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6604), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6700), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6704), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6800), D_ALL);
> >>> - MMIO_D(_MMIO(0xe6804), D_ALL);
> >>> - MMIO_D(PCH_GMBUS4, D_ALL);
> >>> - MMIO_D(PCH_GMBUS5, D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x902c), D_ALL);
> >>> - MMIO_D(_MMIO(0xec008), D_ALL);
> >>> - MMIO_D(_MMIO(0xec00c), D_ALL);
> >>> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
> >>> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
> >>> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
> >>> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
> >>> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
> >>> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
> >>> - MMIO_D(_MMIO(0xec408), D_ALL);
> >>> - MMIO_D(_MMIO(0xec40c), D_ALL);
> >>> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
> >>> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
> >>> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
> >>> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
> >>> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
> >>> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
> >>> - MMIO_D(_MMIO(0xfc810), D_ALL);
> >>> - MMIO_D(_MMIO(0xfc81c), D_ALL);
> >>> - MMIO_D(_MMIO(0xfc828), D_ALL);
> >>> - MMIO_D(_MMIO(0xfc834), D_ALL);
> >>> - MMIO_D(_MMIO(0xfcc00), D_ALL);
> >>> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
> >>> - MMIO_D(_MMIO(0xfcc18), D_ALL);
> >>> - MMIO_D(_MMIO(0xfcc24), D_ALL);
> >>> - MMIO_D(_MMIO(0xfd000), D_ALL);
> >>> - MMIO_D(_MMIO(0xfd00c), D_ALL);
> >>> - MMIO_D(_MMIO(0xfd018), D_ALL);
> >>> - MMIO_D(_MMIO(0xfd024), D_ALL);
> >>> - MMIO_D(_MMIO(0xfd034), D_ALL);
> >>> -
> >>> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
> >>> - MMIO_D(_MMIO(0x2054), D_ALL);
> >>> - MMIO_D(_MMIO(0x12054), D_ALL);
> >>> - MMIO_D(_MMIO(0x22054), D_ALL);
> >>> - MMIO_D(_MMIO(0x1a054), D_ALL);
> >>> -
> >>> - MMIO_D(_MMIO(0x44070), D_ALL);
> >>> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> >>> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
> >>> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> >>> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> >>> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
> >>> -
> >>> - return 0;
> >>> -}
> >>> -
> >>> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
> >>> -{
> >>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> - int ret;
> >>> -
> >>> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
> >>> - intel_vgpu_reg_master_irq_handler);
> >>> -
> >>> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
> >>> - mmio_read_from_hw, NULL);
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0xd0)
> >>> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
> >>> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
> >>> - ring_reset_ctl_write);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x230)
> >>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x234)
> >>> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
> >>> - NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x244)
> >>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x370)
> >>> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x3a0)
> >>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
> >>> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
> >>> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
> >>> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
> >>> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
> >>> -
> >>> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
> >>> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
> >>> -
> >>> -#define RING_REG(base) _MMIO((base) + 0x270)
> >>> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> >>> -#undef RING_REG
> >>> -
> >>> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
> >>> -
> >>> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
> >>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
> >>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(WM_MISC, D_BDW);
> >>> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
> >>> -
> >>> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
> >>> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
> >>> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
> >>> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_D(_MMIO(0xb110), D_BDW);
> >>> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
> >>> -
> >>> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
> >>> - D_BDW_PLUS, NULL, force_nonpriv_write);
> >>> -
> >>> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
> >>> -
> >>> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
> >>> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
> >>> -
> >>> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - return 0;
> >>> -}
> >>> -
> >>> -static int init_skl_mmio_info(struct intel_gvt *gvt)
> >>> -{
> >>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> - int ret;
> >>> -
> >>> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> - dp_aux_ch_ctl_mmio_write);
> >>> -
> >>> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
> >>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
> >>> -
> >>> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
> >>> -
> >>> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
> >>> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> >>> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> >>> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
> >>> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
> >>> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
> >>> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> >>> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> >>> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
> >>> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
> >>> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
> >>> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
> >>> -
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> -
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> -
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> -
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> >>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> >>> -
> >>> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
> >>> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
> >>> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
> >>> -
> >>> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
> >>> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
> >>> -
> >>> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> >>> - NULL, NULL);
> >>> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> >>> - NULL, NULL);
> >>> -
> >>> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
> >>> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
> >>> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
> >>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> -
> >>> - /* TRTT */
> >>> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
> >>> - NULL, gen9_trtte_write);
> >>> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
> >>> - NULL, gen9_trtt_chicken_write);
> >>> -
> >>> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
> >>> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
> >>> -
> >>> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
> >>> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
> >>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
> >>> -
> >>> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
> >>> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
> >>> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, csfe_chicken1_mmio_write);
> >>> -#undef CSFE_CHICKEN1_REG
> >>> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> - NULL, NULL);
> >>> -
> >>> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
> >>> -
> >>> - return 0;
> >>> -}
> >>> -
> >>> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
> >>> -{
> >>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> - int ret;
> >>> -
> >>> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
> >>> -
> >>> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
> >>> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
> >>> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
> >>> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
> >>> - MMIO_D(ERROR_GEN6, D_BXT);
> >>> - MMIO_D(DONE_REG, D_BXT);
> >>> - MMIO_D(EIR, D_BXT);
> >>> - MMIO_D(PGTBL_ER, D_BXT);
> >>> - MMIO_D(_MMIO(0x4194), D_BXT);
> >>> - MMIO_D(_MMIO(0x4294), D_BXT);
> >>> - MMIO_D(_MMIO(0x4494), D_BXT);
> >>> -
> >>> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
> >>> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
> >>> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
> >>> - MMIO_RING_D(RING_IPEHR, D_BXT);
> >>> - MMIO_RING_D(RING_INSTPS, D_BXT);
> >>> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
> >>> - MMIO_RING_D(RING_BBSTATE, D_BXT);
> >>> - MMIO_RING_D(RING_IPEIR, D_BXT);
> >>> -
> >>> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
> >>> -
> >>> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
> >>> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
> >>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
> >>> - NULL, bxt_phy_ctl_family_write);
> >>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
> >>> - NULL, bxt_phy_ctl_family_write);
> >>> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
> >>> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
> >>> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
> >>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
> >>> - NULL, bxt_port_pll_enable_write);
> >>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
> >>> - NULL, bxt_port_pll_enable_write);
> >>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
> >>> - bxt_port_pll_enable_write);
> >>> -
> >>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
> >>> -
> >>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
> >>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
> >>> -
> >>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
> >>> - NULL, bxt_pcs_dw12_grp_write);
> >>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
> >>> - bxt_port_tx_dw3_read, NULL);
> >>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
> >>> -
> >>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
> >>> - NULL, bxt_pcs_dw12_grp_write);
> >>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
> >>> - bxt_port_tx_dw3_read, NULL);
> >>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
> >>> -
> >>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
> >>> - NULL, bxt_pcs_dw12_grp_write);
> >>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
> >>> - bxt_port_tx_dw3_read, NULL);
> >>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
> >>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
> >>> -
> >>> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
> >>> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
> >>> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
> >>> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
> >>> -
> >>> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
> >>> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
> >>> -
> >>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
> >>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
> >>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
> >>> -
> >>> - MMIO_D(RC6_CTX_BASE, D_BXT);
> >>> -
> >>> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
> >>> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
> >>> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
> >>> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
> >>> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> - 0, 0, D_BXT, NULL, NULL);
> >>> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> - 0, 0, D_BXT, NULL, NULL);
> >>> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> - 0, 0, D_BXT, NULL, NULL);
> >>> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> - 0, 0, D_BXT, NULL, NULL);
> >>> -
> >>> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> -
> >>> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
> >>> -
> >>> - return 0;
> >>> -}
> >>> +#include "mmio_table.h"
> >>>
> >>> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
> >>> unsigned int offset)
> >>> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
> >>> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
> >>> {
> >>> struct intel_gvt_device_info *info = &gvt->device_info;
> >>> - struct drm_i915_private *i915 = gvt->gt->i915;
> >>> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
> >>> int ret;
> >>>
> >>> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
> >>> if (!gvt->mmio.mmio_attribute)
> >>> return -ENOMEM;
> >>>
> >>> - ret = init_generic_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> -
> >>> - if (IS_BROADWELL(i915)) {
> >>> - ret = init_bdw_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> - } else if (IS_SKYLAKE(i915) ||
> >>> - IS_KABYLAKE(i915) ||
> >>> - IS_COFFEELAKE(i915) ||
> >>> - IS_COMETLAKE(i915)) {
> >>> - ret = init_bdw_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> - ret = init_skl_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> - } else if (IS_BROXTON(i915)) {
> >>> - ret = init_bdw_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> - ret = init_skl_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> - ret = init_bxt_mmio_info(gvt);
> >>> - if (ret)
> >>> - goto err;
> >>> + ret = intel_gvt_init_mmio_info(gvt);
> >>> + if (ret) {
> >>> + intel_gvt_clean_mmio_info(gvt);
> >>> + return ret;
> >>> }
> >>>
> >>> gvt->mmio.mmio_block = mmio_blocks;
> >>> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
> >>>
> >>> return 0;
> >>> -err:
> >>> - intel_gvt_clean_mmio_info(gvt);
> >>> - return ret;
> >>> }
> >>>
> >>> /**
> >>> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
> >>> new file mode 100644
> >>> index 000000000000..39a4cb59695a
> >>> --- /dev/null
> >>> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
> >>> @@ -0,0 +1,1570 @@
> >>> +/*
> >>> + * Copyright © 2021 Intel Corporation
> >>> + *
> >>> + * Permission is hereby granted, free of charge, to any person obtaining a
> >>> + * copy of this software and associated documentation files (the "Software"),
> >>> + * to deal in the Software without restriction, including without limitation
> >>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> >>> + * and/or sell copies of the Software, and to permit persons to whom the
> >>> + * Software is furnished to do so, subject to the following conditions:
> >>> + *
> >>> + * The above copyright notice and this permission notice (including the next
> >>> + * paragraph) shall be included in all copies or substantial portions of the
> >>> + * Software.
> >>> + *
> >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> >>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> >>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> >>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> >>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> >>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> >>> + * IN THE SOFTWARE.
> >>> + *
> >>> + */
> >>> +
> >>> +#ifndef _GVT_MMIO_TABLE_H_
> >>> +#define _GVT_MMIO_TABLE_H_
> >>> +
> >>> +#ifdef GENERATE_MMIO_TABLE_IN_I915
> >>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> >>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
> >>> + if (ret) \
> >>> + return ret; \
> >>> +} while (0)
> >>> +#else
> >>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> >>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
> >>> + f, s, am, rm, d, r, w); \
> >>> + if (ret) \
> >>> + return ret; \
> >>> +} while (0)
> >>> +#endif
> >>> +
> >>> +#define MMIO_D(reg, d) \
> >>> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
> >>> +
> >>> +#define MMIO_DH(reg, d, r, w) \
> >>> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
> >>> +
> >>> +#define MMIO_DFH(reg, d, f, r, w) \
> >>> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
> >>> +
> >>> +#define MMIO_GM(reg, d, r, w) \
> >>> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
> >>> +
> >>> +#define MMIO_GM_RDR(reg, d, r, w) \
> >>> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
> >>> +
> >>> +#define MMIO_RO(reg, d, f, rm, r, w) \
> >>> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
> >>> +
> >>> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
> >>> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
> >>> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> >>> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> >>> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> >>> + if (HAS_ENGINE(gvt->gt, VCS1)) \
> >>> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
> >>> +} while (0)
> >>> +
> >>> +#define MMIO_RING_D(prefix, d) \
> >>> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
> >>> +
> >>> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
> >>> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
> >>> +
> >>> +#define MMIO_RING_GM(prefix, d, r, w) \
> >>> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
> >>> +
> >>> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
> >>> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
> >>> +
> >>> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
> >>> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
> >>> +
> >>> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
> >>> +{
> >>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> +
> >>> + int ret;
> >>> +
> >>> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
> >>> + intel_vgpu_reg_imr_handler);
> >>> +
> >>> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(SDEISR, D_ALL);
> >>> +
> >>> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
> >>> +
> >>> +
> >>> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
> >>> + gamw_echo_dev_rw_ia_write);
> >>> +
> >>> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x28)
> >>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x134)
> >>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x6c)
> >>> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
> >>> +#undef RING_REG
> >>> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
> >>> +
> >>> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
> >>> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
> >>> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
> >>> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
> >>> +
> >>> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
> >>> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
> >>> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
> >>> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
> >>> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
> >>> +
> >>> + /* RING MODE */
> >>> +#define RING_REG(base) _MMIO((base) + 0x29c)
> >>> + MMIO_RING_DFH(RING_REG, D_ALL,
> >>> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
> >>> + ring_mode_mmio_write);
> >>> +#undef RING_REG
> >>> +
> >>> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
> >>> + mmio_read_from_hw, NULL);
> >>> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
> >>> + mmio_read_from_hw, NULL);
> >>> +
> >>> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
> >>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + /* display */
> >>> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_D(_MMIO(0x602a0), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x65050), D_ALL);
> >>> + MMIO_D(_MMIO(0x650b4), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0xc4040), D_ALL);
> >>> + MMIO_D(DERRMR, D_ALL);
> >>> +
> >>> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
> >>> +
> >>> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
> >>> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
> >>> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
> >>> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
> >>> +
> >>> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
> >>> +
> >>> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
> >>> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
> >>> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(CURPOS(PIPE_A), D_ALL);
> >>> + MMIO_D(CURPOS(PIPE_B), D_ALL);
> >>> + MMIO_D(CURPOS(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(CURBASE(PIPE_A), D_ALL);
> >>> + MMIO_D(CURBASE(PIPE_B), D_ALL);
> >>> + MMIO_D(CURBASE(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
> >>> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
> >>> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x700ac), D_ALL);
> >>> + MMIO_D(_MMIO(0x710ac), D_ALL);
> >>> + MMIO_D(_MMIO(0x720ac), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x70090), D_ALL);
> >>> + MMIO_D(_MMIO(0x70094), D_ALL);
> >>> + MMIO_D(_MMIO(0x70098), D_ALL);
> >>> + MMIO_D(_MMIO(0x7009c), D_ALL);
> >>> +
> >>> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
> >>> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
> >>> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
> >>> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
> >>> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
> >>> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> >>> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
> >>> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
> >>> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
> >>> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
> >>> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
> >>> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
> >>> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
> >>> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
> >>> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
> >>> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
> >>> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
> >>> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
> >>> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
> >>> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
> >>> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
> >>> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
> >>> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
> >>> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
> >>> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
> >>> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
> >>> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
> >>> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
> >>> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
> >>> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
> >>> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
> >>> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
> >>> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
> >>> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
> >>> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
> >>> + reg50080_mmio_write);
> >>> +
> >>> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
> >>> +
> >>> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
> >>> +
> >>> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
> >>> +
> >>> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
> >>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
> >>> +
> >>> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
> >>> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
> >>> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
> >>> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
> >>> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
> >>> +
> >>> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
> >>> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
> >>> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
> >>> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
> >>> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
> >>> +
> >>> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
> >>> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
> >>> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
> >>> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
> >>> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
> >>> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
> >>> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
> >>> + MMIO_D(WM1_LP_ILK, D_ALL);
> >>> + MMIO_D(WM2_LP_ILK, D_ALL);
> >>> + MMIO_D(WM3_LP_ILK, D_ALL);
> >>> + MMIO_D(WM1S_LP_ILK, D_ALL);
> >>> + MMIO_D(WM2S_LP_IVB, D_ALL);
> >>> + MMIO_D(WM3S_LP_IVB, D_ALL);
> >>> +
> >>> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
> >>> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
> >>> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
> >>> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x48268), D_ALL);
> >>> +
> >>> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> >>> + gmbus_mmio_write);
> >>> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> +
> >>> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
> >>> +
> >>> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
> >>> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
> >>> +
> >>> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
> >>> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
> >>> +
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
> >>> +
> >>> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
> >>> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
> >>> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
> >>> +
> >>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
> >>> +
> >>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
> >>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
> >>> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
> >>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
> >>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
> >>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
> >>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
> >>> +
> >>> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
> >>> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
> >>> + MMIO_D(PCH_PP_STATUS, D_ALL);
> >>> + MMIO_D(PCH_LVDS, D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
> >>> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
> >>> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
> >>> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
> >>> + MMIO_D(PCH_DPLL_SEL, D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x61208), D_ALL);
> >>> + MMIO_D(_MMIO(0x6120c), D_ALL);
> >>> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
> >>> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
> >>> +
> >>> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
> >>> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
> >>> +
> >>> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
> >>> + PORTA_HOTPLUG_STATUS_MASK
> >>> + | PORTB_HOTPLUG_STATUS_MASK
> >>> + | PORTC_HOTPLUG_STATUS_MASK
> >>> + | PORTD_HOTPLUG_STATUS_MASK,
> >>> + NULL, NULL);
> >>> +
> >>> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
> >>> + MMIO_D(FUSE_STRAP, D_ALL);
> >>> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
> >>> +
> >>> + MMIO_D(DISP_ARB_CTL, D_ALL);
> >>> + MMIO_D(DISP_ARB_CTL2, D_ALL);
> >>> +
> >>> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
> >>> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
> >>> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
> >>> +
> >>> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
> >>> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
> >>> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
> >>> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
> >>> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
> >>> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
> >>> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
> >>> +
> >>> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
> >>> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
> >>> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
> >>> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
> >>> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
> >>> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
> >>> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
> >>> +
> >>> + MMIO_D(IPS_CTL, D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
> >>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
> >>> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
> >>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
> >>> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
> >>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
> >>> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
> >>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(_MMIO(0x60110), D_ALL);
> >>> + MMIO_D(_MMIO(0x61110), D_ALL);
> >>> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
> >>> +
> >>> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
> >>> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
> >>> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
> >>> + MMIO_D(SPLL_CTL, D_ALL);
> >>> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
> >>> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
> >>> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
> >>> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
> >>> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
> >>> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
> >>> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
> >>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
> >>> +
> >>> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
> >>> + MMIO_D(_MMIO(0x46508), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x49080), D_ALL);
> >>> + MMIO_D(_MMIO(0x49180), D_ALL);
> >>> + MMIO_D(_MMIO(0x49280), D_ALL);
> >>> +
> >>> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
> >>> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
> >>> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
> >>> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
> >>> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
> >>> +
> >>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
> >>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
> >>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
> >>> +
> >>> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
> >>> + MMIO_D(SBI_ADDR, D_ALL);
> >>> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
> >>> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
> >>> + MMIO_D(PIXCLK_GATE, D_ALL);
> >>> +
> >>> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> +
> >>> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
> >>> +
> >>> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
> >>> +
> >>> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
> >>> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
> >>> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
> >>> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
> >>> +
> >>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
> >>> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
> >>> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
> >>> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
> >>> +
> >>> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
> >>> + MMIO_D(FORCEWAKE_ACK, D_ALL);
> >>> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
> >>> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
> >>> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
> >>> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
> >>> + MMIO_D(ECOBUS, D_ALL);
> >>> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
> >>> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
> >>> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
> >>> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
> >>> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
> >>> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
> >>> + MMIO_D(GEN6_RPSTAT1, D_ALL);
> >>> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
> >>> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
> >>> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
> >>> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
> >>> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
> >>> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
> >>> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
> >>> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
> >>> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
> >>> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
> >>> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
> >>> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
> >>> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
> >>> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
> >>> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
> >>> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
> >>> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
> >>> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
> >>> +
> >>> + MMIO_D(RSTDBYCTL, D_ALL);
> >>> +
> >>> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
> >>> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
> >>> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
> >>> +
> >>> + MMIO_D(TILECTL, D_ALL);
> >>> +
> >>> + MMIO_D(GEN6_UCGCTL1, D_ALL);
> >>> + MMIO_D(GEN6_UCGCTL2, D_ALL);
> >>> +
> >>> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
> >>> + MMIO_D(_MMIO(0x13812c), D_ALL);
> >>> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
> >>> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
> >>> + MMIO_D(HSW_IDICR, D_ALL);
> >>> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_D(_MMIO(0x3c), D_ALL);
> >>> + MMIO_D(_MMIO(0x860), D_ALL);
> >>> + MMIO_D(ECOSKPD, D_ALL);
> >>> + MMIO_D(_MMIO(0x121d0), D_ALL);
> >>> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
> >>> + MMIO_D(_MMIO(0x41d0), D_ALL);
> >>> + MMIO_D(GAC_ECO_BITS, D_ALL);
> >>> + MMIO_D(_MMIO(0x6200), D_ALL);
> >>> + MMIO_D(_MMIO(0x6204), D_ALL);
> >>> + MMIO_D(_MMIO(0x6208), D_ALL);
> >>> + MMIO_D(_MMIO(0x7118), D_ALL);
> >>> + MMIO_D(_MMIO(0x7180), D_ALL);
> >>> + MMIO_D(_MMIO(0x7408), D_ALL);
> >>> + MMIO_D(_MMIO(0x7c00), D_ALL);
> >>> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
> >>> + MMIO_D(_MMIO(0x911c), D_ALL);
> >>> + MMIO_D(_MMIO(0x9120), D_ALL);
> >>> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_D(GAB_CTL, D_ALL);
> >>> + MMIO_D(_MMIO(0x48800), D_ALL);
> >>> + MMIO_D(_MMIO(0xce044), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6500), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6504), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6600), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6604), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6700), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6704), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6800), D_ALL);
> >>> + MMIO_D(_MMIO(0xe6804), D_ALL);
> >>> + MMIO_D(PCH_GMBUS4, D_ALL);
> >>> + MMIO_D(PCH_GMBUS5, D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x902c), D_ALL);
> >>> + MMIO_D(_MMIO(0xec008), D_ALL);
> >>> + MMIO_D(_MMIO(0xec00c), D_ALL);
> >>> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
> >>> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
> >>> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
> >>> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
> >>> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
> >>> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
> >>> + MMIO_D(_MMIO(0xec408), D_ALL);
> >>> + MMIO_D(_MMIO(0xec40c), D_ALL);
> >>> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
> >>> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
> >>> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
> >>> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
> >>> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
> >>> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
> >>> + MMIO_D(_MMIO(0xfc810), D_ALL);
> >>> + MMIO_D(_MMIO(0xfc81c), D_ALL);
> >>> + MMIO_D(_MMIO(0xfc828), D_ALL);
> >>> + MMIO_D(_MMIO(0xfc834), D_ALL);
> >>> + MMIO_D(_MMIO(0xfcc00), D_ALL);
> >>> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
> >>> + MMIO_D(_MMIO(0xfcc18), D_ALL);
> >>> + MMIO_D(_MMIO(0xfcc24), D_ALL);
> >>> + MMIO_D(_MMIO(0xfd000), D_ALL);
> >>> + MMIO_D(_MMIO(0xfd00c), D_ALL);
> >>> + MMIO_D(_MMIO(0xfd018), D_ALL);
> >>> + MMIO_D(_MMIO(0xfd024), D_ALL);
> >>> + MMIO_D(_MMIO(0xfd034), D_ALL);
> >>> +
> >>> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
> >>> + MMIO_D(_MMIO(0x2054), D_ALL);
> >>> + MMIO_D(_MMIO(0x12054), D_ALL);
> >>> + MMIO_D(_MMIO(0x22054), D_ALL);
> >>> + MMIO_D(_MMIO(0x1a054), D_ALL);
> >>> +
> >>> + MMIO_D(_MMIO(0x44070), D_ALL);
> >>> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> >>> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
> >>> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
> >>> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
> >>> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> >>> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
> >>> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
> >>> +{
> >>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> + int ret;
> >>> +
> >>> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
> >>> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
> >>> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
> >>> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
> >>> + intel_vgpu_reg_master_irq_handler);
> >>> +
> >>> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
> >>> + mmio_read_from_hw, NULL);
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0xd0)
> >>> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
> >>> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
> >>> + ring_reset_ctl_write);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x230)
> >>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x234)
> >>> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
> >>> + NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x244)
> >>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x370)
> >>> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x3a0)
> >>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
> >>> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
> >>> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
> >>> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
> >>> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
> >>> +
> >>> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
> >>> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
> >>> +
> >>> +#define RING_REG(base) _MMIO((base) + 0x270)
> >>> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
> >>> +#undef RING_REG
> >>> +
> >>> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
> >>> +
> >>> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
> >>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
> >>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(WM_MISC, D_BDW);
> >>> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
> >>> +
> >>> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
> >>> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
> >>> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
> >>> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_D(_MMIO(0xb110), D_BDW);
> >>> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
> >>> +
> >>> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
> >>> + D_BDW_PLUS, NULL, force_nonpriv_write);
> >>> +
> >>> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
> >>> +
> >>> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
> >>> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
> >>> +
> >>> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
> >>> +{
> >>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> + int ret;
> >>> +
> >>> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
> >>> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
> >>> + dp_aux_ch_ctl_mmio_write);
> >>> +
> >>> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
> >>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
> >>> +
> >>> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
> >>> +
> >>> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
> >>> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> >>> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
> >>> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
> >>> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
> >>> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
> >>> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> >>> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
> >>> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
> >>> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
> >>> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
> >>> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
> >>> +
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> +
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> +
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
> >>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
> >>> +
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> >>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> >>> +
> >>> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
> >>> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
> >>> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
> >>> +
> >>> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
> >>> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
> >>> +
> >>> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> >>> + NULL, NULL);
> >>> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
> >>> + NULL, NULL);
> >>> +
> >>> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
> >>> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
> >>> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
> >>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> +
> >>> + /* TRTT */
> >>> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
> >>> + NULL, gen9_trtte_write);
> >>> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
> >>> + NULL, gen9_trtt_chicken_write);
> >>> +
> >>> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
> >>> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
> >>> +
> >>> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
> >>> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
> >>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
> >>> +
> >>> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
> >>> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
> >>> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, csfe_chicken1_mmio_write);
> >>> +#undef CSFE_CHICKEN1_REG
> >>> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
> >>> + NULL, NULL);
> >>> +
> >>> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
> >>> +{
> >>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
> >>> + int ret;
> >>> +
> >>> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
> >>> +
> >>> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
> >>> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
> >>> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
> >>> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
> >>> + MMIO_D(ERROR_GEN6, D_BXT);
> >>> + MMIO_D(DONE_REG, D_BXT);
> >>> + MMIO_D(EIR, D_BXT);
> >>> + MMIO_D(PGTBL_ER, D_BXT);
> >>> + MMIO_D(_MMIO(0x4194), D_BXT);
> >>> + MMIO_D(_MMIO(0x4294), D_BXT);
> >>> + MMIO_D(_MMIO(0x4494), D_BXT);
> >>> +
> >>> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
> >>> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
> >>> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
> >>> + MMIO_RING_D(RING_IPEHR, D_BXT);
> >>> + MMIO_RING_D(RING_INSTPS, D_BXT);
> >>> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
> >>> + MMIO_RING_D(RING_BBSTATE, D_BXT);
> >>> + MMIO_RING_D(RING_IPEIR, D_BXT);
> >>> +
> >>> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
> >>> +
> >>> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
> >>> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
> >>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
> >>> + NULL, bxt_phy_ctl_family_write);
> >>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
> >>> + NULL, bxt_phy_ctl_family_write);
> >>> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
> >>> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
> >>> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
> >>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
> >>> + NULL, bxt_port_pll_enable_write);
> >>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
> >>> + NULL, bxt_port_pll_enable_write);
> >>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
> >>> + bxt_port_pll_enable_write);
> >>> +
> >>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
> >>> +
> >>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
> >>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
> >>> +
> >>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
> >>> + NULL, bxt_pcs_dw12_grp_write);
> >>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
> >>> + bxt_port_tx_dw3_read, NULL);
> >>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
> >>> +
> >>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
> >>> + NULL, bxt_pcs_dw12_grp_write);
> >>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
> >>> + bxt_port_tx_dw3_read, NULL);
> >>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
> >>> +
> >>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
> >>> + NULL, bxt_pcs_dw12_grp_write);
> >>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
> >>> + bxt_port_tx_dw3_read, NULL);
> >>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
> >>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
> >>> +
> >>> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
> >>> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
> >>> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
> >>> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
> >>> +
> >>> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
> >>> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
> >>> +
> >>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
> >>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
> >>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
> >>> +
> >>> + MMIO_D(RC6_CTX_BASE, D_BXT);
> >>> +
> >>> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
> >>> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
> >>> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
> >>> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
> >>> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> + 0, 0, D_BXT, NULL, NULL);
> >>> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> + 0, 0, D_BXT, NULL, NULL);
> >>> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> + 0, 0, D_BXT, NULL, NULL);
> >>> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
> >>> + 0, 0, D_BXT, NULL, NULL);
> >>> +
> >>> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
> >>> +
> >>> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
> >>> +{
> >>> + struct drm_i915_private *i915 = gvt->gt->i915;
> >>> + int ret;
> >>> +
> >>> + ret = intel_gvt_init_generic_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + if (IS_BROADWELL(i915)) {
> >>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + } else if (IS_SKYLAKE(i915) ||
> >>> + IS_KABYLAKE(i915) ||
> >>> + IS_COFFEELAKE(i915) ||
> >>> + IS_COMETLAKE(i915)) {
> >>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + ret = intel_gvt_init_skl_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + } else if (IS_BROXTON(i915)) {
> >>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + ret = intel_gvt_init_skl_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + ret = intel_gvt_init_bxt_mmio_info(gvt);
> >>> + if (ret)
> >>> + return ret;
> >>> + }
> >>> +
> >>> + return 0;
> >>> +}
> >>> +#endif
> >>> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> >>> index 244cc7320b54..05bd2f8e9d94 100644
> >>> --- a/drivers/gpu/drm/i915/gvt/reg.h
> >>> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> >>> @@ -133,6 +133,12 @@
> >>> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
> >>> #define VF_GUARDBAND _MMIO(0x83a4)
> >>>
> >>> +/* XXX FIXME i915 has changed PP_XXX definition */
> >>> +#define PCH_PP_STATUS _MMIO(0xc7200)
> >>> +#define PCH_PP_CONTROL _MMIO(0xc7204)
> >>> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
> >>> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
> >>> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
> >>>
> >>> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
> >>> #endif
> >>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
> >>> index 4e70c1a9ef2e..64846d9bff0b 100644
> >>> --- a/drivers/gpu/drm/i915/intel_gvt.c
> >>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
> >>> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
> >>> dev_priv->params.enable_gvt = 0;
> >>> }
> >>>
> >>> +#define GENERATE_MMIO_TABLE_IN_I915
> >>> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
> >>> +{
> >>> + return 0;
> >>> +}
> >>> +
> >>> +#include "gvt/reg.h"
> >>> +#include "gvt/mmio_table.h"
> >>> +#undef GENERATE_MMIO_TABLE_IN_I915
> >>> +
> >>> +
> >>> /**
> >>> * intel_gvt_init - initialize GVT components
> >>> * @dev_priv: drm i915 private data
> >
> >
>
> --
> Jani Nikula, Intel Open Source Graphics Center
---end quoted text---
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-09 10:36 ` [Intel-gfx] " hch
(?)
@ 2021-11-09 10:51 ` Wang, Zhi A
-1 siblings, 0 replies; 35+ messages in thread
From: Wang, Zhi A @ 2021-11-09 10:51 UTC (permalink / raw)
To: hch, Jani Nikula
Cc: Zhi Wang, joonas.lahtinen, Vivi, Rodrigo, zhenyuw, jgg,
intel-gfx, intel-gvt-dev, dri-devel, linux-kernel
On 11/9/2021 12:36 PM, hch@lst.de wrote:
> On Tue, Nov 09, 2021 at 12:20:24PM +0200, Jani Nikula wrote:
>> Having the functions defined in a single .c file and called (perhaps via
>> just one or two entry points) sounds much better than including code.
>>
>> Perhaps you could pass in the function to call (new_mmio_info) as a
>> parameter in different situations instead of macro magic, to make the
>> code more readable?
>>
>> Basically I want more clarity in the interfaces between the compilation
>> units everywhere in i915.
> So as far as a I can tell the table is used for a few things:
>
> 1) to store the golden state, this is a plain array of u32
> 2) to attach special write (and sometimes read) handlers, and have
> a mask for read-only fields even for writable registers
> 3) to show the difference between the real and virtual registers in
> debugfs
> 4) to restore some registers on pm resume
>
> Can we somehow handle 3 and 4 with the table built for 1?
>
> In that case we only need special handling in the GVT for the registers
> that are overriden, which is a tiny subset and this avoids the giant
> duplication.
That sounds the idea I purposed in the previous reply for Jani. Let me
try to cook the patch with this idea.
> Btw, the mmio_info_table hash is only used to iterate over all entries,
> which is a strange use for a hash. It might make sense to replace it
> with a more suitable data structure and/or actually make use of the
> hash in intel_gvt_find_mmio_info.
Can you elaborate more about this? We need the hash query from the table
ASAP when the hypervisor trapped a mmio access. It's a critical path and
we tried different data structure in the kernel and the hash table gives
the best performance.
>>
>> BR,
>> Jani.
>>
>>
>>> Thanks,
>>>
>>> Zhi.
>>>
>>>> BR,
>>>> Jani.
>>>>
>>>>
>>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
>>>>> Cc: Zhi Wang <zhi.a.wang@intel.com>
>>>>> Cc: Christoph Hellwig <hch@lst.de>
>>>>> Cc: Jason Gunthorpe <jgg@nvidia.com>
>>>>> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
>>>>> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
>>>>> drivers/gpu/drm/i915/gvt/reg.h | 6 +
>>>>> drivers/gpu/drm/i915/intel_gvt.c | 11 +
>>>>> 4 files changed, 1592 insertions(+), 1534 deletions(-)
>>>>> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>>>>> index cde0a477fb49..6a08d362bf66 100644
>>>>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>>>>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>>>>> @@ -41,13 +41,6 @@
>>>>> #include "i915_pvinfo.h"
>>>>> #include "display/intel_display_types.h"
>>>>>
>>>>> -/* XXX FIXME i915 has changed PP_XXX definition */
>>>>> -#define PCH_PP_STATUS _MMIO(0xc7200)
>>>>> -#define PCH_PP_CONTROL _MMIO(0xc7204)
>>>>> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>>>> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>>>> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>>> -
>>>>> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
>>>>> {
>>>>> struct drm_i915_private *i915 = gvt->gt->i915;
>>>>> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
>>>>> return 0;
>>>>> }
>>>>>
>>>>> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>>> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>>>> - f, s, am, rm, d, r, w); \
>>>>> - if (ret) \
>>>>> - return ret; \
>>>>> -} while (0)
>>>>> -
>>>>> -#define MMIO_D(reg, d) \
>>>>> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>>>> -
>>>>> -#define MMIO_DH(reg, d, r, w) \
>>>>> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_DFH(reg, d, f, r, w) \
>>>>> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_GM(reg, d, r, w) \
>>>>> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_GM_RDR(reg, d, r, w) \
>>>>> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RO(reg, d, f, rm, r, w) \
>>>>> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>>>> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - if (HAS_ENGINE(gvt->gt, VCS1)) \
>>>>> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> -} while (0)
>>>>> -
>>>>> -#define MMIO_RING_D(prefix, d) \
>>>>> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>>>> -
>>>>> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_GM(prefix, d, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>>>> -
>>>>> -static int init_generic_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> -
>>>>> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(SDEISR, D_ALL);
>>>>> -
>>>>> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>>>> -
>>>>> -
>>>>> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>>>> - gamw_echo_dev_rw_ia_write);
>>>>> -
>>>>> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x28)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x134)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x6c)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> -#undef RING_REG
>>>>> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>>>> -
>>>>> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>>>> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>>>> -
>>>>> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>>>> -
>>>>> - /* RING MODE */
>>>>> -#define RING_REG(base) _MMIO((base) + 0x29c)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL,
>>>>> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>>>> - ring_mode_mmio_write);
>>>>> -#undef RING_REG
>>>>> -
>>>>> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>>>> - mmio_read_from_hw, NULL);
>>>>> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>>>> - mmio_read_from_hw, NULL);
>>>>> -
>>>>> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - /* display */
>>>>> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_D(_MMIO(0x602a0), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x65050), D_ALL);
>>>>> - MMIO_D(_MMIO(0x650b4), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0xc4040), D_ALL);
>>>>> - MMIO_D(DERRMR, D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>>>> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>>>> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>>>> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>>>> -
>>>>> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>>>> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>>>> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(CURPOS(PIPE_A), D_ALL);
>>>>> - MMIO_D(CURPOS(PIPE_B), D_ALL);
>>>>> - MMIO_D(CURPOS(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(CURBASE(PIPE_A), D_ALL);
>>>>> - MMIO_D(CURBASE(PIPE_B), D_ALL);
>>>>> - MMIO_D(CURBASE(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x700ac), D_ALL);
>>>>> - MMIO_D(_MMIO(0x710ac), D_ALL);
>>>>> - MMIO_D(_MMIO(0x720ac), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x70090), D_ALL);
>>>>> - MMIO_D(_MMIO(0x70094), D_ALL);
>>>>> - MMIO_D(_MMIO(0x70098), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7009c), D_ALL);
>>>>> -
>>>>> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>>>> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>>>> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>>>> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>>>> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>>>> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>>>> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>>>> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>>>> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>>>> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>>>> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>>>> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>>>> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>>>> - MMIO_D(WM1_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM2_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM3_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM1S_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM2S_LP_IVB, D_ALL);
>>>>> - MMIO_D(WM3S_LP_IVB, D_ALL);
>>>>> -
>>>>> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>>>> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>>>> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>>>> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x48268), D_ALL);
>>>>> -
>>>>> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>>>> - gmbus_mmio_write);
>>>>> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>>>> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>>>> -
>>>>> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>>>> -
>>>>> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>>>> -
>>>>> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>>>> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>>>> - MMIO_D(PCH_PP_STATUS, D_ALL);
>>>>> - MMIO_D(PCH_LVDS, D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>>>> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>>>> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>>>> - MMIO_D(PCH_DPLL_SEL, D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x61208), D_ALL);
>>>>> - MMIO_D(_MMIO(0x6120c), D_ALL);
>>>>> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>>>> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> -
>>>>> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>>>> - PORTA_HOTPLUG_STATUS_MASK
>>>>> - | PORTB_HOTPLUG_STATUS_MASK
>>>>> - | PORTC_HOTPLUG_STATUS_MASK
>>>>> - | PORTD_HOTPLUG_STATUS_MASK,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>>>> - MMIO_D(FUSE_STRAP, D_ALL);
>>>>> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>>>> -
>>>>> - MMIO_D(DISP_ARB_CTL, D_ALL);
>>>>> - MMIO_D(DISP_ARB_CTL2, D_ALL);
>>>>> -
>>>>> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>>>> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>>>> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>>>> -
>>>>> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>>>> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>>>> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>>>> -
>>>>> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>>>> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>>>> -
>>>>> - MMIO_D(IPS_CTL, D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>>>> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>>>> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>>>> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x60110), D_ALL);
>>>>> - MMIO_D(_MMIO(0x61110), D_ALL);
>>>>> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>>>> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>>>> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPLL_CTL, D_ALL);
>>>>> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>>>> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>>>> - MMIO_D(_MMIO(0x46508), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x49080), D_ALL);
>>>>> - MMIO_D(_MMIO(0x49180), D_ALL);
>>>>> - MMIO_D(_MMIO(0x49280), D_ALL);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>>>> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>>>> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>>>> - MMIO_D(SBI_ADDR, D_ALL);
>>>>> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>>>> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>>>> - MMIO_D(PIXCLK_GATE, D_ALL);
>>>>> -
>>>>> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>>>> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>>>> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>>>> -
>>>>> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>>>> - MMIO_D(FORCEWAKE_ACK, D_ALL);
>>>>> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>>>> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>>>> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>>>> - MMIO_D(ECOBUS, D_ALL);
>>>>> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>>>> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>>>> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>>>> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>>>> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>>>> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>>>> - MMIO_D(GEN6_RPSTAT1, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>>>> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>>>> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>>>> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>>>> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>>>> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>>>> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>>>> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>>>> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>>>> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>>>> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>>>> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_D(RSTDBYCTL, D_ALL);
>>>>> -
>>>>> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>>>> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>>>> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>>>> -
>>>>> - MMIO_D(TILECTL, D_ALL);
>>>>> -
>>>>> - MMIO_D(GEN6_UCGCTL1, D_ALL);
>>>>> - MMIO_D(GEN6_UCGCTL2, D_ALL);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>>>> - MMIO_D(_MMIO(0x13812c), D_ALL);
>>>>> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>>>> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>>>> - MMIO_D(HSW_IDICR, D_ALL);
>>>>> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x3c), D_ALL);
>>>>> - MMIO_D(_MMIO(0x860), D_ALL);
>>>>> - MMIO_D(ECOSKPD, D_ALL);
>>>>> - MMIO_D(_MMIO(0x121d0), D_ALL);
>>>>> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>>>> - MMIO_D(_MMIO(0x41d0), D_ALL);
>>>>> - MMIO_D(GAC_ECO_BITS, D_ALL);
>>>>> - MMIO_D(_MMIO(0x6200), D_ALL);
>>>>> - MMIO_D(_MMIO(0x6204), D_ALL);
>>>>> - MMIO_D(_MMIO(0x6208), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7118), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7180), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7408), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7c00), D_ALL);
>>>>> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>>>> - MMIO_D(_MMIO(0x911c), D_ALL);
>>>>> - MMIO_D(_MMIO(0x9120), D_ALL);
>>>>> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GAB_CTL, D_ALL);
>>>>> - MMIO_D(_MMIO(0x48800), D_ALL);
>>>>> - MMIO_D(_MMIO(0xce044), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6500), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6504), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6600), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6604), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6700), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6704), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6800), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6804), D_ALL);
>>>>> - MMIO_D(PCH_GMBUS4, D_ALL);
>>>>> - MMIO_D(PCH_GMBUS5, D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x902c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc810), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc81c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc828), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc834), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc00), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc24), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd000), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd00c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd018), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd024), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd034), D_ALL);
>>>>> -
>>>>> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>>>> - MMIO_D(_MMIO(0x2054), D_ALL);
>>>>> - MMIO_D(_MMIO(0x12054), D_ALL);
>>>>> - MMIO_D(_MMIO(0x22054), D_ALL);
>>>>> - MMIO_D(_MMIO(0x1a054), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x44070), D_ALL);
>>>>> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>>>> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>>>> -
>>>>> - return 0;
>>>>> -}
>>>>> -
>>>>> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_master_irq_handler);
>>>>> -
>>>>> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>>>> - mmio_read_from_hw, NULL);
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0xd0)
>>>>> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>>>> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>>>> - ring_reset_ctl_write);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x230)
>>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x234)
>>>>> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>>>> - NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x244)
>>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x370)
>>>>> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x3a0)
>>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>>>> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>>>> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>>>> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>>>> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>>>> -
>>>>> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>>>> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x270)
>>>>> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>>>> -
>>>>> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(WM_MISC, D_BDW);
>>>>> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>>>> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>>>> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>>>> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_D(_MMIO(0xb110), D_BDW);
>>>>> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>>>> - D_BDW_PLUS, NULL, force_nonpriv_write);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - return 0;
>>>>> -}
>>>>> -
>>>>> -static int init_skl_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>>>> -
>>>>> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>>>> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>>>> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>>>> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>>>> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>>>> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>>>> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>>>> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>>>> -
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> -
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> -
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> -
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>>>> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>>>> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>>>> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> - NULL, NULL);
>>>>> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>>>> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>>>> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - /* TRTT */
>>>>> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>>>> - NULL, gen9_trtte_write);
>>>>> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>>>> - NULL, gen9_trtt_chicken_write);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>>>> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>>>> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>>>> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>>>> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, csfe_chicken1_mmio_write);
>>>>> -#undef CSFE_CHICKEN1_REG
>>>>> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>>>> -
>>>>> - return 0;
>>>>> -}
>>>>> -
>>>>> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>>>> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>>>> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>>>> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>>>> - MMIO_D(ERROR_GEN6, D_BXT);
>>>>> - MMIO_D(DONE_REG, D_BXT);
>>>>> - MMIO_D(EIR, D_BXT);
>>>>> - MMIO_D(PGTBL_ER, D_BXT);
>>>>> - MMIO_D(_MMIO(0x4194), D_BXT);
>>>>> - MMIO_D(_MMIO(0x4294), D_BXT);
>>>>> - MMIO_D(_MMIO(0x4494), D_BXT);
>>>>> -
>>>>> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>>>> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>>>> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>>>> - MMIO_RING_D(RING_IPEHR, D_BXT);
>>>>> - MMIO_RING_D(RING_INSTPS, D_BXT);
>>>>> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>>>> - MMIO_RING_D(RING_BBSTATE, D_BXT);
>>>>> - MMIO_RING_D(RING_IPEIR, D_BXT);
>>>>> -
>>>>> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>>>> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>>>> - NULL, bxt_phy_ctl_family_write);
>>>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>>>> - NULL, bxt_phy_ctl_family_write);
>>>>> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>>>> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>>>> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>>>> - NULL, bxt_port_pll_enable_write);
>>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>>>> - NULL, bxt_port_pll_enable_write);
>>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>>>> - bxt_port_pll_enable_write);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> - bxt_port_tx_dw3_read, NULL);
>>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> - bxt_port_tx_dw3_read, NULL);
>>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> - bxt_port_tx_dw3_read, NULL);
>>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>>>> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>>>> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>>>> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>>>> -
>>>>> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>>>> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>>>> -
>>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>>>> -
>>>>> - MMIO_D(RC6_CTX_BASE, D_BXT);
>>>>> -
>>>>> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>>>> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>>>> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>>>> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>>>> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>>>> -
>>>>> - return 0;
>>>>> -}
>>>>> +#include "mmio_table.h"
>>>>>
>>>>> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
>>>>> unsigned int offset)
>>>>> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
>>>>> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>>>> {
>>>>> struct intel_gvt_device_info *info = &gvt->device_info;
>>>>> - struct drm_i915_private *i915 = gvt->gt->i915;
>>>>> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
>>>>> int ret;
>>>>>
>>>>> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>>>> if (!gvt->mmio.mmio_attribute)
>>>>> return -ENOMEM;
>>>>>
>>>>> - ret = init_generic_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> -
>>>>> - if (IS_BROADWELL(i915)) {
>>>>> - ret = init_bdw_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - } else if (IS_SKYLAKE(i915) ||
>>>>> - IS_KABYLAKE(i915) ||
>>>>> - IS_COFFEELAKE(i915) ||
>>>>> - IS_COMETLAKE(i915)) {
>>>>> - ret = init_bdw_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - ret = init_skl_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - } else if (IS_BROXTON(i915)) {
>>>>> - ret = init_bdw_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - ret = init_skl_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - ret = init_bxt_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> + ret = intel_gvt_init_mmio_info(gvt);
>>>>> + if (ret) {
>>>>> + intel_gvt_clean_mmio_info(gvt);
>>>>> + return ret;
>>>>> }
>>>>>
>>>>> gvt->mmio.mmio_block = mmio_blocks;
>>>>> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
>>>>>
>>>>> return 0;
>>>>> -err:
>>>>> - intel_gvt_clean_mmio_info(gvt);
>>>>> - return ret;
>>>>> }
>>>>>
>>>>> /**
>>>>> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>>>> new file mode 100644
>>>>> index 000000000000..39a4cb59695a
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>>>> @@ -0,0 +1,1570 @@
>>>>> +/*
>>>>> + * Copyright © 2021 Intel Corporation
>>>>> + *
>>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>>> + * copy of this software and associated documentation files (the "Software"),
>>>>> + * to deal in the Software without restriction, including without limitation
>>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>>> + * Software is furnished to do so, subject to the following conditions:
>>>>> + *
>>>>> + * The above copyright notice and this permission notice (including the next
>>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>>> + * Software.
>>>>> + *
>>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>>> + * IN THE SOFTWARE.
>>>>> + *
>>>>> + */
>>>>> +
>>>>> +#ifndef _GVT_MMIO_TABLE_H_
>>>>> +#define _GVT_MMIO_TABLE_H_
>>>>> +
>>>>> +#ifdef GENERATE_MMIO_TABLE_IN_I915
>>>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
>>>>> + if (ret) \
>>>>> + return ret; \
>>>>> +} while (0)
>>>>> +#else
>>>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>>>> + f, s, am, rm, d, r, w); \
>>>>> + if (ret) \
>>>>> + return ret; \
>>>>> +} while (0)
>>>>> +#endif
>>>>> +
>>>>> +#define MMIO_D(reg, d) \
>>>>> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>>>> +
>>>>> +#define MMIO_DH(reg, d, r, w) \
>>>>> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_DFH(reg, d, f, r, w) \
>>>>> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_GM(reg, d, r, w) \
>>>>> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_GM_RDR(reg, d, r, w) \
>>>>> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RO(reg, d, f, rm, r, w) \
>>>>> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>>>> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + if (HAS_ENGINE(gvt->gt, VCS1)) \
>>>>> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> +} while (0)
>>>>> +
>>>>> +#define MMIO_RING_D(prefix, d) \
>>>>> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>>>> +
>>>>> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_GM(prefix, d, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>>>> +
>>>>> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> +
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> +
>>>>> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(SDEISR, D_ALL);
>>>>> +
>>>>> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>>>> +
>>>>> +
>>>>> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>>>> + gamw_echo_dev_rw_ia_write);
>>>>> +
>>>>> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x28)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x134)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x6c)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> +#undef RING_REG
>>>>> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>>>> +
>>>>> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>>>> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>>>> +
>>>>> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>>>> +
>>>>> + /* RING MODE */
>>>>> +#define RING_REG(base) _MMIO((base) + 0x29c)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL,
>>>>> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>>>> + ring_mode_mmio_write);
>>>>> +#undef RING_REG
>>>>> +
>>>>> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>>>> + mmio_read_from_hw, NULL);
>>>>> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>>>> + mmio_read_from_hw, NULL);
>>>>> +
>>>>> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + /* display */
>>>>> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_D(_MMIO(0x602a0), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x65050), D_ALL);
>>>>> + MMIO_D(_MMIO(0x650b4), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0xc4040), D_ALL);
>>>>> + MMIO_D(DERRMR, D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>>>> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>>>> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>>>> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>>>> +
>>>>> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>>>> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>>>> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(CURPOS(PIPE_A), D_ALL);
>>>>> + MMIO_D(CURPOS(PIPE_B), D_ALL);
>>>>> + MMIO_D(CURPOS(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(CURBASE(PIPE_A), D_ALL);
>>>>> + MMIO_D(CURBASE(PIPE_B), D_ALL);
>>>>> + MMIO_D(CURBASE(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x700ac), D_ALL);
>>>>> + MMIO_D(_MMIO(0x710ac), D_ALL);
>>>>> + MMIO_D(_MMIO(0x720ac), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x70090), D_ALL);
>>>>> + MMIO_D(_MMIO(0x70094), D_ALL);
>>>>> + MMIO_D(_MMIO(0x70098), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7009c), D_ALL);
>>>>> +
>>>>> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>>>> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>>>> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>>>> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>>>> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>>>> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>>>> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>>>> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>>>> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>>>> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>>>> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>>>> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>>>> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>>>> + MMIO_D(WM1_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM2_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM3_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM1S_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM2S_LP_IVB, D_ALL);
>>>>> + MMIO_D(WM3S_LP_IVB, D_ALL);
>>>>> +
>>>>> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>>>> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>>>> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>>>> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x48268), D_ALL);
>>>>> +
>>>>> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>>>> + gmbus_mmio_write);
>>>>> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>>>> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>>>> +
>>>>> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>>>> +
>>>>> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>>>> +
>>>>> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>>>> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>>>> + MMIO_D(PCH_PP_STATUS, D_ALL);
>>>>> + MMIO_D(PCH_LVDS, D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>>>> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>>>> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>>>> + MMIO_D(PCH_DPLL_SEL, D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x61208), D_ALL);
>>>>> + MMIO_D(_MMIO(0x6120c), D_ALL);
>>>>> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>>>> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> +
>>>>> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>>>> + PORTA_HOTPLUG_STATUS_MASK
>>>>> + | PORTB_HOTPLUG_STATUS_MASK
>>>>> + | PORTC_HOTPLUG_STATUS_MASK
>>>>> + | PORTD_HOTPLUG_STATUS_MASK,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>>>> + MMIO_D(FUSE_STRAP, D_ALL);
>>>>> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>>>> +
>>>>> + MMIO_D(DISP_ARB_CTL, D_ALL);
>>>>> + MMIO_D(DISP_ARB_CTL2, D_ALL);
>>>>> +
>>>>> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>>>> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>>>> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>>>> +
>>>>> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>>>> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>>>> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>>>> +
>>>>> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>>>> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>>>> +
>>>>> + MMIO_D(IPS_CTL, D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>>>> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>>>> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>>>> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x60110), D_ALL);
>>>>> + MMIO_D(_MMIO(0x61110), D_ALL);
>>>>> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>>>> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>>>> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPLL_CTL, D_ALL);
>>>>> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>>>> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>>>> + MMIO_D(_MMIO(0x46508), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x49080), D_ALL);
>>>>> + MMIO_D(_MMIO(0x49180), D_ALL);
>>>>> + MMIO_D(_MMIO(0x49280), D_ALL);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>>>> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>>>> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>>>> + MMIO_D(SBI_ADDR, D_ALL);
>>>>> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>>>> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>>>> + MMIO_D(PIXCLK_GATE, D_ALL);
>>>>> +
>>>>> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>>>> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>>>> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>>>> +
>>>>> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>>>> + MMIO_D(FORCEWAKE_ACK, D_ALL);
>>>>> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>>>> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>>>> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>>>> + MMIO_D(ECOBUS, D_ALL);
>>>>> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>>>> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>>>> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>>>> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>>>> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>>>> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>>>> + MMIO_D(GEN6_RPSTAT1, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>>>> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>>>> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>>>> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>>>> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>>>> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>>>> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>>>> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>>>> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>>>> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>>>> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>>>> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_D(RSTDBYCTL, D_ALL);
>>>>> +
>>>>> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>>>> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>>>> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>>>> +
>>>>> + MMIO_D(TILECTL, D_ALL);
>>>>> +
>>>>> + MMIO_D(GEN6_UCGCTL1, D_ALL);
>>>>> + MMIO_D(GEN6_UCGCTL2, D_ALL);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>>>> + MMIO_D(_MMIO(0x13812c), D_ALL);
>>>>> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>>>> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>>>> + MMIO_D(HSW_IDICR, D_ALL);
>>>>> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x3c), D_ALL);
>>>>> + MMIO_D(_MMIO(0x860), D_ALL);
>>>>> + MMIO_D(ECOSKPD, D_ALL);
>>>>> + MMIO_D(_MMIO(0x121d0), D_ALL);
>>>>> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>>>> + MMIO_D(_MMIO(0x41d0), D_ALL);
>>>>> + MMIO_D(GAC_ECO_BITS, D_ALL);
>>>>> + MMIO_D(_MMIO(0x6200), D_ALL);
>>>>> + MMIO_D(_MMIO(0x6204), D_ALL);
>>>>> + MMIO_D(_MMIO(0x6208), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7118), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7180), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7408), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7c00), D_ALL);
>>>>> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>>>> + MMIO_D(_MMIO(0x911c), D_ALL);
>>>>> + MMIO_D(_MMIO(0x9120), D_ALL);
>>>>> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GAB_CTL, D_ALL);
>>>>> + MMIO_D(_MMIO(0x48800), D_ALL);
>>>>> + MMIO_D(_MMIO(0xce044), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6500), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6504), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6600), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6604), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6700), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6704), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6800), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6804), D_ALL);
>>>>> + MMIO_D(PCH_GMBUS4, D_ALL);
>>>>> + MMIO_D(PCH_GMBUS5, D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x902c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc810), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc81c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc828), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc834), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc00), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc24), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd000), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd00c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd018), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd024), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd034), D_ALL);
>>>>> +
>>>>> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>>>> + MMIO_D(_MMIO(0x2054), D_ALL);
>>>>> + MMIO_D(_MMIO(0x12054), D_ALL);
>>>>> + MMIO_D(_MMIO(0x22054), D_ALL);
>>>>> + MMIO_D(_MMIO(0x1a054), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x44070), D_ALL);
>>>>> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>>>> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_master_irq_handler);
>>>>> +
>>>>> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>>>> + mmio_read_from_hw, NULL);
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0xd0)
>>>>> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>>>> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>>>> + ring_reset_ctl_write);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x230)
>>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x234)
>>>>> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>>>> + NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x244)
>>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x370)
>>>>> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x3a0)
>>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>>>> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>>>> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>>>> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>>>> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>>>> +
>>>>> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>>>> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x270)
>>>>> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>>>> +
>>>>> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(WM_MISC, D_BDW);
>>>>> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>>>> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>>>> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>>>> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_D(_MMIO(0xb110), D_BDW);
>>>>> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>>>> + D_BDW_PLUS, NULL, force_nonpriv_write);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>>>> +
>>>>> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>>>> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>>>> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>>>> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>>>> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>>>> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>>>> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>>>> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>>>> +
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> +
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> +
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> +
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>>>> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>>>> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>>>> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> + NULL, NULL);
>>>>> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>>>> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>>>> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + /* TRTT */
>>>>> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>>>> + NULL, gen9_trtte_write);
>>>>> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>>>> + NULL, gen9_trtt_chicken_write);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>>>> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>>>> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>>>> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>>>> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, csfe_chicken1_mmio_write);
>>>>> +#undef CSFE_CHICKEN1_REG
>>>>> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>>>> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>>>> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>>>> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>>>> + MMIO_D(ERROR_GEN6, D_BXT);
>>>>> + MMIO_D(DONE_REG, D_BXT);
>>>>> + MMIO_D(EIR, D_BXT);
>>>>> + MMIO_D(PGTBL_ER, D_BXT);
>>>>> + MMIO_D(_MMIO(0x4194), D_BXT);
>>>>> + MMIO_D(_MMIO(0x4294), D_BXT);
>>>>> + MMIO_D(_MMIO(0x4494), D_BXT);
>>>>> +
>>>>> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>>>> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>>>> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>>>> + MMIO_RING_D(RING_IPEHR, D_BXT);
>>>>> + MMIO_RING_D(RING_INSTPS, D_BXT);
>>>>> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>>>> + MMIO_RING_D(RING_BBSTATE, D_BXT);
>>>>> + MMIO_RING_D(RING_IPEIR, D_BXT);
>>>>> +
>>>>> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>>>> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>>>> + NULL, bxt_phy_ctl_family_write);
>>>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>>>> + NULL, bxt_phy_ctl_family_write);
>>>>> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>>>> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>>>> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>>>> + NULL, bxt_port_pll_enable_write);
>>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>>>> + NULL, bxt_port_pll_enable_write);
>>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>>>> + bxt_port_pll_enable_write);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> + bxt_port_tx_dw3_read, NULL);
>>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> + bxt_port_tx_dw3_read, NULL);
>>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> + bxt_port_tx_dw3_read, NULL);
>>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>>>> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>>>> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>>>> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>>>> +
>>>>> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>>>> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>>>> +
>>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>>>> +
>>>>> + MMIO_D(RC6_CTX_BASE, D_BXT);
>>>>> +
>>>>> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>>>> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>>>> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>>>> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>>>> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *i915 = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + ret = intel_gvt_init_generic_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> +
>>>>> + if (IS_BROADWELL(i915)) {
>>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + } else if (IS_SKYLAKE(i915) ||
>>>>> + IS_KABYLAKE(i915) ||
>>>>> + IS_COFFEELAKE(i915) ||
>>>>> + IS_COMETLAKE(i915)) {
>>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + } else if (IS_BROXTON(i915)) {
>>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + ret = intel_gvt_init_bxt_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +#endif
>>>>> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
>>>>> index 244cc7320b54..05bd2f8e9d94 100644
>>>>> --- a/drivers/gpu/drm/i915/gvt/reg.h
>>>>> +++ b/drivers/gpu/drm/i915/gvt/reg.h
>>>>> @@ -133,6 +133,12 @@
>>>>> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
>>>>> #define VF_GUARDBAND _MMIO(0x83a4)
>>>>>
>>>>> +/* XXX FIXME i915 has changed PP_XXX definition */
>>>>> +#define PCH_PP_STATUS _MMIO(0xc7200)
>>>>> +#define PCH_PP_CONTROL _MMIO(0xc7204)
>>>>> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>>>> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>>>> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>>>
>>>>> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
>>>>> #endif
>>>>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
>>>>> index 4e70c1a9ef2e..64846d9bff0b 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_gvt.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
>>>>> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>>>>> dev_priv->params.enable_gvt = 0;
>>>>> }
>>>>>
>>>>> +#define GENERATE_MMIO_TABLE_IN_I915
>>>>> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
>>>>> +{
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +#include "gvt/reg.h"
>>>>> +#include "gvt/mmio_table.h"
>>>>> +#undef GENERATE_MMIO_TABLE_IN_I915
>>>>> +
>>>>> +
>>>>> /**
>>>>> * intel_gvt_init - initialize GVT components
>>>>> * @dev_priv: drm i915 private data
>>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
> ---end quoted text---
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 10:51 ` Wang, Zhi A
0 siblings, 0 replies; 35+ messages in thread
From: Wang, Zhi A @ 2021-11-09 10:51 UTC (permalink / raw)
To: hch, Jani Nikula
Cc: Zhi Wang, intel-gfx, linux-kernel, dri-devel, jgg, intel-gvt-dev
On 11/9/2021 12:36 PM, hch@lst.de wrote:
> On Tue, Nov 09, 2021 at 12:20:24PM +0200, Jani Nikula wrote:
>> Having the functions defined in a single .c file and called (perhaps via
>> just one or two entry points) sounds much better than including code.
>>
>> Perhaps you could pass in the function to call (new_mmio_info) as a
>> parameter in different situations instead of macro magic, to make the
>> code more readable?
>>
>> Basically I want more clarity in the interfaces between the compilation
>> units everywhere in i915.
> So as far as a I can tell the table is used for a few things:
>
> 1) to store the golden state, this is a plain array of u32
> 2) to attach special write (and sometimes read) handlers, and have
> a mask for read-only fields even for writable registers
> 3) to show the difference between the real and virtual registers in
> debugfs
> 4) to restore some registers on pm resume
>
> Can we somehow handle 3 and 4 with the table built for 1?
>
> In that case we only need special handling in the GVT for the registers
> that are overriden, which is a tiny subset and this avoids the giant
> duplication.
That sounds the idea I purposed in the previous reply for Jani. Let me
try to cook the patch with this idea.
> Btw, the mmio_info_table hash is only used to iterate over all entries,
> which is a strange use for a hash. It might make sense to replace it
> with a more suitable data structure and/or actually make use of the
> hash in intel_gvt_find_mmio_info.
Can you elaborate more about this? We need the hash query from the table
ASAP when the hypervisor trapped a mmio access. It's a critical path and
we tried different data structure in the kernel and the hash table gives
the best performance.
>>
>> BR,
>> Jani.
>>
>>
>>> Thanks,
>>>
>>> Zhi.
>>>
>>>> BR,
>>>> Jani.
>>>>
>>>>
>>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
>>>>> Cc: Zhi Wang <zhi.a.wang@intel.com>
>>>>> Cc: Christoph Hellwig <hch@lst.de>
>>>>> Cc: Jason Gunthorpe <jgg@nvidia.com>
>>>>> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
>>>>> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
>>>>> drivers/gpu/drm/i915/gvt/reg.h | 6 +
>>>>> drivers/gpu/drm/i915/intel_gvt.c | 11 +
>>>>> 4 files changed, 1592 insertions(+), 1534 deletions(-)
>>>>> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>>>>> index cde0a477fb49..6a08d362bf66 100644
>>>>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>>>>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>>>>> @@ -41,13 +41,6 @@
>>>>> #include "i915_pvinfo.h"
>>>>> #include "display/intel_display_types.h"
>>>>>
>>>>> -/* XXX FIXME i915 has changed PP_XXX definition */
>>>>> -#define PCH_PP_STATUS _MMIO(0xc7200)
>>>>> -#define PCH_PP_CONTROL _MMIO(0xc7204)
>>>>> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>>>> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>>>> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>>> -
>>>>> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
>>>>> {
>>>>> struct drm_i915_private *i915 = gvt->gt->i915;
>>>>> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
>>>>> return 0;
>>>>> }
>>>>>
>>>>> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>>> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>>>> - f, s, am, rm, d, r, w); \
>>>>> - if (ret) \
>>>>> - return ret; \
>>>>> -} while (0)
>>>>> -
>>>>> -#define MMIO_D(reg, d) \
>>>>> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>>>> -
>>>>> -#define MMIO_DH(reg, d, r, w) \
>>>>> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_DFH(reg, d, f, r, w) \
>>>>> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_GM(reg, d, r, w) \
>>>>> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_GM_RDR(reg, d, r, w) \
>>>>> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RO(reg, d, f, rm, r, w) \
>>>>> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>>>> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - if (HAS_ENGINE(gvt->gt, VCS1)) \
>>>>> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> -} while (0)
>>>>> -
>>>>> -#define MMIO_RING_D(prefix, d) \
>>>>> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>>>> -
>>>>> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_GM(prefix, d, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>>>> -
>>>>> -static int init_generic_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> -
>>>>> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(SDEISR, D_ALL);
>>>>> -
>>>>> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>>>> -
>>>>> -
>>>>> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>>>> - gamw_echo_dev_rw_ia_write);
>>>>> -
>>>>> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x28)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x134)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x6c)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> -#undef RING_REG
>>>>> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>>>> -
>>>>> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>>>> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>>>> -
>>>>> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>>>> -
>>>>> - /* RING MODE */
>>>>> -#define RING_REG(base) _MMIO((base) + 0x29c)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL,
>>>>> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>>>> - ring_mode_mmio_write);
>>>>> -#undef RING_REG
>>>>> -
>>>>> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>>>> - mmio_read_from_hw, NULL);
>>>>> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>>>> - mmio_read_from_hw, NULL);
>>>>> -
>>>>> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - /* display */
>>>>> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_D(_MMIO(0x602a0), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x65050), D_ALL);
>>>>> - MMIO_D(_MMIO(0x650b4), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0xc4040), D_ALL);
>>>>> - MMIO_D(DERRMR, D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>>>> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>>>> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>>>> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>>>> -
>>>>> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>>>> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>>>> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(CURPOS(PIPE_A), D_ALL);
>>>>> - MMIO_D(CURPOS(PIPE_B), D_ALL);
>>>>> - MMIO_D(CURPOS(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(CURBASE(PIPE_A), D_ALL);
>>>>> - MMIO_D(CURBASE(PIPE_B), D_ALL);
>>>>> - MMIO_D(CURBASE(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x700ac), D_ALL);
>>>>> - MMIO_D(_MMIO(0x710ac), D_ALL);
>>>>> - MMIO_D(_MMIO(0x720ac), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x70090), D_ALL);
>>>>> - MMIO_D(_MMIO(0x70094), D_ALL);
>>>>> - MMIO_D(_MMIO(0x70098), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7009c), D_ALL);
>>>>> -
>>>>> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>>>> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>>>> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>>>> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>>>> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>>>> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>>>> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>>>> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>>>> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>>>> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>>>> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>>>> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>>>> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>>>> - MMIO_D(WM1_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM2_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM3_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM1S_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM2S_LP_IVB, D_ALL);
>>>>> - MMIO_D(WM3S_LP_IVB, D_ALL);
>>>>> -
>>>>> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>>>> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>>>> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>>>> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x48268), D_ALL);
>>>>> -
>>>>> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>>>> - gmbus_mmio_write);
>>>>> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>>>> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>>>> -
>>>>> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>>>> -
>>>>> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>>>> -
>>>>> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>>>> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>>>> - MMIO_D(PCH_PP_STATUS, D_ALL);
>>>>> - MMIO_D(PCH_LVDS, D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>>>> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>>>> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>>>> - MMIO_D(PCH_DPLL_SEL, D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x61208), D_ALL);
>>>>> - MMIO_D(_MMIO(0x6120c), D_ALL);
>>>>> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>>>> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> -
>>>>> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>>>> - PORTA_HOTPLUG_STATUS_MASK
>>>>> - | PORTB_HOTPLUG_STATUS_MASK
>>>>> - | PORTC_HOTPLUG_STATUS_MASK
>>>>> - | PORTD_HOTPLUG_STATUS_MASK,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>>>> - MMIO_D(FUSE_STRAP, D_ALL);
>>>>> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>>>> -
>>>>> - MMIO_D(DISP_ARB_CTL, D_ALL);
>>>>> - MMIO_D(DISP_ARB_CTL2, D_ALL);
>>>>> -
>>>>> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>>>> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>>>> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>>>> -
>>>>> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>>>> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>>>> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>>>> -
>>>>> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>>>> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>>>> -
>>>>> - MMIO_D(IPS_CTL, D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>>>> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>>>> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>>>> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x60110), D_ALL);
>>>>> - MMIO_D(_MMIO(0x61110), D_ALL);
>>>>> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>>>> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>>>> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPLL_CTL, D_ALL);
>>>>> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>>>> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>>>> - MMIO_D(_MMIO(0x46508), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x49080), D_ALL);
>>>>> - MMIO_D(_MMIO(0x49180), D_ALL);
>>>>> - MMIO_D(_MMIO(0x49280), D_ALL);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>>>> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>>>> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>>>> - MMIO_D(SBI_ADDR, D_ALL);
>>>>> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>>>> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>>>> - MMIO_D(PIXCLK_GATE, D_ALL);
>>>>> -
>>>>> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>>>> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>>>> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>>>> -
>>>>> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>>>> - MMIO_D(FORCEWAKE_ACK, D_ALL);
>>>>> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>>>> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>>>> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>>>> - MMIO_D(ECOBUS, D_ALL);
>>>>> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>>>> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>>>> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>>>> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>>>> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>>>> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>>>> - MMIO_D(GEN6_RPSTAT1, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>>>> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>>>> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>>>> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>>>> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>>>> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>>>> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>>>> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>>>> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>>>> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>>>> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>>>> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_D(RSTDBYCTL, D_ALL);
>>>>> -
>>>>> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>>>> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>>>> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>>>> -
>>>>> - MMIO_D(TILECTL, D_ALL);
>>>>> -
>>>>> - MMIO_D(GEN6_UCGCTL1, D_ALL);
>>>>> - MMIO_D(GEN6_UCGCTL2, D_ALL);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>>>> - MMIO_D(_MMIO(0x13812c), D_ALL);
>>>>> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>>>> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>>>> - MMIO_D(HSW_IDICR, D_ALL);
>>>>> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x3c), D_ALL);
>>>>> - MMIO_D(_MMIO(0x860), D_ALL);
>>>>> - MMIO_D(ECOSKPD, D_ALL);
>>>>> - MMIO_D(_MMIO(0x121d0), D_ALL);
>>>>> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>>>> - MMIO_D(_MMIO(0x41d0), D_ALL);
>>>>> - MMIO_D(GAC_ECO_BITS, D_ALL);
>>>>> - MMIO_D(_MMIO(0x6200), D_ALL);
>>>>> - MMIO_D(_MMIO(0x6204), D_ALL);
>>>>> - MMIO_D(_MMIO(0x6208), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7118), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7180), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7408), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7c00), D_ALL);
>>>>> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>>>> - MMIO_D(_MMIO(0x911c), D_ALL);
>>>>> - MMIO_D(_MMIO(0x9120), D_ALL);
>>>>> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GAB_CTL, D_ALL);
>>>>> - MMIO_D(_MMIO(0x48800), D_ALL);
>>>>> - MMIO_D(_MMIO(0xce044), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6500), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6504), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6600), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6604), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6700), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6704), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6800), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6804), D_ALL);
>>>>> - MMIO_D(PCH_GMBUS4, D_ALL);
>>>>> - MMIO_D(PCH_GMBUS5, D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x902c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc810), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc81c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc828), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc834), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc00), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc24), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd000), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd00c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd018), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd024), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd034), D_ALL);
>>>>> -
>>>>> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>>>> - MMIO_D(_MMIO(0x2054), D_ALL);
>>>>> - MMIO_D(_MMIO(0x12054), D_ALL);
>>>>> - MMIO_D(_MMIO(0x22054), D_ALL);
>>>>> - MMIO_D(_MMIO(0x1a054), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x44070), D_ALL);
>>>>> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>>>> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>>>> -
>>>>> - return 0;
>>>>> -}
>>>>> -
>>>>> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_master_irq_handler);
>>>>> -
>>>>> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>>>> - mmio_read_from_hw, NULL);
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0xd0)
>>>>> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>>>> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>>>> - ring_reset_ctl_write);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x230)
>>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x234)
>>>>> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>>>> - NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x244)
>>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x370)
>>>>> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x3a0)
>>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>>>> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>>>> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>>>> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>>>> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>>>> -
>>>>> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>>>> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x270)
>>>>> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>>>> -
>>>>> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(WM_MISC, D_BDW);
>>>>> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>>>> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>>>> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>>>> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_D(_MMIO(0xb110), D_BDW);
>>>>> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>>>> - D_BDW_PLUS, NULL, force_nonpriv_write);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - return 0;
>>>>> -}
>>>>> -
>>>>> -static int init_skl_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>>>> -
>>>>> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>>>> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>>>> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>>>> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>>>> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>>>> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>>>> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>>>> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>>>> -
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> -
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> -
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> -
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>>>> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>>>> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>>>> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> - NULL, NULL);
>>>>> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>>>> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>>>> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - /* TRTT */
>>>>> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>>>> - NULL, gen9_trtte_write);
>>>>> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>>>> - NULL, gen9_trtt_chicken_write);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>>>> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>>>> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>>>> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>>>> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, csfe_chicken1_mmio_write);
>>>>> -#undef CSFE_CHICKEN1_REG
>>>>> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>>>> -
>>>>> - return 0;
>>>>> -}
>>>>> -
>>>>> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>>>> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>>>> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>>>> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>>>> - MMIO_D(ERROR_GEN6, D_BXT);
>>>>> - MMIO_D(DONE_REG, D_BXT);
>>>>> - MMIO_D(EIR, D_BXT);
>>>>> - MMIO_D(PGTBL_ER, D_BXT);
>>>>> - MMIO_D(_MMIO(0x4194), D_BXT);
>>>>> - MMIO_D(_MMIO(0x4294), D_BXT);
>>>>> - MMIO_D(_MMIO(0x4494), D_BXT);
>>>>> -
>>>>> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>>>> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>>>> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>>>> - MMIO_RING_D(RING_IPEHR, D_BXT);
>>>>> - MMIO_RING_D(RING_INSTPS, D_BXT);
>>>>> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>>>> - MMIO_RING_D(RING_BBSTATE, D_BXT);
>>>>> - MMIO_RING_D(RING_IPEIR, D_BXT);
>>>>> -
>>>>> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>>>> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>>>> - NULL, bxt_phy_ctl_family_write);
>>>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>>>> - NULL, bxt_phy_ctl_family_write);
>>>>> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>>>> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>>>> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>>>> - NULL, bxt_port_pll_enable_write);
>>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>>>> - NULL, bxt_port_pll_enable_write);
>>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>>>> - bxt_port_pll_enable_write);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> - bxt_port_tx_dw3_read, NULL);
>>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> - bxt_port_tx_dw3_read, NULL);
>>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> - bxt_port_tx_dw3_read, NULL);
>>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>>>> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>>>> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>>>> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>>>> -
>>>>> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>>>> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>>>> -
>>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>>>> -
>>>>> - MMIO_D(RC6_CTX_BASE, D_BXT);
>>>>> -
>>>>> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>>>> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>>>> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>>>> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>>>> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>>>> -
>>>>> - return 0;
>>>>> -}
>>>>> +#include "mmio_table.h"
>>>>>
>>>>> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
>>>>> unsigned int offset)
>>>>> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
>>>>> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>>>> {
>>>>> struct intel_gvt_device_info *info = &gvt->device_info;
>>>>> - struct drm_i915_private *i915 = gvt->gt->i915;
>>>>> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
>>>>> int ret;
>>>>>
>>>>> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>>>> if (!gvt->mmio.mmio_attribute)
>>>>> return -ENOMEM;
>>>>>
>>>>> - ret = init_generic_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> -
>>>>> - if (IS_BROADWELL(i915)) {
>>>>> - ret = init_bdw_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - } else if (IS_SKYLAKE(i915) ||
>>>>> - IS_KABYLAKE(i915) ||
>>>>> - IS_COFFEELAKE(i915) ||
>>>>> - IS_COMETLAKE(i915)) {
>>>>> - ret = init_bdw_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - ret = init_skl_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - } else if (IS_BROXTON(i915)) {
>>>>> - ret = init_bdw_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - ret = init_skl_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - ret = init_bxt_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> + ret = intel_gvt_init_mmio_info(gvt);
>>>>> + if (ret) {
>>>>> + intel_gvt_clean_mmio_info(gvt);
>>>>> + return ret;
>>>>> }
>>>>>
>>>>> gvt->mmio.mmio_block = mmio_blocks;
>>>>> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
>>>>>
>>>>> return 0;
>>>>> -err:
>>>>> - intel_gvt_clean_mmio_info(gvt);
>>>>> - return ret;
>>>>> }
>>>>>
>>>>> /**
>>>>> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>>>> new file mode 100644
>>>>> index 000000000000..39a4cb59695a
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>>>> @@ -0,0 +1,1570 @@
>>>>> +/*
>>>>> + * Copyright © 2021 Intel Corporation
>>>>> + *
>>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>>> + * copy of this software and associated documentation files (the "Software"),
>>>>> + * to deal in the Software without restriction, including without limitation
>>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>>> + * Software is furnished to do so, subject to the following conditions:
>>>>> + *
>>>>> + * The above copyright notice and this permission notice (including the next
>>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>>> + * Software.
>>>>> + *
>>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>>> + * IN THE SOFTWARE.
>>>>> + *
>>>>> + */
>>>>> +
>>>>> +#ifndef _GVT_MMIO_TABLE_H_
>>>>> +#define _GVT_MMIO_TABLE_H_
>>>>> +
>>>>> +#ifdef GENERATE_MMIO_TABLE_IN_I915
>>>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
>>>>> + if (ret) \
>>>>> + return ret; \
>>>>> +} while (0)
>>>>> +#else
>>>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>>>> + f, s, am, rm, d, r, w); \
>>>>> + if (ret) \
>>>>> + return ret; \
>>>>> +} while (0)
>>>>> +#endif
>>>>> +
>>>>> +#define MMIO_D(reg, d) \
>>>>> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>>>> +
>>>>> +#define MMIO_DH(reg, d, r, w) \
>>>>> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_DFH(reg, d, f, r, w) \
>>>>> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_GM(reg, d, r, w) \
>>>>> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_GM_RDR(reg, d, r, w) \
>>>>> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RO(reg, d, f, rm, r, w) \
>>>>> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>>>> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + if (HAS_ENGINE(gvt->gt, VCS1)) \
>>>>> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> +} while (0)
>>>>> +
>>>>> +#define MMIO_RING_D(prefix, d) \
>>>>> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>>>> +
>>>>> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_GM(prefix, d, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>>>> +
>>>>> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> +
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> +
>>>>> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(SDEISR, D_ALL);
>>>>> +
>>>>> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>>>> +
>>>>> +
>>>>> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>>>> + gamw_echo_dev_rw_ia_write);
>>>>> +
>>>>> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x28)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x134)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x6c)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> +#undef RING_REG
>>>>> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>>>> +
>>>>> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>>>> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>>>> +
>>>>> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>>>> +
>>>>> + /* RING MODE */
>>>>> +#define RING_REG(base) _MMIO((base) + 0x29c)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL,
>>>>> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>>>> + ring_mode_mmio_write);
>>>>> +#undef RING_REG
>>>>> +
>>>>> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>>>> + mmio_read_from_hw, NULL);
>>>>> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>>>> + mmio_read_from_hw, NULL);
>>>>> +
>>>>> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + /* display */
>>>>> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_D(_MMIO(0x602a0), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x65050), D_ALL);
>>>>> + MMIO_D(_MMIO(0x650b4), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0xc4040), D_ALL);
>>>>> + MMIO_D(DERRMR, D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>>>> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>>>> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>>>> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>>>> +
>>>>> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>>>> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>>>> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(CURPOS(PIPE_A), D_ALL);
>>>>> + MMIO_D(CURPOS(PIPE_B), D_ALL);
>>>>> + MMIO_D(CURPOS(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(CURBASE(PIPE_A), D_ALL);
>>>>> + MMIO_D(CURBASE(PIPE_B), D_ALL);
>>>>> + MMIO_D(CURBASE(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x700ac), D_ALL);
>>>>> + MMIO_D(_MMIO(0x710ac), D_ALL);
>>>>> + MMIO_D(_MMIO(0x720ac), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x70090), D_ALL);
>>>>> + MMIO_D(_MMIO(0x70094), D_ALL);
>>>>> + MMIO_D(_MMIO(0x70098), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7009c), D_ALL);
>>>>> +
>>>>> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>>>> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>>>> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>>>> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>>>> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>>>> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>>>> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>>>> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>>>> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>>>> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>>>> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>>>> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>>>> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>>>> + MMIO_D(WM1_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM2_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM3_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM1S_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM2S_LP_IVB, D_ALL);
>>>>> + MMIO_D(WM3S_LP_IVB, D_ALL);
>>>>> +
>>>>> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>>>> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>>>> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>>>> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x48268), D_ALL);
>>>>> +
>>>>> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>>>> + gmbus_mmio_write);
>>>>> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>>>> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>>>> +
>>>>> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>>>> +
>>>>> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>>>> +
>>>>> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>>>> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>>>> + MMIO_D(PCH_PP_STATUS, D_ALL);
>>>>> + MMIO_D(PCH_LVDS, D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>>>> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>>>> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>>>> + MMIO_D(PCH_DPLL_SEL, D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x61208), D_ALL);
>>>>> + MMIO_D(_MMIO(0x6120c), D_ALL);
>>>>> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>>>> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> +
>>>>> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>>>> + PORTA_HOTPLUG_STATUS_MASK
>>>>> + | PORTB_HOTPLUG_STATUS_MASK
>>>>> + | PORTC_HOTPLUG_STATUS_MASK
>>>>> + | PORTD_HOTPLUG_STATUS_MASK,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>>>> + MMIO_D(FUSE_STRAP, D_ALL);
>>>>> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>>>> +
>>>>> + MMIO_D(DISP_ARB_CTL, D_ALL);
>>>>> + MMIO_D(DISP_ARB_CTL2, D_ALL);
>>>>> +
>>>>> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>>>> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>>>> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>>>> +
>>>>> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>>>> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>>>> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>>>> +
>>>>> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>>>> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>>>> +
>>>>> + MMIO_D(IPS_CTL, D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>>>> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>>>> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>>>> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x60110), D_ALL);
>>>>> + MMIO_D(_MMIO(0x61110), D_ALL);
>>>>> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>>>> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>>>> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPLL_CTL, D_ALL);
>>>>> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>>>> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>>>> + MMIO_D(_MMIO(0x46508), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x49080), D_ALL);
>>>>> + MMIO_D(_MMIO(0x49180), D_ALL);
>>>>> + MMIO_D(_MMIO(0x49280), D_ALL);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>>>> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>>>> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>>>> + MMIO_D(SBI_ADDR, D_ALL);
>>>>> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>>>> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>>>> + MMIO_D(PIXCLK_GATE, D_ALL);
>>>>> +
>>>>> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>>>> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>>>> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>>>> +
>>>>> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>>>> + MMIO_D(FORCEWAKE_ACK, D_ALL);
>>>>> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>>>> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>>>> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>>>> + MMIO_D(ECOBUS, D_ALL);
>>>>> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>>>> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>>>> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>>>> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>>>> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>>>> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>>>> + MMIO_D(GEN6_RPSTAT1, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>>>> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>>>> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>>>> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>>>> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>>>> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>>>> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>>>> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>>>> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>>>> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>>>> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>>>> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_D(RSTDBYCTL, D_ALL);
>>>>> +
>>>>> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>>>> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>>>> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>>>> +
>>>>> + MMIO_D(TILECTL, D_ALL);
>>>>> +
>>>>> + MMIO_D(GEN6_UCGCTL1, D_ALL);
>>>>> + MMIO_D(GEN6_UCGCTL2, D_ALL);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>>>> + MMIO_D(_MMIO(0x13812c), D_ALL);
>>>>> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>>>> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>>>> + MMIO_D(HSW_IDICR, D_ALL);
>>>>> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x3c), D_ALL);
>>>>> + MMIO_D(_MMIO(0x860), D_ALL);
>>>>> + MMIO_D(ECOSKPD, D_ALL);
>>>>> + MMIO_D(_MMIO(0x121d0), D_ALL);
>>>>> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>>>> + MMIO_D(_MMIO(0x41d0), D_ALL);
>>>>> + MMIO_D(GAC_ECO_BITS, D_ALL);
>>>>> + MMIO_D(_MMIO(0x6200), D_ALL);
>>>>> + MMIO_D(_MMIO(0x6204), D_ALL);
>>>>> + MMIO_D(_MMIO(0x6208), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7118), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7180), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7408), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7c00), D_ALL);
>>>>> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>>>> + MMIO_D(_MMIO(0x911c), D_ALL);
>>>>> + MMIO_D(_MMIO(0x9120), D_ALL);
>>>>> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GAB_CTL, D_ALL);
>>>>> + MMIO_D(_MMIO(0x48800), D_ALL);
>>>>> + MMIO_D(_MMIO(0xce044), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6500), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6504), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6600), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6604), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6700), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6704), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6800), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6804), D_ALL);
>>>>> + MMIO_D(PCH_GMBUS4, D_ALL);
>>>>> + MMIO_D(PCH_GMBUS5, D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x902c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc810), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc81c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc828), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc834), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc00), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc24), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd000), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd00c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd018), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd024), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd034), D_ALL);
>>>>> +
>>>>> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>>>> + MMIO_D(_MMIO(0x2054), D_ALL);
>>>>> + MMIO_D(_MMIO(0x12054), D_ALL);
>>>>> + MMIO_D(_MMIO(0x22054), D_ALL);
>>>>> + MMIO_D(_MMIO(0x1a054), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x44070), D_ALL);
>>>>> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>>>> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_master_irq_handler);
>>>>> +
>>>>> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>>>> + mmio_read_from_hw, NULL);
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0xd0)
>>>>> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>>>> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>>>> + ring_reset_ctl_write);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x230)
>>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x234)
>>>>> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>>>> + NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x244)
>>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x370)
>>>>> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x3a0)
>>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>>>> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>>>> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>>>> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>>>> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>>>> +
>>>>> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>>>> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x270)
>>>>> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>>>> +
>>>>> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(WM_MISC, D_BDW);
>>>>> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>>>> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>>>> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>>>> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_D(_MMIO(0xb110), D_BDW);
>>>>> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>>>> + D_BDW_PLUS, NULL, force_nonpriv_write);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>>>> +
>>>>> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>>>> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>>>> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>>>> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>>>> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>>>> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>>>> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>>>> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>>>> +
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> +
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> +
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> +
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>>>> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>>>> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>>>> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> + NULL, NULL);
>>>>> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>>>> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>>>> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + /* TRTT */
>>>>> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>>>> + NULL, gen9_trtte_write);
>>>>> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>>>> + NULL, gen9_trtt_chicken_write);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>>>> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>>>> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>>>> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>>>> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, csfe_chicken1_mmio_write);
>>>>> +#undef CSFE_CHICKEN1_REG
>>>>> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>>>> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>>>> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>>>> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>>>> + MMIO_D(ERROR_GEN6, D_BXT);
>>>>> + MMIO_D(DONE_REG, D_BXT);
>>>>> + MMIO_D(EIR, D_BXT);
>>>>> + MMIO_D(PGTBL_ER, D_BXT);
>>>>> + MMIO_D(_MMIO(0x4194), D_BXT);
>>>>> + MMIO_D(_MMIO(0x4294), D_BXT);
>>>>> + MMIO_D(_MMIO(0x4494), D_BXT);
>>>>> +
>>>>> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>>>> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>>>> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>>>> + MMIO_RING_D(RING_IPEHR, D_BXT);
>>>>> + MMIO_RING_D(RING_INSTPS, D_BXT);
>>>>> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>>>> + MMIO_RING_D(RING_BBSTATE, D_BXT);
>>>>> + MMIO_RING_D(RING_IPEIR, D_BXT);
>>>>> +
>>>>> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>>>> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>>>> + NULL, bxt_phy_ctl_family_write);
>>>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>>>> + NULL, bxt_phy_ctl_family_write);
>>>>> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>>>> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>>>> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>>>> + NULL, bxt_port_pll_enable_write);
>>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>>>> + NULL, bxt_port_pll_enable_write);
>>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>>>> + bxt_port_pll_enable_write);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> + bxt_port_tx_dw3_read, NULL);
>>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> + bxt_port_tx_dw3_read, NULL);
>>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> + bxt_port_tx_dw3_read, NULL);
>>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>>>> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>>>> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>>>> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>>>> +
>>>>> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>>>> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>>>> +
>>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>>>> +
>>>>> + MMIO_D(RC6_CTX_BASE, D_BXT);
>>>>> +
>>>>> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>>>> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>>>> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>>>> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>>>> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *i915 = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + ret = intel_gvt_init_generic_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> +
>>>>> + if (IS_BROADWELL(i915)) {
>>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + } else if (IS_SKYLAKE(i915) ||
>>>>> + IS_KABYLAKE(i915) ||
>>>>> + IS_COFFEELAKE(i915) ||
>>>>> + IS_COMETLAKE(i915)) {
>>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + } else if (IS_BROXTON(i915)) {
>>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + ret = intel_gvt_init_bxt_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +#endif
>>>>> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
>>>>> index 244cc7320b54..05bd2f8e9d94 100644
>>>>> --- a/drivers/gpu/drm/i915/gvt/reg.h
>>>>> +++ b/drivers/gpu/drm/i915/gvt/reg.h
>>>>> @@ -133,6 +133,12 @@
>>>>> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
>>>>> #define VF_GUARDBAND _MMIO(0x83a4)
>>>>>
>>>>> +/* XXX FIXME i915 has changed PP_XXX definition */
>>>>> +#define PCH_PP_STATUS _MMIO(0xc7200)
>>>>> +#define PCH_PP_CONTROL _MMIO(0xc7204)
>>>>> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>>>> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>>>> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>>>
>>>>> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
>>>>> #endif
>>>>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
>>>>> index 4e70c1a9ef2e..64846d9bff0b 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_gvt.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
>>>>> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>>>>> dev_priv->params.enable_gvt = 0;
>>>>> }
>>>>>
>>>>> +#define GENERATE_MMIO_TABLE_IN_I915
>>>>> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
>>>>> +{
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +#include "gvt/reg.h"
>>>>> +#include "gvt/mmio_table.h"
>>>>> +#undef GENERATE_MMIO_TABLE_IN_I915
>>>>> +
>>>>> +
>>>>> /**
>>>>> * intel_gvt_init - initialize GVT components
>>>>> * @dev_priv: drm i915 private data
>>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
> ---end quoted text---
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 10:51 ` Wang, Zhi A
0 siblings, 0 replies; 35+ messages in thread
From: Wang, Zhi A @ 2021-11-09 10:51 UTC (permalink / raw)
To: hch, Jani Nikula
Cc: Zhi Wang, intel-gfx, linux-kernel, dri-devel, jgg, Vivi, Rodrigo,
intel-gvt-dev
On 11/9/2021 12:36 PM, hch@lst.de wrote:
> On Tue, Nov 09, 2021 at 12:20:24PM +0200, Jani Nikula wrote:
>> Having the functions defined in a single .c file and called (perhaps via
>> just one or two entry points) sounds much better than including code.
>>
>> Perhaps you could pass in the function to call (new_mmio_info) as a
>> parameter in different situations instead of macro magic, to make the
>> code more readable?
>>
>> Basically I want more clarity in the interfaces between the compilation
>> units everywhere in i915.
> So as far as a I can tell the table is used for a few things:
>
> 1) to store the golden state, this is a plain array of u32
> 2) to attach special write (and sometimes read) handlers, and have
> a mask for read-only fields even for writable registers
> 3) to show the difference between the real and virtual registers in
> debugfs
> 4) to restore some registers on pm resume
>
> Can we somehow handle 3 and 4 with the table built for 1?
>
> In that case we only need special handling in the GVT for the registers
> that are overriden, which is a tiny subset and this avoids the giant
> duplication.
That sounds the idea I purposed in the previous reply for Jani. Let me
try to cook the patch with this idea.
> Btw, the mmio_info_table hash is only used to iterate over all entries,
> which is a strange use for a hash. It might make sense to replace it
> with a more suitable data structure and/or actually make use of the
> hash in intel_gvt_find_mmio_info.
Can you elaborate more about this? We need the hash query from the table
ASAP when the hypervisor trapped a mmio access. It's a critical path and
we tried different data structure in the kernel and the hash table gives
the best performance.
>>
>> BR,
>> Jani.
>>
>>
>>> Thanks,
>>>
>>> Zhi.
>>>
>>>> BR,
>>>> Jani.
>>>>
>>>>
>>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
>>>>> Cc: Zhi Wang <zhi.a.wang@intel.com>
>>>>> Cc: Christoph Hellwig <hch@lst.de>
>>>>> Cc: Jason Gunthorpe <jgg@nvidia.com>
>>>>> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
>>>>> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
>>>>> drivers/gpu/drm/i915/gvt/reg.h | 6 +
>>>>> drivers/gpu/drm/i915/intel_gvt.c | 11 +
>>>>> 4 files changed, 1592 insertions(+), 1534 deletions(-)
>>>>> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>>>>> index cde0a477fb49..6a08d362bf66 100644
>>>>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>>>>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>>>>> @@ -41,13 +41,6 @@
>>>>> #include "i915_pvinfo.h"
>>>>> #include "display/intel_display_types.h"
>>>>>
>>>>> -/* XXX FIXME i915 has changed PP_XXX definition */
>>>>> -#define PCH_PP_STATUS _MMIO(0xc7200)
>>>>> -#define PCH_PP_CONTROL _MMIO(0xc7204)
>>>>> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>>>> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>>>> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>>> -
>>>>> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
>>>>> {
>>>>> struct drm_i915_private *i915 = gvt->gt->i915;
>>>>> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
>>>>> return 0;
>>>>> }
>>>>>
>>>>> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>>> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>>>> - f, s, am, rm, d, r, w); \
>>>>> - if (ret) \
>>>>> - return ret; \
>>>>> -} while (0)
>>>>> -
>>>>> -#define MMIO_D(reg, d) \
>>>>> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>>>> -
>>>>> -#define MMIO_DH(reg, d, r, w) \
>>>>> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_DFH(reg, d, f, r, w) \
>>>>> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_GM(reg, d, r, w) \
>>>>> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_GM_RDR(reg, d, r, w) \
>>>>> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RO(reg, d, f, rm, r, w) \
>>>>> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>>>> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> - if (HAS_ENGINE(gvt->gt, VCS1)) \
>>>>> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> -} while (0)
>>>>> -
>>>>> -#define MMIO_RING_D(prefix, d) \
>>>>> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>>>> -
>>>>> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_GM(prefix, d, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>>>> -
>>>>> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>>>> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>>>> -
>>>>> -static int init_generic_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> -
>>>>> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(SDEISR, D_ALL);
>>>>> -
>>>>> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>>>> -
>>>>> -
>>>>> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>>>> - gamw_echo_dev_rw_ia_write);
>>>>> -
>>>>> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x28)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x134)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x6c)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> -#undef RING_REG
>>>>> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>>>> -
>>>>> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>>>> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>>>> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>>>> -
>>>>> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>>>> -
>>>>> - /* RING MODE */
>>>>> -#define RING_REG(base) _MMIO((base) + 0x29c)
>>>>> - MMIO_RING_DFH(RING_REG, D_ALL,
>>>>> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>>>> - ring_mode_mmio_write);
>>>>> -#undef RING_REG
>>>>> -
>>>>> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>>>> - mmio_read_from_hw, NULL);
>>>>> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>>>> - mmio_read_from_hw, NULL);
>>>>> -
>>>>> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - /* display */
>>>>> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_D(_MMIO(0x602a0), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x65050), D_ALL);
>>>>> - MMIO_D(_MMIO(0x650b4), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0xc4040), D_ALL);
>>>>> - MMIO_D(DERRMR, D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>>>> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>>>> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>>>> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>>>> -
>>>>> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>>>> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>>>> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(CURPOS(PIPE_A), D_ALL);
>>>>> - MMIO_D(CURPOS(PIPE_B), D_ALL);
>>>>> - MMIO_D(CURPOS(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(CURBASE(PIPE_A), D_ALL);
>>>>> - MMIO_D(CURBASE(PIPE_B), D_ALL);
>>>>> - MMIO_D(CURBASE(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x700ac), D_ALL);
>>>>> - MMIO_D(_MMIO(0x710ac), D_ALL);
>>>>> - MMIO_D(_MMIO(0x720ac), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x70090), D_ALL);
>>>>> - MMIO_D(_MMIO(0x70094), D_ALL);
>>>>> - MMIO_D(_MMIO(0x70098), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7009c), D_ALL);
>>>>> -
>>>>> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>>>> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>>>> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>>>> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>>>> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>>>> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>>>> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>>>> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>>>> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>>>> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>>>> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>>>> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>>>> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>>>> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>>>> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>>>> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>>>> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>>>> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>>>> - reg50080_mmio_write);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>>>> -
>>>>> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>>>> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>>>> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>>>> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>>>> - MMIO_D(WM1_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM2_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM3_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM1S_LP_ILK, D_ALL);
>>>>> - MMIO_D(WM2S_LP_IVB, D_ALL);
>>>>> - MMIO_D(WM3S_LP_IVB, D_ALL);
>>>>> -
>>>>> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>>>> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>>>> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>>>> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x48268), D_ALL);
>>>>> -
>>>>> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>>>> - gmbus_mmio_write);
>>>>> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>>>> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>>>> -
>>>>> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>>>> -
>>>>> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>>>> -
>>>>> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>>>> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>>>> - MMIO_D(PCH_PP_STATUS, D_ALL);
>>>>> - MMIO_D(PCH_LVDS, D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>>>> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>>>> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>>>> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>>>> - MMIO_D(PCH_DPLL_SEL, D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x61208), D_ALL);
>>>>> - MMIO_D(_MMIO(0x6120c), D_ALL);
>>>>> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>>>> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> -
>>>>> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>>>> - PORTA_HOTPLUG_STATUS_MASK
>>>>> - | PORTB_HOTPLUG_STATUS_MASK
>>>>> - | PORTC_HOTPLUG_STATUS_MASK
>>>>> - | PORTD_HOTPLUG_STATUS_MASK,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>>>> - MMIO_D(FUSE_STRAP, D_ALL);
>>>>> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>>>> -
>>>>> - MMIO_D(DISP_ARB_CTL, D_ALL);
>>>>> - MMIO_D(DISP_ARB_CTL2, D_ALL);
>>>>> -
>>>>> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>>>> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>>>> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>>>> -
>>>>> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>>>> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>>>> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>>>> -
>>>>> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>>>> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>>>> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>>>> -
>>>>> - MMIO_D(IPS_CTL, D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>>>> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>>>> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>>>> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x60110), D_ALL);
>>>>> - MMIO_D(_MMIO(0x61110), D_ALL);
>>>>> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>>>> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>>>> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>>>> - MMIO_D(SPLL_CTL, D_ALL);
>>>>> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>>>> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>>>> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>>>> - MMIO_D(_MMIO(0x46508), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x49080), D_ALL);
>>>>> - MMIO_D(_MMIO(0x49180), D_ALL);
>>>>> - MMIO_D(_MMIO(0x49280), D_ALL);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>>>> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>>>> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>>>> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>>>> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>>>> -
>>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>>>> -
>>>>> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>>>> - MMIO_D(SBI_ADDR, D_ALL);
>>>>> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>>>> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>>>> - MMIO_D(PIXCLK_GATE, D_ALL);
>>>>> -
>>>>> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>>>> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>>>> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>>>> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>>>> -
>>>>> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>>>> - MMIO_D(FORCEWAKE_ACK, D_ALL);
>>>>> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>>>> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>>>> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>>>> - MMIO_D(ECOBUS, D_ALL);
>>>>> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>>>> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>>>> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>>>> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>>>> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>>>> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>>>> - MMIO_D(GEN6_RPSTAT1, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>>>> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>>>> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>>>> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>>>> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>>>> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>>>> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>>>> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>>>> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>>>> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>>>> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>>>> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>>>> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>>>> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_D(RSTDBYCTL, D_ALL);
>>>>> -
>>>>> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>>>> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>>>> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>>>> -
>>>>> - MMIO_D(TILECTL, D_ALL);
>>>>> -
>>>>> - MMIO_D(GEN6_UCGCTL1, D_ALL);
>>>>> - MMIO_D(GEN6_UCGCTL2, D_ALL);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>>>> - MMIO_D(_MMIO(0x13812c), D_ALL);
>>>>> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>>>> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>>>> - MMIO_D(HSW_IDICR, D_ALL);
>>>>> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x3c), D_ALL);
>>>>> - MMIO_D(_MMIO(0x860), D_ALL);
>>>>> - MMIO_D(ECOSKPD, D_ALL);
>>>>> - MMIO_D(_MMIO(0x121d0), D_ALL);
>>>>> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>>>> - MMIO_D(_MMIO(0x41d0), D_ALL);
>>>>> - MMIO_D(GAC_ECO_BITS, D_ALL);
>>>>> - MMIO_D(_MMIO(0x6200), D_ALL);
>>>>> - MMIO_D(_MMIO(0x6204), D_ALL);
>>>>> - MMIO_D(_MMIO(0x6208), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7118), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7180), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7408), D_ALL);
>>>>> - MMIO_D(_MMIO(0x7c00), D_ALL);
>>>>> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>>>> - MMIO_D(_MMIO(0x911c), D_ALL);
>>>>> - MMIO_D(_MMIO(0x9120), D_ALL);
>>>>> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GAB_CTL, D_ALL);
>>>>> - MMIO_D(_MMIO(0x48800), D_ALL);
>>>>> - MMIO_D(_MMIO(0xce044), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6500), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6504), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6600), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6604), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6700), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6704), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6800), D_ALL);
>>>>> - MMIO_D(_MMIO(0xe6804), D_ALL);
>>>>> - MMIO_D(PCH_GMBUS4, D_ALL);
>>>>> - MMIO_D(PCH_GMBUS5, D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x902c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc810), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc81c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc828), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfc834), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc00), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc18), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfcc24), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd000), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd00c), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd018), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd024), D_ALL);
>>>>> - MMIO_D(_MMIO(0xfd034), D_ALL);
>>>>> -
>>>>> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>>>> - MMIO_D(_MMIO(0x2054), D_ALL);
>>>>> - MMIO_D(_MMIO(0x12054), D_ALL);
>>>>> - MMIO_D(_MMIO(0x22054), D_ALL);
>>>>> - MMIO_D(_MMIO(0x1a054), D_ALL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x44070), D_ALL);
>>>>> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>>>> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>>>> -
>>>>> - return 0;
>>>>> -}
>>>>> -
>>>>> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>>>> - intel_vgpu_reg_master_irq_handler);
>>>>> -
>>>>> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>>>> - mmio_read_from_hw, NULL);
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0xd0)
>>>>> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>>>> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>>>> - ring_reset_ctl_write);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x230)
>>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x234)
>>>>> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>>>> - NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x244)
>>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x370)
>>>>> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x3a0)
>>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>>>> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>>>> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>>>> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>>>> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>>>> -
>>>>> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>>>> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>>>> -
>>>>> -#define RING_REG(base) _MMIO((base) + 0x270)
>>>>> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> -#undef RING_REG
>>>>> -
>>>>> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>>>> -
>>>>> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(WM_MISC, D_BDW);
>>>>> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>>>> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>>>> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>>>> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_D(_MMIO(0xb110), D_BDW);
>>>>> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>>>> - D_BDW_PLUS, NULL, force_nonpriv_write);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>>>> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - return 0;
>>>>> -}
>>>>> -
>>>>> -static int init_skl_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> - dp_aux_ch_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>>>> -
>>>>> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>>>> -
>>>>> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>>>> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>>>> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>>>> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>>>> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>>>> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>>>> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>>>> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>>>> -
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> -
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> -
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> -
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>>>> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>>>> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>>>> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> - NULL, NULL);
>>>>> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>>>> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>>>> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - /* TRTT */
>>>>> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>>>> - NULL, gen9_trtte_write);
>>>>> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>>>> - NULL, gen9_trtt_chicken_write);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>>>> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>>>> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>>>> -
>>>>> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>>>> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>>>> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, csfe_chicken1_mmio_write);
>>>>> -#undef CSFE_CHICKEN1_REG
>>>>> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> - NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>>>> -
>>>>> - return 0;
>>>>> -}
>>>>> -
>>>>> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
>>>>> -{
>>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> - int ret;
>>>>> -
>>>>> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> -
>>>>> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>>>> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>>>> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>>>> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>>>> - MMIO_D(ERROR_GEN6, D_BXT);
>>>>> - MMIO_D(DONE_REG, D_BXT);
>>>>> - MMIO_D(EIR, D_BXT);
>>>>> - MMIO_D(PGTBL_ER, D_BXT);
>>>>> - MMIO_D(_MMIO(0x4194), D_BXT);
>>>>> - MMIO_D(_MMIO(0x4294), D_BXT);
>>>>> - MMIO_D(_MMIO(0x4494), D_BXT);
>>>>> -
>>>>> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>>>> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>>>> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>>>> - MMIO_RING_D(RING_IPEHR, D_BXT);
>>>>> - MMIO_RING_D(RING_INSTPS, D_BXT);
>>>>> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>>>> - MMIO_RING_D(RING_BBSTATE, D_BXT);
>>>>> - MMIO_RING_D(RING_IPEIR, D_BXT);
>>>>> -
>>>>> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>>>> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>>>> - NULL, bxt_phy_ctl_family_write);
>>>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>>>> - NULL, bxt_phy_ctl_family_write);
>>>>> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>>>> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>>>> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>>>> - NULL, bxt_port_pll_enable_write);
>>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>>>> - NULL, bxt_port_pll_enable_write);
>>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>>>> - bxt_port_pll_enable_write);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> - bxt_port_tx_dw3_read, NULL);
>>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> - bxt_port_tx_dw3_read, NULL);
>>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> - bxt_port_tx_dw3_read, NULL);
>>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>>>> -
>>>>> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>>>> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>>>> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>>>> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>>>> -
>>>>> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>>>> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>>>> -
>>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>>>> -
>>>>> - MMIO_D(RC6_CTX_BASE, D_BXT);
>>>>> -
>>>>> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>>>> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>>>> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>>>> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>>>> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> - 0, 0, D_BXT, NULL, NULL);
>>>>> -
>>>>> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> -
>>>>> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>>>> -
>>>>> - return 0;
>>>>> -}
>>>>> +#include "mmio_table.h"
>>>>>
>>>>> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
>>>>> unsigned int offset)
>>>>> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
>>>>> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>>>> {
>>>>> struct intel_gvt_device_info *info = &gvt->device_info;
>>>>> - struct drm_i915_private *i915 = gvt->gt->i915;
>>>>> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
>>>>> int ret;
>>>>>
>>>>> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>>>> if (!gvt->mmio.mmio_attribute)
>>>>> return -ENOMEM;
>>>>>
>>>>> - ret = init_generic_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> -
>>>>> - if (IS_BROADWELL(i915)) {
>>>>> - ret = init_bdw_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - } else if (IS_SKYLAKE(i915) ||
>>>>> - IS_KABYLAKE(i915) ||
>>>>> - IS_COFFEELAKE(i915) ||
>>>>> - IS_COMETLAKE(i915)) {
>>>>> - ret = init_bdw_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - ret = init_skl_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - } else if (IS_BROXTON(i915)) {
>>>>> - ret = init_bdw_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - ret = init_skl_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> - ret = init_bxt_mmio_info(gvt);
>>>>> - if (ret)
>>>>> - goto err;
>>>>> + ret = intel_gvt_init_mmio_info(gvt);
>>>>> + if (ret) {
>>>>> + intel_gvt_clean_mmio_info(gvt);
>>>>> + return ret;
>>>>> }
>>>>>
>>>>> gvt->mmio.mmio_block = mmio_blocks;
>>>>> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
>>>>>
>>>>> return 0;
>>>>> -err:
>>>>> - intel_gvt_clean_mmio_info(gvt);
>>>>> - return ret;
>>>>> }
>>>>>
>>>>> /**
>>>>> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>>>> new file mode 100644
>>>>> index 000000000000..39a4cb59695a
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>>>> @@ -0,0 +1,1570 @@
>>>>> +/*
>>>>> + * Copyright © 2021 Intel Corporation
>>>>> + *
>>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>>> + * copy of this software and associated documentation files (the "Software"),
>>>>> + * to deal in the Software without restriction, including without limitation
>>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>>> + * Software is furnished to do so, subject to the following conditions:
>>>>> + *
>>>>> + * The above copyright notice and this permission notice (including the next
>>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>>> + * Software.
>>>>> + *
>>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>>> + * IN THE SOFTWARE.
>>>>> + *
>>>>> + */
>>>>> +
>>>>> +#ifndef _GVT_MMIO_TABLE_H_
>>>>> +#define _GVT_MMIO_TABLE_H_
>>>>> +
>>>>> +#ifdef GENERATE_MMIO_TABLE_IN_I915
>>>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
>>>>> + if (ret) \
>>>>> + return ret; \
>>>>> +} while (0)
>>>>> +#else
>>>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>>>> + f, s, am, rm, d, r, w); \
>>>>> + if (ret) \
>>>>> + return ret; \
>>>>> +} while (0)
>>>>> +#endif
>>>>> +
>>>>> +#define MMIO_D(reg, d) \
>>>>> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>>>> +
>>>>> +#define MMIO_DH(reg, d, r, w) \
>>>>> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_DFH(reg, d, f, r, w) \
>>>>> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_GM(reg, d, r, w) \
>>>>> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_GM_RDR(reg, d, r, w) \
>>>>> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RO(reg, d, f, rm, r, w) \
>>>>> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>>>> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> + if (HAS_ENGINE(gvt->gt, VCS1)) \
>>>>> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>>>> +} while (0)
>>>>> +
>>>>> +#define MMIO_RING_D(prefix, d) \
>>>>> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>>>> +
>>>>> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_GM(prefix, d, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>>>> +
>>>>> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>>>> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>>>> +
>>>>> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> +
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> +
>>>>> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(SDEISR, D_ALL);
>>>>> +
>>>>> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>>>> +
>>>>> +
>>>>> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>>>> + gamw_echo_dev_rw_ia_write);
>>>>> +
>>>>> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x28)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x134)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x6c)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> +#undef RING_REG
>>>>> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>>>> +
>>>>> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>>>> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>>>> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>>>> +
>>>>> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>>>> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>>>> +
>>>>> + /* RING MODE */
>>>>> +#define RING_REG(base) _MMIO((base) + 0x29c)
>>>>> + MMIO_RING_DFH(RING_REG, D_ALL,
>>>>> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>>>> + ring_mode_mmio_write);
>>>>> +#undef RING_REG
>>>>> +
>>>>> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>>>> + mmio_read_from_hw, NULL);
>>>>> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>>>> + mmio_read_from_hw, NULL);
>>>>> +
>>>>> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + /* display */
>>>>> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_D(_MMIO(0x602a0), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x65050), D_ALL);
>>>>> + MMIO_D(_MMIO(0x650b4), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0xc4040), D_ALL);
>>>>> + MMIO_D(DERRMR, D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>>>> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>>>> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>>>> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>>>> +
>>>>> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>>>> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>>>> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(CURPOS(PIPE_A), D_ALL);
>>>>> + MMIO_D(CURPOS(PIPE_B), D_ALL);
>>>>> + MMIO_D(CURPOS(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(CURBASE(PIPE_A), D_ALL);
>>>>> + MMIO_D(CURBASE(PIPE_B), D_ALL);
>>>>> + MMIO_D(CURBASE(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x700ac), D_ALL);
>>>>> + MMIO_D(_MMIO(0x710ac), D_ALL);
>>>>> + MMIO_D(_MMIO(0x720ac), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x70090), D_ALL);
>>>>> + MMIO_D(_MMIO(0x70094), D_ALL);
>>>>> + MMIO_D(_MMIO(0x70098), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7009c), D_ALL);
>>>>> +
>>>>> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>>>> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>>>> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>>>> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>>>> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>>>> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>>>> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>>>> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>>>> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>>>> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>>>> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>>>> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>>>> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>>>> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>>>> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>>>> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>>>> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>>>> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>>>> + reg50080_mmio_write);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>>>> +
>>>>> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>>>> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>>>> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>>>> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>>>> + MMIO_D(WM1_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM2_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM3_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM1S_LP_ILK, D_ALL);
>>>>> + MMIO_D(WM2S_LP_IVB, D_ALL);
>>>>> + MMIO_D(WM3S_LP_IVB, D_ALL);
>>>>> +
>>>>> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>>>> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>>>> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>>>> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x48268), D_ALL);
>>>>> +
>>>>> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>>>> + gmbus_mmio_write);
>>>>> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>>>> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>>>> +
>>>>> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>>> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>>>> +
>>>>> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>>>> +
>>>>> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>>>> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>>>> + MMIO_D(PCH_PP_STATUS, D_ALL);
>>>>> + MMIO_D(PCH_LVDS, D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>>>> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>>>> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>>>> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>>>> + MMIO_D(PCH_DPLL_SEL, D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x61208), D_ALL);
>>>>> + MMIO_D(_MMIO(0x6120c), D_ALL);
>>>>> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>>>> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>>>> +
>>>>> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>>>> + PORTA_HOTPLUG_STATUS_MASK
>>>>> + | PORTB_HOTPLUG_STATUS_MASK
>>>>> + | PORTC_HOTPLUG_STATUS_MASK
>>>>> + | PORTD_HOTPLUG_STATUS_MASK,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>>>> + MMIO_D(FUSE_STRAP, D_ALL);
>>>>> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>>>> +
>>>>> + MMIO_D(DISP_ARB_CTL, D_ALL);
>>>>> + MMIO_D(DISP_ARB_CTL2, D_ALL);
>>>>> +
>>>>> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>>>> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>>>> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>>>> +
>>>>> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>>>> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>>>> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>>>> +
>>>>> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>>>> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>>>> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>>>> +
>>>>> + MMIO_D(IPS_CTL, D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>>>> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>>>> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>>>> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x60110), D_ALL);
>>>>> + MMIO_D(_MMIO(0x61110), D_ALL);
>>>>> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>>>> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>>>> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>>>> + MMIO_D(SPLL_CTL, D_ALL);
>>>>> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>>>> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>>>> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>>>> + MMIO_D(_MMIO(0x46508), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x49080), D_ALL);
>>>>> + MMIO_D(_MMIO(0x49180), D_ALL);
>>>>> + MMIO_D(_MMIO(0x49280), D_ALL);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>>>> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>>>> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>>>> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>>>> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>>>> +
>>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>>>> +
>>>>> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>>>> + MMIO_D(SBI_ADDR, D_ALL);
>>>>> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>>>> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>>>> + MMIO_D(PIXCLK_GATE, D_ALL);
>>>>> +
>>>>> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>>>> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>>>> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>>>> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>>>> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>>>> +
>>>>> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>>>> + MMIO_D(FORCEWAKE_ACK, D_ALL);
>>>>> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>>>> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>>>> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>>>> + MMIO_D(ECOBUS, D_ALL);
>>>>> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>>>> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>>>> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>>>> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>>>> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>>>> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>>>> + MMIO_D(GEN6_RPSTAT1, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>>>> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>>>> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>>>> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>>>> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>>>> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>>>> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>>>> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>>>> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>>>> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>>>> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>>>> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>>>> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>>>> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_D(RSTDBYCTL, D_ALL);
>>>>> +
>>>>> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>>>> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>>>> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>>>> +
>>>>> + MMIO_D(TILECTL, D_ALL);
>>>>> +
>>>>> + MMIO_D(GEN6_UCGCTL1, D_ALL);
>>>>> + MMIO_D(GEN6_UCGCTL2, D_ALL);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>>>> + MMIO_D(_MMIO(0x13812c), D_ALL);
>>>>> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>>>> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>>>> + MMIO_D(HSW_IDICR, D_ALL);
>>>>> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x3c), D_ALL);
>>>>> + MMIO_D(_MMIO(0x860), D_ALL);
>>>>> + MMIO_D(ECOSKPD, D_ALL);
>>>>> + MMIO_D(_MMIO(0x121d0), D_ALL);
>>>>> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>>>> + MMIO_D(_MMIO(0x41d0), D_ALL);
>>>>> + MMIO_D(GAC_ECO_BITS, D_ALL);
>>>>> + MMIO_D(_MMIO(0x6200), D_ALL);
>>>>> + MMIO_D(_MMIO(0x6204), D_ALL);
>>>>> + MMIO_D(_MMIO(0x6208), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7118), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7180), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7408), D_ALL);
>>>>> + MMIO_D(_MMIO(0x7c00), D_ALL);
>>>>> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>>>> + MMIO_D(_MMIO(0x911c), D_ALL);
>>>>> + MMIO_D(_MMIO(0x9120), D_ALL);
>>>>> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GAB_CTL, D_ALL);
>>>>> + MMIO_D(_MMIO(0x48800), D_ALL);
>>>>> + MMIO_D(_MMIO(0xce044), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6500), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6504), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6600), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6604), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6700), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6704), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6800), D_ALL);
>>>>> + MMIO_D(_MMIO(0xe6804), D_ALL);
>>>>> + MMIO_D(PCH_GMBUS4, D_ALL);
>>>>> + MMIO_D(PCH_GMBUS5, D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x902c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc810), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc81c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc828), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfc834), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc00), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc18), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfcc24), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd000), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd00c), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd018), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd024), D_ALL);
>>>>> + MMIO_D(_MMIO(0xfd034), D_ALL);
>>>>> +
>>>>> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>>>> + MMIO_D(_MMIO(0x2054), D_ALL);
>>>>> + MMIO_D(_MMIO(0x12054), D_ALL);
>>>>> + MMIO_D(_MMIO(0x22054), D_ALL);
>>>>> + MMIO_D(_MMIO(0x1a054), D_ALL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x44070), D_ALL);
>>>>> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>>>> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>>> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>>> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>>> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>>> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>>> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>>>> + intel_vgpu_reg_master_irq_handler);
>>>>> +
>>>>> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>>>> + mmio_read_from_hw, NULL);
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0xd0)
>>>>> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>>>> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>>>> + ring_reset_ctl_write);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x230)
>>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x234)
>>>>> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>>>> + NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x244)
>>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x370)
>>>>> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x3a0)
>>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>>>> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>>>> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>>>> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>>>> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>>>> +
>>>>> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>>>> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>>>> +
>>>>> +#define RING_REG(base) _MMIO((base) + 0x270)
>>>>> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>>> +#undef RING_REG
>>>>> +
>>>>> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>>>> +
>>>>> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(WM_MISC, D_BDW);
>>>>> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>>>> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>>>> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>>>> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_D(_MMIO(0xb110), D_BDW);
>>>>> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>>>> + D_BDW_PLUS, NULL, force_nonpriv_write);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>>>> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>>> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>>> + dp_aux_ch_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>>>> +
>>>>> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>>>> +
>>>>> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>>>> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>>> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>>>> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>>>> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>>>> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>>> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>>>> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>>>> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>>>> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>>>> +
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> +
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> +
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>>> +
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>>>> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>>>> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>>>> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> + NULL, NULL);
>>>>> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>>>> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>>>> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + /* TRTT */
>>>>> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>>>> + NULL, gen9_trtte_write);
>>>>> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>>>> + NULL, gen9_trtt_chicken_write);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>>>> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>>>> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>>>> +
>>>>> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>>>> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>>>> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, csfe_chicken1_mmio_write);
>>>>> +#undef CSFE_CHICKEN1_REG
>>>>> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>>> + NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> +
>>>>> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>>>> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>>>> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>>>> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>>>> + MMIO_D(ERROR_GEN6, D_BXT);
>>>>> + MMIO_D(DONE_REG, D_BXT);
>>>>> + MMIO_D(EIR, D_BXT);
>>>>> + MMIO_D(PGTBL_ER, D_BXT);
>>>>> + MMIO_D(_MMIO(0x4194), D_BXT);
>>>>> + MMIO_D(_MMIO(0x4294), D_BXT);
>>>>> + MMIO_D(_MMIO(0x4494), D_BXT);
>>>>> +
>>>>> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>>>> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>>>> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>>>> + MMIO_RING_D(RING_IPEHR, D_BXT);
>>>>> + MMIO_RING_D(RING_INSTPS, D_BXT);
>>>>> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>>>> + MMIO_RING_D(RING_BBSTATE, D_BXT);
>>>>> + MMIO_RING_D(RING_IPEIR, D_BXT);
>>>>> +
>>>>> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>>>> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>>>> + NULL, bxt_phy_ctl_family_write);
>>>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>>>> + NULL, bxt_phy_ctl_family_write);
>>>>> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>>>> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>>>> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>>>> + NULL, bxt_port_pll_enable_write);
>>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>>>> + NULL, bxt_port_pll_enable_write);
>>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>>>> + bxt_port_pll_enable_write);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>>> + bxt_port_tx_dw3_read, NULL);
>>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>>> + bxt_port_tx_dw3_read, NULL);
>>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>>> + bxt_port_tx_dw3_read, NULL);
>>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>>>> +
>>>>> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>>>> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>>>> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>>>> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>>>> +
>>>>> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>>>> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>>>> +
>>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>>>> +
>>>>> + MMIO_D(RC6_CTX_BASE, D_BXT);
>>>>> +
>>>>> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>>>> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>>>> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>>>> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>>>> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>>> + 0, 0, D_BXT, NULL, NULL);
>>>>> +
>>>>> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>>> +
>>>>> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
>>>>> +{
>>>>> + struct drm_i915_private *i915 = gvt->gt->i915;
>>>>> + int ret;
>>>>> +
>>>>> + ret = intel_gvt_init_generic_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> +
>>>>> + if (IS_BROADWELL(i915)) {
>>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + } else if (IS_SKYLAKE(i915) ||
>>>>> + IS_KABYLAKE(i915) ||
>>>>> + IS_COFFEELAKE(i915) ||
>>>>> + IS_COMETLAKE(i915)) {
>>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + } else if (IS_BROXTON(i915)) {
>>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + ret = intel_gvt_init_bxt_mmio_info(gvt);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +#endif
>>>>> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
>>>>> index 244cc7320b54..05bd2f8e9d94 100644
>>>>> --- a/drivers/gpu/drm/i915/gvt/reg.h
>>>>> +++ b/drivers/gpu/drm/i915/gvt/reg.h
>>>>> @@ -133,6 +133,12 @@
>>>>> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
>>>>> #define VF_GUARDBAND _MMIO(0x83a4)
>>>>>
>>>>> +/* XXX FIXME i915 has changed PP_XXX definition */
>>>>> +#define PCH_PP_STATUS _MMIO(0xc7200)
>>>>> +#define PCH_PP_CONTROL _MMIO(0xc7204)
>>>>> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>>>> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>>>> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>>>
>>>>> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
>>>>> #endif
>>>>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
>>>>> index 4e70c1a9ef2e..64846d9bff0b 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_gvt.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
>>>>> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>>>>> dev_priv->params.enable_gvt = 0;
>>>>> }
>>>>>
>>>>> +#define GENERATE_MMIO_TABLE_IN_I915
>>>>> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
>>>>> +{
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +#include "gvt/reg.h"
>>>>> +#include "gvt/mmio_table.h"
>>>>> +#undef GENERATE_MMIO_TABLE_IN_I915
>>>>> +
>>>>> +
>>>>> /**
>>>>> * intel_gvt_init - initialize GVT components
>>>>> * @dev_priv: drm i915 private data
>>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
> ---end quoted text---
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-09 10:20 ` [Intel-gfx] " Jani Nikula
@ 2021-11-09 10:53 ` Wang, Zhi A
-1 siblings, 0 replies; 35+ messages in thread
From: Wang, Zhi A @ 2021-11-09 10:53 UTC (permalink / raw)
To: Jani Nikula, Zhi Wang, joonas.lahtinen, Vivi, Rodrigo, zhenyuw,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
On 11/9/2021 12:20 PM, Jani Nikula wrote:
> On Tue, 09 Nov 2021, "Wang, Zhi A" <zhi.a.wang@intel.com> wrote:
>> On 11/9/2021 9:00 AM, Jani Nikula wrote:
>>> On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
>>>> From: Zhi Wang <zhi.wang.linux@gmail.com>
>>>>
>>>> To support the new mdev interfaces and the re-factor patches from
>>>> Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
>>>> MMIO snapshot still needs to be saved in i915 so that the inital clean HW
>>>> state can be used for the further vGPU. Seperate the tracked MMIO table
>>>> from GVT-g, so that GVT-g and i915 can both use it.
>>> Do you really have to both put code in a header and then include that in
>>> multiple places?
>>>
>>> I think you may need to rethink the whole approach, maybe make them
>>> actual tables instead of code.
>>>
>> Hi Jani:
>>
>> Sadly we can't not use a static-defined struct for a MMIO table. (That's
>> actually how the code was before) Because:
>>
>> 1) We use the register defininations from i915.
>>
>> 2) Every MMIO register definiation in i915 is not a number. It's a macro
>> _MMIO(r), which can't be put in the static-defined struct. That's how
>> the code has been modified like this when it was merged upstream. The
>> MMIO table has to be created dynamically.
> Right.
>
>> The MMIO table in the current GVT-g contains handlers in GVT-g code,
>> which shouldn't be built into i915 after it was moved into a dedicated
>> module. That's the reason I think putting it in a common header would be
>> better.
>>
>> It would be nice to have some better ideas. Currently what in my mind
>> is: 1) Start a new .c file in gvt which contains the code to build MMIO
>> table and let it be used both by i915 and gvt. 2) i915 builds the table
>> and only use it for HW state saving. GVT-g builds a superior table and
>> attach the handlers. Does that sounds better?
> Having the functions defined in a single .c file and called (perhaps via
> just one or two entry points) sounds much better than including code.
>
> Perhaps you could pass in the function to call (new_mmio_info) as a
> parameter in different situations instead of macro magic, to make the
> code more readable?
>
> Basically I want more clarity in the interfaces between the compilation
> units everywhere in i915.
I got it. Thanks so much for the explanation. Will try that approach in V2
>
> BR,
> Jani.
>
>
>> Thanks,
>>
>> Zhi.
>>
>>> BR,
>>> Jani.
>>>
>>>
>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
>>>> Cc: Zhi Wang <zhi.a.wang@intel.com>
>>>> Cc: Christoph Hellwig <hch@lst.de>
>>>> Cc: Jason Gunthorpe <jgg@nvidia.com>
>>>> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
>>>> ---
>>>> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
>>>> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
>>>> drivers/gpu/drm/i915/gvt/reg.h | 6 +
>>>> drivers/gpu/drm/i915/intel_gvt.c | 11 +
>>>> 4 files changed, 1592 insertions(+), 1534 deletions(-)
>>>> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>>>> index cde0a477fb49..6a08d362bf66 100644
>>>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>>>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>>>> @@ -41,13 +41,6 @@
>>>> #include "i915_pvinfo.h"
>>>> #include "display/intel_display_types.h"
>>>>
>>>> -/* XXX FIXME i915 has changed PP_XXX definition */
>>>> -#define PCH_PP_STATUS _MMIO(0xc7200)
>>>> -#define PCH_PP_CONTROL _MMIO(0xc7204)
>>>> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>>> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>>> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>> -
>>>> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
>>>> {
>>>> struct drm_i915_private *i915 = gvt->gt->i915;
>>>> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
>>>> return 0;
>>>> }
>>>>
>>>> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>>> - f, s, am, rm, d, r, w); \
>>>> - if (ret) \
>>>> - return ret; \
>>>> -} while (0)
>>>> -
>>>> -#define MMIO_D(reg, d) \
>>>> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>>> -
>>>> -#define MMIO_DH(reg, d, r, w) \
>>>> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>>> -
>>>> -#define MMIO_DFH(reg, d, f, r, w) \
>>>> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>>> -
>>>> -#define MMIO_GM(reg, d, r, w) \
>>>> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>>> -
>>>> -#define MMIO_GM_RDR(reg, d, r, w) \
>>>> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>>> -
>>>> -#define MMIO_RO(reg, d, f, rm, r, w) \
>>>> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>>> -
>>>> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>>> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>>> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>>> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>>> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>>> - if (HAS_ENGINE(gvt->gt, VCS1)) \
>>>> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>>> -} while (0)
>>>> -
>>>> -#define MMIO_RING_D(prefix, d) \
>>>> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>>> -
>>>> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>>> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>>> -
>>>> -#define MMIO_RING_GM(prefix, d, r, w) \
>>>> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>>> -
>>>> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>>> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>>> -
>>>> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>>> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>>> -
>>>> -static int init_generic_mmio_info(struct intel_gvt *gvt)
>>>> -{
>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> - int ret;
>>>> -
>>>> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>>> - intel_vgpu_reg_imr_handler);
>>>> -
>>>> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(SDEISR, D_ALL);
>>>> -
>>>> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>>> -
>>>> -
>>>> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>>> - gamw_echo_dev_rw_ia_write);
>>>> -
>>>> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x28)
>>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x134)
>>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x6c)
>>>> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>>> -#undef RING_REG
>>>> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>>> -
>>>> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>>> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>>> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>>> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>>> -
>>>> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>>> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>>> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>>> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>>> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>>> -
>>>> - /* RING MODE */
>>>> -#define RING_REG(base) _MMIO((base) + 0x29c)
>>>> - MMIO_RING_DFH(RING_REG, D_ALL,
>>>> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>>> - ring_mode_mmio_write);
>>>> -#undef RING_REG
>>>> -
>>>> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>>> - mmio_read_from_hw, NULL);
>>>> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>>> - mmio_read_from_hw, NULL);
>>>> -
>>>> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - /* display */
>>>> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_D(_MMIO(0x602a0), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x65050), D_ALL);
>>>> - MMIO_D(_MMIO(0x650b4), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0xc4040), D_ALL);
>>>> - MMIO_D(DERRMR, D_ALL);
>>>> -
>>>> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>>> -
>>>> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>>> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>>> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>>> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>>> -
>>>> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>> -
>>>> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>>> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>>> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(CURPOS(PIPE_A), D_ALL);
>>>> - MMIO_D(CURPOS(PIPE_B), D_ALL);
>>>> - MMIO_D(CURPOS(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(CURBASE(PIPE_A), D_ALL);
>>>> - MMIO_D(CURBASE(PIPE_B), D_ALL);
>>>> - MMIO_D(CURBASE(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>>> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>>> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x700ac), D_ALL);
>>>> - MMIO_D(_MMIO(0x710ac), D_ALL);
>>>> - MMIO_D(_MMIO(0x720ac), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x70090), D_ALL);
>>>> - MMIO_D(_MMIO(0x70094), D_ALL);
>>>> - MMIO_D(_MMIO(0x70098), D_ALL);
>>>> - MMIO_D(_MMIO(0x7009c), D_ALL);
>>>> -
>>>> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>>> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>>> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>>> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>>> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>>> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>>> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>>> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>>> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>>> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>>> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>>> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>>> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>>> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>>> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>>> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>>> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>>> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>>> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>>> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>>> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>>> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>>> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>>> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>>> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>>> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>>> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>>> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>>> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>>> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>>> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>>> -
>>>> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>>> -
>>>> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>>> -
>>>> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>>> -
>>>> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>>> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>>> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>>> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>>> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>>> -
>>>> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>>> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>>> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>>> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>>> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>>> -
>>>> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>>> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>>> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>>> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>>> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>>> - MMIO_D(WM1_LP_ILK, D_ALL);
>>>> - MMIO_D(WM2_LP_ILK, D_ALL);
>>>> - MMIO_D(WM3_LP_ILK, D_ALL);
>>>> - MMIO_D(WM1S_LP_ILK, D_ALL);
>>>> - MMIO_D(WM2S_LP_IVB, D_ALL);
>>>> - MMIO_D(WM3S_LP_IVB, D_ALL);
>>>> -
>>>> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>>> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>>> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>>> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x48268), D_ALL);
>>>> -
>>>> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>>> - gmbus_mmio_write);
>>>> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> -
>>>> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>>> -
>>>> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>>> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>>> -
>>>> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> -
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>>> -
>>>> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>>> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>>> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>>> -
>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>>> -
>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>>> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>>> -
>>>> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>>> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>>> - MMIO_D(PCH_PP_STATUS, D_ALL);
>>>> - MMIO_D(PCH_LVDS, D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>>> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>>> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>>> - MMIO_D(PCH_DPLL_SEL, D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x61208), D_ALL);
>>>> - MMIO_D(_MMIO(0x6120c), D_ALL);
>>>> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>>> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>>> -
>>>> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>>> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> -
>>>> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>>> - PORTA_HOTPLUG_STATUS_MASK
>>>> - | PORTB_HOTPLUG_STATUS_MASK
>>>> - | PORTC_HOTPLUG_STATUS_MASK
>>>> - | PORTD_HOTPLUG_STATUS_MASK,
>>>> - NULL, NULL);
>>>> -
>>>> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>>> - MMIO_D(FUSE_STRAP, D_ALL);
>>>> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>>> -
>>>> - MMIO_D(DISP_ARB_CTL, D_ALL);
>>>> - MMIO_D(DISP_ARB_CTL2, D_ALL);
>>>> -
>>>> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>>> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>>> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>>> -
>>>> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>>> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>>> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>>> -
>>>> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>>> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>>> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>>> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>>> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>>> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>>> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>>> -
>>>> - MMIO_D(IPS_CTL, D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>>> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>>> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>>> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(_MMIO(0x60110), D_ALL);
>>>> - MMIO_D(_MMIO(0x61110), D_ALL);
>>>> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> -
>>>> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>>> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>>> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>>> - MMIO_D(SPLL_CTL, D_ALL);
>>>> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>>> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>>> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>>> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>>> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>>> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>>> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>>> -
>>>> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>>> - MMIO_D(_MMIO(0x46508), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x49080), D_ALL);
>>>> - MMIO_D(_MMIO(0x49180), D_ALL);
>>>> - MMIO_D(_MMIO(0x49280), D_ALL);
>>>> -
>>>> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>>> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>>> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>>> -
>>>> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>>> - MMIO_D(SBI_ADDR, D_ALL);
>>>> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>>> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>>> - MMIO_D(PIXCLK_GATE, D_ALL);
>>>> -
>>>> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> -
>>>> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> -
>>>> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> -
>>>> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>>> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>>> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>>> -
>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>>> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>>> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>>> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>>> -
>>>> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>>> - MMIO_D(FORCEWAKE_ACK, D_ALL);
>>>> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>>> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>>> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>>> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>>> - MMIO_D(ECOBUS, D_ALL);
>>>> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>>> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>>> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>>> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>>> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>>> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>>> - MMIO_D(GEN6_RPSTAT1, D_ALL);
>>>> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>>> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>>> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>>> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>>> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>>> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>>> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>>> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>>> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>>> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>>> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>>> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>>> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>>> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>>> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>>> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>>> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> -
>>>> - MMIO_D(RSTDBYCTL, D_ALL);
>>>> -
>>>> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>>> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>>> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>>> -
>>>> - MMIO_D(TILECTL, D_ALL);
>>>> -
>>>> - MMIO_D(GEN6_UCGCTL1, D_ALL);
>>>> - MMIO_D(GEN6_UCGCTL2, D_ALL);
>>>> -
>>>> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>>> - MMIO_D(_MMIO(0x13812c), D_ALL);
>>>> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>>> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>>> - MMIO_D(HSW_IDICR, D_ALL);
>>>> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(_MMIO(0x3c), D_ALL);
>>>> - MMIO_D(_MMIO(0x860), D_ALL);
>>>> - MMIO_D(ECOSKPD, D_ALL);
>>>> - MMIO_D(_MMIO(0x121d0), D_ALL);
>>>> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>>> - MMIO_D(_MMIO(0x41d0), D_ALL);
>>>> - MMIO_D(GAC_ECO_BITS, D_ALL);
>>>> - MMIO_D(_MMIO(0x6200), D_ALL);
>>>> - MMIO_D(_MMIO(0x6204), D_ALL);
>>>> - MMIO_D(_MMIO(0x6208), D_ALL);
>>>> - MMIO_D(_MMIO(0x7118), D_ALL);
>>>> - MMIO_D(_MMIO(0x7180), D_ALL);
>>>> - MMIO_D(_MMIO(0x7408), D_ALL);
>>>> - MMIO_D(_MMIO(0x7c00), D_ALL);
>>>> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>>> - MMIO_D(_MMIO(0x911c), D_ALL);
>>>> - MMIO_D(_MMIO(0x9120), D_ALL);
>>>> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_D(GAB_CTL, D_ALL);
>>>> - MMIO_D(_MMIO(0x48800), D_ALL);
>>>> - MMIO_D(_MMIO(0xce044), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6500), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6504), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6600), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6604), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6700), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6704), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6800), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6804), D_ALL);
>>>> - MMIO_D(PCH_GMBUS4, D_ALL);
>>>> - MMIO_D(PCH_GMBUS5, D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x902c), D_ALL);
>>>> - MMIO_D(_MMIO(0xec008), D_ALL);
>>>> - MMIO_D(_MMIO(0xec00c), D_ALL);
>>>> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>>> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>>> - MMIO_D(_MMIO(0xec408), D_ALL);
>>>> - MMIO_D(_MMIO(0xec40c), D_ALL);
>>>> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>>> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>>> - MMIO_D(_MMIO(0xfc810), D_ALL);
>>>> - MMIO_D(_MMIO(0xfc81c), D_ALL);
>>>> - MMIO_D(_MMIO(0xfc828), D_ALL);
>>>> - MMIO_D(_MMIO(0xfc834), D_ALL);
>>>> - MMIO_D(_MMIO(0xfcc00), D_ALL);
>>>> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>>> - MMIO_D(_MMIO(0xfcc18), D_ALL);
>>>> - MMIO_D(_MMIO(0xfcc24), D_ALL);
>>>> - MMIO_D(_MMIO(0xfd000), D_ALL);
>>>> - MMIO_D(_MMIO(0xfd00c), D_ALL);
>>>> - MMIO_D(_MMIO(0xfd018), D_ALL);
>>>> - MMIO_D(_MMIO(0xfd024), D_ALL);
>>>> - MMIO_D(_MMIO(0xfd034), D_ALL);
>>>> -
>>>> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>>> - MMIO_D(_MMIO(0x2054), D_ALL);
>>>> - MMIO_D(_MMIO(0x12054), D_ALL);
>>>> - MMIO_D(_MMIO(0x22054), D_ALL);
>>>> - MMIO_D(_MMIO(0x1a054), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x44070), D_ALL);
>>>> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>>> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>>> -
>>>> - return 0;
>>>> -}
>>>> -
>>>> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
>>>> -{
>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> - int ret;
>>>> -
>>>> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_master_irq_handler);
>>>> -
>>>> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>>> - mmio_read_from_hw, NULL);
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0xd0)
>>>> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>>> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>>> - ring_reset_ctl_write);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x230)
>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x234)
>>>> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>>> - NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x244)
>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x370)
>>>> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x3a0)
>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>>> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>>> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>>> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>>> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>>> -
>>>> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>>> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x270)
>>>> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>>> -
>>>> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(WM_MISC, D_BDW);
>>>> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>>> -
>>>> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>>> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>>> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>>> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_D(_MMIO(0xb110), D_BDW);
>>>> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>>> -
>>>> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>>> - D_BDW_PLUS, NULL, force_nonpriv_write);
>>>> -
>>>> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>>> -
>>>> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - return 0;
>>>> -}
>>>> -
>>>> -static int init_skl_mmio_info(struct intel_gvt *gvt)
>>>> -{
>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> - int ret;
>>>> -
>>>> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> -
>>>> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>>> -
>>>> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>>> -
>>>> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>>> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>>> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>>> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>>> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>>> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>>> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>>> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>>> -
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> -
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> -
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> -
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>>> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>>> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>>> -
>>>> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>>> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>>> -
>>>> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>> - NULL, NULL);
>>>> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>> - NULL, NULL);
>>>> -
>>>> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>>> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>>> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> -
>>>> - /* TRTT */
>>>> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>>> - NULL, gen9_trtte_write);
>>>> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>>> - NULL, gen9_trtt_chicken_write);
>>>> -
>>>> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>>> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>>> -
>>>> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>>> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>>> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>>> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, csfe_chicken1_mmio_write);
>>>> -#undef CSFE_CHICKEN1_REG
>>>> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> -
>>>> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>>> -
>>>> - return 0;
>>>> -}
>>>> -
>>>> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
>>>> -{
>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> - int ret;
>>>> -
>>>> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>>> -
>>>> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>>> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>>> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>>> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>>> - MMIO_D(ERROR_GEN6, D_BXT);
>>>> - MMIO_D(DONE_REG, D_BXT);
>>>> - MMIO_D(EIR, D_BXT);
>>>> - MMIO_D(PGTBL_ER, D_BXT);
>>>> - MMIO_D(_MMIO(0x4194), D_BXT);
>>>> - MMIO_D(_MMIO(0x4294), D_BXT);
>>>> - MMIO_D(_MMIO(0x4494), D_BXT);
>>>> -
>>>> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>>> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>>> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>>> - MMIO_RING_D(RING_IPEHR, D_BXT);
>>>> - MMIO_RING_D(RING_INSTPS, D_BXT);
>>>> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>>> - MMIO_RING_D(RING_BBSTATE, D_BXT);
>>>> - MMIO_RING_D(RING_IPEIR, D_BXT);
>>>> -
>>>> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>>> -
>>>> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>>> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>>> - NULL, bxt_phy_ctl_family_write);
>>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>>> - NULL, bxt_phy_ctl_family_write);
>>>> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>>> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>>> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>>> - NULL, bxt_port_pll_enable_write);
>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>>> - NULL, bxt_port_pll_enable_write);
>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>>> - bxt_port_pll_enable_write);
>>>> -
>>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>>> -
>>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>>> -
>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>> - bxt_port_tx_dw3_read, NULL);
>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>>> -
>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>> - bxt_port_tx_dw3_read, NULL);
>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>>> -
>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>> - bxt_port_tx_dw3_read, NULL);
>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>>> -
>>>> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>>> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>>> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>>> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>>> -
>>>> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>>> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>>> -
>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>>> -
>>>> - MMIO_D(RC6_CTX_BASE, D_BXT);
>>>> -
>>>> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>>> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>>> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>>> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>>> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> - 0, 0, D_BXT, NULL, NULL);
>>>> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> - 0, 0, D_BXT, NULL, NULL);
>>>> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> - 0, 0, D_BXT, NULL, NULL);
>>>> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> - 0, 0, D_BXT, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>>> -
>>>> - return 0;
>>>> -}
>>>> +#include "mmio_table.h"
>>>>
>>>> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
>>>> unsigned int offset)
>>>> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
>>>> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>>> {
>>>> struct intel_gvt_device_info *info = &gvt->device_info;
>>>> - struct drm_i915_private *i915 = gvt->gt->i915;
>>>> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
>>>> int ret;
>>>>
>>>> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>>> if (!gvt->mmio.mmio_attribute)
>>>> return -ENOMEM;
>>>>
>>>> - ret = init_generic_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> -
>>>> - if (IS_BROADWELL(i915)) {
>>>> - ret = init_bdw_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> - } else if (IS_SKYLAKE(i915) ||
>>>> - IS_KABYLAKE(i915) ||
>>>> - IS_COFFEELAKE(i915) ||
>>>> - IS_COMETLAKE(i915)) {
>>>> - ret = init_bdw_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> - ret = init_skl_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> - } else if (IS_BROXTON(i915)) {
>>>> - ret = init_bdw_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> - ret = init_skl_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> - ret = init_bxt_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> + ret = intel_gvt_init_mmio_info(gvt);
>>>> + if (ret) {
>>>> + intel_gvt_clean_mmio_info(gvt);
>>>> + return ret;
>>>> }
>>>>
>>>> gvt->mmio.mmio_block = mmio_blocks;
>>>> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
>>>>
>>>> return 0;
>>>> -err:
>>>> - intel_gvt_clean_mmio_info(gvt);
>>>> - return ret;
>>>> }
>>>>
>>>> /**
>>>> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>>> new file mode 100644
>>>> index 000000000000..39a4cb59695a
>>>> --- /dev/null
>>>> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>>> @@ -0,0 +1,1570 @@
>>>> +/*
>>>> + * Copyright © 2021 Intel Corporation
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>> + * copy of this software and associated documentation files (the "Software"),
>>>> + * to deal in the Software without restriction, including without limitation
>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>> + * Software is furnished to do so, subject to the following conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice (including the next
>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>> + * Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>> + * IN THE SOFTWARE.
>>>> + *
>>>> + */
>>>> +
>>>> +#ifndef _GVT_MMIO_TABLE_H_
>>>> +#define _GVT_MMIO_TABLE_H_
>>>> +
>>>> +#ifdef GENERATE_MMIO_TABLE_IN_I915
>>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
>>>> + if (ret) \
>>>> + return ret; \
>>>> +} while (0)
>>>> +#else
>>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>>> + f, s, am, rm, d, r, w); \
>>>> + if (ret) \
>>>> + return ret; \
>>>> +} while (0)
>>>> +#endif
>>>> +
>>>> +#define MMIO_D(reg, d) \
>>>> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>>> +
>>>> +#define MMIO_DH(reg, d, r, w) \
>>>> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>>> +
>>>> +#define MMIO_DFH(reg, d, f, r, w) \
>>>> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>>> +
>>>> +#define MMIO_GM(reg, d, r, w) \
>>>> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>>> +
>>>> +#define MMIO_GM_RDR(reg, d, r, w) \
>>>> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>>> +
>>>> +#define MMIO_RO(reg, d, f, rm, r, w) \
>>>> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>>> +
>>>> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>>> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>>> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>>> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>>> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>>> + if (HAS_ENGINE(gvt->gt, VCS1)) \
>>>> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>>> +} while (0)
>>>> +
>>>> +#define MMIO_RING_D(prefix, d) \
>>>> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>>> +
>>>> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>>> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>>> +
>>>> +#define MMIO_RING_GM(prefix, d, r, w) \
>>>> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>>> +
>>>> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>>> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>>> +
>>>> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>>> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>>> +
>>>> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
>>>> +{
>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> +
>>>> + int ret;
>>>> +
>>>> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>>> + intel_vgpu_reg_imr_handler);
>>>> +
>>>> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(SDEISR, D_ALL);
>>>> +
>>>> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>>> +
>>>> +
>>>> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>>> + gamw_echo_dev_rw_ia_write);
>>>> +
>>>> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x28)
>>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x134)
>>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x6c)
>>>> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>>> +#undef RING_REG
>>>> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>>> +
>>>> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>>> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>>> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>>> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>>> +
>>>> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>>> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>>> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>>> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>>> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>>> +
>>>> + /* RING MODE */
>>>> +#define RING_REG(base) _MMIO((base) + 0x29c)
>>>> + MMIO_RING_DFH(RING_REG, D_ALL,
>>>> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>>> + ring_mode_mmio_write);
>>>> +#undef RING_REG
>>>> +
>>>> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>>> + mmio_read_from_hw, NULL);
>>>> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>>> + mmio_read_from_hw, NULL);
>>>> +
>>>> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + /* display */
>>>> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_D(_MMIO(0x602a0), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x65050), D_ALL);
>>>> + MMIO_D(_MMIO(0x650b4), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0xc4040), D_ALL);
>>>> + MMIO_D(DERRMR, D_ALL);
>>>> +
>>>> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>>> +
>>>> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>>> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>>> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>>> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>>> +
>>>> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>> +
>>>> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>>> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>>> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(CURPOS(PIPE_A), D_ALL);
>>>> + MMIO_D(CURPOS(PIPE_B), D_ALL);
>>>> + MMIO_D(CURPOS(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(CURBASE(PIPE_A), D_ALL);
>>>> + MMIO_D(CURBASE(PIPE_B), D_ALL);
>>>> + MMIO_D(CURBASE(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>>> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>>> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x700ac), D_ALL);
>>>> + MMIO_D(_MMIO(0x710ac), D_ALL);
>>>> + MMIO_D(_MMIO(0x720ac), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x70090), D_ALL);
>>>> + MMIO_D(_MMIO(0x70094), D_ALL);
>>>> + MMIO_D(_MMIO(0x70098), D_ALL);
>>>> + MMIO_D(_MMIO(0x7009c), D_ALL);
>>>> +
>>>> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>>> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>>> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>>> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>>> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>>> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>>> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>>> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>>> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>>> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>>> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>>> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>>> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>>> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>>> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>>> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>>> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>>> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>>> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>>> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>>> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>>> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>>> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>>> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>>> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>>> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>>> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>>> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>>> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>>> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>>> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>>> +
>>>> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>>> +
>>>> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>>> +
>>>> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>>> +
>>>> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>>> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>>> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>>> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>>> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>>> +
>>>> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>>> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>>> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>>> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>>> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>>> +
>>>> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>>> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>>> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>>> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>>> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>>> + MMIO_D(WM1_LP_ILK, D_ALL);
>>>> + MMIO_D(WM2_LP_ILK, D_ALL);
>>>> + MMIO_D(WM3_LP_ILK, D_ALL);
>>>> + MMIO_D(WM1S_LP_ILK, D_ALL);
>>>> + MMIO_D(WM2S_LP_IVB, D_ALL);
>>>> + MMIO_D(WM3S_LP_IVB, D_ALL);
>>>> +
>>>> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>>> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>>> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>>> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x48268), D_ALL);
>>>> +
>>>> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>>> + gmbus_mmio_write);
>>>> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> +
>>>> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>>> +
>>>> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>>> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>>> +
>>>> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> +
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>>> +
>>>> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>>> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>>> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>>> +
>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>>> +
>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>>> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>>> +
>>>> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>>> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>>> + MMIO_D(PCH_PP_STATUS, D_ALL);
>>>> + MMIO_D(PCH_LVDS, D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>>> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>>> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>>> + MMIO_D(PCH_DPLL_SEL, D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x61208), D_ALL);
>>>> + MMIO_D(_MMIO(0x6120c), D_ALL);
>>>> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>>> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>>> +
>>>> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>>> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> +
>>>> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>>> + PORTA_HOTPLUG_STATUS_MASK
>>>> + | PORTB_HOTPLUG_STATUS_MASK
>>>> + | PORTC_HOTPLUG_STATUS_MASK
>>>> + | PORTD_HOTPLUG_STATUS_MASK,
>>>> + NULL, NULL);
>>>> +
>>>> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>>> + MMIO_D(FUSE_STRAP, D_ALL);
>>>> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>>> +
>>>> + MMIO_D(DISP_ARB_CTL, D_ALL);
>>>> + MMIO_D(DISP_ARB_CTL2, D_ALL);
>>>> +
>>>> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>>> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>>> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>>> +
>>>> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>>> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>>> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>>> +
>>>> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>>> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>>> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>>> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>>> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>>> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>>> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>>> +
>>>> + MMIO_D(IPS_CTL, D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>>> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>>> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>>> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(_MMIO(0x60110), D_ALL);
>>>> + MMIO_D(_MMIO(0x61110), D_ALL);
>>>> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> +
>>>> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>>> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>>> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>>> + MMIO_D(SPLL_CTL, D_ALL);
>>>> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>>> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>>> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>>> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>>> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>>> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>>> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>>> +
>>>> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>>> + MMIO_D(_MMIO(0x46508), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x49080), D_ALL);
>>>> + MMIO_D(_MMIO(0x49180), D_ALL);
>>>> + MMIO_D(_MMIO(0x49280), D_ALL);
>>>> +
>>>> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>>> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>>> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>>> +
>>>> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>>> + MMIO_D(SBI_ADDR, D_ALL);
>>>> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>>> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>>> + MMIO_D(PIXCLK_GATE, D_ALL);
>>>> +
>>>> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> +
>>>> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> +
>>>> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> +
>>>> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>>> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>>> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>>> +
>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>>> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>>> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>>> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>>> +
>>>> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>>> + MMIO_D(FORCEWAKE_ACK, D_ALL);
>>>> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>>> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>>> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>>> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>>> + MMIO_D(ECOBUS, D_ALL);
>>>> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>>> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>>> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>>> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>>> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>>> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>>> + MMIO_D(GEN6_RPSTAT1, D_ALL);
>>>> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>>> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>>> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>>> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>>> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>>> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>>> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>>> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>>> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>>> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>>> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>>> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>>> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>>> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>>> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>>> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>>> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> +
>>>> + MMIO_D(RSTDBYCTL, D_ALL);
>>>> +
>>>> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>>> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>>> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>>> +
>>>> + MMIO_D(TILECTL, D_ALL);
>>>> +
>>>> + MMIO_D(GEN6_UCGCTL1, D_ALL);
>>>> + MMIO_D(GEN6_UCGCTL2, D_ALL);
>>>> +
>>>> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>>> + MMIO_D(_MMIO(0x13812c), D_ALL);
>>>> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>>> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>>> + MMIO_D(HSW_IDICR, D_ALL);
>>>> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(_MMIO(0x3c), D_ALL);
>>>> + MMIO_D(_MMIO(0x860), D_ALL);
>>>> + MMIO_D(ECOSKPD, D_ALL);
>>>> + MMIO_D(_MMIO(0x121d0), D_ALL);
>>>> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>>> + MMIO_D(_MMIO(0x41d0), D_ALL);
>>>> + MMIO_D(GAC_ECO_BITS, D_ALL);
>>>> + MMIO_D(_MMIO(0x6200), D_ALL);
>>>> + MMIO_D(_MMIO(0x6204), D_ALL);
>>>> + MMIO_D(_MMIO(0x6208), D_ALL);
>>>> + MMIO_D(_MMIO(0x7118), D_ALL);
>>>> + MMIO_D(_MMIO(0x7180), D_ALL);
>>>> + MMIO_D(_MMIO(0x7408), D_ALL);
>>>> + MMIO_D(_MMIO(0x7c00), D_ALL);
>>>> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>>> + MMIO_D(_MMIO(0x911c), D_ALL);
>>>> + MMIO_D(_MMIO(0x9120), D_ALL);
>>>> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_D(GAB_CTL, D_ALL);
>>>> + MMIO_D(_MMIO(0x48800), D_ALL);
>>>> + MMIO_D(_MMIO(0xce044), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6500), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6504), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6600), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6604), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6700), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6704), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6800), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6804), D_ALL);
>>>> + MMIO_D(PCH_GMBUS4, D_ALL);
>>>> + MMIO_D(PCH_GMBUS5, D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x902c), D_ALL);
>>>> + MMIO_D(_MMIO(0xec008), D_ALL);
>>>> + MMIO_D(_MMIO(0xec00c), D_ALL);
>>>> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>>> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>>> + MMIO_D(_MMIO(0xec408), D_ALL);
>>>> + MMIO_D(_MMIO(0xec40c), D_ALL);
>>>> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>>> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>>> + MMIO_D(_MMIO(0xfc810), D_ALL);
>>>> + MMIO_D(_MMIO(0xfc81c), D_ALL);
>>>> + MMIO_D(_MMIO(0xfc828), D_ALL);
>>>> + MMIO_D(_MMIO(0xfc834), D_ALL);
>>>> + MMIO_D(_MMIO(0xfcc00), D_ALL);
>>>> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>>> + MMIO_D(_MMIO(0xfcc18), D_ALL);
>>>> + MMIO_D(_MMIO(0xfcc24), D_ALL);
>>>> + MMIO_D(_MMIO(0xfd000), D_ALL);
>>>> + MMIO_D(_MMIO(0xfd00c), D_ALL);
>>>> + MMIO_D(_MMIO(0xfd018), D_ALL);
>>>> + MMIO_D(_MMIO(0xfd024), D_ALL);
>>>> + MMIO_D(_MMIO(0xfd034), D_ALL);
>>>> +
>>>> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>>> + MMIO_D(_MMIO(0x2054), D_ALL);
>>>> + MMIO_D(_MMIO(0x12054), D_ALL);
>>>> + MMIO_D(_MMIO(0x22054), D_ALL);
>>>> + MMIO_D(_MMIO(0x1a054), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x44070), D_ALL);
>>>> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>>> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
>>>> +{
>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> + int ret;
>>>> +
>>>> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_master_irq_handler);
>>>> +
>>>> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>>> + mmio_read_from_hw, NULL);
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0xd0)
>>>> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>>> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>>> + ring_reset_ctl_write);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x230)
>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x234)
>>>> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>>> + NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x244)
>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x370)
>>>> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x3a0)
>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>>> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>>> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>>> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>>> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>>> +
>>>> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>>> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x270)
>>>> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>>> +
>>>> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(WM_MISC, D_BDW);
>>>> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>>> +
>>>> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>>> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>>> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>>> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_D(_MMIO(0xb110), D_BDW);
>>>> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>>> +
>>>> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>>> + D_BDW_PLUS, NULL, force_nonpriv_write);
>>>> +
>>>> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>>> +
>>>> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
>>>> +{
>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> + int ret;
>>>> +
>>>> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> +
>>>> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>>> +
>>>> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>>> +
>>>> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>>> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>>> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>>> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>>> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>>> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>>> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>>> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>>> +
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> +
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> +
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> +
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>>> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>>> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>>> +
>>>> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>>> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>>> +
>>>> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>> + NULL, NULL);
>>>> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>> + NULL, NULL);
>>>> +
>>>> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>>> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>>> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> +
>>>> + /* TRTT */
>>>> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>>> + NULL, gen9_trtte_write);
>>>> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>>> + NULL, gen9_trtt_chicken_write);
>>>> +
>>>> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>>> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>>> +
>>>> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>>> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>>> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>>> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, csfe_chicken1_mmio_write);
>>>> +#undef CSFE_CHICKEN1_REG
>>>> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> +
>>>> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
>>>> +{
>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> + int ret;
>>>> +
>>>> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>>> +
>>>> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>>> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>>> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>>> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>>> + MMIO_D(ERROR_GEN6, D_BXT);
>>>> + MMIO_D(DONE_REG, D_BXT);
>>>> + MMIO_D(EIR, D_BXT);
>>>> + MMIO_D(PGTBL_ER, D_BXT);
>>>> + MMIO_D(_MMIO(0x4194), D_BXT);
>>>> + MMIO_D(_MMIO(0x4294), D_BXT);
>>>> + MMIO_D(_MMIO(0x4494), D_BXT);
>>>> +
>>>> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>>> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>>> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>>> + MMIO_RING_D(RING_IPEHR, D_BXT);
>>>> + MMIO_RING_D(RING_INSTPS, D_BXT);
>>>> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>>> + MMIO_RING_D(RING_BBSTATE, D_BXT);
>>>> + MMIO_RING_D(RING_IPEIR, D_BXT);
>>>> +
>>>> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>>> +
>>>> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>>> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>>> + NULL, bxt_phy_ctl_family_write);
>>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>>> + NULL, bxt_phy_ctl_family_write);
>>>> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>>> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>>> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>>> + NULL, bxt_port_pll_enable_write);
>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>>> + NULL, bxt_port_pll_enable_write);
>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>>> + bxt_port_pll_enable_write);
>>>> +
>>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>>> +
>>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>>> +
>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>> + bxt_port_tx_dw3_read, NULL);
>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>>> +
>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>> + bxt_port_tx_dw3_read, NULL);
>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>>> +
>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>> + bxt_port_tx_dw3_read, NULL);
>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>>> +
>>>> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>>> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>>> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>>> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>>> +
>>>> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>>> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>>> +
>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>>> +
>>>> + MMIO_D(RC6_CTX_BASE, D_BXT);
>>>> +
>>>> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>>> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>>> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>>> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>>> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> + 0, 0, D_BXT, NULL, NULL);
>>>> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> + 0, 0, D_BXT, NULL, NULL);
>>>> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> + 0, 0, D_BXT, NULL, NULL);
>>>> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> + 0, 0, D_BXT, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
>>>> +{
>>>> + struct drm_i915_private *i915 = gvt->gt->i915;
>>>> + int ret;
>>>> +
>>>> + ret = intel_gvt_init_generic_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> +
>>>> + if (IS_BROADWELL(i915)) {
>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + } else if (IS_SKYLAKE(i915) ||
>>>> + IS_KABYLAKE(i915) ||
>>>> + IS_COFFEELAKE(i915) ||
>>>> + IS_COMETLAKE(i915)) {
>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + } else if (IS_BROXTON(i915)) {
>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + ret = intel_gvt_init_bxt_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + }
>>>> +
>>>> + return 0;
>>>> +}
>>>> +#endif
>>>> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
>>>> index 244cc7320b54..05bd2f8e9d94 100644
>>>> --- a/drivers/gpu/drm/i915/gvt/reg.h
>>>> +++ b/drivers/gpu/drm/i915/gvt/reg.h
>>>> @@ -133,6 +133,12 @@
>>>> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
>>>> #define VF_GUARDBAND _MMIO(0x83a4)
>>>>
>>>> +/* XXX FIXME i915 has changed PP_XXX definition */
>>>> +#define PCH_PP_STATUS _MMIO(0xc7200)
>>>> +#define PCH_PP_CONTROL _MMIO(0xc7204)
>>>> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>>> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>>> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>>
>>>> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
>>>> #endif
>>>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
>>>> index 4e70c1a9ef2e..64846d9bff0b 100644
>>>> --- a/drivers/gpu/drm/i915/intel_gvt.c
>>>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
>>>> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>>>> dev_priv->params.enable_gvt = 0;
>>>> }
>>>>
>>>> +#define GENERATE_MMIO_TABLE_IN_I915
>>>> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
>>>> +{
>>>> + return 0;
>>>> +}
>>>> +
>>>> +#include "gvt/reg.h"
>>>> +#include "gvt/mmio_table.h"
>>>> +#undef GENERATE_MMIO_TABLE_IN_I915
>>>> +
>>>> +
>>>> /**
>>>> * intel_gvt_init - initialize GVT components
>>>> * @dev_priv: drm i915 private data
>>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 10:53 ` Wang, Zhi A
0 siblings, 0 replies; 35+ messages in thread
From: Wang, Zhi A @ 2021-11-09 10:53 UTC (permalink / raw)
To: Jani Nikula, Zhi Wang, joonas.lahtinen, Vivi, Rodrigo, zhenyuw,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, hch
On 11/9/2021 12:20 PM, Jani Nikula wrote:
> On Tue, 09 Nov 2021, "Wang, Zhi A" <zhi.a.wang@intel.com> wrote:
>> On 11/9/2021 9:00 AM, Jani Nikula wrote:
>>> On Mon, 08 Nov 2021, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
>>>> From: Zhi Wang <zhi.wang.linux@gmail.com>
>>>>
>>>> To support the new mdev interfaces and the re-factor patches from
>>>> Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
>>>> MMIO snapshot still needs to be saved in i915 so that the inital clean HW
>>>> state can be used for the further vGPU. Seperate the tracked MMIO table
>>>> from GVT-g, so that GVT-g and i915 can both use it.
>>> Do you really have to both put code in a header and then include that in
>>> multiple places?
>>>
>>> I think you may need to rethink the whole approach, maybe make them
>>> actual tables instead of code.
>>>
>> Hi Jani:
>>
>> Sadly we can't not use a static-defined struct for a MMIO table. (That's
>> actually how the code was before) Because:
>>
>> 1) We use the register defininations from i915.
>>
>> 2) Every MMIO register definiation in i915 is not a number. It's a macro
>> _MMIO(r), which can't be put in the static-defined struct. That's how
>> the code has been modified like this when it was merged upstream. The
>> MMIO table has to be created dynamically.
> Right.
>
>> The MMIO table in the current GVT-g contains handlers in GVT-g code,
>> which shouldn't be built into i915 after it was moved into a dedicated
>> module. That's the reason I think putting it in a common header would be
>> better.
>>
>> It would be nice to have some better ideas. Currently what in my mind
>> is: 1) Start a new .c file in gvt which contains the code to build MMIO
>> table and let it be used both by i915 and gvt. 2) i915 builds the table
>> and only use it for HW state saving. GVT-g builds a superior table and
>> attach the handlers. Does that sounds better?
> Having the functions defined in a single .c file and called (perhaps via
> just one or two entry points) sounds much better than including code.
>
> Perhaps you could pass in the function to call (new_mmio_info) as a
> parameter in different situations instead of macro magic, to make the
> code more readable?
>
> Basically I want more clarity in the interfaces between the compilation
> units everywhere in i915.
I got it. Thanks so much for the explanation. Will try that approach in V2
>
> BR,
> Jani.
>
>
>> Thanks,
>>
>> Zhi.
>>
>>> BR,
>>> Jani.
>>>
>>>
>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
>>>> Cc: Zhi Wang <zhi.a.wang@intel.com>
>>>> Cc: Christoph Hellwig <hch@lst.de>
>>>> Cc: Jason Gunthorpe <jgg@nvidia.com>
>>>> Signed-off-by: Zhi Wang <zhi.wang.linux@gmail.com>
>>>> ---
>>>> drivers/gpu/drm/i915/gvt/handlers.c | 1539 +-----------------------
>>>> drivers/gpu/drm/i915/gvt/mmio_table.h | 1570 +++++++++++++++++++++++++
>>>> drivers/gpu/drm/i915/gvt/reg.h | 6 +
>>>> drivers/gpu/drm/i915/intel_gvt.c | 11 +
>>>> 4 files changed, 1592 insertions(+), 1534 deletions(-)
>>>> create mode 100644 drivers/gpu/drm/i915/gvt/mmio_table.h
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>>>> index cde0a477fb49..6a08d362bf66 100644
>>>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>>>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>>>> @@ -41,13 +41,6 @@
>>>> #include "i915_pvinfo.h"
>>>> #include "display/intel_display_types.h"
>>>>
>>>> -/* XXX FIXME i915 has changed PP_XXX definition */
>>>> -#define PCH_PP_STATUS _MMIO(0xc7200)
>>>> -#define PCH_PP_CONTROL _MMIO(0xc7204)
>>>> -#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>>> -#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>>> -#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>> -
>>>> unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
>>>> {
>>>> struct drm_i915_private *i915 = gvt->gt->i915;
>>>> @@ -2131,1501 +2124,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
>>>> return 0;
>>>> }
>>>>
>>>> -#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>> - ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>>> - f, s, am, rm, d, r, w); \
>>>> - if (ret) \
>>>> - return ret; \
>>>> -} while (0)
>>>> -
>>>> -#define MMIO_D(reg, d) \
>>>> - MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>>> -
>>>> -#define MMIO_DH(reg, d, r, w) \
>>>> - MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>>> -
>>>> -#define MMIO_DFH(reg, d, f, r, w) \
>>>> - MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>>> -
>>>> -#define MMIO_GM(reg, d, r, w) \
>>>> - MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>>> -
>>>> -#define MMIO_GM_RDR(reg, d, r, w) \
>>>> - MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>>> -
>>>> -#define MMIO_RO(reg, d, f, rm, r, w) \
>>>> - MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>>> -
>>>> -#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>>> - MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>>> - MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>>> - MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>>> - MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>>> - if (HAS_ENGINE(gvt->gt, VCS1)) \
>>>> - MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>>> -} while (0)
>>>> -
>>>> -#define MMIO_RING_D(prefix, d) \
>>>> - MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>>> -
>>>> -#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>>> - MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>>> -
>>>> -#define MMIO_RING_GM(prefix, d, r, w) \
>>>> - MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>>> -
>>>> -#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>>> - MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>>> -
>>>> -#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>>> - MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>>> -
>>>> -static int init_generic_mmio_info(struct intel_gvt *gvt)
>>>> -{
>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> - int ret;
>>>> -
>>>> - MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>>> - intel_vgpu_reg_imr_handler);
>>>> -
>>>> - MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(SDEISR, D_ALL);
>>>> -
>>>> - MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>>> -
>>>> -
>>>> - MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>>> - gamw_echo_dev_rw_ia_write);
>>>> -
>>>> - MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> - MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> - MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x28)
>>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x134)
>>>> - MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x6c)
>>>> - MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>>> -#undef RING_REG
>>>> - MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>>> -
>>>> - MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>>> - MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>>> - MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>>> - MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>>> -
>>>> - MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>>> - MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>>> - MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>>> - MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>>> - MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>>> -
>>>> - /* RING MODE */
>>>> -#define RING_REG(base) _MMIO((base) + 0x29c)
>>>> - MMIO_RING_DFH(RING_REG, D_ALL,
>>>> - F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>>> - ring_mode_mmio_write);
>>>> -#undef RING_REG
>>>> -
>>>> - MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>>> - mmio_read_from_hw, NULL);
>>>> - MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>>> - mmio_read_from_hw, NULL);
>>>> -
>>>> - MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - /* display */
>>>> - MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_D(_MMIO(0x602a0), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x65050), D_ALL);
>>>> - MMIO_D(_MMIO(0x650b4), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0xc4040), D_ALL);
>>>> - MMIO_D(DERRMR, D_ALL);
>>>> -
>>>> - MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>>> -
>>>> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>>> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>>> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>>> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>>> -
>>>> - MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>> -
>>>> - MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>>> - MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>>> - MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(CURPOS(PIPE_A), D_ALL);
>>>> - MMIO_D(CURPOS(PIPE_B), D_ALL);
>>>> - MMIO_D(CURPOS(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(CURBASE(PIPE_A), D_ALL);
>>>> - MMIO_D(CURBASE(PIPE_B), D_ALL);
>>>> - MMIO_D(CURBASE(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>>> - MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>>> - MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x700ac), D_ALL);
>>>> - MMIO_D(_MMIO(0x710ac), D_ALL);
>>>> - MMIO_D(_MMIO(0x720ac), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x70090), D_ALL);
>>>> - MMIO_D(_MMIO(0x70094), D_ALL);
>>>> - MMIO_D(_MMIO(0x70098), D_ALL);
>>>> - MMIO_D(_MMIO(0x7009c), D_ALL);
>>>> -
>>>> - MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>>> - MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>>> - MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>>> - MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>>> - MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>>> - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>>> - MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>>> - MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>>> - MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>>> - MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>>> - MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>>> - MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>>> - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>>> - MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>>> - MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>>> - MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>>> - MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>>> - MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>>> - MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>>> - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>>> - MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>>> - MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>>> - MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>>> - MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>>> - MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>>> - MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>>> - MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>>> - MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>>> - MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>>> - MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>>> - MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>>> - MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>>> - MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>>> - MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>>> - MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>>> - reg50080_mmio_write);
>>>> -
>>>> - MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>>> -
>>>> - MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>>> -
>>>> - MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>>> -
>>>> - MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>>> - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>>> -
>>>> - MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>>> - MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>>> - MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>>> - MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>>> - MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>>> -
>>>> - MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>>> - MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>>> - MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>>> - MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>>> - MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>>> -
>>>> - MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>>> - MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>>> - MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>>> - MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>>> - MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>>> - MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>>> - MMIO_D(WM1_LP_ILK, D_ALL);
>>>> - MMIO_D(WM2_LP_ILK, D_ALL);
>>>> - MMIO_D(WM3_LP_ILK, D_ALL);
>>>> - MMIO_D(WM1S_LP_ILK, D_ALL);
>>>> - MMIO_D(WM2S_LP_IVB, D_ALL);
>>>> - MMIO_D(WM3S_LP_IVB, D_ALL);
>>>> -
>>>> - MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>>> - MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>>> - MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>>> - MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x48268), D_ALL);
>>>> -
>>>> - MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>>> - gmbus_mmio_write);
>>>> - MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> -
>>>> - MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>>> -
>>>> - MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>>> - MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>>> -
>>>> - MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> - MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> - MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> - MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> - MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> - MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> - MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> - MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> - MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> -
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>>> -
>>>> - MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>>> - MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>>> - MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>>> -
>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>>> -
>>>> - MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>>> - MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>>> - MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>>> - MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>>> - MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>>> -
>>>> - MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>>> - MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>>> - MMIO_D(PCH_PP_STATUS, D_ALL);
>>>> - MMIO_D(PCH_LVDS, D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>>> - MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>>> - MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>>> - MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>>> - MMIO_D(PCH_DPLL_SEL, D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x61208), D_ALL);
>>>> - MMIO_D(_MMIO(0x6120c), D_ALL);
>>>> - MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>>> - MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>>> -
>>>> - MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> - MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> - MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> - MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> - MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>>> - MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> -
>>>> - MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>>> - PORTA_HOTPLUG_STATUS_MASK
>>>> - | PORTB_HOTPLUG_STATUS_MASK
>>>> - | PORTC_HOTPLUG_STATUS_MASK
>>>> - | PORTD_HOTPLUG_STATUS_MASK,
>>>> - NULL, NULL);
>>>> -
>>>> - MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>>> - MMIO_D(FUSE_STRAP, D_ALL);
>>>> - MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>>> -
>>>> - MMIO_D(DISP_ARB_CTL, D_ALL);
>>>> - MMIO_D(DISP_ARB_CTL2, D_ALL);
>>>> -
>>>> - MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>>> - MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>>> - MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>>> -
>>>> - MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>>> - MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>>> - MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>>> - MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>>> - MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>>> -
>>>> - MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>>> - MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>>> - MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>>> - MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>>> - MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>>> - MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>>> - MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>>> -
>>>> - MMIO_D(IPS_CTL, D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>>> - MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>>> - MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>>> - MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>>> - MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>>> - MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(_MMIO(0x60110), D_ALL);
>>>> - MMIO_D(_MMIO(0x61110), D_ALL);
>>>> - MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> -
>>>> - MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>>> - MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>>> - MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>>> - MMIO_D(SPLL_CTL, D_ALL);
>>>> - MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>>> - MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>>> - MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>>> - MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>>> - MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>>> - MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>>> - MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>>> -
>>>> - MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>>> - MMIO_D(_MMIO(0x46508), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x49080), D_ALL);
>>>> - MMIO_D(_MMIO(0x49180), D_ALL);
>>>> - MMIO_D(_MMIO(0x49280), D_ALL);
>>>> -
>>>> - MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>>> - MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>>> - MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>>> - MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>>> - MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>>> -
>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>>> - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>>> -
>>>> - MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>>> - MMIO_D(SBI_ADDR, D_ALL);
>>>> - MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>>> - MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>>> - MMIO_D(PIXCLK_GATE, D_ALL);
>>>> -
>>>> - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> -
>>>> - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> -
>>>> - MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> - MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> - MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> - MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> - MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> -
>>>> - MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> - MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> - MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> - MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> - MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>>> - MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>>> - MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>>> -
>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>>> - MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>>> - MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>>> - MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>>> -
>>>> - MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>>> - MMIO_D(FORCEWAKE_ACK, D_ALL);
>>>> - MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>>> - MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>>> - MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>>> - MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>>> - MMIO_D(ECOBUS, D_ALL);
>>>> - MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>>> - MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>>> - MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>>> - MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>>> - MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>>> - MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>>> - MMIO_D(GEN6_RPSTAT1, D_ALL);
>>>> - MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>>> - MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>>> - MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>>> - MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>>> - MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>>> - MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>>> - MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>>> - MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>>> - MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>>> - MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>>> - MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>>> - MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>>> - MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>>> - MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>>> - MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>>> - MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>>> - MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>>> - MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> -
>>>> - MMIO_D(RSTDBYCTL, D_ALL);
>>>> -
>>>> - MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>>> - MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>>> - MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>>> -
>>>> - MMIO_D(TILECTL, D_ALL);
>>>> -
>>>> - MMIO_D(GEN6_UCGCTL1, D_ALL);
>>>> - MMIO_D(GEN6_UCGCTL2, D_ALL);
>>>> -
>>>> - MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>>> - MMIO_D(_MMIO(0x13812c), D_ALL);
>>>> - MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>>> - MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>>> - MMIO_D(HSW_IDICR, D_ALL);
>>>> - MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_D(_MMIO(0x3c), D_ALL);
>>>> - MMIO_D(_MMIO(0x860), D_ALL);
>>>> - MMIO_D(ECOSKPD, D_ALL);
>>>> - MMIO_D(_MMIO(0x121d0), D_ALL);
>>>> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>>> - MMIO_D(_MMIO(0x41d0), D_ALL);
>>>> - MMIO_D(GAC_ECO_BITS, D_ALL);
>>>> - MMIO_D(_MMIO(0x6200), D_ALL);
>>>> - MMIO_D(_MMIO(0x6204), D_ALL);
>>>> - MMIO_D(_MMIO(0x6208), D_ALL);
>>>> - MMIO_D(_MMIO(0x7118), D_ALL);
>>>> - MMIO_D(_MMIO(0x7180), D_ALL);
>>>> - MMIO_D(_MMIO(0x7408), D_ALL);
>>>> - MMIO_D(_MMIO(0x7c00), D_ALL);
>>>> - MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>>> - MMIO_D(_MMIO(0x911c), D_ALL);
>>>> - MMIO_D(_MMIO(0x9120), D_ALL);
>>>> - MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_D(GAB_CTL, D_ALL);
>>>> - MMIO_D(_MMIO(0x48800), D_ALL);
>>>> - MMIO_D(_MMIO(0xce044), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6500), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6504), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6600), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6604), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6700), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6704), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6800), D_ALL);
>>>> - MMIO_D(_MMIO(0xe6804), D_ALL);
>>>> - MMIO_D(PCH_GMBUS4, D_ALL);
>>>> - MMIO_D(PCH_GMBUS5, D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x902c), D_ALL);
>>>> - MMIO_D(_MMIO(0xec008), D_ALL);
>>>> - MMIO_D(_MMIO(0xec00c), D_ALL);
>>>> - MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>>> - MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>>> - MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>>> - MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>>> - MMIO_D(_MMIO(0xec408), D_ALL);
>>>> - MMIO_D(_MMIO(0xec40c), D_ALL);
>>>> - MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>>> - MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>>> - MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>>> - MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>>> - MMIO_D(_MMIO(0xfc810), D_ALL);
>>>> - MMIO_D(_MMIO(0xfc81c), D_ALL);
>>>> - MMIO_D(_MMIO(0xfc828), D_ALL);
>>>> - MMIO_D(_MMIO(0xfc834), D_ALL);
>>>> - MMIO_D(_MMIO(0xfcc00), D_ALL);
>>>> - MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>>> - MMIO_D(_MMIO(0xfcc18), D_ALL);
>>>> - MMIO_D(_MMIO(0xfcc24), D_ALL);
>>>> - MMIO_D(_MMIO(0xfd000), D_ALL);
>>>> - MMIO_D(_MMIO(0xfd00c), D_ALL);
>>>> - MMIO_D(_MMIO(0xfd018), D_ALL);
>>>> - MMIO_D(_MMIO(0xfd024), D_ALL);
>>>> - MMIO_D(_MMIO(0xfd034), D_ALL);
>>>> -
>>>> - MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>>> - MMIO_D(_MMIO(0x2054), D_ALL);
>>>> - MMIO_D(_MMIO(0x12054), D_ALL);
>>>> - MMIO_D(_MMIO(0x22054), D_ALL);
>>>> - MMIO_D(_MMIO(0x1a054), D_ALL);
>>>> -
>>>> - MMIO_D(_MMIO(0x44070), D_ALL);
>>>> - MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>> - MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>>> - MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> - MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> - MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> - MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> - MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> - MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> - MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>> - MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>> - MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>>> -
>>>> - return 0;
>>>> -}
>>>> -
>>>> -static int init_bdw_mmio_info(struct intel_gvt *gvt)
>>>> -{
>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> - int ret;
>>>> -
>>>> - MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> - MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> - MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> - MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>>> - intel_vgpu_reg_master_irq_handler);
>>>> -
>>>> - MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>>> - mmio_read_from_hw, NULL);
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0xd0)
>>>> - MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>>> - ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>>> - ring_reset_ctl_write);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x230)
>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x234)
>>>> - MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>>> - NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x244)
>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x370)
>>>> - MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x3a0)
>>>> - MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> - MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>>> - MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>>> - MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>>> - MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>>> - MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>>> -
>>>> - MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>>> - MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>>> -
>>>> -#define RING_REG(base) _MMIO((base) + 0x270)
>>>> - MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>> -#undef RING_REG
>>>> -
>>>> - MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>>> -
>>>> - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>>> - MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(WM_MISC, D_BDW);
>>>> - MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>>> -
>>>> - MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>>> - MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>>> - MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>>> - MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_D(_MMIO(0xb110), D_BDW);
>>>> - MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>>> -
>>>> - MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>>> - D_BDW_PLUS, NULL, force_nonpriv_write);
>>>> -
>>>> - MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>>> -
>>>> - MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>>> - MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>>> -
>>>> - MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - return 0;
>>>> -}
>>>> -
>>>> -static int init_skl_mmio_info(struct intel_gvt *gvt)
>>>> -{
>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> - int ret;
>>>> -
>>>> - MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> - MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> - MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> - MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> - MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> - dp_aux_ch_ctl_mmio_write);
>>>> -
>>>> - MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>>> - MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>>> -
>>>> - MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>>> -
>>>> - MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>>> - MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>> - MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>> - MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>>> - MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>>> - MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>>> - MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>> - MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>> - MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>>> - MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>>> - MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>>> - MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>>> -
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> -
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> -
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> - MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> -
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>> -
>>>> - MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>>> - MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>>> - MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>>> -
>>>> - MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>>> - MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>>> -
>>>> - MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>> - NULL, NULL);
>>>> - MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>> - NULL, NULL);
>>>> -
>>>> - MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>>> - MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>>> - MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>>> - F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> -
>>>> - /* TRTT */
>>>> - MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>>> - NULL, gen9_trtte_write);
>>>> - MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>>> - NULL, gen9_trtt_chicken_write);
>>>> -
>>>> - MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>>> - MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>>> -
>>>> - MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>>> - MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>>> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>>> -
>>>> - MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>>> -#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>>> - MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, csfe_chicken1_mmio_write);
>>>> -#undef CSFE_CHICKEN1_REG
>>>> - MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> - MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> - NULL, NULL);
>>>> -
>>>> - MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>>> -
>>>> - return 0;
>>>> -}
>>>> -
>>>> -static int init_bxt_mmio_info(struct intel_gvt *gvt)
>>>> -{
>>>> - struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> - int ret;
>>>> -
>>>> - MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>>> -
>>>> - MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>>> - MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>>> - MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>>> - MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>>> - MMIO_D(ERROR_GEN6, D_BXT);
>>>> - MMIO_D(DONE_REG, D_BXT);
>>>> - MMIO_D(EIR, D_BXT);
>>>> - MMIO_D(PGTBL_ER, D_BXT);
>>>> - MMIO_D(_MMIO(0x4194), D_BXT);
>>>> - MMIO_D(_MMIO(0x4294), D_BXT);
>>>> - MMIO_D(_MMIO(0x4494), D_BXT);
>>>> -
>>>> - MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>>> - MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>>> - MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>>> - MMIO_RING_D(RING_IPEHR, D_BXT);
>>>> - MMIO_RING_D(RING_INSTPS, D_BXT);
>>>> - MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>>> - MMIO_RING_D(RING_BBSTATE, D_BXT);
>>>> - MMIO_RING_D(RING_IPEIR, D_BXT);
>>>> -
>>>> - MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>>> -
>>>> - MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>>> - MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>>> - NULL, bxt_phy_ctl_family_write);
>>>> - MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>>> - NULL, bxt_phy_ctl_family_write);
>>>> - MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>>> - MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>>> - MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>>> - NULL, bxt_port_pll_enable_write);
>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>>> - NULL, bxt_port_pll_enable_write);
>>>> - MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>>> - bxt_port_pll_enable_write);
>>>> -
>>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>>> -
>>>> - MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>>> - MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>>> -
>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>> - bxt_port_tx_dw3_read, NULL);
>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>>> -
>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>> - bxt_port_tx_dw3_read, NULL);
>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>>> -
>>>> - MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>> - NULL, bxt_pcs_dw12_grp_write);
>>>> - MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>> - bxt_port_tx_dw3_read, NULL);
>>>> - MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>>> - MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>>> -
>>>> - MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>>> - MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>>> - MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>>> - MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>>> -
>>>> - MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>>> - MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>>> -
>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>>> - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>>> -
>>>> - MMIO_D(RC6_CTX_BASE, D_BXT);
>>>> -
>>>> - MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>>> - MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>>> - MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>>> - MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>>> - MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> - MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> - 0, 0, D_BXT, NULL, NULL);
>>>> - MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> - 0, 0, D_BXT, NULL, NULL);
>>>> - MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> - 0, 0, D_BXT, NULL, NULL);
>>>> - MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> - 0, 0, D_BXT, NULL, NULL);
>>>> -
>>>> - MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> -
>>>> - MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>>> -
>>>> - return 0;
>>>> -}
>>>> +#include "mmio_table.h"
>>>>
>>>> static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
>>>> unsigned int offset)
>>>> @@ -3693,7 +2192,6 @@ static struct gvt_mmio_block mmio_blocks[] = {
>>>> int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>>> {
>>>> struct intel_gvt_device_info *info = &gvt->device_info;
>>>> - struct drm_i915_private *i915 = gvt->gt->i915;
>>>> int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
>>>> int ret;
>>>>
>>>> @@ -3701,43 +2199,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
>>>> if (!gvt->mmio.mmio_attribute)
>>>> return -ENOMEM;
>>>>
>>>> - ret = init_generic_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> -
>>>> - if (IS_BROADWELL(i915)) {
>>>> - ret = init_bdw_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> - } else if (IS_SKYLAKE(i915) ||
>>>> - IS_KABYLAKE(i915) ||
>>>> - IS_COFFEELAKE(i915) ||
>>>> - IS_COMETLAKE(i915)) {
>>>> - ret = init_bdw_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> - ret = init_skl_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> - } else if (IS_BROXTON(i915)) {
>>>> - ret = init_bdw_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> - ret = init_skl_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> - ret = init_bxt_mmio_info(gvt);
>>>> - if (ret)
>>>> - goto err;
>>>> + ret = intel_gvt_init_mmio_info(gvt);
>>>> + if (ret) {
>>>> + intel_gvt_clean_mmio_info(gvt);
>>>> + return ret;
>>>> }
>>>>
>>>> gvt->mmio.mmio_block = mmio_blocks;
>>>> gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
>>>>
>>>> return 0;
>>>> -err:
>>>> - intel_gvt_clean_mmio_info(gvt);
>>>> - return ret;
>>>> }
>>>>
>>>> /**
>>>> diff --git a/drivers/gpu/drm/i915/gvt/mmio_table.h b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>>> new file mode 100644
>>>> index 000000000000..39a4cb59695a
>>>> --- /dev/null
>>>> +++ b/drivers/gpu/drm/i915/gvt/mmio_table.h
>>>> @@ -0,0 +1,1570 @@
>>>> +/*
>>>> + * Copyright © 2021 Intel Corporation
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>> + * copy of this software and associated documentation files (the "Software"),
>>>> + * to deal in the Software without restriction, including without limitation
>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>> + * Software is furnished to do so, subject to the following conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice (including the next
>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>> + * Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>> + * IN THE SOFTWARE.
>>>> + *
>>>> + */
>>>> +
>>>> +#ifndef _GVT_MMIO_TABLE_H_
>>>> +#define _GVT_MMIO_TABLE_H_
>>>> +
>>>> +#ifdef GENERATE_MMIO_TABLE_IN_I915
>>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
>>>> + if (ret) \
>>>> + return ret; \
>>>> +} while (0)
>>>> +#else
>>>> +#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
>>>> + ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
>>>> + f, s, am, rm, d, r, w); \
>>>> + if (ret) \
>>>> + return ret; \
>>>> +} while (0)
>>>> +#endif
>>>> +
>>>> +#define MMIO_D(reg, d) \
>>>> + MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
>>>> +
>>>> +#define MMIO_DH(reg, d, r, w) \
>>>> + MMIO_F(reg, 4, 0, 0, 0, d, r, w)
>>>> +
>>>> +#define MMIO_DFH(reg, d, f, r, w) \
>>>> + MMIO_F(reg, 4, f, 0, 0, d, r, w)
>>>> +
>>>> +#define MMIO_GM(reg, d, r, w) \
>>>> + MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
>>>> +
>>>> +#define MMIO_GM_RDR(reg, d, r, w) \
>>>> + MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
>>>> +
>>>> +#define MMIO_RO(reg, d, f, rm, r, w) \
>>>> + MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
>>>> +
>>>> +#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
>>>> + MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
>>>> + MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
>>>> + MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
>>>> + MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
>>>> + if (HAS_ENGINE(gvt->gt, VCS1)) \
>>>> + MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
>>>> +} while (0)
>>>> +
>>>> +#define MMIO_RING_D(prefix, d) \
>>>> + MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
>>>> +
>>>> +#define MMIO_RING_DFH(prefix, d, f, r, w) \
>>>> + MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
>>>> +
>>>> +#define MMIO_RING_GM(prefix, d, r, w) \
>>>> + MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
>>>> +
>>>> +#define MMIO_RING_GM_RDR(prefix, d, r, w) \
>>>> + MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
>>>> +
>>>> +#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
>>>> + MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
>>>> +
>>>> +static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
>>>> +{
>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> +
>>>> + int ret;
>>>> +
>>>> + MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
>>>> + intel_vgpu_reg_imr_handler);
>>>> +
>>>> + MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(SDEISR, D_ALL);
>>>> +
>>>> + MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
>>>> +
>>>> +
>>>> + MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
>>>> + gamw_echo_dev_rw_ia_write);
>>>> +
>>>> + MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> + MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> + MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x28)
>>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x134)
>>>> + MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x6c)
>>>> + MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
>>>> +#undef RING_REG
>>>> + MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
>>>> +
>>>> + MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
>>>> + MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
>>>> + MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
>>>> + MMIO_D(GEN7_CXT_SIZE, D_ALL);
>>>> +
>>>> + MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
>>>> + MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
>>>> + MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
>>>> + MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
>>>> + MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
>>>> +
>>>> + /* RING MODE */
>>>> +#define RING_REG(base) _MMIO((base) + 0x29c)
>>>> + MMIO_RING_DFH(RING_REG, D_ALL,
>>>> + F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
>>>> + ring_mode_mmio_write);
>>>> +#undef RING_REG
>>>> +
>>>> + MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
>>>> + mmio_read_from_hw, NULL);
>>>> + MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
>>>> + mmio_read_from_hw, NULL);
>>>> +
>>>> + MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
>>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + /* display */
>>>> + MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_D(_MMIO(0x602a0), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x65050), D_ALL);
>>>> + MMIO_D(_MMIO(0x650b4), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0xc4040), D_ALL);
>>>> + MMIO_D(DERRMR, D_ALL);
>>>> +
>>>> + MMIO_D(PIPEDSL(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPEDSL(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPEDSL(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
>>>> +
>>>> + MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
>>>> + MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
>>>> + MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
>>>> + MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
>>>> +
>>>> + MMIO_D(PIPESTAT(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPESTAT(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPESTAT(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
>>>> +
>>>> + MMIO_D(CURCNTR(PIPE_A), D_ALL);
>>>> + MMIO_D(CURCNTR(PIPE_B), D_ALL);
>>>> + MMIO_D(CURCNTR(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(CURPOS(PIPE_A), D_ALL);
>>>> + MMIO_D(CURPOS(PIPE_B), D_ALL);
>>>> + MMIO_D(CURPOS(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(CURBASE(PIPE_A), D_ALL);
>>>> + MMIO_D(CURBASE(PIPE_B), D_ALL);
>>>> + MMIO_D(CURBASE(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
>>>> + MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
>>>> + MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x700ac), D_ALL);
>>>> + MMIO_D(_MMIO(0x710ac), D_ALL);
>>>> + MMIO_D(_MMIO(0x720ac), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x70090), D_ALL);
>>>> + MMIO_D(_MMIO(0x70094), D_ALL);
>>>> + MMIO_D(_MMIO(0x70098), D_ALL);
>>>> + MMIO_D(_MMIO(0x7009c), D_ALL);
>>>> +
>>>> + MMIO_D(DSPCNTR(PIPE_A), D_ALL);
>>>> + MMIO_D(DSPADDR(PIPE_A), D_ALL);
>>>> + MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
>>>> + MMIO_D(DSPPOS(PIPE_A), D_ALL);
>>>> + MMIO_D(DSPSIZE(PIPE_A), D_ALL);
>>>> + MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>>>> + MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
>>>> + MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(DSPCNTR(PIPE_B), D_ALL);
>>>> + MMIO_D(DSPADDR(PIPE_B), D_ALL);
>>>> + MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
>>>> + MMIO_D(DSPPOS(PIPE_B), D_ALL);
>>>> + MMIO_D(DSPSIZE(PIPE_B), D_ALL);
>>>> + MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
>>>> + MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
>>>> + MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(DSPCNTR(PIPE_C), D_ALL);
>>>> + MMIO_D(DSPADDR(PIPE_C), D_ALL);
>>>> + MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
>>>> + MMIO_D(DSPPOS(PIPE_C), D_ALL);
>>>> + MMIO_D(DSPSIZE(PIPE_C), D_ALL);
>>>> + MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
>>>> + MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
>>>> + MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(SPRCTL(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRPOS(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRSIZE(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
>>>> + MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
>>>> + MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
>>>> + MMIO_D(SPROFFSET(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRSCALE(PIPE_A), D_ALL);
>>>> + MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(SPRCTL(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRPOS(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRSIZE(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
>>>> + MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
>>>> + MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
>>>> + MMIO_D(SPROFFSET(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRSCALE(PIPE_B), D_ALL);
>>>> + MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(SPRCTL(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRPOS(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRSIZE(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
>>>> + MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
>>>> + MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
>>>> + MMIO_D(SPROFFSET(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRSCALE(PIPE_C), D_ALL);
>>>> + MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
>>>> + MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
>>>> + reg50080_mmio_write);
>>>> +
>>>> + MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
>>>> +
>>>> + MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
>>>> +
>>>> + MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
>>>> +
>>>> + MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
>>>> + MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
>>>> +
>>>> + MMIO_D(PF_CTL(PIPE_A), D_ALL);
>>>> + MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
>>>> + MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
>>>> + MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
>>>> + MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
>>>> +
>>>> + MMIO_D(PF_CTL(PIPE_B), D_ALL);
>>>> + MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
>>>> + MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
>>>> + MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
>>>> + MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
>>>> +
>>>> + MMIO_D(PF_CTL(PIPE_C), D_ALL);
>>>> + MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
>>>> + MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
>>>> + MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
>>>> + MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
>>>> + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
>>>> + MMIO_D(WM1_LP_ILK, D_ALL);
>>>> + MMIO_D(WM2_LP_ILK, D_ALL);
>>>> + MMIO_D(WM3_LP_ILK, D_ALL);
>>>> + MMIO_D(WM1S_LP_ILK, D_ALL);
>>>> + MMIO_D(WM2S_LP_IVB, D_ALL);
>>>> + MMIO_D(WM3S_LP_IVB, D_ALL);
>>>> +
>>>> + MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
>>>> + MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
>>>> + MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
>>>> + MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x48268), D_ALL);
>>>> +
>>>> + MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>>>> + gmbus_mmio_write);
>>>> + MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> + MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> + MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> +
>>>> + MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
>>>> +
>>>> + MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
>>>> + MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
>>>> +
>>>> + MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> + MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> + MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
>>>> + MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> + MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> + MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> + MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> + MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> + MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
>>>> +
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
>>>> +
>>>> + MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
>>>> + MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
>>>> + MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
>>>> +
>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
>>>> +
>>>> + MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
>>>> + MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
>>>> + MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
>>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
>>>> + MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
>>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
>>>> + MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
>>>> +
>>>> + MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
>>>> + MMIO_D(PCH_PP_DIVISOR, D_ALL);
>>>> + MMIO_D(PCH_PP_STATUS, D_ALL);
>>>> + MMIO_D(PCH_LVDS, D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
>>>> + MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
>>>> + MMIO_D(PCH_DREF_CONTROL, D_ALL);
>>>> + MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
>>>> + MMIO_D(PCH_DPLL_SEL, D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x61208), D_ALL);
>>>> + MMIO_D(_MMIO(0x6120c), D_ALL);
>>>> + MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
>>>> + MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
>>>> +
>>>> + MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> + MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> + MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> + MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> + MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
>>>> + MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
>>>> +
>>>> + MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
>>>> + PORTA_HOTPLUG_STATUS_MASK
>>>> + | PORTB_HOTPLUG_STATUS_MASK
>>>> + | PORTC_HOTPLUG_STATUS_MASK
>>>> + | PORTD_HOTPLUG_STATUS_MASK,
>>>> + NULL, NULL);
>>>> +
>>>> + MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
>>>> + MMIO_D(FUSE_STRAP, D_ALL);
>>>> + MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
>>>> +
>>>> + MMIO_D(DISP_ARB_CTL, D_ALL);
>>>> + MMIO_D(DISP_ARB_CTL2, D_ALL);
>>>> +
>>>> + MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
>>>> + MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
>>>> + MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
>>>> +
>>>> + MMIO_D(SOUTH_CHICKEN1, D_ALL);
>>>> + MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
>>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
>>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
>>>> + MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
>>>> + MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
>>>> + MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
>>>> +
>>>> + MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
>>>> + MMIO_D(ILK_DPFC_CONTROL, D_ALL);
>>>> + MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
>>>> + MMIO_D(ILK_DPFC_STATUS, D_ALL);
>>>> + MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
>>>> + MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
>>>> + MMIO_D(ILK_FBC_RT_BASE, D_ALL);
>>>> +
>>>> + MMIO_D(IPS_CTL, D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
>>>> + MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
>>>> + MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
>>>> + MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
>>>> + MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
>>>> + MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(_MMIO(0x60110), D_ALL);
>>>> + MMIO_D(_MMIO(0x61110), D_ALL);
>>>> + MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
>>>> +
>>>> + MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
>>>> + MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
>>>> + MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
>>>> + MMIO_D(SPLL_CTL, D_ALL);
>>>> + MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
>>>> + MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
>>>> + MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
>>>> + MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
>>>> + MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
>>>> + MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
>>>> + MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
>>>> +
>>>> + MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
>>>> + MMIO_D(_MMIO(0x46508), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x49080), D_ALL);
>>>> + MMIO_D(_MMIO(0x49180), D_ALL);
>>>> + MMIO_D(_MMIO(0x49280), D_ALL);
>>>> +
>>>> + MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
>>>> + MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
>>>> + MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
>>>> + MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
>>>> + MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
>>>> +
>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
>>>> + MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
>>>> +
>>>> + MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
>>>> + MMIO_D(SBI_ADDR, D_ALL);
>>>> + MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
>>>> + MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
>>>> + MMIO_D(PIXCLK_GATE, D_ALL);
>>>> +
>>>> + MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> +
>>>> + MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> + MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> + MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> + MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> + MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
>>>> +
>>>> + MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> + MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> + MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> + MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> + MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
>>>> +
>>>> + MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> + MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> + MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> + MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
>>>> + MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
>>>> + MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
>>>> + MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
>>>> +
>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
>>>> + MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
>>>> + MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
>>>> + MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
>>>> +
>>>> + MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
>>>> + MMIO_D(FORCEWAKE_ACK, D_ALL);
>>>> + MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
>>>> + MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
>>>> + MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
>>>> + MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
>>>> + MMIO_D(ECOBUS, D_ALL);
>>>> + MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
>>>> + MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
>>>> + MMIO_D(GEN6_RPNSWREQ, D_ALL);
>>>> + MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
>>>> + MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
>>>> + MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
>>>> + MMIO_D(GEN6_RPSTAT1, D_ALL);
>>>> + MMIO_D(GEN6_RP_CONTROL, D_ALL);
>>>> + MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
>>>> + MMIO_D(GEN6_RP_CUR_UP, D_ALL);
>>>> + MMIO_D(GEN6_RP_PREV_UP, D_ALL);
>>>> + MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
>>>> + MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
>>>> + MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
>>>> + MMIO_D(GEN6_RP_UP_EI, D_ALL);
>>>> + MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
>>>> + MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
>>>> + MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
>>>> + MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
>>>> + MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
>>>> + MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
>>>> + MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
>>>> + MMIO_D(GEN6_RC_SLEEP, D_ALL);
>>>> + MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
>>>> + MMIO_D(GEN6_PMINTRMSK, D_ALL);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
>>>> +
>>>> + MMIO_D(RSTDBYCTL, D_ALL);
>>>> +
>>>> + MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
>>>> + MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
>>>> + MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
>>>> +
>>>> + MMIO_D(TILECTL, D_ALL);
>>>> +
>>>> + MMIO_D(GEN6_UCGCTL1, D_ALL);
>>>> + MMIO_D(GEN6_UCGCTL2, D_ALL);
>>>> +
>>>> + MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(GEN6_PCODE_DATA, D_ALL);
>>>> + MMIO_D(_MMIO(0x13812c), D_ALL);
>>>> + MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
>>>> + MMIO_D(HSW_EDRAM_CAP, D_ALL);
>>>> + MMIO_D(HSW_IDICR, D_ALL);
>>>> + MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_D(_MMIO(0x3c), D_ALL);
>>>> + MMIO_D(_MMIO(0x860), D_ALL);
>>>> + MMIO_D(ECOSKPD, D_ALL);
>>>> + MMIO_D(_MMIO(0x121d0), D_ALL);
>>>> + MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
>>>> + MMIO_D(_MMIO(0x41d0), D_ALL);
>>>> + MMIO_D(GAC_ECO_BITS, D_ALL);
>>>> + MMIO_D(_MMIO(0x6200), D_ALL);
>>>> + MMIO_D(_MMIO(0x6204), D_ALL);
>>>> + MMIO_D(_MMIO(0x6208), D_ALL);
>>>> + MMIO_D(_MMIO(0x7118), D_ALL);
>>>> + MMIO_D(_MMIO(0x7180), D_ALL);
>>>> + MMIO_D(_MMIO(0x7408), D_ALL);
>>>> + MMIO_D(_MMIO(0x7c00), D_ALL);
>>>> + MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
>>>> + MMIO_D(_MMIO(0x911c), D_ALL);
>>>> + MMIO_D(_MMIO(0x9120), D_ALL);
>>>> + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_D(GAB_CTL, D_ALL);
>>>> + MMIO_D(_MMIO(0x48800), D_ALL);
>>>> + MMIO_D(_MMIO(0xce044), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6500), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6504), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6600), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6604), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6700), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6704), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6800), D_ALL);
>>>> + MMIO_D(_MMIO(0xe6804), D_ALL);
>>>> + MMIO_D(PCH_GMBUS4, D_ALL);
>>>> + MMIO_D(PCH_GMBUS5, D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x902c), D_ALL);
>>>> + MMIO_D(_MMIO(0xec008), D_ALL);
>>>> + MMIO_D(_MMIO(0xec00c), D_ALL);
>>>> + MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
>>>> + MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
>>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
>>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
>>>> + MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
>>>> + MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
>>>> + MMIO_D(_MMIO(0xec408), D_ALL);
>>>> + MMIO_D(_MMIO(0xec40c), D_ALL);
>>>> + MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
>>>> + MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
>>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
>>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
>>>> + MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
>>>> + MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
>>>> + MMIO_D(_MMIO(0xfc810), D_ALL);
>>>> + MMIO_D(_MMIO(0xfc81c), D_ALL);
>>>> + MMIO_D(_MMIO(0xfc828), D_ALL);
>>>> + MMIO_D(_MMIO(0xfc834), D_ALL);
>>>> + MMIO_D(_MMIO(0xfcc00), D_ALL);
>>>> + MMIO_D(_MMIO(0xfcc0c), D_ALL);
>>>> + MMIO_D(_MMIO(0xfcc18), D_ALL);
>>>> + MMIO_D(_MMIO(0xfcc24), D_ALL);
>>>> + MMIO_D(_MMIO(0xfd000), D_ALL);
>>>> + MMIO_D(_MMIO(0xfd00c), D_ALL);
>>>> + MMIO_D(_MMIO(0xfd018), D_ALL);
>>>> + MMIO_D(_MMIO(0xfd024), D_ALL);
>>>> + MMIO_D(_MMIO(0xfd034), D_ALL);
>>>> +
>>>> + MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
>>>> + MMIO_D(_MMIO(0x2054), D_ALL);
>>>> + MMIO_D(_MMIO(0x12054), D_ALL);
>>>> + MMIO_D(_MMIO(0x22054), D_ALL);
>>>> + MMIO_D(_MMIO(0x1a054), D_ALL);
>>>> +
>>>> + MMIO_D(_MMIO(0x44070), D_ALL);
>>>> + MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>> + MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
>>>> + MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
>>>> + MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> + MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> + MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> + MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> + MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
>>>> + MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>> + MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
>>>> + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int intel_gvt_init_bdw_mmio_info(struct intel_gvt *gvt)
>>>> +{
>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> + int ret;
>>>> +
>>>> + MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
>>>> + MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
>>>> + MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
>>>> + MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
>>>> + intel_vgpu_reg_master_irq_handler);
>>>> +
>>>> + MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
>>>> + mmio_read_from_hw, NULL);
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0xd0)
>>>> + MMIO_RING_F(RING_REG, 4, F_RO, 0,
>>>> + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
>>>> + ring_reset_ctl_write);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x230)
>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x234)
>>>> + MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
>>>> + NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x244)
>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x370)
>>>> + MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x3a0)
>>>> + MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> + MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
>>>> + MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
>>>> + MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
>>>> + MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
>>>> + MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>>> +
>>>> + MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
>>>> + MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>>> +
>>>> +#define RING_REG(base) _MMIO((base) + 0x270)
>>>> + MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
>>>> +#undef RING_REG
>>>> +
>>>> + MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
>>>> +
>>>> + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
>>>> + MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(WM_MISC, D_BDW);
>>>> + MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
>>>> +
>>>> + MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
>>>> + MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
>>>> + MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
>>>> + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_D(_MMIO(0xb110), D_BDW);
>>>> + MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);
>>>> +
>>>> + MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
>>>> + D_BDW_PLUS, NULL, force_nonpriv_write);
>>>> +
>>>> + MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
>>>> +
>>>> + MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
>>>> + MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
>>>> +
>>>> + MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int intel_gvt_init_skl_mmio_info(struct intel_gvt *gvt)
>>>> +{
>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> + int ret;
>>>> +
>>>> + MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> + MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> + MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
>>>> + MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> + MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
>>>> + dp_aux_ch_ctl_mmio_write);
>>>> +
>>>> + MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
>>>> + MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
>>>> +
>>>> + MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
>>>> +
>>>> + MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
>>>> + MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>> + MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
>>>> + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_D(DC_STATE_EN, D_SKL_PLUS);
>>>> + MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
>>>> + MMIO_D(CDCLK_CTL, D_SKL_PLUS);
>>>> + MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>> + MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
>>>> + MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
>>>> + MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
>>>> + MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
>>>> + MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
>>>> +
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> +
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> +
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
>>>> + MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
>>>> +
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
>>>> + MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
>>>> +
>>>> + MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(DMC_SSP_BASE, D_SKL_PLUS);
>>>> + MMIO_D(DMC_HTP_SKL, D_SKL_PLUS);
>>>> + MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS);
>>>> +
>>>> + MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_D(SKL_DFSM, D_SKL_PLUS);
>>>> + MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
>>>> +
>>>> + MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>> + NULL, NULL);
>>>> + MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
>>>> + NULL, NULL);
>>>> +
>>>> + MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
>>>> + MMIO_D(RC6_LOCATION, D_SKL_PLUS);
>>>> + MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
>>>> + F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> +
>>>> + /* TRTT */
>>>> + MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
>>>> + NULL, gen9_trtte_write);
>>>> + MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
>>>> + NULL, gen9_trtt_chicken_write);
>>>> +
>>>> + MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
>>>> + MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
>>>> +
>>>> + MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
>>>> + MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
>>>> + MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
>>>> +
>>>> + MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
>>>> +#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
>>>> + MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, csfe_chicken1_mmio_write);
>>>> +#undef CSFE_CHICKEN1_REG
>>>> + MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
>>>> + NULL, NULL);
>>>> +
>>>> + MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int intel_gvt_init_bxt_mmio_info(struct intel_gvt *gvt)
>>>> +{
>>>> + struct drm_i915_private *dev_priv = gvt->gt->i915;
>>>> + int ret;
>>>> +
>>>> + MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
>>>> +
>>>> + MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
>>>> + MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
>>>> + MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
>>>> + MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
>>>> + MMIO_D(ERROR_GEN6, D_BXT);
>>>> + MMIO_D(DONE_REG, D_BXT);
>>>> + MMIO_D(EIR, D_BXT);
>>>> + MMIO_D(PGTBL_ER, D_BXT);
>>>> + MMIO_D(_MMIO(0x4194), D_BXT);
>>>> + MMIO_D(_MMIO(0x4294), D_BXT);
>>>> + MMIO_D(_MMIO(0x4494), D_BXT);
>>>> +
>>>> + MMIO_RING_D(RING_PSMI_CTL, D_BXT);
>>>> + MMIO_RING_D(RING_DMA_FADD, D_BXT);
>>>> + MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
>>>> + MMIO_RING_D(RING_IPEHR, D_BXT);
>>>> + MMIO_RING_D(RING_INSTPS, D_BXT);
>>>> + MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
>>>> + MMIO_RING_D(RING_BBSTATE, D_BXT);
>>>> + MMIO_RING_D(RING_IPEIR, D_BXT);
>>>> +
>>>> + MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
>>>> +
>>>> + MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
>>>> + MMIO_D(BXT_RP_STATE_CAP, D_BXT);
>>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
>>>> + NULL, bxt_phy_ctl_family_write);
>>>> + MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
>>>> + NULL, bxt_phy_ctl_family_write);
>>>> + MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
>>>> + MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
>>>> + MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
>>>> + NULL, bxt_port_pll_enable_write);
>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
>>>> + NULL, bxt_port_pll_enable_write);
>>>> + MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
>>>> + bxt_port_pll_enable_write);
>>>> +
>>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
>>>> +
>>>> + MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
>>>> + MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
>>>> +
>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
>>>> + bxt_port_tx_dw3_read, NULL);
>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
>>>> +
>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
>>>> + bxt_port_tx_dw3_read, NULL);
>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
>>>> +
>>>> + MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>> + NULL, bxt_pcs_dw12_grp_write);
>>>> + MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
>>>> + bxt_port_tx_dw3_read, NULL);
>>>> + MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
>>>> + MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
>>>> +
>>>> + MMIO_D(BXT_DE_PLL_CTL, D_BXT);
>>>> + MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
>>>> + MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
>>>> + MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
>>>> +
>>>> + MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
>>>> + MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
>>>> +
>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
>>>> + MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
>>>> +
>>>> + MMIO_D(RC6_CTX_BASE, D_BXT);
>>>> +
>>>> + MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
>>>> + MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
>>>> + MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
>>>> + MMIO_D(GEN6_GFXPAUSE, D_BXT);
>>>> + MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> + MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> + 0, 0, D_BXT, NULL, NULL);
>>>> + MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> + 0, 0, D_BXT, NULL, NULL);
>>>> + MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> + 0, 0, D_BXT, NULL, NULL);
>>>> + MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
>>>> + 0, 0, D_BXT, NULL, NULL);
>>>> +
>>>> + MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
>>>> +
>>>> + MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static inline int intel_gvt_init_mmio_info(struct intel_gvt *gvt)
>>>> +{
>>>> + struct drm_i915_private *i915 = gvt->gt->i915;
>>>> + int ret;
>>>> +
>>>> + ret = intel_gvt_init_generic_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> +
>>>> + if (IS_BROADWELL(i915)) {
>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + } else if (IS_SKYLAKE(i915) ||
>>>> + IS_KABYLAKE(i915) ||
>>>> + IS_COFFEELAKE(i915) ||
>>>> + IS_COMETLAKE(i915)) {
>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + } else if (IS_BROXTON(i915)) {
>>>> + ret = intel_gvt_init_bdw_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + ret = intel_gvt_init_skl_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + ret = intel_gvt_init_bxt_mmio_info(gvt);
>>>> + if (ret)
>>>> + return ret;
>>>> + }
>>>> +
>>>> + return 0;
>>>> +}
>>>> +#endif
>>>> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
>>>> index 244cc7320b54..05bd2f8e9d94 100644
>>>> --- a/drivers/gpu/drm/i915/gvt/reg.h
>>>> +++ b/drivers/gpu/drm/i915/gvt/reg.h
>>>> @@ -133,6 +133,12 @@
>>>> #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
>>>> #define VF_GUARDBAND _MMIO(0x83a4)
>>>>
>>>> +/* XXX FIXME i915 has changed PP_XXX definition */
>>>> +#define PCH_PP_STATUS _MMIO(0xc7200)
>>>> +#define PCH_PP_CONTROL _MMIO(0xc7204)
>>>> +#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
>>>> +#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
>>>> +#define PCH_PP_DIVISOR _MMIO(0xc7210)
>>>>
>>>> #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
>>>> #endif
>>>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
>>>> index 4e70c1a9ef2e..64846d9bff0b 100644
>>>> --- a/drivers/gpu/drm/i915/intel_gvt.c
>>>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
>>>> @@ -86,6 +86,17 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>>>> dev_priv->params.enable_gvt = 0;
>>>> }
>>>>
>>>> +#define GENERATE_MMIO_TABLE_IN_I915
>>>> +static int new_mmio_info(struct intel_gvt *gvt, u64 offset)
>>>> +{
>>>> + return 0;
>>>> +}
>>>> +
>>>> +#include "gvt/reg.h"
>>>> +#include "gvt/mmio_table.h"
>>>> +#undef GENERATE_MMIO_TABLE_IN_I915
>>>> +
>>>> +
>>>> /**
>>>> * intel_gvt_init - initialize GVT components
>>>> * @dev_priv: drm i915 private data
>>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-09 10:51 ` [Intel-gfx] " Wang, Zhi A
@ 2021-11-09 10:58 ` hch
-1 siblings, 0 replies; 35+ messages in thread
From: hch @ 2021-11-09 10:58 UTC (permalink / raw)
To: Wang, Zhi A
Cc: hch, Jani Nikula, Zhi Wang, joonas.lahtinen, Vivi, Rodrigo,
zhenyuw, jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel
On Tue, Nov 09, 2021 at 10:51:27AM +0000, Wang, Zhi A wrote:
> Can you elaborate more about this? We need the hash query from the table
> ASAP when the hypervisor trapped a mmio access. It's a critical path and
> we tried different data structure in the kernel and the hash table gives
> the best performance.
Ok, I misunderstood the hashtable.h interface. hash_for_each_possible
actually does a hash lookup instead of an interation despite the rather
misleading name.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 10:58 ` hch
0 siblings, 0 replies; 35+ messages in thread
From: hch @ 2021-11-09 10:58 UTC (permalink / raw)
To: Wang, Zhi A
Cc: dri-devel, Zhi Wang, intel-gfx, linux-kernel, jgg, intel-gvt-dev, hch
On Tue, Nov 09, 2021 at 10:51:27AM +0000, Wang, Zhi A wrote:
> Can you elaborate more about this? We need the hash query from the table
> ASAP when the hypervisor trapped a mmio access. It's a critical path and
> we tried different data structure in the kernel and the hash table gives
> the best performance.
Ok, I misunderstood the hashtable.h interface. hash_for_each_possible
actually does a hash lookup instead of an interation despite the rather
misleading name.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-09 10:58 ` [Intel-gfx] " hch
(?)
@ 2021-11-09 11:02 ` Wang, Zhi A
-1 siblings, 0 replies; 35+ messages in thread
From: Wang, Zhi A @ 2021-11-09 11:02 UTC (permalink / raw)
To: hch
Cc: Jani Nikula, Zhi Wang, joonas.lahtinen, Vivi, Rodrigo, zhenyuw,
jgg, intel-gfx, intel-gvt-dev, dri-devel, linux-kernel
On 11/9/2021 12:58 PM, hch@lst.de wrote:
> On Tue, Nov 09, 2021 at 10:51:27AM +0000, Wang, Zhi A wrote:
>> Can you elaborate more about this? We need the hash query from the table
>> ASAP when the hypervisor trapped a mmio access. It's a critical path and
>> we tried different data structure in the kernel and the hash table gives
>> the best performance.
> Ok, I misunderstood the hashtable.h interface. hash_for_each_possible
> actually does a hash lookup instead of an interation despite the rather
> misleading name.
Yes. Maybe with a keyword "lookup" in the name of the interface would be
better since it's widely used in the kernel. :)
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 11:02 ` Wang, Zhi A
0 siblings, 0 replies; 35+ messages in thread
From: Wang, Zhi A @ 2021-11-09 11:02 UTC (permalink / raw)
To: hch
Cc: dri-devel, Zhi Wang, intel-gfx, linux-kernel, jgg, Vivi, Rodrigo,
intel-gvt-dev
On 11/9/2021 12:58 PM, hch@lst.de wrote:
> On Tue, Nov 09, 2021 at 10:51:27AM +0000, Wang, Zhi A wrote:
>> Can you elaborate more about this? We need the hash query from the table
>> ASAP when the hypervisor trapped a mmio access. It's a critical path and
>> we tried different data structure in the kernel and the hash table gives
>> the best performance.
> Ok, I misunderstood the hashtable.h interface. hash_for_each_possible
> actually does a hash lookup instead of an interation despite the rather
> misleading name.
Yes. Maybe with a keyword "lookup" in the name of the interface would be
better since it's widely used in the kernel. :)
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-09 11:02 ` Wang, Zhi A
0 siblings, 0 replies; 35+ messages in thread
From: Wang, Zhi A @ 2021-11-09 11:02 UTC (permalink / raw)
To: hch; +Cc: dri-devel, Zhi Wang, intel-gfx, linux-kernel, jgg, intel-gvt-dev
On 11/9/2021 12:58 PM, hch@lst.de wrote:
> On Tue, Nov 09, 2021 at 10:51:27AM +0000, Wang, Zhi A wrote:
>> Can you elaborate more about this? We need the hash query from the table
>> ASAP when the hypervisor trapped a mmio access. It's a critical path and
>> we tried different data structure in the kernel and the hash table gives
>> the best performance.
> Ok, I misunderstood the hashtable.h interface. hash_for_each_possible
> actually does a hash lookup instead of an interation despite the rather
> misleading name.
Yes. Maybe with a keyword "lookup" in the name of the interface would be
better since it's widely used in the kernel. :)
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-08 21:27 ` [Intel-gfx] " Zhi Wang
` (3 preceding siblings ...)
(?)
@ 2021-11-09 14:33 ` Patchwork
-1 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2021-11-09 14:33 UTC (permalink / raw)
To: Zhi Wang; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] i915/gvt: seperate tracked MMIO table from handlers.c
URL : https://patchwork.freedesktop.org/series/96704/
State : failure
== Summary ==
Applying: i915/gvt: seperate tracked MMIO table from handlers.c
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/gvt/gvt.h).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 i915/gvt: seperate tracked MMIO table from handlers.c
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
2021-11-08 21:27 ` [Intel-gfx] " Zhi Wang
(?)
@ 2021-11-11 23:32 ` kernel test robot
-1 siblings, 0 replies; 35+ messages in thread
From: kernel test robot @ 2021-11-11 23:32 UTC (permalink / raw)
To: Zhi Wang, jani.nikula, joonas.lahtinen, rodrigo.vivi, zhenyuw,
zhi.a.wang, jgg, intel-gfx, intel-gvt-dev, dri-devel,
linux-kernel
Cc: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 60730 bytes --]
Hi Zhi,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.15 next-20211111]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Zhi-Wang/i915-gvt-seperate-tracked-MMIO-table-from-handlers-c/20211109-052907
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/8d4393b277b5196206271d5191d25fe61b1b34f1
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Zhi-Wang/i915-gvt-seperate-tracked-MMIO-table-from-handlers-c/20211109-052907
git checkout 8d4393b277b5196206271d5191d25fe61b1b34f1
# save the attached .config to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from <command-line>:
drivers/gpu/drm/i915/gvt/mmio_table.h:85:52: error: 'struct intel_gvt' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
85 | static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
| ^~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h: In function 'intel_gvt_init_generic_mmio_info':
>> drivers/gpu/drm/i915/gvt/mmio_table.h:87:41: error: dereferencing pointer to incomplete type 'struct intel_gvt'
87 | struct drm_i915_private *dev_priv = gvt->gt->i915;
| ^~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:36:8: error: implicit declaration of function 'new_mmio_info' [-Werror=implicit-function-declaration]
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:2: note: in expansion of macro 'MMIO_F'
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:36:27: error: implicit declaration of function 'i915_mmio_reg_offset' [-Werror=implicit-function-declaration]
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:2: note: in expansion of macro 'MMIO_F'
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:16: error: implicit declaration of function 'RING_IMR' [-Werror=implicit-function-declaration]
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:62:16: error: 'RENDER_RING_BASE' undeclared (first use in this function)
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:16: note: each undeclared identifier is reported only once for each function it appears in
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:26: error: 'D_ALL' undeclared (first use in this function)
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:17: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:36: error: 'NULL' undeclared (first use in this function)
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:20: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:1:1: note: 'NULL' is defined in header '<stddef.h>'; did you forget to '#include <stddef.h>'?
+++ |+#include <stddef.h>
1 | /*
>> drivers/gpu/drm/i915/gvt/mmio_table.h:92:3: error: 'intel_vgpu_reg_imr_handler' undeclared (first use in this function)
92 | intel_vgpu_reg_imr_handler);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:63:16: error: 'BLT_RING_BASE' undeclared (first use in this function)
63 | MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:64:16: error: 'GEN6_BSD_RING_BASE' undeclared (first use in this function)
64 | MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:65:16: error: 'VEBOX_RING_BASE' undeclared (first use in this function)
65 | MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:66:6: error: implicit declaration of function 'HAS_ENGINE' [-Werror=implicit-function-declaration]
66 | if (HAS_ENGINE(gvt->gt, VCS1)) \
| ^~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:66:26: error: 'VCS1' undeclared (first use in this function)
66 | if (HAS_ENGINE(gvt->gt, VCS1)) \
| ^~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:67:17: error: 'GEN8_BSD2_RING_BASE' undeclared (first use in this function)
67 | MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:94:11: error: 'SDEIMR' undeclared (first use in this function)
94 | MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:94:2: note: in expansion of macro 'MMIO_DFH'
94 | MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:95:11: error: 'SDEIER' undeclared (first use in this function)
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:95:2: note: in expansion of macro 'MMIO_DFH'
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:95:35: error: 'intel_vgpu_reg_ier_handler' undeclared (first use in this function)
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:95:2: note: in expansion of macro 'MMIO_DFH'
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:96:11: error: 'SDEIIR' undeclared (first use in this function)
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:96:2: note: in expansion of macro 'MMIO_DFH'
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:96:35: error: 'intel_vgpu_reg_iir_handler' undeclared (first use in this function)
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:96:2: note: in expansion of macro 'MMIO_DFH'
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:97:9: error: 'SDEISR' undeclared (first use in this function)
97 | MMIO_D(SDEISR, D_ALL);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:97:2: note: in expansion of macro 'MMIO_D'
97 | MMIO_D(SDEISR, D_ALL);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:99:16: error: implicit declaration of function 'RING_HWSTAM' [-Werror=implicit-function-declaration]
99 | MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:99:2: note: in expansion of macro 'MMIO_RING_DFH'
99 | MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:102:10: error: 'GEN8_GAMW_ECO_DEV_RW_IA' undeclared (first use in this function)
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:102:35: error: 'D_BDW_PLUS' undeclared (first use in this function)
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:17: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:103:3: error: 'gamw_echo_dev_rw_ia_write' undeclared (first use in this function)
103 | gamw_echo_dev_rw_ia_write);
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:105:14: error: 'BSD_HWS_PGA_GEN7' undeclared (first use in this function)
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:56:17: error: 'F_GMADR' undeclared (first use in this function)
56 | MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:3: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:56:27: error: 'F_CMD_ACCESS' undeclared (first use in this function)
56 | MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:3: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:106:14: error: 'BLT_HWS_PGA_GEN7' undeclared (first use in this function)
106 | MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:106:2: note: in expansion of macro 'MMIO_GM_RDR'
106 | MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:107:14: error: 'VEBOX_HWS_PGA_GEN7' undeclared (first use in this function)
107 | MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:107:2: note: in expansion of macro 'MMIO_GM_RDR'
107 | MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:109:24: error: implicit declaration of function '_MMIO' [-Werror=implicit-function-declaration]
109 | #define RING_REG(base) _MMIO((base) + 0x28)
| ^~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:9: note: in expansion of macro 'RING_REG'
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
vim +87 drivers/gpu/drm/i915/gvt/mmio_table.h
27
28 #ifdef GENERATE_MMIO_TABLE_IN_I915
29 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
30 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
31 if (ret) \
32 return ret; \
33 } while (0)
34 #else
35 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> 36 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
37 f, s, am, rm, d, r, w); \
38 if (ret) \
39 return ret; \
40 } while (0)
41 #endif
42
43 #define MMIO_D(reg, d) \
44 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
45
46 #define MMIO_DH(reg, d, r, w) \
47 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
48
49 #define MMIO_DFH(reg, d, f, r, w) \
50 MMIO_F(reg, 4, f, 0, 0, d, r, w)
51
52 #define MMIO_GM(reg, d, r, w) \
53 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
54
55 #define MMIO_GM_RDR(reg, d, r, w) \
> 56 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
57
58 #define MMIO_RO(reg, d, f, rm, r, w) \
> 59 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
60
61 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
> 62 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
> 63 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> 64 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> 65 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> 66 if (HAS_ENGINE(gvt->gt, VCS1)) \
> 67 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
68 } while (0)
69
70 #define MMIO_RING_D(prefix, d) \
71 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
72
73 #define MMIO_RING_DFH(prefix, d, f, r, w) \
74 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
75
76 #define MMIO_RING_GM(prefix, d, r, w) \
77 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
78
79 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
80 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
81
82 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
83 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
84
85 static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
86 {
> 87 struct drm_i915_private *dev_priv = gvt->gt->i915;
88
89 int ret;
90
> 91 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
> 92 intel_vgpu_reg_imr_handler);
93
> 94 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
> 95 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
> 96 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
> 97 MMIO_D(SDEISR, D_ALL);
98
> 99 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
100
101
> 102 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
> 103 gamw_echo_dev_rw_ia_write);
104
> 105 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> 106 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> 107 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
108
> 109 #define RING_REG(base) _MMIO((base) + 0x28)
110 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
111 #undef RING_REG
112
113 #define RING_REG(base) _MMIO((base) + 0x134)
114 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
115 #undef RING_REG
116
117 #define RING_REG(base) _MMIO((base) + 0x6c)
> 118 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
119 #undef RING_REG
> 120 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
121
122 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
> 123 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
124 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
> 125 MMIO_D(GEN7_CXT_SIZE, D_ALL);
126
> 127 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
> 128 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
> 129 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
> 130 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
> 131 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
132
133 /* RING MODE */
134 #define RING_REG(base) _MMIO((base) + 0x29c)
135 MMIO_RING_DFH(RING_REG, D_ALL,
> 136 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
> 137 ring_mode_mmio_write);
138 #undef RING_REG
139
> 140 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
141 NULL, NULL);
> 142 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
143 NULL, NULL);
> 144 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
145 mmio_read_from_hw, NULL);
> 146 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
147 mmio_read_from_hw, NULL);
148
> 149 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 150 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
151 NULL, NULL);
> 152 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 153 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
154 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
155
156 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 157 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
158 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 159 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
160 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
161 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 162 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
> 163 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
164 NULL, NULL);
> 165 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
166 NULL, NULL);
167 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
168 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
169 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
170 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
171 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
172 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
173 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
174 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 175 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 176 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
177
178 /* display */
179 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
180 MMIO_D(_MMIO(0x602a0), D_ALL);
181
182 MMIO_D(_MMIO(0x65050), D_ALL);
183 MMIO_D(_MMIO(0x650b4), D_ALL);
184
185 MMIO_D(_MMIO(0xc4040), D_ALL);
> 186 MMIO_D(DERRMR, D_ALL);
187
> 188 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
> 189 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
> 190 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
> 191 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
192
> 193 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
194 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
195 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
196 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
197
> 198 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
199 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
200 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
201 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
202
> 203 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
204 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
205 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
206 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
207
> 208 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
209 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
210 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
211 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
212
> 213 MMIO_D(CURCNTR(PIPE_A), D_ALL);
214 MMIO_D(CURCNTR(PIPE_B), D_ALL);
215 MMIO_D(CURCNTR(PIPE_C), D_ALL);
216
> 217 MMIO_D(CURPOS(PIPE_A), D_ALL);
218 MMIO_D(CURPOS(PIPE_B), D_ALL);
219 MMIO_D(CURPOS(PIPE_C), D_ALL);
220
> 221 MMIO_D(CURBASE(PIPE_A), D_ALL);
222 MMIO_D(CURBASE(PIPE_B), D_ALL);
223 MMIO_D(CURBASE(PIPE_C), D_ALL);
224
> 225 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
226 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
227 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
228
229 MMIO_D(_MMIO(0x700ac), D_ALL);
230 MMIO_D(_MMIO(0x710ac), D_ALL);
231 MMIO_D(_MMIO(0x720ac), D_ALL);
232
233 MMIO_D(_MMIO(0x70090), D_ALL);
234 MMIO_D(_MMIO(0x70094), D_ALL);
235 MMIO_D(_MMIO(0x70098), D_ALL);
236 MMIO_D(_MMIO(0x7009c), D_ALL);
237
> 238 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
> 239 MMIO_D(DSPADDR(PIPE_A), D_ALL);
> 240 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
> 241 MMIO_D(DSPPOS(PIPE_A), D_ALL);
> 242 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
> 243 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> 244 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
> 245 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
> 246 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> 247 reg50080_mmio_write);
248
249 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
250 MMIO_D(DSPADDR(PIPE_B), D_ALL);
251 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
252 MMIO_D(DSPPOS(PIPE_B), D_ALL);
253 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
254 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
255 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
256 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
257 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
258 reg50080_mmio_write);
259
260 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
261 MMIO_D(DSPADDR(PIPE_C), D_ALL);
262 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
263 MMIO_D(DSPPOS(PIPE_C), D_ALL);
264 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
265 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
266 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
267 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
268 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
269 reg50080_mmio_write);
270
> 271 MMIO_D(SPRCTL(PIPE_A), D_ALL);
> 272 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
> 273 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
> 274 MMIO_D(SPRPOS(PIPE_A), D_ALL);
> 275 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
> 276 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
> 277 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
> 278 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
> 279 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
> 280 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
> 281 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
> 282 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
> 283 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
284 reg50080_mmio_write);
285
286 MMIO_D(SPRCTL(PIPE_B), D_ALL);
287 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
288 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
289 MMIO_D(SPRPOS(PIPE_B), D_ALL);
290 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
291 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
292 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
293 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
294 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
295 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
296 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
297 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
298 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
299 reg50080_mmio_write);
300
301 MMIO_D(SPRCTL(PIPE_C), D_ALL);
302 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
303 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
304 MMIO_D(SPRPOS(PIPE_C), D_ALL);
305 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
306 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
307 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
308 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
309 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
310 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
311 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
312 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
313 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
314 reg50080_mmio_write);
315
316 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
317 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
318 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
319 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
320 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
321 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
322 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
323 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
324 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
325
326 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
327 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
328 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
329 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
330 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
331 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
332 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
333 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
334 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
335
336 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
337 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
338 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
339 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
340 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
341 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
342 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
343 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
344 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
345
346 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
347 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
348 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
349 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
350 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
351 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
352 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
353 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
354
355 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
356 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
357 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
358 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
359 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
360 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
361 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
362 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
363
364 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
365 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
366 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
367 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
368 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
369 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
370 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
371 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
372
373 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
374 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
375 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
376 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
377 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
378 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
379 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
380 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
381
382 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
383 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
384 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
385 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
386 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
387 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
388 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
389 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
390
391 MMIO_D(PF_CTL(PIPE_A), D_ALL);
392 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
393 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
394 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
395 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
396
397 MMIO_D(PF_CTL(PIPE_B), D_ALL);
398 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
399 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
400 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
401 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
402
403 MMIO_D(PF_CTL(PIPE_C), D_ALL);
404 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
405 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
406 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
407 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
408
409 MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
410 MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
411 MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
412 MMIO_D(WM1_LP_ILK, D_ALL);
413 MMIO_D(WM2_LP_ILK, D_ALL);
414 MMIO_D(WM3_LP_ILK, D_ALL);
415 MMIO_D(WM1S_LP_ILK, D_ALL);
416 MMIO_D(WM2S_LP_IVB, D_ALL);
417 MMIO_D(WM3S_LP_IVB, D_ALL);
418
419 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
420 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
421 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
422 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
423
424 MMIO_D(_MMIO(0x48268), D_ALL);
425
426 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
427 gmbus_mmio_write);
428 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
429 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
430
431 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
432 dp_aux_ch_ctl_mmio_write);
433 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
434 dp_aux_ch_ctl_mmio_write);
435 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
436 dp_aux_ch_ctl_mmio_write);
437
438 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
439
440 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
441 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
442
443 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
444 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
445 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
446 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
447 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
448 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
449 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
450 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
451 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
452
453 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
454 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
455 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
456 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
457 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
458 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
459 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
460
461 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
462 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
463 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
464 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
465 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
466 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
467 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
468
469 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
470 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
471 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
472 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
473 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
474 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
475 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
476 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
477
478 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
479 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
480 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
481
482 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
483 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
484 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
485
486 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
487 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
488 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
489
490 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
491 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
492 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
493
494 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
495 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
496 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
497 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
498 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
499 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
500
501 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
502 MMIO_D(PCH_PP_DIVISOR, D_ALL);
503 MMIO_D(PCH_PP_STATUS, D_ALL);
504 MMIO_D(PCH_LVDS, D_ALL);
505 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
506 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
507 MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
508 MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
509 MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
510 MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
511 MMIO_D(PCH_DREF_CONTROL, D_ALL);
512 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
513 MMIO_D(PCH_DPLL_SEL, D_ALL);
514
515 MMIO_D(_MMIO(0x61208), D_ALL);
516 MMIO_D(_MMIO(0x6120c), D_ALL);
517 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
518 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
519
520 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
521 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
522 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
523 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
524 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
525 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
526
527 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
528 PORTA_HOTPLUG_STATUS_MASK
529 | PORTB_HOTPLUG_STATUS_MASK
530 | PORTC_HOTPLUG_STATUS_MASK
531 | PORTD_HOTPLUG_STATUS_MASK,
532 NULL, NULL);
533
534 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
535 MMIO_D(FUSE_STRAP, D_ALL);
536 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
537
538 MMIO_D(DISP_ARB_CTL, D_ALL);
539 MMIO_D(DISP_ARB_CTL2, D_ALL);
540
541 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
542 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
543 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
544
545 MMIO_D(SOUTH_CHICKEN1, D_ALL);
546 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
547 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
548 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
549 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
550 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
551 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
552
553 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
554 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
555 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
556 MMIO_D(ILK_DPFC_STATUS, D_ALL);
557 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
558 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
559 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
560
561 MMIO_D(IPS_CTL, D_ALL);
562
563 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
564 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
565 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
566 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
567 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
568 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
569 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
570 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
571 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
572 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
573 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
574 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
575 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
576
577 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
578 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
579 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
580 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
581 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
582 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
583 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
584 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
585 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
586 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
587 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
588 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
589 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
590
591 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
592 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
593 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
594 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
595 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
596 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
597 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
598 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
599 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
600 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
601 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
602 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
603 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
604
605 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
606 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
607 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
608
609 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
610 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
611 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
612
613 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
614 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
615 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
616
617 MMIO_D(_MMIO(0x60110), D_ALL);
618 MMIO_D(_MMIO(0x61110), D_ALL);
619 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
620 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
621 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
622 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
623 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
624 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
625 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
626 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
627 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
628
629 MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
630 MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
631 MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
632 MMIO_D(SPLL_CTL, D_ALL);
633 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
634 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
635 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
636 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
637 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
638 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
639 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
640 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
641 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
642 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
643
644 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
645 MMIO_D(_MMIO(0x46508), D_ALL);
646
647 MMIO_D(_MMIO(0x49080), D_ALL);
648 MMIO_D(_MMIO(0x49180), D_ALL);
649 MMIO_D(_MMIO(0x49280), D_ALL);
650
651 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
652 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
653 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
654
655 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
656 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
657 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
658
659 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
660 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
661 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
662
663 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
664 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
665 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
666
667 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
668 MMIO_D(SBI_ADDR, D_ALL);
669 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
670 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
671 MMIO_D(PIXCLK_GATE, D_ALL);
672
673 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
674 dp_aux_ch_ctl_mmio_write);
675
676 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
677 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
678 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
679 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
680 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
681
682 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
683 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
684 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
685 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
686 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
687
688 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
689 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
690 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
691 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
692 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
693
694 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
695 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
696 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
697 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
698 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
699
700 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
701 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
702 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
703
704 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
705 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
706 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
707 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
708
709 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
710 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
711 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
712 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
713
714 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
715 MMIO_D(FORCEWAKE_ACK, D_ALL);
716 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
717 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
718 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
719 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
720 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
721 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
722 MMIO_D(ECOBUS, D_ALL);
723 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
724 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
725 MMIO_D(GEN6_RPNSWREQ, D_ALL);
726 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
727 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
728 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
729 MMIO_D(GEN6_RPSTAT1, D_ALL);
730 MMIO_D(GEN6_RP_CONTROL, D_ALL);
731 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
732 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
733 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
734 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
735 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
736 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
737 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
738 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
739 MMIO_D(GEN6_RP_UP_EI, D_ALL);
740 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
741 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
742 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
743 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
744 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
745 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
746 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
747 MMIO_D(GEN6_RC_SLEEP, D_ALL);
748 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
749 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
750 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
751 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
752 MMIO_D(GEN6_PMINTRMSK, D_ALL);
753 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
754 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
755 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
756 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
757 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
758 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
759
760 MMIO_D(RSTDBYCTL, D_ALL);
761
762 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
763 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
764 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
765
766 MMIO_D(TILECTL, D_ALL);
767
768 MMIO_D(GEN6_UCGCTL1, D_ALL);
769 MMIO_D(GEN6_UCGCTL2, D_ALL);
770
771 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
772
773 MMIO_D(GEN6_PCODE_DATA, D_ALL);
774 MMIO_D(_MMIO(0x13812c), D_ALL);
775 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
776 MMIO_D(HSW_EDRAM_CAP, D_ALL);
777 MMIO_D(HSW_IDICR, D_ALL);
778 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
779
780 MMIO_D(_MMIO(0x3c), D_ALL);
781 MMIO_D(_MMIO(0x860), D_ALL);
782 MMIO_D(ECOSKPD, D_ALL);
783 MMIO_D(_MMIO(0x121d0), D_ALL);
784 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
785 MMIO_D(_MMIO(0x41d0), D_ALL);
786 MMIO_D(GAC_ECO_BITS, D_ALL);
787 MMIO_D(_MMIO(0x6200), D_ALL);
788 MMIO_D(_MMIO(0x6204), D_ALL);
789 MMIO_D(_MMIO(0x6208), D_ALL);
790 MMIO_D(_MMIO(0x7118), D_ALL);
791 MMIO_D(_MMIO(0x7180), D_ALL);
792 MMIO_D(_MMIO(0x7408), D_ALL);
793 MMIO_D(_MMIO(0x7c00), D_ALL);
794 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
795 MMIO_D(_MMIO(0x911c), D_ALL);
796 MMIO_D(_MMIO(0x9120), D_ALL);
797 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
798
799 MMIO_D(GAB_CTL, D_ALL);
800 MMIO_D(_MMIO(0x48800), D_ALL);
801 MMIO_D(_MMIO(0xce044), D_ALL);
802 MMIO_D(_MMIO(0xe6500), D_ALL);
803 MMIO_D(_MMIO(0xe6504), D_ALL);
804 MMIO_D(_MMIO(0xe6600), D_ALL);
805 MMIO_D(_MMIO(0xe6604), D_ALL);
806 MMIO_D(_MMIO(0xe6700), D_ALL);
807 MMIO_D(_MMIO(0xe6704), D_ALL);
808 MMIO_D(_MMIO(0xe6800), D_ALL);
809 MMIO_D(_MMIO(0xe6804), D_ALL);
810 MMIO_D(PCH_GMBUS4, D_ALL);
811 MMIO_D(PCH_GMBUS5, D_ALL);
812
813 MMIO_D(_MMIO(0x902c), D_ALL);
814 MMIO_D(_MMIO(0xec008), D_ALL);
815 MMIO_D(_MMIO(0xec00c), D_ALL);
816 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
817 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
818 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
819 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
820 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
821 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
822 MMIO_D(_MMIO(0xec408), D_ALL);
823 MMIO_D(_MMIO(0xec40c), D_ALL);
824 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
825 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
826 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
827 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
828 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
829 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
830 MMIO_D(_MMIO(0xfc810), D_ALL);
831 MMIO_D(_MMIO(0xfc81c), D_ALL);
832 MMIO_D(_MMIO(0xfc828), D_ALL);
833 MMIO_D(_MMIO(0xfc834), D_ALL);
834 MMIO_D(_MMIO(0xfcc00), D_ALL);
835 MMIO_D(_MMIO(0xfcc0c), D_ALL);
836 MMIO_D(_MMIO(0xfcc18), D_ALL);
837 MMIO_D(_MMIO(0xfcc24), D_ALL);
838 MMIO_D(_MMIO(0xfd000), D_ALL);
839 MMIO_D(_MMIO(0xfd00c), D_ALL);
840 MMIO_D(_MMIO(0xfd018), D_ALL);
841 MMIO_D(_MMIO(0xfd024), D_ALL);
842 MMIO_D(_MMIO(0xfd034), D_ALL);
843
844 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
845 MMIO_D(_MMIO(0x2054), D_ALL);
846 MMIO_D(_MMIO(0x12054), D_ALL);
847 MMIO_D(_MMIO(0x22054), D_ALL);
848 MMIO_D(_MMIO(0x1a054), D_ALL);
849
850 MMIO_D(_MMIO(0x44070), D_ALL);
851 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
852 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
853 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
854 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
855 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
856
857 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
858 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
859 MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
860 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
861 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
862 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
863
864 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
865 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
866 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
867
868 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
869 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
870 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
871 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
872 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
873 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
874 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
875 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
876 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
877 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
878 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
879 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
880 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
881 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
882 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
883 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
884 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
885
886 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
887 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
888 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
889 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
890 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
891 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
892 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
893 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
894 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
895 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
896 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
897
898 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
899 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
900 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
901
902 return 0;
903 }
904
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
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^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-11 23:32 ` kernel test robot
0 siblings, 0 replies; 35+ messages in thread
From: kernel test robot @ 2021-11-11 23:32 UTC (permalink / raw)
To: Zhi Wang, jani.nikula, joonas.lahtinen, rodrigo.vivi, zhenyuw,
zhi.a.wang, jgg, intel-gfx, intel-gvt-dev, dri-devel,
linux-kernel
Cc: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 60730 bytes --]
Hi Zhi,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.15 next-20211111]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Zhi-Wang/i915-gvt-seperate-tracked-MMIO-table-from-handlers-c/20211109-052907
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/8d4393b277b5196206271d5191d25fe61b1b34f1
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Zhi-Wang/i915-gvt-seperate-tracked-MMIO-table-from-handlers-c/20211109-052907
git checkout 8d4393b277b5196206271d5191d25fe61b1b34f1
# save the attached .config to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from <command-line>:
drivers/gpu/drm/i915/gvt/mmio_table.h:85:52: error: 'struct intel_gvt' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
85 | static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
| ^~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h: In function 'intel_gvt_init_generic_mmio_info':
>> drivers/gpu/drm/i915/gvt/mmio_table.h:87:41: error: dereferencing pointer to incomplete type 'struct intel_gvt'
87 | struct drm_i915_private *dev_priv = gvt->gt->i915;
| ^~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:36:8: error: implicit declaration of function 'new_mmio_info' [-Werror=implicit-function-declaration]
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:2: note: in expansion of macro 'MMIO_F'
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:36:27: error: implicit declaration of function 'i915_mmio_reg_offset' [-Werror=implicit-function-declaration]
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:2: note: in expansion of macro 'MMIO_F'
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:16: error: implicit declaration of function 'RING_IMR' [-Werror=implicit-function-declaration]
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:62:16: error: 'RENDER_RING_BASE' undeclared (first use in this function)
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:16: note: each undeclared identifier is reported only once for each function it appears in
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:26: error: 'D_ALL' undeclared (first use in this function)
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:17: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:36: error: 'NULL' undeclared (first use in this function)
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:20: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:1:1: note: 'NULL' is defined in header '<stddef.h>'; did you forget to '#include <stddef.h>'?
+++ |+#include <stddef.h>
1 | /*
>> drivers/gpu/drm/i915/gvt/mmio_table.h:92:3: error: 'intel_vgpu_reg_imr_handler' undeclared (first use in this function)
92 | intel_vgpu_reg_imr_handler);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:63:16: error: 'BLT_RING_BASE' undeclared (first use in this function)
63 | MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:64:16: error: 'GEN6_BSD_RING_BASE' undeclared (first use in this function)
64 | MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:65:16: error: 'VEBOX_RING_BASE' undeclared (first use in this function)
65 | MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:66:6: error: implicit declaration of function 'HAS_ENGINE' [-Werror=implicit-function-declaration]
66 | if (HAS_ENGINE(gvt->gt, VCS1)) \
| ^~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:66:26: error: 'VCS1' undeclared (first use in this function)
66 | if (HAS_ENGINE(gvt->gt, VCS1)) \
| ^~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:67:17: error: 'GEN8_BSD2_RING_BASE' undeclared (first use in this function)
67 | MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:94:11: error: 'SDEIMR' undeclared (first use in this function)
94 | MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:94:2: note: in expansion of macro 'MMIO_DFH'
94 | MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:95:11: error: 'SDEIER' undeclared (first use in this function)
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:95:2: note: in expansion of macro 'MMIO_DFH'
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:95:35: error: 'intel_vgpu_reg_ier_handler' undeclared (first use in this function)
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:95:2: note: in expansion of macro 'MMIO_DFH'
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:96:11: error: 'SDEIIR' undeclared (first use in this function)
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:96:2: note: in expansion of macro 'MMIO_DFH'
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:96:35: error: 'intel_vgpu_reg_iir_handler' undeclared (first use in this function)
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:96:2: note: in expansion of macro 'MMIO_DFH'
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:97:9: error: 'SDEISR' undeclared (first use in this function)
97 | MMIO_D(SDEISR, D_ALL);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:97:2: note: in expansion of macro 'MMIO_D'
97 | MMIO_D(SDEISR, D_ALL);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:99:16: error: implicit declaration of function 'RING_HWSTAM' [-Werror=implicit-function-declaration]
99 | MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:99:2: note: in expansion of macro 'MMIO_RING_DFH'
99 | MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:102:10: error: 'GEN8_GAMW_ECO_DEV_RW_IA' undeclared (first use in this function)
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:102:35: error: 'D_BDW_PLUS' undeclared (first use in this function)
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:17: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:103:3: error: 'gamw_echo_dev_rw_ia_write' undeclared (first use in this function)
103 | gamw_echo_dev_rw_ia_write);
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:105:14: error: 'BSD_HWS_PGA_GEN7' undeclared (first use in this function)
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:56:17: error: 'F_GMADR' undeclared (first use in this function)
56 | MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:3: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:56:27: error: 'F_CMD_ACCESS' undeclared (first use in this function)
56 | MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:3: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:106:14: error: 'BLT_HWS_PGA_GEN7' undeclared (first use in this function)
106 | MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:106:2: note: in expansion of macro 'MMIO_GM_RDR'
106 | MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:107:14: error: 'VEBOX_HWS_PGA_GEN7' undeclared (first use in this function)
107 | MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:107:2: note: in expansion of macro 'MMIO_GM_RDR'
107 | MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:109:24: error: implicit declaration of function '_MMIO' [-Werror=implicit-function-declaration]
109 | #define RING_REG(base) _MMIO((base) + 0x28)
| ^~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:9: note: in expansion of macro 'RING_REG'
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
vim +87 drivers/gpu/drm/i915/gvt/mmio_table.h
27
28 #ifdef GENERATE_MMIO_TABLE_IN_I915
29 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
30 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
31 if (ret) \
32 return ret; \
33 } while (0)
34 #else
35 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> 36 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
37 f, s, am, rm, d, r, w); \
38 if (ret) \
39 return ret; \
40 } while (0)
41 #endif
42
43 #define MMIO_D(reg, d) \
44 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
45
46 #define MMIO_DH(reg, d, r, w) \
47 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
48
49 #define MMIO_DFH(reg, d, f, r, w) \
50 MMIO_F(reg, 4, f, 0, 0, d, r, w)
51
52 #define MMIO_GM(reg, d, r, w) \
53 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
54
55 #define MMIO_GM_RDR(reg, d, r, w) \
> 56 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
57
58 #define MMIO_RO(reg, d, f, rm, r, w) \
> 59 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
60
61 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
> 62 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
> 63 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> 64 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> 65 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> 66 if (HAS_ENGINE(gvt->gt, VCS1)) \
> 67 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
68 } while (0)
69
70 #define MMIO_RING_D(prefix, d) \
71 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
72
73 #define MMIO_RING_DFH(prefix, d, f, r, w) \
74 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
75
76 #define MMIO_RING_GM(prefix, d, r, w) \
77 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
78
79 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
80 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
81
82 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
83 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
84
85 static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
86 {
> 87 struct drm_i915_private *dev_priv = gvt->gt->i915;
88
89 int ret;
90
> 91 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
> 92 intel_vgpu_reg_imr_handler);
93
> 94 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
> 95 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
> 96 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
> 97 MMIO_D(SDEISR, D_ALL);
98
> 99 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
100
101
> 102 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
> 103 gamw_echo_dev_rw_ia_write);
104
> 105 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> 106 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> 107 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
108
> 109 #define RING_REG(base) _MMIO((base) + 0x28)
110 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
111 #undef RING_REG
112
113 #define RING_REG(base) _MMIO((base) + 0x134)
114 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
115 #undef RING_REG
116
117 #define RING_REG(base) _MMIO((base) + 0x6c)
> 118 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
119 #undef RING_REG
> 120 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
121
122 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
> 123 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
124 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
> 125 MMIO_D(GEN7_CXT_SIZE, D_ALL);
126
> 127 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
> 128 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
> 129 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
> 130 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
> 131 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
132
133 /* RING MODE */
134 #define RING_REG(base) _MMIO((base) + 0x29c)
135 MMIO_RING_DFH(RING_REG, D_ALL,
> 136 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
> 137 ring_mode_mmio_write);
138 #undef RING_REG
139
> 140 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
141 NULL, NULL);
> 142 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
143 NULL, NULL);
> 144 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
145 mmio_read_from_hw, NULL);
> 146 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
147 mmio_read_from_hw, NULL);
148
> 149 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 150 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
151 NULL, NULL);
> 152 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 153 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
154 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
155
156 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 157 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
158 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 159 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
160 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
161 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 162 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
> 163 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
164 NULL, NULL);
> 165 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
166 NULL, NULL);
167 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
168 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
169 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
170 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
171 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
172 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
173 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
174 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 175 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 176 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
177
178 /* display */
179 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
180 MMIO_D(_MMIO(0x602a0), D_ALL);
181
182 MMIO_D(_MMIO(0x65050), D_ALL);
183 MMIO_D(_MMIO(0x650b4), D_ALL);
184
185 MMIO_D(_MMIO(0xc4040), D_ALL);
> 186 MMIO_D(DERRMR, D_ALL);
187
> 188 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
> 189 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
> 190 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
> 191 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
192
> 193 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
194 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
195 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
196 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
197
> 198 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
199 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
200 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
201 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
202
> 203 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
204 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
205 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
206 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
207
> 208 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
209 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
210 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
211 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
212
> 213 MMIO_D(CURCNTR(PIPE_A), D_ALL);
214 MMIO_D(CURCNTR(PIPE_B), D_ALL);
215 MMIO_D(CURCNTR(PIPE_C), D_ALL);
216
> 217 MMIO_D(CURPOS(PIPE_A), D_ALL);
218 MMIO_D(CURPOS(PIPE_B), D_ALL);
219 MMIO_D(CURPOS(PIPE_C), D_ALL);
220
> 221 MMIO_D(CURBASE(PIPE_A), D_ALL);
222 MMIO_D(CURBASE(PIPE_B), D_ALL);
223 MMIO_D(CURBASE(PIPE_C), D_ALL);
224
> 225 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
226 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
227 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
228
229 MMIO_D(_MMIO(0x700ac), D_ALL);
230 MMIO_D(_MMIO(0x710ac), D_ALL);
231 MMIO_D(_MMIO(0x720ac), D_ALL);
232
233 MMIO_D(_MMIO(0x70090), D_ALL);
234 MMIO_D(_MMIO(0x70094), D_ALL);
235 MMIO_D(_MMIO(0x70098), D_ALL);
236 MMIO_D(_MMIO(0x7009c), D_ALL);
237
> 238 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
> 239 MMIO_D(DSPADDR(PIPE_A), D_ALL);
> 240 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
> 241 MMIO_D(DSPPOS(PIPE_A), D_ALL);
> 242 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
> 243 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> 244 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
> 245 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
> 246 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> 247 reg50080_mmio_write);
248
249 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
250 MMIO_D(DSPADDR(PIPE_B), D_ALL);
251 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
252 MMIO_D(DSPPOS(PIPE_B), D_ALL);
253 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
254 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
255 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
256 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
257 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
258 reg50080_mmio_write);
259
260 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
261 MMIO_D(DSPADDR(PIPE_C), D_ALL);
262 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
263 MMIO_D(DSPPOS(PIPE_C), D_ALL);
264 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
265 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
266 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
267 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
268 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
269 reg50080_mmio_write);
270
> 271 MMIO_D(SPRCTL(PIPE_A), D_ALL);
> 272 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
> 273 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
> 274 MMIO_D(SPRPOS(PIPE_A), D_ALL);
> 275 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
> 276 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
> 277 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
> 278 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
> 279 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
> 280 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
> 281 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
> 282 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
> 283 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
284 reg50080_mmio_write);
285
286 MMIO_D(SPRCTL(PIPE_B), D_ALL);
287 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
288 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
289 MMIO_D(SPRPOS(PIPE_B), D_ALL);
290 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
291 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
292 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
293 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
294 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
295 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
296 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
297 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
298 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
299 reg50080_mmio_write);
300
301 MMIO_D(SPRCTL(PIPE_C), D_ALL);
302 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
303 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
304 MMIO_D(SPRPOS(PIPE_C), D_ALL);
305 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
306 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
307 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
308 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
309 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
310 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
311 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
312 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
313 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
314 reg50080_mmio_write);
315
316 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
317 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
318 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
319 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
320 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
321 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
322 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
323 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
324 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
325
326 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
327 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
328 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
329 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
330 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
331 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
332 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
333 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
334 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
335
336 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
337 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
338 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
339 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
340 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
341 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
342 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
343 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
344 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
345
346 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
347 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
348 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
349 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
350 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
351 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
352 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
353 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
354
355 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
356 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
357 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
358 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
359 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
360 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
361 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
362 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
363
364 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
365 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
366 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
367 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
368 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
369 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
370 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
371 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
372
373 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
374 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
375 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
376 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
377 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
378 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
379 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
380 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
381
382 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
383 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
384 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
385 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
386 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
387 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
388 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
389 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
390
391 MMIO_D(PF_CTL(PIPE_A), D_ALL);
392 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
393 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
394 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
395 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
396
397 MMIO_D(PF_CTL(PIPE_B), D_ALL);
398 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
399 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
400 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
401 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
402
403 MMIO_D(PF_CTL(PIPE_C), D_ALL);
404 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
405 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
406 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
407 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
408
409 MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
410 MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
411 MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
412 MMIO_D(WM1_LP_ILK, D_ALL);
413 MMIO_D(WM2_LP_ILK, D_ALL);
414 MMIO_D(WM3_LP_ILK, D_ALL);
415 MMIO_D(WM1S_LP_ILK, D_ALL);
416 MMIO_D(WM2S_LP_IVB, D_ALL);
417 MMIO_D(WM3S_LP_IVB, D_ALL);
418
419 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
420 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
421 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
422 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
423
424 MMIO_D(_MMIO(0x48268), D_ALL);
425
426 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
427 gmbus_mmio_write);
428 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
429 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
430
431 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
432 dp_aux_ch_ctl_mmio_write);
433 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
434 dp_aux_ch_ctl_mmio_write);
435 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
436 dp_aux_ch_ctl_mmio_write);
437
438 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
439
440 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
441 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
442
443 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
444 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
445 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
446 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
447 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
448 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
449 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
450 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
451 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
452
453 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
454 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
455 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
456 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
457 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
458 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
459 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
460
461 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
462 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
463 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
464 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
465 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
466 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
467 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
468
469 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
470 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
471 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
472 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
473 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
474 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
475 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
476 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
477
478 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
479 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
480 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
481
482 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
483 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
484 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
485
486 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
487 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
488 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
489
490 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
491 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
492 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
493
494 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
495 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
496 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
497 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
498 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
499 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
500
501 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
502 MMIO_D(PCH_PP_DIVISOR, D_ALL);
503 MMIO_D(PCH_PP_STATUS, D_ALL);
504 MMIO_D(PCH_LVDS, D_ALL);
505 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
506 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
507 MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
508 MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
509 MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
510 MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
511 MMIO_D(PCH_DREF_CONTROL, D_ALL);
512 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
513 MMIO_D(PCH_DPLL_SEL, D_ALL);
514
515 MMIO_D(_MMIO(0x61208), D_ALL);
516 MMIO_D(_MMIO(0x6120c), D_ALL);
517 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
518 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
519
520 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
521 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
522 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
523 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
524 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
525 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
526
527 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
528 PORTA_HOTPLUG_STATUS_MASK
529 | PORTB_HOTPLUG_STATUS_MASK
530 | PORTC_HOTPLUG_STATUS_MASK
531 | PORTD_HOTPLUG_STATUS_MASK,
532 NULL, NULL);
533
534 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
535 MMIO_D(FUSE_STRAP, D_ALL);
536 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
537
538 MMIO_D(DISP_ARB_CTL, D_ALL);
539 MMIO_D(DISP_ARB_CTL2, D_ALL);
540
541 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
542 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
543 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
544
545 MMIO_D(SOUTH_CHICKEN1, D_ALL);
546 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
547 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
548 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
549 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
550 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
551 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
552
553 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
554 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
555 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
556 MMIO_D(ILK_DPFC_STATUS, D_ALL);
557 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
558 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
559 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
560
561 MMIO_D(IPS_CTL, D_ALL);
562
563 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
564 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
565 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
566 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
567 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
568 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
569 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
570 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
571 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
572 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
573 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
574 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
575 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
576
577 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
578 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
579 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
580 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
581 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
582 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
583 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
584 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
585 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
586 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
587 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
588 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
589 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
590
591 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
592 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
593 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
594 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
595 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
596 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
597 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
598 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
599 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
600 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
601 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
602 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
603 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
604
605 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
606 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
607 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
608
609 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
610 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
611 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
612
613 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
614 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
615 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
616
617 MMIO_D(_MMIO(0x60110), D_ALL);
618 MMIO_D(_MMIO(0x61110), D_ALL);
619 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
620 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
621 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
622 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
623 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
624 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
625 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
626 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
627 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
628
629 MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
630 MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
631 MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
632 MMIO_D(SPLL_CTL, D_ALL);
633 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
634 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
635 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
636 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
637 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
638 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
639 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
640 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
641 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
642 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
643
644 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
645 MMIO_D(_MMIO(0x46508), D_ALL);
646
647 MMIO_D(_MMIO(0x49080), D_ALL);
648 MMIO_D(_MMIO(0x49180), D_ALL);
649 MMIO_D(_MMIO(0x49280), D_ALL);
650
651 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
652 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
653 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
654
655 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
656 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
657 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
658
659 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
660 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
661 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
662
663 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
664 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
665 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
666
667 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
668 MMIO_D(SBI_ADDR, D_ALL);
669 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
670 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
671 MMIO_D(PIXCLK_GATE, D_ALL);
672
673 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
674 dp_aux_ch_ctl_mmio_write);
675
676 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
677 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
678 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
679 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
680 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
681
682 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
683 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
684 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
685 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
686 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
687
688 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
689 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
690 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
691 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
692 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
693
694 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
695 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
696 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
697 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
698 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
699
700 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
701 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
702 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
703
704 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
705 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
706 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
707 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
708
709 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
710 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
711 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
712 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
713
714 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
715 MMIO_D(FORCEWAKE_ACK, D_ALL);
716 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
717 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
718 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
719 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
720 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
721 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
722 MMIO_D(ECOBUS, D_ALL);
723 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
724 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
725 MMIO_D(GEN6_RPNSWREQ, D_ALL);
726 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
727 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
728 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
729 MMIO_D(GEN6_RPSTAT1, D_ALL);
730 MMIO_D(GEN6_RP_CONTROL, D_ALL);
731 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
732 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
733 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
734 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
735 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
736 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
737 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
738 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
739 MMIO_D(GEN6_RP_UP_EI, D_ALL);
740 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
741 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
742 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
743 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
744 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
745 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
746 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
747 MMIO_D(GEN6_RC_SLEEP, D_ALL);
748 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
749 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
750 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
751 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
752 MMIO_D(GEN6_PMINTRMSK, D_ALL);
753 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
754 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
755 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
756 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
757 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
758 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
759
760 MMIO_D(RSTDBYCTL, D_ALL);
761
762 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
763 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
764 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
765
766 MMIO_D(TILECTL, D_ALL);
767
768 MMIO_D(GEN6_UCGCTL1, D_ALL);
769 MMIO_D(GEN6_UCGCTL2, D_ALL);
770
771 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
772
773 MMIO_D(GEN6_PCODE_DATA, D_ALL);
774 MMIO_D(_MMIO(0x13812c), D_ALL);
775 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
776 MMIO_D(HSW_EDRAM_CAP, D_ALL);
777 MMIO_D(HSW_IDICR, D_ALL);
778 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
779
780 MMIO_D(_MMIO(0x3c), D_ALL);
781 MMIO_D(_MMIO(0x860), D_ALL);
782 MMIO_D(ECOSKPD, D_ALL);
783 MMIO_D(_MMIO(0x121d0), D_ALL);
784 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
785 MMIO_D(_MMIO(0x41d0), D_ALL);
786 MMIO_D(GAC_ECO_BITS, D_ALL);
787 MMIO_D(_MMIO(0x6200), D_ALL);
788 MMIO_D(_MMIO(0x6204), D_ALL);
789 MMIO_D(_MMIO(0x6208), D_ALL);
790 MMIO_D(_MMIO(0x7118), D_ALL);
791 MMIO_D(_MMIO(0x7180), D_ALL);
792 MMIO_D(_MMIO(0x7408), D_ALL);
793 MMIO_D(_MMIO(0x7c00), D_ALL);
794 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
795 MMIO_D(_MMIO(0x911c), D_ALL);
796 MMIO_D(_MMIO(0x9120), D_ALL);
797 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
798
799 MMIO_D(GAB_CTL, D_ALL);
800 MMIO_D(_MMIO(0x48800), D_ALL);
801 MMIO_D(_MMIO(0xce044), D_ALL);
802 MMIO_D(_MMIO(0xe6500), D_ALL);
803 MMIO_D(_MMIO(0xe6504), D_ALL);
804 MMIO_D(_MMIO(0xe6600), D_ALL);
805 MMIO_D(_MMIO(0xe6604), D_ALL);
806 MMIO_D(_MMIO(0xe6700), D_ALL);
807 MMIO_D(_MMIO(0xe6704), D_ALL);
808 MMIO_D(_MMIO(0xe6800), D_ALL);
809 MMIO_D(_MMIO(0xe6804), D_ALL);
810 MMIO_D(PCH_GMBUS4, D_ALL);
811 MMIO_D(PCH_GMBUS5, D_ALL);
812
813 MMIO_D(_MMIO(0x902c), D_ALL);
814 MMIO_D(_MMIO(0xec008), D_ALL);
815 MMIO_D(_MMIO(0xec00c), D_ALL);
816 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
817 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
818 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
819 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
820 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
821 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
822 MMIO_D(_MMIO(0xec408), D_ALL);
823 MMIO_D(_MMIO(0xec40c), D_ALL);
824 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
825 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
826 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
827 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
828 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
829 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
830 MMIO_D(_MMIO(0xfc810), D_ALL);
831 MMIO_D(_MMIO(0xfc81c), D_ALL);
832 MMIO_D(_MMIO(0xfc828), D_ALL);
833 MMIO_D(_MMIO(0xfc834), D_ALL);
834 MMIO_D(_MMIO(0xfcc00), D_ALL);
835 MMIO_D(_MMIO(0xfcc0c), D_ALL);
836 MMIO_D(_MMIO(0xfcc18), D_ALL);
837 MMIO_D(_MMIO(0xfcc24), D_ALL);
838 MMIO_D(_MMIO(0xfd000), D_ALL);
839 MMIO_D(_MMIO(0xfd00c), D_ALL);
840 MMIO_D(_MMIO(0xfd018), D_ALL);
841 MMIO_D(_MMIO(0xfd024), D_ALL);
842 MMIO_D(_MMIO(0xfd034), D_ALL);
843
844 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
845 MMIO_D(_MMIO(0x2054), D_ALL);
846 MMIO_D(_MMIO(0x12054), D_ALL);
847 MMIO_D(_MMIO(0x22054), D_ALL);
848 MMIO_D(_MMIO(0x1a054), D_ALL);
849
850 MMIO_D(_MMIO(0x44070), D_ALL);
851 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
852 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
853 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
854 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
855 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
856
857 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
858 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
859 MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
860 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
861 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
862 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
863
864 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
865 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
866 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
867
868 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
869 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
870 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
871 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
872 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
873 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
874 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
875 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
876 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
877 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
878 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
879 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
880 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
881 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
882 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
883 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
884 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
885
886 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
887 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
888 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
889 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
890 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
891 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
892 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
893 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
894 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
895 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
896 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
897
898 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
899 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
900 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
901
902 return 0;
903 }
904
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
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^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c
@ 2021-11-11 23:32 ` kernel test robot
0 siblings, 0 replies; 35+ messages in thread
From: kernel test robot @ 2021-11-11 23:32 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 61965 bytes --]
Hi Zhi,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.15 next-20211111]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Zhi-Wang/i915-gvt-seperate-tracked-MMIO-table-from-handlers-c/20211109-052907
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/8d4393b277b5196206271d5191d25fe61b1b34f1
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Zhi-Wang/i915-gvt-seperate-tracked-MMIO-table-from-handlers-c/20211109-052907
git checkout 8d4393b277b5196206271d5191d25fe61b1b34f1
# save the attached .config to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from <command-line>:
drivers/gpu/drm/i915/gvt/mmio_table.h:85:52: error: 'struct intel_gvt' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
85 | static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
| ^~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h: In function 'intel_gvt_init_generic_mmio_info':
>> drivers/gpu/drm/i915/gvt/mmio_table.h:87:41: error: dereferencing pointer to incomplete type 'struct intel_gvt'
87 | struct drm_i915_private *dev_priv = gvt->gt->i915;
| ^~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:36:8: error: implicit declaration of function 'new_mmio_info' [-Werror=implicit-function-declaration]
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:2: note: in expansion of macro 'MMIO_F'
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:36:27: error: implicit declaration of function 'i915_mmio_reg_offset' [-Werror=implicit-function-declaration]
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:2: note: in expansion of macro 'MMIO_F'
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:16: error: implicit declaration of function 'RING_IMR' [-Werror=implicit-function-declaration]
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:62:16: error: 'RENDER_RING_BASE' undeclared (first use in this function)
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:16: note: each undeclared identifier is reported only once for each function it appears in
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:26: error: 'D_ALL' undeclared (first use in this function)
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:17: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:36: error: 'NULL' undeclared (first use in this function)
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:20: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:1:1: note: 'NULL' is defined in header '<stddef.h>'; did you forget to '#include <stddef.h>'?
+++ |+#include <stddef.h>
1 | /*
>> drivers/gpu/drm/i915/gvt/mmio_table.h:92:3: error: 'intel_vgpu_reg_imr_handler' undeclared (first use in this function)
92 | intel_vgpu_reg_imr_handler);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:63:16: error: 'BLT_RING_BASE' undeclared (first use in this function)
63 | MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:64:16: error: 'GEN6_BSD_RING_BASE' undeclared (first use in this function)
64 | MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:65:16: error: 'VEBOX_RING_BASE' undeclared (first use in this function)
65 | MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:66:6: error: implicit declaration of function 'HAS_ENGINE' [-Werror=implicit-function-declaration]
66 | if (HAS_ENGINE(gvt->gt, VCS1)) \
| ^~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:66:26: error: 'VCS1' undeclared (first use in this function)
66 | if (HAS_ENGINE(gvt->gt, VCS1)) \
| ^~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:67:17: error: 'GEN8_BSD2_RING_BASE' undeclared (first use in this function)
67 | MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
91 | MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
| ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:94:11: error: 'SDEIMR' undeclared (first use in this function)
94 | MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:94:2: note: in expansion of macro 'MMIO_DFH'
94 | MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:95:11: error: 'SDEIER' undeclared (first use in this function)
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:95:2: note: in expansion of macro 'MMIO_DFH'
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:95:35: error: 'intel_vgpu_reg_ier_handler' undeclared (first use in this function)
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:95:2: note: in expansion of macro 'MMIO_DFH'
95 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:96:11: error: 'SDEIIR' undeclared (first use in this function)
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:96:2: note: in expansion of macro 'MMIO_DFH'
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:96:35: error: 'intel_vgpu_reg_iir_handler' undeclared (first use in this function)
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:96:2: note: in expansion of macro 'MMIO_DFH'
96 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
| ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:97:9: error: 'SDEISR' undeclared (first use in this function)
97 | MMIO_D(SDEISR, D_ALL);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:97:2: note: in expansion of macro 'MMIO_D'
97 | MMIO_D(SDEISR, D_ALL);
| ^~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:99:16: error: implicit declaration of function 'RING_HWSTAM' [-Werror=implicit-function-declaration]
99 | MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
74 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:99:2: note: in expansion of macro 'MMIO_RING_DFH'
99 | MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:102:10: error: 'GEN8_GAMW_ECO_DEV_RW_IA' undeclared (first use in this function)
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:102:35: error: 'D_BDW_PLUS' undeclared (first use in this function)
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:17: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:103:3: error: 'gamw_echo_dev_rw_ia_write' undeclared (first use in this function)
103 | gamw_echo_dev_rw_ia_write);
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
102 | MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:105:14: error: 'BSD_HWS_PGA_GEN7' undeclared (first use in this function)
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:56:17: error: 'F_GMADR' undeclared (first use in this function)
56 | MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
| ^~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:3: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:56:27: error: 'F_CMD_ACCESS' undeclared (first use in this function)
56 | MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:37:3: note: in definition of macro 'MMIO_F'
37 | f, s, am, rm, d, r, w); \
| ^
drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
105 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:106:14: error: 'BLT_HWS_PGA_GEN7' undeclared (first use in this function)
106 | MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:106:2: note: in expansion of macro 'MMIO_GM_RDR'
106 | MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:107:14: error: 'VEBOX_HWS_PGA_GEN7' undeclared (first use in this function)
107 | MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:107:2: note: in expansion of macro 'MMIO_GM_RDR'
107 | MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
| ^~~~~~~~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:109:24: error: implicit declaration of function '_MMIO' [-Werror=implicit-function-declaration]
109 | #define RING_REG(base) _MMIO((base) + 0x28)
| ^~~~~
drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
36 | ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
| ^~~
drivers/gpu/drm/i915/gvt/mmio_table.h:62:9: note: in expansion of macro 'RING_REG'
62 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
vim +87 drivers/gpu/drm/i915/gvt/mmio_table.h
27
28 #ifdef GENERATE_MMIO_TABLE_IN_I915
29 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
30 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
31 if (ret) \
32 return ret; \
33 } while (0)
34 #else
35 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
> 36 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
37 f, s, am, rm, d, r, w); \
38 if (ret) \
39 return ret; \
40 } while (0)
41 #endif
42
43 #define MMIO_D(reg, d) \
44 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
45
46 #define MMIO_DH(reg, d, r, w) \
47 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
48
49 #define MMIO_DFH(reg, d, f, r, w) \
50 MMIO_F(reg, 4, f, 0, 0, d, r, w)
51
52 #define MMIO_GM(reg, d, r, w) \
53 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
54
55 #define MMIO_GM_RDR(reg, d, r, w) \
> 56 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
57
58 #define MMIO_RO(reg, d, f, rm, r, w) \
> 59 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
60
61 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
> 62 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
> 63 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
> 64 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
> 65 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
> 66 if (HAS_ENGINE(gvt->gt, VCS1)) \
> 67 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
68 } while (0)
69
70 #define MMIO_RING_D(prefix, d) \
71 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
72
73 #define MMIO_RING_DFH(prefix, d, f, r, w) \
74 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
75
76 #define MMIO_RING_GM(prefix, d, r, w) \
77 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
78
79 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
80 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
81
82 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
83 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
84
85 static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
86 {
> 87 struct drm_i915_private *dev_priv = gvt->gt->i915;
88
89 int ret;
90
> 91 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
> 92 intel_vgpu_reg_imr_handler);
93
> 94 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
> 95 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
> 96 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
> 97 MMIO_D(SDEISR, D_ALL);
98
> 99 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
100
101
> 102 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
> 103 gamw_echo_dev_rw_ia_write);
104
> 105 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> 106 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
> 107 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
108
> 109 #define RING_REG(base) _MMIO((base) + 0x28)
110 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
111 #undef RING_REG
112
113 #define RING_REG(base) _MMIO((base) + 0x134)
114 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
115 #undef RING_REG
116
117 #define RING_REG(base) _MMIO((base) + 0x6c)
> 118 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
119 #undef RING_REG
> 120 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
121
122 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
> 123 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
124 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
> 125 MMIO_D(GEN7_CXT_SIZE, D_ALL);
126
> 127 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
> 128 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
> 129 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
> 130 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
> 131 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
132
133 /* RING MODE */
134 #define RING_REG(base) _MMIO((base) + 0x29c)
135 MMIO_RING_DFH(RING_REG, D_ALL,
> 136 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
> 137 ring_mode_mmio_write);
138 #undef RING_REG
139
> 140 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
141 NULL, NULL);
> 142 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
143 NULL, NULL);
> 144 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
145 mmio_read_from_hw, NULL);
> 146 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
147 mmio_read_from_hw, NULL);
148
> 149 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 150 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
151 NULL, NULL);
> 152 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 153 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
154 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
155
156 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 157 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
158 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 159 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
160 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
161 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 162 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
> 163 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
164 NULL, NULL);
> 165 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
166 NULL, NULL);
167 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
168 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
169 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
170 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
171 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
172 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
173 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
174 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 175 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> 176 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
177
178 /* display */
179 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
180 MMIO_D(_MMIO(0x602a0), D_ALL);
181
182 MMIO_D(_MMIO(0x65050), D_ALL);
183 MMIO_D(_MMIO(0x650b4), D_ALL);
184
185 MMIO_D(_MMIO(0xc4040), D_ALL);
> 186 MMIO_D(DERRMR, D_ALL);
187
> 188 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
> 189 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
> 190 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
> 191 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
192
> 193 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
194 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
195 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
196 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
197
> 198 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
199 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
200 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
201 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
202
> 203 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
204 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
205 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
206 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
207
> 208 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
209 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
210 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
211 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
212
> 213 MMIO_D(CURCNTR(PIPE_A), D_ALL);
214 MMIO_D(CURCNTR(PIPE_B), D_ALL);
215 MMIO_D(CURCNTR(PIPE_C), D_ALL);
216
> 217 MMIO_D(CURPOS(PIPE_A), D_ALL);
218 MMIO_D(CURPOS(PIPE_B), D_ALL);
219 MMIO_D(CURPOS(PIPE_C), D_ALL);
220
> 221 MMIO_D(CURBASE(PIPE_A), D_ALL);
222 MMIO_D(CURBASE(PIPE_B), D_ALL);
223 MMIO_D(CURBASE(PIPE_C), D_ALL);
224
> 225 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
226 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
227 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
228
229 MMIO_D(_MMIO(0x700ac), D_ALL);
230 MMIO_D(_MMIO(0x710ac), D_ALL);
231 MMIO_D(_MMIO(0x720ac), D_ALL);
232
233 MMIO_D(_MMIO(0x70090), D_ALL);
234 MMIO_D(_MMIO(0x70094), D_ALL);
235 MMIO_D(_MMIO(0x70098), D_ALL);
236 MMIO_D(_MMIO(0x7009c), D_ALL);
237
> 238 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
> 239 MMIO_D(DSPADDR(PIPE_A), D_ALL);
> 240 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
> 241 MMIO_D(DSPPOS(PIPE_A), D_ALL);
> 242 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
> 243 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> 244 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
> 245 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
> 246 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> 247 reg50080_mmio_write);
248
249 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
250 MMIO_D(DSPADDR(PIPE_B), D_ALL);
251 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
252 MMIO_D(DSPPOS(PIPE_B), D_ALL);
253 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
254 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
255 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
256 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
257 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
258 reg50080_mmio_write);
259
260 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
261 MMIO_D(DSPADDR(PIPE_C), D_ALL);
262 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
263 MMIO_D(DSPPOS(PIPE_C), D_ALL);
264 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
265 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
266 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
267 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
268 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
269 reg50080_mmio_write);
270
> 271 MMIO_D(SPRCTL(PIPE_A), D_ALL);
> 272 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
> 273 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
> 274 MMIO_D(SPRPOS(PIPE_A), D_ALL);
> 275 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
> 276 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
> 277 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
> 278 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
> 279 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
> 280 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
> 281 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
> 282 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
> 283 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
284 reg50080_mmio_write);
285
286 MMIO_D(SPRCTL(PIPE_B), D_ALL);
287 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
288 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
289 MMIO_D(SPRPOS(PIPE_B), D_ALL);
290 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
291 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
292 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
293 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
294 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
295 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
296 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
297 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
298 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
299 reg50080_mmio_write);
300
301 MMIO_D(SPRCTL(PIPE_C), D_ALL);
302 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
303 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
304 MMIO_D(SPRPOS(PIPE_C), D_ALL);
305 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
306 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
307 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
308 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
309 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
310 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
311 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
312 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
313 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
314 reg50080_mmio_write);
315
316 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
317 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
318 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
319 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
320 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
321 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
322 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
323 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
324 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
325
326 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
327 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
328 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
329 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
330 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
331 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
332 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
333 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
334 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
335
336 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
337 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
338 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
339 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
340 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
341 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
342 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
343 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
344 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
345
346 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
347 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
348 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
349 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
350 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
351 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
352 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
353 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
354
355 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
356 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
357 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
358 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
359 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
360 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
361 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
362 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
363
364 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
365 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
366 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
367 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
368 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
369 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
370 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
371 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
372
373 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
374 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
375 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
376 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
377 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
378 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
379 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
380 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
381
382 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
383 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
384 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
385 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
386 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
387 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
388 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
389 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
390
391 MMIO_D(PF_CTL(PIPE_A), D_ALL);
392 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
393 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
394 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
395 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
396
397 MMIO_D(PF_CTL(PIPE_B), D_ALL);
398 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
399 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
400 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
401 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
402
403 MMIO_D(PF_CTL(PIPE_C), D_ALL);
404 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
405 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
406 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
407 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
408
409 MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
410 MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
411 MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
412 MMIO_D(WM1_LP_ILK, D_ALL);
413 MMIO_D(WM2_LP_ILK, D_ALL);
414 MMIO_D(WM3_LP_ILK, D_ALL);
415 MMIO_D(WM1S_LP_ILK, D_ALL);
416 MMIO_D(WM2S_LP_IVB, D_ALL);
417 MMIO_D(WM3S_LP_IVB, D_ALL);
418
419 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
420 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
421 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
422 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
423
424 MMIO_D(_MMIO(0x48268), D_ALL);
425
426 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
427 gmbus_mmio_write);
428 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
429 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
430
431 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
432 dp_aux_ch_ctl_mmio_write);
433 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
434 dp_aux_ch_ctl_mmio_write);
435 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
436 dp_aux_ch_ctl_mmio_write);
437
438 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
439
440 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
441 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
442
443 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
444 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
445 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
446 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
447 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
448 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
449 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
450 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
451 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
452
453 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
454 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
455 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
456 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
457 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
458 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
459 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
460
461 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
462 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
463 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
464 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
465 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
466 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
467 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
468
469 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
470 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
471 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
472 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
473 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
474 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
475 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
476 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
477
478 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
479 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
480 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
481
482 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
483 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
484 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
485
486 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
487 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
488 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
489
490 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
491 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
492 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
493
494 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
495 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
496 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
497 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
498 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
499 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
500
501 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
502 MMIO_D(PCH_PP_DIVISOR, D_ALL);
503 MMIO_D(PCH_PP_STATUS, D_ALL);
504 MMIO_D(PCH_LVDS, D_ALL);
505 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
506 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
507 MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
508 MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
509 MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
510 MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
511 MMIO_D(PCH_DREF_CONTROL, D_ALL);
512 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
513 MMIO_D(PCH_DPLL_SEL, D_ALL);
514
515 MMIO_D(_MMIO(0x61208), D_ALL);
516 MMIO_D(_MMIO(0x6120c), D_ALL);
517 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
518 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
519
520 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
521 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
522 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
523 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
524 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
525 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
526
527 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
528 PORTA_HOTPLUG_STATUS_MASK
529 | PORTB_HOTPLUG_STATUS_MASK
530 | PORTC_HOTPLUG_STATUS_MASK
531 | PORTD_HOTPLUG_STATUS_MASK,
532 NULL, NULL);
533
534 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
535 MMIO_D(FUSE_STRAP, D_ALL);
536 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
537
538 MMIO_D(DISP_ARB_CTL, D_ALL);
539 MMIO_D(DISP_ARB_CTL2, D_ALL);
540
541 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
542 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
543 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
544
545 MMIO_D(SOUTH_CHICKEN1, D_ALL);
546 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
547 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
548 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
549 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
550 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
551 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
552
553 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
554 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
555 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
556 MMIO_D(ILK_DPFC_STATUS, D_ALL);
557 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
558 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
559 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
560
561 MMIO_D(IPS_CTL, D_ALL);
562
563 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
564 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
565 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
566 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
567 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
568 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
569 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
570 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
571 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
572 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
573 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
574 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
575 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
576
577 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
578 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
579 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
580 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
581 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
582 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
583 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
584 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
585 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
586 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
587 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
588 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
589 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
590
591 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
592 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
593 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
594 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
595 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
596 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
597 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
598 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
599 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
600 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
601 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
602 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
603 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
604
605 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
606 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
607 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
608
609 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
610 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
611 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
612
613 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
614 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
615 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
616
617 MMIO_D(_MMIO(0x60110), D_ALL);
618 MMIO_D(_MMIO(0x61110), D_ALL);
619 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
620 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
621 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
622 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
623 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
624 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
625 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
626 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
627 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
628
629 MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
630 MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
631 MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
632 MMIO_D(SPLL_CTL, D_ALL);
633 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
634 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
635 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
636 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
637 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
638 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
639 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
640 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
641 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
642 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
643
644 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
645 MMIO_D(_MMIO(0x46508), D_ALL);
646
647 MMIO_D(_MMIO(0x49080), D_ALL);
648 MMIO_D(_MMIO(0x49180), D_ALL);
649 MMIO_D(_MMIO(0x49280), D_ALL);
650
651 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
652 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
653 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
654
655 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
656 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
657 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
658
659 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
660 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
661 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
662
663 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
664 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
665 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
666
667 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
668 MMIO_D(SBI_ADDR, D_ALL);
669 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
670 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
671 MMIO_D(PIXCLK_GATE, D_ALL);
672
673 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
674 dp_aux_ch_ctl_mmio_write);
675
676 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
677 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
678 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
679 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
680 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
681
682 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
683 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
684 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
685 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
686 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
687
688 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
689 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
690 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
691 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
692 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
693
694 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
695 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
696 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
697 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
698 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
699
700 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
701 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
702 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
703
704 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
705 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
706 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
707 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
708
709 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
710 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
711 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
712 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
713
714 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
715 MMIO_D(FORCEWAKE_ACK, D_ALL);
716 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
717 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
718 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
719 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
720 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
721 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
722 MMIO_D(ECOBUS, D_ALL);
723 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
724 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
725 MMIO_D(GEN6_RPNSWREQ, D_ALL);
726 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
727 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
728 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
729 MMIO_D(GEN6_RPSTAT1, D_ALL);
730 MMIO_D(GEN6_RP_CONTROL, D_ALL);
731 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
732 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
733 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
734 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
735 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
736 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
737 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
738 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
739 MMIO_D(GEN6_RP_UP_EI, D_ALL);
740 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
741 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
742 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
743 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
744 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
745 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
746 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
747 MMIO_D(GEN6_RC_SLEEP, D_ALL);
748 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
749 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
750 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
751 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
752 MMIO_D(GEN6_PMINTRMSK, D_ALL);
753 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
754 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
755 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
756 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
757 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
758 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
759
760 MMIO_D(RSTDBYCTL, D_ALL);
761
762 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
763 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
764 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
765
766 MMIO_D(TILECTL, D_ALL);
767
768 MMIO_D(GEN6_UCGCTL1, D_ALL);
769 MMIO_D(GEN6_UCGCTL2, D_ALL);
770
771 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
772
773 MMIO_D(GEN6_PCODE_DATA, D_ALL);
774 MMIO_D(_MMIO(0x13812c), D_ALL);
775 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
776 MMIO_D(HSW_EDRAM_CAP, D_ALL);
777 MMIO_D(HSW_IDICR, D_ALL);
778 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
779
780 MMIO_D(_MMIO(0x3c), D_ALL);
781 MMIO_D(_MMIO(0x860), D_ALL);
782 MMIO_D(ECOSKPD, D_ALL);
783 MMIO_D(_MMIO(0x121d0), D_ALL);
784 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
785 MMIO_D(_MMIO(0x41d0), D_ALL);
786 MMIO_D(GAC_ECO_BITS, D_ALL);
787 MMIO_D(_MMIO(0x6200), D_ALL);
788 MMIO_D(_MMIO(0x6204), D_ALL);
789 MMIO_D(_MMIO(0x6208), D_ALL);
790 MMIO_D(_MMIO(0x7118), D_ALL);
791 MMIO_D(_MMIO(0x7180), D_ALL);
792 MMIO_D(_MMIO(0x7408), D_ALL);
793 MMIO_D(_MMIO(0x7c00), D_ALL);
794 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
795 MMIO_D(_MMIO(0x911c), D_ALL);
796 MMIO_D(_MMIO(0x9120), D_ALL);
797 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
798
799 MMIO_D(GAB_CTL, D_ALL);
800 MMIO_D(_MMIO(0x48800), D_ALL);
801 MMIO_D(_MMIO(0xce044), D_ALL);
802 MMIO_D(_MMIO(0xe6500), D_ALL);
803 MMIO_D(_MMIO(0xe6504), D_ALL);
804 MMIO_D(_MMIO(0xe6600), D_ALL);
805 MMIO_D(_MMIO(0xe6604), D_ALL);
806 MMIO_D(_MMIO(0xe6700), D_ALL);
807 MMIO_D(_MMIO(0xe6704), D_ALL);
808 MMIO_D(_MMIO(0xe6800), D_ALL);
809 MMIO_D(_MMIO(0xe6804), D_ALL);
810 MMIO_D(PCH_GMBUS4, D_ALL);
811 MMIO_D(PCH_GMBUS5, D_ALL);
812
813 MMIO_D(_MMIO(0x902c), D_ALL);
814 MMIO_D(_MMIO(0xec008), D_ALL);
815 MMIO_D(_MMIO(0xec00c), D_ALL);
816 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
817 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
818 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
819 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
820 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
821 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
822 MMIO_D(_MMIO(0xec408), D_ALL);
823 MMIO_D(_MMIO(0xec40c), D_ALL);
824 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
825 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
826 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
827 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
828 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
829 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
830 MMIO_D(_MMIO(0xfc810), D_ALL);
831 MMIO_D(_MMIO(0xfc81c), D_ALL);
832 MMIO_D(_MMIO(0xfc828), D_ALL);
833 MMIO_D(_MMIO(0xfc834), D_ALL);
834 MMIO_D(_MMIO(0xfcc00), D_ALL);
835 MMIO_D(_MMIO(0xfcc0c), D_ALL);
836 MMIO_D(_MMIO(0xfcc18), D_ALL);
837 MMIO_D(_MMIO(0xfcc24), D_ALL);
838 MMIO_D(_MMIO(0xfd000), D_ALL);
839 MMIO_D(_MMIO(0xfd00c), D_ALL);
840 MMIO_D(_MMIO(0xfd018), D_ALL);
841 MMIO_D(_MMIO(0xfd024), D_ALL);
842 MMIO_D(_MMIO(0xfd034), D_ALL);
843
844 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
845 MMIO_D(_MMIO(0x2054), D_ALL);
846 MMIO_D(_MMIO(0x12054), D_ALL);
847 MMIO_D(_MMIO(0x22054), D_ALL);
848 MMIO_D(_MMIO(0x1a054), D_ALL);
849
850 MMIO_D(_MMIO(0x44070), D_ALL);
851 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
852 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
853 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
854 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
855 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
856
857 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
858 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
859 MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
860 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
861 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
862 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
863
864 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
865 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
866 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
867
868 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
869 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
870 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
871 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
872 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
873 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
874 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
875 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
876 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
877 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
878 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
879 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
880 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
881 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
882 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
883 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
884 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
885
886 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
887 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
888 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
889 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
890 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
891 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
892 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
893 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
894 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
895 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
896 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
897
898 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
899 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
900 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
901
902 return 0;
903 }
904
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 66042 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/3] i915/gvt: save the initial HW state snapshot in i915.
2022-01-27 12:05 ` Zhi Wang
(?)
@ 2022-01-31 6:38 ` Christoph Hellwig
-1 siblings, 0 replies; 35+ messages in thread
From: Christoph Hellwig @ 2022-01-31 6:38 UTC (permalink / raw)
To: Zhi Wang
Cc: hch, jgg, jani.nikula, intel-gfx, intel-gvt-dev, dri-devel,
linux-kernel, Zhi Wang, Joonas Lahtinen, Vivi Rodrigo,
Zhenyu Wang
On Thu, Jan 27, 2022 at 07:05:07AM -0500, Zhi Wang wrote:
> +static void save_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,
> + u32 size)
> +{
> + struct drm_i915_private *dev_priv = iter->i915;
> + void *mmio = iter->data;
> + u32 start, end, i;
> +
> + start = offset;
> + end = offset + size;
> +
> + for (i = start; i < end; i += 4) {
> + *(u32 *)(mmio + i) = intel_uncore_read_notrace(
> + to_gt(dev_priv)->uncore, _MMIO(offset));
> + }
> +}
This can be simplified to:
static void intel_gvt_save_mmio(struct intel_gvt_mmio_table_iter *iter,
u32 offset, u32 size)
{
struct drm_i915_private *dev_priv = iter->i915;
u32 *mmio = iter->data, i;
for (i = offset; i < offset + size; i += 4) {
mmio[i] = intel_uncore_read_notrace(to_gt(dev_priv)->uncore,
_MMIO(offset));
}
}
> + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> + struct intel_gvt_device_info info;
> + struct i915_virtual_gpu *vgpu = &dev_priv->vgpu;
> + struct intel_gvt_mmio_table_iter iter;
> + void *mem;
> + int i, ret;
> +
> + intel_gvt_init_device_info(dev_priv, &info);
There is no real need for this call.
> +
> + mem = kzalloc(info.cfg_space_size, GFP_KERNEL);
> + if (!mem)
> + return -ENOMEM;
info.cfg_space_size is always PCI_CFG_SPACE_EXP_SIZE, and the code relies
onb that just a few lines below.
> + mem = vzalloc(info.mmio_size);
And info.mmio_size is a constant that can just use a define.
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 2/3] i915/gvt: save the initial HW state snapshot in i915.
2022-01-27 12:05 [PATCH 1/3] i915/gvt: Introduce the mmio_table.c to support VFIO new mdev API Zhi Wang
@ 2022-01-27 12:05 ` Zhi Wang
0 siblings, 0 replies; 35+ messages in thread
From: Zhi Wang @ 2022-01-27 12:05 UTC (permalink / raw)
To: hch, jgg, jani.nikula
Cc: intel-gfx, intel-gvt-dev, dri-devel, linux-kernel, Zhi Wang,
Joonas Lahtinen, Vivi Rodrigo, Zhenyu Wang
Save the inital HW state snapshot in i915 so that the rest code of GVT-g
can be moved into a dedicated module while it can still get a clean
initial HW state saved at the correct time during the initialization of
i915. The futhrer vGPU created by GVT-g will use this HW state as the
initial HW state.
Cc: Christoph Hellwig <hch@lst.de>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Vivi Rodrigo <rodrigo.vivi@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_gvt.c | 110 ++++++++++++++++++++++++++++++-
2 files changed, 110 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 44c1f98144b4..2a230840cdfa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -606,6 +606,8 @@ struct i915_virtual_gpu {
struct mutex lock; /* serialises sending of g2v_notify command pkts */
bool active;
u32 caps;
+ u32 *initial_mmio;
+ u8 *initial_cfg_space;
};
struct i915_selftest_stash {
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index cf6e98962d82..a3d8bdb24d3f 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -86,6 +86,103 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
dev_priv->params.enable_gvt = 0;
}
+static void free_initial_hw_state(struct drm_i915_private *dev_priv)
+{
+ struct i915_virtual_gpu *vgpu = &dev_priv->vgpu;
+
+ vfree(vgpu->initial_mmio);
+ vgpu->initial_mmio = NULL;
+
+ kfree(vgpu->initial_cfg_space);
+ vgpu->initial_cfg_space = NULL;
+}
+
+static void save_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,
+ u32 size)
+{
+ struct drm_i915_private *dev_priv = iter->i915;
+ void *mmio = iter->data;
+ u32 start, end, i;
+
+ start = offset;
+ end = offset + size;
+
+ for (i = start; i < end; i += 4) {
+ *(u32 *)(mmio + i) = intel_uncore_read_notrace(
+ to_gt(dev_priv)->uncore, _MMIO(offset));
+ }
+}
+
+static int do_mmio(u32 offset, u16 flags, u32 size, u32 addr_mask,
+ u32 ro_mask, u32 device,
+ struct intel_gvt_mmio_table_iter *iter)
+{
+ if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ return -EINVAL;
+
+ save_mmio(iter, offset, size);
+ return 0;
+}
+
+static int do_mmio_block(u32 offset, u32 size, u32 device,
+ struct intel_gvt_mmio_table_iter *iter)
+{
+ if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ return -EINVAL;
+
+ save_mmio(iter, offset, size);
+ return 0;
+}
+
+static int save_inital_hw_state(struct drm_i915_private *dev_priv)
+{
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct intel_gvt_device_info info;
+ struct i915_virtual_gpu *vgpu = &dev_priv->vgpu;
+ struct intel_gvt_mmio_table_iter iter;
+ void *mem;
+ int i, ret;
+
+ intel_gvt_init_device_info(dev_priv, &info);
+
+ mem = kzalloc(info.cfg_space_size, GFP_KERNEL);
+ if (!mem)
+ return -ENOMEM;
+
+ vgpu->initial_cfg_space = mem;
+
+ for (i = 0; i < PCI_CFG_SPACE_EXP_SIZE; i += 4)
+ pci_read_config_dword(pdev, i, mem + i);
+
+ mem = vzalloc(info.mmio_size);
+ if (!mem) {
+ ret = -ENOMEM;
+ goto err_mmio;
+ }
+
+ vgpu->initial_mmio = mem;
+
+ iter.i915 = dev_priv;
+ iter.data = vgpu->initial_mmio;
+ iter.do_mmio = do_mmio;
+ iter.do_mmio_block = do_mmio_block;
+
+ ret = intel_gvt_iterate_mmio_table(&iter);
+ if (ret)
+ goto err_iterate;
+
+ return 0;
+
+err_iterate:
+ vfree(vgpu->initial_mmio);
+ vgpu->initial_mmio = NULL;
+err_mmio:
+ kfree(vgpu->initial_cfg_space);
+ vgpu->initial_cfg_space = NULL;
+
+ return ret;
+}
+
/**
* intel_gvt_init - initialize GVT components
* @dev_priv: drm i915 private data
@@ -115,15 +212,23 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return -EIO;
}
+ ret = save_inital_hw_state(dev_priv);
+ if (ret) {
+ drm_dbg(&dev_priv->drm, "Fail to save inital HW state\n");
+ goto err_save_hw_state;
+ }
+
ret = intel_gvt_init_device(dev_priv);
if (ret) {
drm_dbg(&dev_priv->drm, "Fail to init GVT device\n");
- goto bail;
+ goto err_init_device;
}
return 0;
-bail:
+err_init_device:
+ free_initial_hw_state(dev_priv);
+err_save_hw_state:
dev_priv->params.enable_gvt = 0;
return 0;
}
@@ -147,6 +252,7 @@ void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)
return;
intel_gvt_clean_device(dev_priv);
+ free_initial_hw_state(dev_priv);
}
/**
--
2.25.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 2/3] i915/gvt: save the initial HW state snapshot in i915.
@ 2022-01-27 12:05 ` Zhi Wang
0 siblings, 0 replies; 35+ messages in thread
From: Zhi Wang @ 2022-01-27 12:05 UTC (permalink / raw)
To: hch, jgg, jani.nikula
Cc: intel-gfx, linux-kernel, dri-devel, Vivi Rodrigo, intel-gvt-dev,
Zhi Wang
Save the inital HW state snapshot in i915 so that the rest code of GVT-g
can be moved into a dedicated module while it can still get a clean
initial HW state saved at the correct time during the initialization of
i915. The futhrer vGPU created by GVT-g will use this HW state as the
initial HW state.
Cc: Christoph Hellwig <hch@lst.de>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Vivi Rodrigo <rodrigo.vivi@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_gvt.c | 110 ++++++++++++++++++++++++++++++-
2 files changed, 110 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 44c1f98144b4..2a230840cdfa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -606,6 +606,8 @@ struct i915_virtual_gpu {
struct mutex lock; /* serialises sending of g2v_notify command pkts */
bool active;
u32 caps;
+ u32 *initial_mmio;
+ u8 *initial_cfg_space;
};
struct i915_selftest_stash {
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index cf6e98962d82..a3d8bdb24d3f 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -86,6 +86,103 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
dev_priv->params.enable_gvt = 0;
}
+static void free_initial_hw_state(struct drm_i915_private *dev_priv)
+{
+ struct i915_virtual_gpu *vgpu = &dev_priv->vgpu;
+
+ vfree(vgpu->initial_mmio);
+ vgpu->initial_mmio = NULL;
+
+ kfree(vgpu->initial_cfg_space);
+ vgpu->initial_cfg_space = NULL;
+}
+
+static void save_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,
+ u32 size)
+{
+ struct drm_i915_private *dev_priv = iter->i915;
+ void *mmio = iter->data;
+ u32 start, end, i;
+
+ start = offset;
+ end = offset + size;
+
+ for (i = start; i < end; i += 4) {
+ *(u32 *)(mmio + i) = intel_uncore_read_notrace(
+ to_gt(dev_priv)->uncore, _MMIO(offset));
+ }
+}
+
+static int do_mmio(u32 offset, u16 flags, u32 size, u32 addr_mask,
+ u32 ro_mask, u32 device,
+ struct intel_gvt_mmio_table_iter *iter)
+{
+ if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ return -EINVAL;
+
+ save_mmio(iter, offset, size);
+ return 0;
+}
+
+static int do_mmio_block(u32 offset, u32 size, u32 device,
+ struct intel_gvt_mmio_table_iter *iter)
+{
+ if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ return -EINVAL;
+
+ save_mmio(iter, offset, size);
+ return 0;
+}
+
+static int save_inital_hw_state(struct drm_i915_private *dev_priv)
+{
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct intel_gvt_device_info info;
+ struct i915_virtual_gpu *vgpu = &dev_priv->vgpu;
+ struct intel_gvt_mmio_table_iter iter;
+ void *mem;
+ int i, ret;
+
+ intel_gvt_init_device_info(dev_priv, &info);
+
+ mem = kzalloc(info.cfg_space_size, GFP_KERNEL);
+ if (!mem)
+ return -ENOMEM;
+
+ vgpu->initial_cfg_space = mem;
+
+ for (i = 0; i < PCI_CFG_SPACE_EXP_SIZE; i += 4)
+ pci_read_config_dword(pdev, i, mem + i);
+
+ mem = vzalloc(info.mmio_size);
+ if (!mem) {
+ ret = -ENOMEM;
+ goto err_mmio;
+ }
+
+ vgpu->initial_mmio = mem;
+
+ iter.i915 = dev_priv;
+ iter.data = vgpu->initial_mmio;
+ iter.do_mmio = do_mmio;
+ iter.do_mmio_block = do_mmio_block;
+
+ ret = intel_gvt_iterate_mmio_table(&iter);
+ if (ret)
+ goto err_iterate;
+
+ return 0;
+
+err_iterate:
+ vfree(vgpu->initial_mmio);
+ vgpu->initial_mmio = NULL;
+err_mmio:
+ kfree(vgpu->initial_cfg_space);
+ vgpu->initial_cfg_space = NULL;
+
+ return ret;
+}
+
/**
* intel_gvt_init - initialize GVT components
* @dev_priv: drm i915 private data
@@ -115,15 +212,23 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return -EIO;
}
+ ret = save_inital_hw_state(dev_priv);
+ if (ret) {
+ drm_dbg(&dev_priv->drm, "Fail to save inital HW state\n");
+ goto err_save_hw_state;
+ }
+
ret = intel_gvt_init_device(dev_priv);
if (ret) {
drm_dbg(&dev_priv->drm, "Fail to init GVT device\n");
- goto bail;
+ goto err_init_device;
}
return 0;
-bail:
+err_init_device:
+ free_initial_hw_state(dev_priv);
+err_save_hw_state:
dev_priv->params.enable_gvt = 0;
return 0;
}
@@ -147,6 +252,7 @@ void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)
return;
intel_gvt_clean_device(dev_priv);
+ free_initial_hw_state(dev_priv);
}
/**
--
2.25.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
end of thread, other threads:[~2022-01-31 6:38 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-08 21:27 [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c Zhi Wang
2021-11-08 21:27 ` [Intel-gfx] " Zhi Wang
2021-11-08 21:27 ` [PATCH 2/3] i915/gvt: save the initial HW state snapshot in i915 Zhi Wang
2021-11-08 21:27 ` [Intel-gfx] " Zhi Wang
2021-11-08 21:27 ` [PATCH 3/3] i915/gvt: Use the initial HW state snapshot saved " Zhi Wang
2021-11-08 21:27 ` [Intel-gfx] " Zhi Wang
2021-11-09 7:00 ` [PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c Jani Nikula
2021-11-09 7:00 ` [Intel-gfx] " Jani Nikula
2021-11-09 7:51 ` Christoph Hellwig
2021-11-09 7:51 ` [Intel-gfx] " Christoph Hellwig
2021-11-09 8:41 ` Wang, Zhi A
2021-11-09 8:41 ` [Intel-gfx] " Wang, Zhi A
2021-11-09 10:20 ` Jani Nikula
2021-11-09 10:20 ` [Intel-gfx] " Jani Nikula
2021-11-09 10:36 ` hch
2021-11-09 10:36 ` [Intel-gfx] " hch
2021-11-09 10:51 ` Wang, Zhi A
2021-11-09 10:51 ` Wang, Zhi A
2021-11-09 10:51 ` [Intel-gfx] " Wang, Zhi A
2021-11-09 10:58 ` hch
2021-11-09 10:58 ` [Intel-gfx] " hch
2021-11-09 11:02 ` Wang, Zhi A
2021-11-09 11:02 ` [Intel-gfx] " Wang, Zhi A
2021-11-09 11:02 ` Wang, Zhi A
2021-11-09 10:53 ` Wang, Zhi A
2021-11-09 10:53 ` [Intel-gfx] " Wang, Zhi A
2021-11-09 9:44 ` Christoph Hellwig
2021-11-09 9:44 ` [Intel-gfx] " Christoph Hellwig
2021-11-09 14:33 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] " Patchwork
2021-11-11 23:32 ` [PATCH 1/3] " kernel test robot
2021-11-11 23:32 ` kernel test robot
2021-11-11 23:32 ` [Intel-gfx] " kernel test robot
2022-01-27 12:05 [PATCH 1/3] i915/gvt: Introduce the mmio_table.c to support VFIO new mdev API Zhi Wang
2022-01-27 12:05 ` [PATCH 2/3] i915/gvt: save the initial HW state snapshot in i915 Zhi Wang
2022-01-27 12:05 ` Zhi Wang
2022-01-31 6:38 ` Christoph Hellwig
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