* [igt-dev] [PATCH 0/2] Test parallel execbuf
@ 2021-11-09 22:59 Matthew Brost
2021-11-09 22:59 ` [igt-dev] [PATCH 1/2] i915_drm.h sync with drm-next Matthew Brost
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Matthew Brost @ 2021-11-09 22:59 UTC (permalink / raw)
To: igt-dev
v2:
(Daniele)
- Sync i915_drm.h
- Address comments in test
v3:
(Daniele)
- Read timeslice from sysfs
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Matthew Brost (2):
i915_drm.h sync with drm-next
i915/gem_exec_balancer: Test parallel execbuf
include/drm-uapi/i915_drm.h | 242 +++++++++++++++-
lib/i915/i915_drm_local.h | 13 -
lib/intel_ctx.c | 30 +-
lib/intel_ctx.h | 2 +
lib/intel_reg.h | 5 +
tests/i915/gem_exec_balancer.c | 486 +++++++++++++++++++++++++++++++++
6 files changed, 763 insertions(+), 15 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH 1/2] i915_drm.h sync with drm-next
2021-11-09 22:59 [igt-dev] [PATCH 0/2] Test parallel execbuf Matthew Brost
@ 2021-11-09 22:59 ` Matthew Brost
2021-11-09 22:59 ` [igt-dev] [PATCH 2/2] i915/gem_exec_balancer: Test parallel execbuf Matthew Brost
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Matthew Brost @ 2021-11-09 22:59 UTC (permalink / raw)
To: igt-dev
Also delete PXP defines / structures from i915_drm_local.h.
Taken from 806acd381960 ("Merge tag 'amd-drm-fixes-5.16-2021-11-03' of https://gitlab.freedesktop.org/agd5f/linux into drm-next")
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
include/drm-uapi/i915_drm.h | 242 +++++++++++++++++++++++++++++++++++-
lib/i915/i915_drm_local.h | 13 --
2 files changed, 241 insertions(+), 14 deletions(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index c788a1ab4..9c9e1afa6 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1522,6 +1522,12 @@ struct drm_i915_gem_caching {
#define I915_TILING_NONE 0
#define I915_TILING_X 1
#define I915_TILING_Y 2
+/*
+ * Do not add new tiling types here. The I915_TILING_* values are for
+ * de-tiling fence registers that no longer exist on modern platforms. Although
+ * the hardware may support new types of tiling in general (e.g., Tile4), we
+ * do not need to add them to the uapi that is specific to now-defunct ioctls.
+ */
#define I915_TILING_LAST I915_TILING_Y
#define I915_BIT_6_SWIZZLE_NONE 0
@@ -1824,6 +1830,7 @@ struct drm_i915_gem_context_param {
* Extensions:
* i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
* i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
+ * i915_context_engines_parallel_submit (I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT)
*/
#define I915_CONTEXT_PARAM_ENGINES 0xa
@@ -1846,6 +1853,55 @@ struct drm_i915_gem_context_param {
* attempted to use it, never re-use this context param number.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
+
+/*
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * Mark that the context makes use of protected content, which will result
+ * in the context being invalidated when the protected content session is.
+ * Given that the protected content session is killed on suspend, the device
+ * is kept awake for the lifetime of a protected context, so the user should
+ * make sure to dispose of them once done.
+ * This flag can only be set at context creation time and, when set to true,
+ * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
+ * to false. This flag can't be set to true in conjunction with setting the
+ * I915_CONTEXT_PARAM_BANNABLE flag to false. Creation example:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_gem_context_create_ext_setparam p_protected = {
+ * .base = {
+ * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ * },
+ * .param = {
+ * .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+ * .value = 1,
+ * }
+ * };
+ * struct drm_i915_gem_context_create_ext_setparam p_norecover = {
+ * .base = {
+ * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ * .next_extension = to_user_pointer(&p_protected),
+ * },
+ * .param = {
+ * .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ * .value = 0,
+ * }
+ * };
+ * struct drm_i915_gem_context_create_ext create = {
+ * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ * .extensions = to_user_pointer(&p_norecover);
+ * };
+ *
+ * ctx_id = gem_context_create_ext(drm_fd, &create);
+ *
+ * In addition to the normal failure cases, setting this flag during context
+ * creation can result in the following errors:
+ *
+ * -ENODEV: feature not available
+ * -EPERM: trying to mark a recoverable or not bannable context as protected
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
/* Must be kept compact -- no holes and well documented */
__u64 value;
@@ -2049,6 +2105,135 @@ struct i915_context_engines_bond {
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
+/**
+ * struct i915_context_engines_parallel_submit - Configure engine for
+ * parallel submission.
+ *
+ * Setup a slot in the context engine map to allow multiple BBs to be submitted
+ * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU
+ * in parallel. Multiple hardware contexts are created internally in the i915 to
+ * run these BBs. Once a slot is configured for N BBs only N BBs can be
+ * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user
+ * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how
+ * many BBs there are based on the slot's configuration. The N BBs are the last
+ * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.
+ *
+ * The default placement behavior is to create implicit bonds between each
+ * context if each context maps to more than 1 physical engine (e.g. context is
+ * a virtual engine). Also we only allow contexts of same engine class and these
+ * contexts must be in logically contiguous order. Examples of the placement
+ * behavior are described below. Lastly, the default is to not allow BBs to be
+ * preempted mid-batch. Rather insert coordinated preemption points on all
+ * hardware contexts between each set of BBs. Flags could be added in the future
+ * to change both of these default behaviors.
+ *
+ * Returns -EINVAL if hardware context placement configuration is invalid or if
+ * the placement configuration isn't supported on the platform / submission
+ * interface.
+ * Returns -ENODEV if extension isn't supported on the platform / submission
+ * interface.
+ *
+ * .. code-block:: none
+ *
+ * Examples syntax:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ *
+ * Example 1 pseudo code:
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=1,
+ * engines=CS[0],CS[1])
+ *
+ * Results in the following valid placement:
+ * CS[0], CS[1]
+ *
+ * Example 2 pseudo code:
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=2,
+ * engines=CS[0],CS[2],CS[1],CS[3])
+ *
+ * Results in the following valid placements:
+ * CS[0], CS[1]
+ * CS[2], CS[3]
+ *
+ * This can be thought of as two virtual engines, each containing two
+ * engines thereby making a 2D array. However, there are bonds tying the
+ * entries together and placing restrictions on how they can be scheduled.
+ * Specifically, the scheduler can choose only vertical columns from the 2D
+ * array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the
+ * scheduler wants to submit to CS[0], it must also choose CS[1] and vice
+ * versa. Same for CS[2] requires also using CS[3].
+ * VE[0] = CS[0], CS[2]
+ * VE[1] = CS[1], CS[3]
+ *
+ * Example 3 pseudo code:
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=2,
+ * engines=CS[0],CS[1],CS[1],CS[3])
+ *
+ * Results in the following valid and invalid placements:
+ * CS[0], CS[1]
+ * CS[1], CS[3] - Not logically contiguous, return -EINVAL
+ */
+struct i915_context_engines_parallel_submit {
+ /**
+ * @base: base user extension.
+ */
+ struct i915_user_extension base;
+
+ /**
+ * @engine_index: slot for parallel engine
+ */
+ __u16 engine_index;
+
+ /**
+ * @width: number of contexts per parallel engine or in other words the
+ * number of batches in each submission
+ */
+ __u16 width;
+
+ /**
+ * @num_siblings: number of siblings per context or in other words the
+ * number of possible placements for each submission
+ */
+ __u16 num_siblings;
+
+ /**
+ * @mbz16: reserved for future use; must be zero
+ */
+ __u16 mbz16;
+
+ /**
+ * @flags: all undefined flags must be zero, currently not defined flags
+ */
+ __u64 flags;
+
+ /**
+ * @mbz64: reserved for future use; must be zero
+ */
+ __u64 mbz64[3];
+
+ /**
+ * @engines: 2-d array of engine instances to configure parallel engine
+ *
+ * length = width (i) * num_siblings (j)
+ * index = j + i * num_siblings
+ */
+ struct i915_engine_class_instance engines[0];
+
+} __attribute__((packed));
+
+#define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \
+ struct i915_user_extension base; \
+ __u16 engine_index; \
+ __u16 width; \
+ __u16 num_siblings; \
+ __u16 mbz16; \
+ __u64 flags; \
+ __u64 mbz64[3]; \
+ struct i915_engine_class_instance engines[N__]; \
+} __attribute__((packed)) name__
+
/**
* DOC: Context Engine Map uAPI
*
@@ -2108,6 +2293,7 @@ struct i915_context_param_engines {
__u64 extensions; /* linked chain of extension blocks, 0 terminates */
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
+#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
struct i915_engine_class_instance engines[0];
} __attribute__((packed));
@@ -2726,14 +2912,20 @@ struct drm_i915_engine_info {
/** @flags: Engine flags. */
__u64 flags;
+#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0)
/** @capabilities: Capabilities of this engine. */
__u64 capabilities;
#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
+ /** @logical_instance: Logical instance of engine */
+ __u16 logical_instance;
+
/** @rsvd1: Reserved fields. */
- __u64 rsvd1[4];
+ __u16 rsvd1[3];
+ /** @rsvd2: Reserved fields. */
+ __u64 rsvd2[3];
};
/**
@@ -2979,8 +3171,12 @@ struct drm_i915_gem_create_ext {
*
* For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
* struct drm_i915_gem_create_ext_memory_regions.
+ *
+ * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
+ * struct drm_i915_gem_create_ext_protected_content.
*/
#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
+#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
__u64 extensions;
};
@@ -3038,6 +3234,50 @@ struct drm_i915_gem_create_ext_memory_regions {
__u64 regions;
};
+/**
+ * struct drm_i915_gem_create_ext_protected_content - The
+ * I915_OBJECT_PARAM_PROTECTED_CONTENT extension.
+ *
+ * If this extension is provided, buffer contents are expected to be protected
+ * by PXP encryption and require decryption for scan out and processing. This
+ * is only possible on platforms that have PXP enabled, on all other scenarios
+ * using this extension will cause the ioctl to fail and return -ENODEV. The
+ * flags parameter is reserved for future expansion and must currently be set
+ * to zero.
+ *
+ * The buffer contents are considered invalid after a PXP session teardown.
+ *
+ * The encryption is guaranteed to be processed correctly only if the object
+ * is submitted with a context created using the
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks
+ * at submission time on the validity of the objects involved.
+ *
+ * Below is an example on how to create a protected object:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_gem_create_ext_protected_content protected_ext = {
+ * .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT },
+ * .flags = 0,
+ * };
+ * struct drm_i915_gem_create_ext create_ext = {
+ * .size = PAGE_SIZE,
+ * .extensions = (uintptr_t)&protected_ext,
+ * };
+ *
+ * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+ * if (err) ...
+ */
+struct drm_i915_gem_create_ext_protected_content {
+ /** @base: Extension link. See struct i915_user_extension. */
+ struct i915_user_extension base;
+ /** @flags: reserved for future usage, currently MBZ */
+ __u32 flags;
+};
+
+/* ID of the protected content session managed by i915 when PXP is active */
+#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
+
#if defined(__cplusplus)
}
#endif
diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index 74b85c853..9e82c9688 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -21,19 +21,6 @@ extern "C" {
*/
#define I915_ENGINE_CLASS_COMPUTE 4
-/* Needed for PXP */
-#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
-#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
-#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
-
-/* Needed for PXP */
-struct drm_i915_gem_create_ext_protected_content {
- /** @base: Extension link. See struct i915_user_extension. */
- struct i915_user_extension base;
- /** @flags: reserved for future usage, currently MBZ */
- __u32 flags;
-};
-
#if defined(__cplusplus)
}
#endif
--
2.32.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH 2/2] i915/gem_exec_balancer: Test parallel execbuf
2021-11-09 22:59 [igt-dev] [PATCH 0/2] Test parallel execbuf Matthew Brost
2021-11-09 22:59 ` [igt-dev] [PATCH 1/2] i915_drm.h sync with drm-next Matthew Brost
@ 2021-11-09 22:59 ` Matthew Brost
2021-11-11 18:56 ` Daniele Ceraolo Spurio
2021-11-10 1:45 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2021-11-10 4:06 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: Matthew Brost @ 2021-11-09 22:59 UTC (permalink / raw)
To: igt-dev
Add basic parallel execbuf submission test which more or less just
submits the same BB in loop a which does an atomic increment to a memory
location. The memory location is checked at the end for the correct
value. Different sections use various IOCTL options (e.g. fences,
location of BBs, etc...).
In addition to above sections, an additional section ensure the ordering
of parallel submission by submitting a spinning batch to 1 individual
engine, submit a parallel execbuf to all engines instances within the
class, verify none on parallel execbuf make to hardware, release
spinner, and finally verify everything has completed.
The parallel-ordering section assumes default timeslice / preemption
timeout values. If these values are changed the test may fail.
v2:
(Daniele)
- Add assert to ensure parallel & load_balance both not set in ctx lib
- s/count/expected/g in check_bo()
- use existing query library functions
- clean up bb_per_execbuf / count usage
- drop dead loop
- add comment for parallel-ordering
- don't declare loop variables inside loop
v3:
(Daniele)
- Read timeslice from sysfs
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
lib/intel_ctx.c | 30 +-
lib/intel_ctx.h | 2 +
lib/intel_reg.h | 5 +
tests/i915/gem_exec_balancer.c | 486 +++++++++++++++++++++++++++++++++
4 files changed, 522 insertions(+), 1 deletion(-)
diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c
index f28c15544..e19a54a89 100644
--- a/lib/intel_ctx.c
+++ b/lib/intel_ctx.c
@@ -83,6 +83,7 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg, uint32_t *ctx_id)
{
uint64_t ext_root = 0;
I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(balance, GEM_MAX_ENGINES);
+ I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(parallel, GEM_MAX_ENGINES);
I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, GEM_MAX_ENGINES);
struct drm_i915_gem_context_create_ext_setparam engines_param, vm_param;
struct drm_i915_gem_context_create_ext_setparam persist_param;
@@ -117,7 +118,31 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg, uint32_t *ctx_id)
unsigned num_logical_engines;
memset(&engines, 0, sizeof(engines));
- if (cfg->load_balance) {
+ igt_assert(!(cfg->parallel && cfg->load_balance));
+
+ if (cfg->parallel) {
+ memset(¶llel, 0, sizeof(parallel));
+
+ num_logical_engines = 1;
+
+ parallel.base.name =
+ I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT;
+
+ engines.engines[0].engine_class =
+ I915_ENGINE_CLASS_INVALID;
+ engines.engines[0].engine_instance =
+ I915_ENGINE_CLASS_INVALID_NONE;
+
+ parallel.num_siblings = cfg->num_engines;
+ parallel.width = cfg->width;
+ for (i = 0; i < cfg->num_engines * cfg->width; i++) {
+ igt_assert_eq(cfg->engines[0].engine_class,
+ cfg->engines[i].engine_class);
+ parallel.engines[i] = cfg->engines[i];
+ }
+
+ engines.extensions = to_user_pointer(¶llel);
+ } else if (cfg->load_balance) {
memset(&balance, 0, sizeof(balance));
/* In this case, the first engine is the virtual
@@ -127,6 +152,9 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg, uint32_t *ctx_id)
igt_assert(cfg->num_engines + 1 <= GEM_MAX_ENGINES);
num_logical_engines = cfg->num_engines + 1;
+ balance.base.name =
+ I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE;
+
engines.engines[0].engine_class =
I915_ENGINE_CLASS_INVALID;
engines.engines[0].engine_instance =
diff --git a/lib/intel_ctx.h b/lib/intel_ctx.h
index 9649f6d96..89c65fcd3 100644
--- a/lib/intel_ctx.h
+++ b/lib/intel_ctx.h
@@ -46,7 +46,9 @@ typedef struct intel_ctx_cfg {
uint32_t vm;
bool nopersist;
bool load_balance;
+ bool parallel;
unsigned int num_engines;
+ unsigned int width;
struct i915_engine_class_instance engines[GEM_MAX_ENGINES];
} intel_ctx_cfg_t;
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index c447525a0..44b0d480f 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2642,6 +2642,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16))
+/* Atomics */
+#define MI_ATOMIC ((0x2f << 23) | 2)
+#define MI_ATOMIC_INLINE_DATA (1 << 18)
+#define MI_ATOMIC_ADD (0x7 << 8)
+
/* Batch */
#define MI_BATCH_BUFFER ((0x30 << 23) | 1)
#define MI_BATCH_BUFFER_START (0x31 << 23)
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index e4e5cda4a..0e7703a0d 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -25,8 +25,10 @@
#include <sched.h>
#include <sys/ioctl.h>
#include <sys/signal.h>
+#include <poll.h>
#include "i915/gem.h"
+#include "i915/gem_engine_topology.h"
#include "i915/gem_create.h"
#include "i915/gem_vm.h"
#include "igt.h"
@@ -2752,6 +2754,403 @@ static void nohangcheck(int i915)
close(params);
}
+static void check_bo(int i915, uint32_t handle, unsigned int expected,
+ bool wait)
+{
+ uint32_t *map;
+
+ map = gem_mmap__cpu(i915, handle, 0, 4096, PROT_READ);
+ if (wait)
+ gem_set_domain(i915, handle, I915_GEM_DOMAIN_CPU,
+ I915_GEM_DOMAIN_CPU);
+ igt_assert_eq(map[0], expected);
+ munmap(map, 4096);
+}
+
+static struct drm_i915_query_engine_info *query_engine_info(int i915)
+{
+ struct drm_i915_query_engine_info *engines;
+
+#define QUERY_SIZE 0x4000
+ engines = malloc(QUERY_SIZE);
+ igt_assert(engines);
+ memset(engines, 0, QUERY_SIZE);
+ igt_assert(!__gem_query_engines(i915, engines, QUERY_SIZE));
+#undef QUERY_SIZE
+
+ return engines;
+}
+
+/* This function only works if siblings contains all instances of a class */
+static void logical_sort_siblings(int i915,
+ struct i915_engine_class_instance *siblings,
+ unsigned int count)
+{
+ struct i915_engine_class_instance *sorted;
+ struct drm_i915_query_engine_info *engines;
+ unsigned int i, j;
+
+ sorted = calloc(count, sizeof(*sorted));
+ igt_assert(sorted);
+
+ engines = query_engine_info(i915);
+
+ for (j = 0; j < count; ++j) {
+ for (i = 0; i < engines->num_engines; ++i) {
+ if (siblings[j].engine_class ==
+ engines->engines[i].engine.engine_class &&
+ siblings[j].engine_instance ==
+ engines->engines[i].engine.engine_instance) {
+ uint16_t logical_instance =
+ engines->engines[i].logical_instance;
+
+ igt_assert(logical_instance < count);
+ igt_assert(!sorted[logical_instance].engine_class);
+ igt_assert(!sorted[logical_instance].engine_instance);
+
+ sorted[logical_instance] = siblings[j];
+ break;
+ }
+ }
+ igt_assert(i != engines->num_engines);
+ }
+
+ memcpy(siblings, sorted, sizeof(*sorted) * count);
+ free(sorted);
+ free(engines);
+}
+
+#define PARALLEL_BB_FIRST (0x1 << 0)
+#define PARALLEL_OUT_FENCE (0x1 << 1)
+#define PARALLEL_IN_FENCE (0x1 << 2)
+#define PARALLEL_SUBMIT_FENCE (0x1 << 3)
+#define PARALLEL_CONTEXTS (0x1 << 4)
+#define PARALLEL_VIRTUAL (0x1 << 5)
+
+static void parallel_thread(int i915, unsigned int flags,
+ struct i915_engine_class_instance *siblings,
+ unsigned int count, unsigned int bb_per_execbuf)
+{
+ const intel_ctx_t *ctx = NULL;
+ int n, i, j, fence = 0;
+ uint32_t batch[16];
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_exec_object2 obj[32];
+#define PARALLEL_BB_LOOP_COUNT 512
+ const intel_ctx_t *ctxs[PARALLEL_BB_LOOP_COUNT];
+ uint32_t target_bo_idx = 0;
+ uint32_t first_bb_idx = 1;
+ intel_ctx_cfg_t cfg;
+
+ igt_assert(bb_per_execbuf < 32);
+
+ if (flags & PARALLEL_BB_FIRST) {
+ target_bo_idx = bb_per_execbuf;
+ first_bb_idx = 0;
+ }
+
+ igt_assert(count >= bb_per_execbuf &&
+ count % bb_per_execbuf == 0);
+ memset(&cfg, 0, sizeof(cfg));
+ cfg.parallel = true;
+ cfg.num_engines = count / bb_per_execbuf;
+ cfg.width = bb_per_execbuf;
+ if (flags & PARALLEL_VIRTUAL) {
+ for (i = 0; i < cfg.width; ++i)
+ for (j = 0; j < cfg.num_engines; ++j)
+ memcpy(cfg.engines + i * cfg.num_engines + j,
+ siblings + j * cfg.width + i,
+ sizeof(*siblings));
+ } else {
+ memcpy(cfg.engines, siblings, sizeof(*siblings) * count);
+ }
+ ctx = intel_ctx_create(i915, &cfg);
+
+ i = 0;
+ batch[i] = MI_ATOMIC | MI_ATOMIC_INLINE_DATA |
+ MI_ATOMIC_ADD;
+#define TARGET_BO_OFFSET (0x1 << 16)
+ batch[++i] = TARGET_BO_OFFSET;
+ batch[++i] = 0;
+ batch[++i] = 1;
+ batch[++i] = MI_BATCH_BUFFER_END;
+
+ memset(obj, 0, sizeof(obj));
+ obj[target_bo_idx].offset = TARGET_BO_OFFSET;
+ obj[target_bo_idx].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+ obj[target_bo_idx].handle = gem_create(i915, 4096);
+
+ for (i = first_bb_idx; i < bb_per_execbuf + first_bb_idx; ++i) {
+ obj[i].handle = gem_create(i915, 4096);
+ gem_write(i915, obj[i].handle, 0, batch,
+ sizeof(batch));
+ }
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = bb_per_execbuf + 1;
+ execbuf.flags |= I915_EXEC_HANDLE_LUT;
+ if (flags & PARALLEL_BB_FIRST)
+ execbuf.flags |= I915_EXEC_BATCH_FIRST;
+ if (flags & PARALLEL_OUT_FENCE)
+ execbuf.flags |= I915_EXEC_FENCE_OUT;
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.rsvd1 = ctx->id;
+
+ for (n = 0; n < PARALLEL_BB_LOOP_COUNT; ++n) {
+ execbuf.flags &= ~0x3full;
+ gem_execbuf_wr(i915, &execbuf);
+
+ if (flags & PARALLEL_OUT_FENCE) {
+ igt_assert_eq(sync_fence_wait(execbuf.rsvd2 >> 32,
+ 1000), 0);
+ igt_assert_eq(sync_fence_status(execbuf.rsvd2 >> 32), 1);
+
+ if (fence)
+ close(fence);
+ fence = execbuf.rsvd2 >> 32;
+
+ if (flags & PARALLEL_SUBMIT_FENCE) {
+ execbuf.flags |=
+ I915_EXEC_FENCE_SUBMIT;
+ execbuf.rsvd2 >>= 32;
+ } else if (flags & PARALLEL_IN_FENCE) {
+ execbuf.flags |=
+ I915_EXEC_FENCE_IN;
+ execbuf.rsvd2 >>= 32;
+ } else {
+ execbuf.rsvd2 = 0;
+ }
+ }
+
+ if (flags & PARALLEL_CONTEXTS) {
+ ctxs[n] = ctx;
+ ctx = intel_ctx_create(i915, &cfg);
+ execbuf.rsvd1 = ctx->id;
+ }
+ }
+ if (fence)
+ close(fence);
+
+ check_bo(i915, obj[target_bo_idx].handle,
+ bb_per_execbuf * PARALLEL_BB_LOOP_COUNT, true);
+
+ intel_ctx_destroy(i915, ctx);
+ for (i = 0; flags & PARALLEL_CONTEXTS &&
+ i < PARALLEL_BB_LOOP_COUNT; ++i) {
+ intel_ctx_destroy(i915, ctxs[i]);
+ }
+ for (i = 0; i < bb_per_execbuf + 1; ++i)
+ gem_close(i915, obj[i].handle);
+}
+
+static void parallel(int i915, unsigned int flags)
+{
+ int class;
+
+ for (class = 0; class < 32; class++) {
+ struct i915_engine_class_instance *siblings;
+ unsigned int count, bb_per_execbuf;
+
+ siblings = list_engines(i915, 1u << class, &count);
+ if (!siblings)
+ continue;
+
+ if (count < 2) {
+ free(siblings);
+ continue;
+ }
+
+ logical_sort_siblings(i915, siblings, count);
+ bb_per_execbuf = count;
+
+ parallel_thread(i915, flags, siblings,
+ count, bb_per_execbuf);
+
+ free(siblings);
+ }
+}
+
+static void parallel_balancer(int i915, unsigned int flags)
+{
+ int class;
+
+ for (class = 0; class < 32; class++) {
+ struct i915_engine_class_instance *siblings;
+ unsigned int bb_per_execbuf;
+ unsigned int count;
+
+ siblings = list_engines(i915, 1u << class, &count);
+ if (!siblings)
+ continue;
+
+ if (count < 4) {
+ free(siblings);
+ continue;
+ }
+
+ logical_sort_siblings(i915, siblings, count);
+
+ for (bb_per_execbuf = 2; count / bb_per_execbuf > 1;
+ ++bb_per_execbuf) {
+ igt_fork(child, count / bb_per_execbuf)
+ parallel_thread(i915,
+ flags | PARALLEL_VIRTUAL,
+ siblings,
+ count,
+ bb_per_execbuf);
+ igt_waitchildren();
+ }
+
+ free(siblings);
+ }
+}
+
+static bool fence_busy(int fence)
+{
+ return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
+}
+
+static unsigned int get_timeslice(int i915,
+ struct i915_engine_class_instance engine)
+{
+ unsigned int val;
+
+ switch (engine.engine_class) {
+ case I915_ENGINE_CLASS_RENDER:
+ gem_engine_property_scanf(i915, "rcs0", "timeslice_duration_ms",
+ "%d", &val);
+ break;
+ case I915_ENGINE_CLASS_COPY:
+ gem_engine_property_scanf(i915, "bcs0", "timeslice_duration_ms",
+ "%d", &val);
+ break;
+ case I915_ENGINE_CLASS_VIDEO:
+ gem_engine_property_scanf(i915, "vcs0", "timeslice_duration_ms",
+ "%d", &val);
+ break;
+ case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ gem_engine_property_scanf(i915, "vecs0", "timeslice_duration_ms",
+ "%d", &val);
+ break;
+ }
+
+ return val;
+}
+
+/*
+ * Ensure a parallel submit actually runs on HW in parallel by putting on a
+ * spinner on 1 engine, doing a parallel submit, and parallel submit is blocked
+ * behind spinner.
+ */
+static void parallel_ordering(int i915, unsigned int flags)
+{
+ int class;
+
+ for (class = 0; class < 32; class++) {
+ const intel_ctx_t *ctx = NULL, *spin_ctx = NULL;
+ struct i915_engine_class_instance *siblings;
+ unsigned int count;
+ int i = 0, fence = 0;
+ uint32_t batch[16];
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_exec_object2 obj[32];
+ igt_spin_t *spin;
+ intel_ctx_cfg_t cfg;
+
+ siblings = list_engines(i915, 1u << class, &count);
+ if (!siblings)
+ continue;
+
+ if (count < 2) {
+ free(siblings);
+ continue;
+ }
+
+ logical_sort_siblings(i915, siblings, count);
+
+ memset(&cfg, 0, sizeof(cfg));
+ cfg.parallel = true;
+ cfg.num_engines = 1;
+ cfg.width = count;
+ memcpy(cfg.engines, siblings, sizeof(*siblings) * count);
+
+ ctx = intel_ctx_create(i915, &cfg);
+
+ batch[i] = MI_ATOMIC | MI_ATOMIC_INLINE_DATA |
+ MI_ATOMIC_ADD;
+ batch[++i] = TARGET_BO_OFFSET;
+ batch[++i] = 0;
+ batch[++i] = 1;
+ batch[++i] = MI_BATCH_BUFFER_END;
+
+ memset(obj, 0, sizeof(obj));
+ obj[0].offset = TARGET_BO_OFFSET;
+ obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+ obj[0].handle = gem_create(i915, 4096);
+
+ for (i = 1; i < count + 1; ++i) {
+ obj[i].handle = gem_create(i915, 4096);
+ gem_write(i915, obj[i].handle, 0, batch,
+ sizeof(batch));
+ }
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = count + 1;
+ execbuf.flags |= I915_EXEC_HANDLE_LUT;
+ execbuf.flags |= I915_EXEC_NO_RELOC;
+ execbuf.flags |= I915_EXEC_FENCE_OUT;
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.rsvd1 = ctx->id;
+
+ /* Block parallel submission */
+ spin_ctx = ctx_create_engines(i915, siblings, count);
+ spin = __igt_spin_new(i915,
+ .ctx = spin_ctx,
+ .engine = 0,
+ .flags = IGT_SPIN_FENCE_OUT |
+ IGT_SPIN_NO_PREEMPTION);
+
+ /* Wait for spinners to start */
+ usleep(5 * 10000);
+ igt_assert(fence_busy(spin->out_fence));
+
+ /* Submit parallel execbuf */
+ gem_execbuf_wr(i915, &execbuf);
+ fence = execbuf.rsvd2 >> 32;
+
+ /*
+ * Wait long enough for timeslcing to kick in but not
+ * preemption. Spinner + parallel execbuf should be
+ * active. Assuming default timeslice / preemption values, if
+ * these are changed it is possible for the test to fail.
+ */
+ usleep(get_timeslice(i915, siblings[0]) * 2);
+ igt_assert(fence_busy(spin->out_fence));
+ igt_assert(fence_busy(fence));
+ check_bo(i915, obj[0].handle, 0, false);
+
+ /*
+ * End spinner and wait for spinner + parallel execbuf
+ * to compelte.
+ */
+ igt_spin_end(spin);
+ igt_assert_eq(sync_fence_wait(fence, 1000), 0);
+ igt_assert_eq(sync_fence_status(fence), 1);
+ check_bo(i915, obj[0].handle, count, true);
+ close(fence);
+
+ /* Clean up */
+ intel_ctx_destroy(i915, ctx);
+ intel_ctx_destroy(i915, spin_ctx);
+ for (i = 0; i < count + 1; ++i)
+ gem_close(i915, obj[i].handle);
+ free(siblings);
+ igt_spin_free(i915, spin);
+ }
+}
+
static bool has_persistence(int i915)
{
struct drm_i915_gem_context_param p = {
@@ -2786,6 +3185,61 @@ static bool has_load_balancer(int i915)
return err == 0;
}
+static bool has_logical_mapping(int i915)
+{
+ struct drm_i915_query_engine_info *engines;
+ unsigned int i;
+
+ engines = query_engine_info(i915);
+
+ for (i = 0; i < engines->num_engines; ++i)
+ if (!(engines->engines[i].flags &
+ I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE)) {
+ free(engines);
+ return false;
+ }
+
+ free(engines);
+ return true;
+}
+
+static bool has_parallel_execbuf(int i915)
+{
+ intel_ctx_cfg_t cfg = {
+ .parallel = true,
+ .num_engines = 1,
+ };
+ const intel_ctx_t *ctx = NULL;
+ int err;
+
+ for (int class = 0; class < 32; class++) {
+ struct i915_engine_class_instance *siblings;
+ unsigned int count;
+
+ siblings = list_engines(i915, 1u << class, &count);
+ if (!siblings)
+ continue;
+
+ if (count < 2) {
+ free(siblings);
+ continue;
+ }
+
+ logical_sort_siblings(i915, siblings, count);
+
+ cfg.width = count;
+ memcpy(cfg.engines, siblings, sizeof(*siblings) * count);
+ free(siblings);
+
+ err = __intel_ctx_create(i915, &cfg, &ctx);
+ intel_ctx_destroy(i915, ctx);
+
+ return err == 0;
+ }
+
+ return false;
+}
+
igt_main
{
int i915 = -1;
@@ -2886,6 +3340,38 @@ igt_main
igt_stop_hang_detector();
}
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(has_logical_mapping(i915));
+ igt_require(has_parallel_execbuf(i915));
+ }
+
+ igt_subtest("parallel-ordering")
+ parallel_ordering(i915, 0);
+
+ igt_subtest("parallel")
+ parallel(i915, 0);
+
+ igt_subtest("parallel-bb-first")
+ parallel(i915, PARALLEL_BB_FIRST);
+
+ igt_subtest("parallel-out-fence")
+ parallel(i915, PARALLEL_OUT_FENCE);
+
+ igt_subtest("parallel-keep-in-fence")
+ parallel(i915, PARALLEL_OUT_FENCE | PARALLEL_IN_FENCE);
+
+ igt_subtest("parallel-keep-submit-fence")
+ parallel(i915, PARALLEL_OUT_FENCE |
+ PARALLEL_SUBMIT_FENCE);
+
+ igt_subtest("parallel-contexts")
+ parallel(i915, PARALLEL_CONTEXTS);
+
+ igt_subtest("parallel-balancer")
+ parallel_balancer(i915, 0);
+ }
+
igt_subtest_group {
igt_hang_t hang;
--
2.32.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Test parallel execbuf
2021-11-09 22:59 [igt-dev] [PATCH 0/2] Test parallel execbuf Matthew Brost
2021-11-09 22:59 ` [igt-dev] [PATCH 1/2] i915_drm.h sync with drm-next Matthew Brost
2021-11-09 22:59 ` [igt-dev] [PATCH 2/2] i915/gem_exec_balancer: Test parallel execbuf Matthew Brost
@ 2021-11-10 1:45 ` Patchwork
2021-11-10 4:06 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-11-10 1:45 UTC (permalink / raw)
To: Matthew Brost; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 5445 bytes --]
== Series Details ==
Series: Test parallel execbuf
URL : https://patchwork.freedesktop.org/series/96734/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10859 -> IGTPW_6387
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/index.html
Participating hosts (37 -> 32)
------------------------------
Additional (2): fi-tgl-1115g4 fi-pnv-d510
Missing (7): fi-bdw-5557u bat-dg1-6 fi-tgl-u2 fi-icl-u2 fi-bsw-cyan bat-adlp-4 fi-ctg-p8600
Known issues
------------
Here are the changes found in IGTPW_6387 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4: NOTRUN -> [SKIP][1] ([fdo#109315])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315] / [i915#2575]) +16 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#1155])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([fdo#111827]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([i915#4103]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([fdo#109285])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#1072]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][9] ([fdo#109271]) +53 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([i915#3301])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-bxt-dsi: NOTRUN -> [FAIL][11] ([i915#2426] / [i915#3363])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-bxt-dsi/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][12] ([i915#3303]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6275 -> IGTPW_6387
CI-20190529: 20190529
CI_DRM_10859: b6a4397b540c326ddaf8ccc1d2c14096702900f6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_6387: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/index.html
IGT_6275: 6d172a5cf51ffff5f2780e2837860d613db5067f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Testlist changes ==
+igt@gem_exec_balancer@parallel
+igt@gem_exec_balancer@parallel-balancer
+igt@gem_exec_balancer@parallel-bb-first
+igt@gem_exec_balancer@parallel-contexts
+igt@gem_exec_balancer@parallel-keep-in-fence
+igt@gem_exec_balancer@parallel-keep-submit-fence
+igt@gem_exec_balancer@parallel-ordering
+igt@gem_exec_balancer@parallel-out-fence
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/index.html
[-- Attachment #2: Type: text/html, Size: 6455 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Test parallel execbuf
2021-11-09 22:59 [igt-dev] [PATCH 0/2] Test parallel execbuf Matthew Brost
` (2 preceding siblings ...)
2021-11-10 1:45 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
@ 2021-11-10 4:06 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-11-10 4:06 UTC (permalink / raw)
To: Matthew Brost; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 30239 bytes --]
== Series Details ==
Series: Test parallel execbuf
URL : https://patchwork.freedesktop.org/series/96734/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10859_full -> IGTPW_6387_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_6387_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_6387_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/index.html
Participating hosts (10 -> 7)
------------------------------
Missing (3): pig-skl-6260u pig-glk-j5005 shard-rkl
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_6387_full:
### IGT changes ###
#### Possible regressions ####
* {igt@gem_exec_balancer@parallel-contexts} (NEW):
- shard-tglb: NOTRUN -> [SKIP][1] +5 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb2/igt@gem_exec_balancer@parallel-contexts.html
* {igt@gem_exec_balancer@parallel-out-fence} (NEW):
- shard-iclb: NOTRUN -> [SKIP][2] +7 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb3/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_userptr_blits@huge-split:
- shard-snb: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-snb5/igt@gem_userptr_blits@huge-split.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-snb2/igt@gem_userptr_blits@huge-split.html
New tests
---------
New tests have been introduced between CI_DRM_10859_full and IGTPW_6387_full:
### New IGT tests (8) ###
* igt@gem_exec_balancer@parallel:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@parallel-balancer:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@parallel-bb-first:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@parallel-contexts:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@parallel-keep-in-fence:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@parallel-ordering:
- Statuses : 3 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_balancer@parallel-out-fence:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_6387_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][5] ([i915#3002])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl4/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-tglb: [PASS][6] -> [INCOMPLETE][7] ([i915#456])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-tglb5/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-snb6/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-iclb: [PASS][9] -> [TIMEOUT][10] ([i915#3070])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-iclb2/igt@gem_eio@in-flight-contexts-1us.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb1/igt@gem_eio@in-flight-contexts-1us.html
* {igt@gem_exec_balancer@parallel-out-fence} (NEW):
- shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271]) +86 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk7/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
- shard-glk: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
- shard-tglb: NOTRUN -> [FAIL][14] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][17] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk8/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][20] -> [FAIL][21] ([i915#2849])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][22] -> [DMESG-WARN][23] ([i915#180]) +3 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-kbl3/igt@gem_exec_suspend@basic-s3.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl6/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-glk: [PASS][24] -> [DMESG-WARN][25] ([i915#118])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-glk4/igt@gem_exec_whisper@basic-contexts-priority-all.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk6/igt@gem_exec_whisper@basic-contexts-priority-all.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#4270]) +4 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb1/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-iclb: NOTRUN -> [SKIP][27] ([i915#4270])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb8/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- shard-iclb: NOTRUN -> [SKIP][28] ([i915#768])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb8/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [PASS][29] -> [INCOMPLETE][30] ([i915#3614] / [i915#794])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-kbl2/igt@gem_softpin@noreloc-s3.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl3/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][31] ([i915#3002])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-apl6/igt@gem_userptr_blits@input-checking.html
* igt@gen7_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109289]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb6/igt@gen7_exec_parse@cmd-crossing-page.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109289]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb1/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@allowed-all:
- shard-tglb: NOTRUN -> [SKIP][34] ([i915#2856]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb1/igt@gen9_exec_parse@allowed-all.html
- shard-glk: [PASS][35] -> [DMESG-WARN][36] ([i915#1436] / [i915#716])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-glk4/igt@gen9_exec_parse@allowed-all.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk3/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@valid-registers:
- shard-iclb: NOTRUN -> [SKIP][37] ([i915#2856]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb6/igt@gen9_exec_parse@valid-registers.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][38] -> [FAIL][39] ([i915#454])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
- shard-kbl: NOTRUN -> [FAIL][40] ([i915#454])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl4/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#111644] / [i915#1397] / [i915#2411])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb8/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][42] ([fdo#111614])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb7/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3777]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#111615]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb8/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#110723])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3886]) +5 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk1/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +4 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-apl6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109278] / [i915#3886])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb2/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +6 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl3/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3689]) +4 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb5/igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_chamelium@hdmi-audio:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +8 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-apl2/igt@kms_chamelium@hdmi-audio.html
* igt@kms_chamelium@hdmi-edid-read:
- shard-tglb: NOTRUN -> [SKIP][52] ([fdo#109284] / [fdo#111827]) +5 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb8/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd:
- shard-glk: NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +5 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk1/igt@kms_chamelium@hdmi-hpd.html
* igt@kms_color_chamelium@pipe-b-ctm-blue-to-red:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109284] / [fdo#111827]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb2/igt@kms_color_chamelium@pipe-b-ctm-blue-to-red.html
- shard-snb: NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-snb5/igt@kms_color_chamelium@pipe-b-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-c-gamma:
- shard-kbl: NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +14 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl4/igt@kms_color_chamelium@pipe-c-gamma.html
* igt@kms_color_chamelium@pipe-d-ctm-0-5:
- shard-iclb: NOTRUN -> [SKIP][57] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb4/igt@kms_color_chamelium@pipe-d-ctm-0-5.html
* igt@kms_content_protection@srm:
- shard-kbl: NOTRUN -> [TIMEOUT][58] ([i915#1319])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl7/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271]) +130 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-tglb: [PASS][60] -> [INCOMPLETE][61] ([i915#2411] / [i915#2828] / [i915#456])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][62] ([i915#3319]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-onscreen:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109278] / [fdo#109279]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb2/igt@kms_cursor_crc@pipe-b-cursor-512x512-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][64] ([i915#3359]) +3 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-random:
- shard-tglb: NOTRUN -> [SKIP][65] ([fdo#109279] / [i915#3359]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-iclb: NOTRUN -> [SKIP][66] ([fdo#109274] / [fdo#109278]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb3/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-glk: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#533])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk9/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_cursor_legacy@pipe-d-single-move:
- shard-iclb: NOTRUN -> [SKIP][68] ([fdo#109278]) +10 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb1/igt@kms_cursor_legacy@pipe-d-single-move.html
* igt@kms_flip@2x-nonexisting-fb-interruptible:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109274])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb4/igt@kms_flip@2x-nonexisting-fb-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][70] -> [DMESG-WARN][71] ([i915#180]) +5 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-tglb: [PASS][72] -> [INCOMPLETE][73] ([i915#2411] / [i915#456]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-tglb2/igt@kms_flip@flip-vs-suspend@a-edp1.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb7/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-glk: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2672])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-kbl: NOTRUN -> [SKIP][75] ([fdo#109271]) +222 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109280]) +9 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt:
- shard-tglb: NOTRUN -> [SKIP][77] ([fdo#111825]) +25 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-snb: NOTRUN -> [SKIP][78] ([fdo#109271]) +67 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-snb4/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][79] ([i915#180])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@static-toggle-dpms:
- shard-tglb: NOTRUN -> [SKIP][80] ([i915#1187])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb3/igt@kms_hdr@static-toggle-dpms.html
- shard-iclb: NOTRUN -> [SKIP][81] ([i915#1187])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb2/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#533])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-apl4/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#533]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-glk: NOTRUN -> [FAIL][84] ([fdo#108145] / [i915#265])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][85] ([i915#265])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-apl3/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
- shard-kbl: NOTRUN -> [FAIL][86] ([i915#265])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-tglb: NOTRUN -> [SKIP][87] ([i915#3536]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#658]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-apl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#658]) +2 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-glk: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#658])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-tglb: NOTRUN -> [SKIP][91] ([i915#2920])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [PASS][92] -> [SKIP][93] ([fdo#109441])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: NOTRUN -> [SKIP][94] ([fdo#109441])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-tglb: NOTRUN -> [FAIL][95] ([i915#132] / [i915#3467]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb7/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_setmode@basic:
- shard-glk: [PASS][96] -> [FAIL][97] ([i915#31])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-glk3/igt@kms_setmode@basic.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk8/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][98] -> [DMESG-WARN][99] ([i915#180] / [i915#295])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2437]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl6/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-tglb: NOTRUN -> [SKIP][101] ([i915#2530])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb8/igt@nouveau_crc@pipe-a-source-rg.html
* igt@prime_nv_api@i915_nv_import_twice:
- shard-iclb: NOTRUN -> [SKIP][102] ([fdo#109291]) +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb1/igt@prime_nv_api@i915_nv_import_twice.html
* igt@prime_nv_pcopy@test3_1:
- shard-tglb: NOTRUN -> [SKIP][103] ([fdo#109291]) +3 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb2/igt@prime_nv_pcopy@test3_1.html
* igt@sysfs_clients@busy:
- shard-tglb: NOTRUN -> [SKIP][104] ([i915#2994]) +2 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb3/igt@sysfs_clients@busy.html
* igt@sysfs_clients@sema-25:
- shard-kbl: NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#2994]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl7/igt@sysfs_clients@sema-25.html
* igt@sysfs_clients@split-25:
- shard-glk: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2994]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk6/igt@sysfs_clients@split-25.html
#### Possible fixes ####
* igt@gem_ctx_shared@q-smoketest-all:
- shard-glk: [DMESG-WARN][107] ([i915#118]) -> [PASS][108] +2 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-glk1/igt@gem_ctx_shared@q-smoketest-all.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk3/igt@gem_ctx_shared@q-smoketest-all.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][109] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-tglb2/igt@gem_eio@unwedge-stress.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb2/igt@gem_eio@unwedge-stress.html
- shard-iclb: [TIMEOUT][111] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-iclb1/igt@gem_eio@unwedge-stress.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [FAIL][113] ([i915#2842]) -> [PASS][114] +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-kbl4/igt@gem_exec_fair@basic-none-vip@rcs0.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl3/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: [FAIL][115] ([i915#2842]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][117] ([i915#2842]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-tglb: [INCOMPLETE][119] ([i915#456]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-tglb7/igt@i915_pm_backlight@fade_with_suspend.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb5/igt@i915_pm_backlight@fade_with_suspend.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-apl: [FAIL][121] ([i915#2521]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-apl6/igt@kms_async_flips@alternate-sync-async-flip.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-apl4/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [DMESG-WARN][123] ([i915#180]) -> [PASS][124] +4 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [DMESG-WARN][125] ([i915#180]) -> [PASS][126] +5 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-kbl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-iclb: [SKIP][127] ([i915#3701]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-tglb: [INCOMPLETE][129] ([i915#4182]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/shard-tglb1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][131] ([fdo#109441]) -> [PASS][132] +2 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10859/shard-iclb3/igt@kms_psr@psr2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6387/index.html
[-- Attachment #2: Type: text/html, Size: 33866 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [igt-dev] [PATCH 2/2] i915/gem_exec_balancer: Test parallel execbuf
2021-11-09 22:59 ` [igt-dev] [PATCH 2/2] i915/gem_exec_balancer: Test parallel execbuf Matthew Brost
@ 2021-11-11 18:56 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 9+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-11-11 18:56 UTC (permalink / raw)
To: Matthew Brost, igt-dev
On 11/9/2021 2:59 PM, Matthew Brost wrote:
> Add basic parallel execbuf submission test which more or less just
> submits the same BB in loop a which does an atomic increment to a memory
> location. The memory location is checked at the end for the correct
> value. Different sections use various IOCTL options (e.g. fences,
> location of BBs, etc...).
>
> In addition to above sections, an additional section ensure the ordering
> of parallel submission by submitting a spinning batch to 1 individual
> engine, submit a parallel execbuf to all engines instances within the
> class, verify none on parallel execbuf make to hardware, release
> spinner, and finally verify everything has completed.
>
> The parallel-ordering section assumes default timeslice / preemption
> timeout values. If these values are changed the test may fail.
>
> v2:
> (Daniele)
> - Add assert to ensure parallel & load_balance both not set in ctx lib
> - s/count/expected/g in check_bo()
> - use existing query library functions
> - clean up bb_per_execbuf / count usage
> - drop dead loop
> - add comment for parallel-ordering
> - don't declare loop variables inside loop
> v3:
> (Daniele)
> - Read timeslice from sysfs
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> lib/intel_ctx.c | 30 +-
> lib/intel_ctx.h | 2 +
> lib/intel_reg.h | 5 +
> tests/i915/gem_exec_balancer.c | 486 +++++++++++++++++++++++++++++++++
> 4 files changed, 522 insertions(+), 1 deletion(-)
>
> diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c
> index f28c15544..e19a54a89 100644
> --- a/lib/intel_ctx.c
> +++ b/lib/intel_ctx.c
> @@ -83,6 +83,7 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg, uint32_t *ctx_id)
> {
> uint64_t ext_root = 0;
> I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(balance, GEM_MAX_ENGINES);
> + I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(parallel, GEM_MAX_ENGINES);
> I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, GEM_MAX_ENGINES);
> struct drm_i915_gem_context_create_ext_setparam engines_param, vm_param;
> struct drm_i915_gem_context_create_ext_setparam persist_param;
> @@ -117,7 +118,31 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg, uint32_t *ctx_id)
> unsigned num_logical_engines;
> memset(&engines, 0, sizeof(engines));
>
> - if (cfg->load_balance) {
> + igt_assert(!(cfg->parallel && cfg->load_balance));
> +
> + if (cfg->parallel) {
> + memset(¶llel, 0, sizeof(parallel));
> +
> + num_logical_engines = 1;
> +
> + parallel.base.name =
> + I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT;
> +
> + engines.engines[0].engine_class =
> + I915_ENGINE_CLASS_INVALID;
> + engines.engines[0].engine_instance =
> + I915_ENGINE_CLASS_INVALID_NONE;
> +
> + parallel.num_siblings = cfg->num_engines;
> + parallel.width = cfg->width;
> + for (i = 0; i < cfg->num_engines * cfg->width; i++) {
> + igt_assert_eq(cfg->engines[0].engine_class,
> + cfg->engines[i].engine_class);
> + parallel.engines[i] = cfg->engines[i];
> + }
> +
> + engines.extensions = to_user_pointer(¶llel);
> + } else if (cfg->load_balance) {
> memset(&balance, 0, sizeof(balance));
>
> /* In this case, the first engine is the virtual
> @@ -127,6 +152,9 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg, uint32_t *ctx_id)
> igt_assert(cfg->num_engines + 1 <= GEM_MAX_ENGINES);
> num_logical_engines = cfg->num_engines + 1;
>
> + balance.base.name =
> + I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE;
> +
> engines.engines[0].engine_class =
> I915_ENGINE_CLASS_INVALID;
> engines.engines[0].engine_instance =
> diff --git a/lib/intel_ctx.h b/lib/intel_ctx.h
> index 9649f6d96..89c65fcd3 100644
> --- a/lib/intel_ctx.h
> +++ b/lib/intel_ctx.h
> @@ -46,7 +46,9 @@ typedef struct intel_ctx_cfg {
> uint32_t vm;
> bool nopersist;
> bool load_balance;
> + bool parallel;
> unsigned int num_engines;
> + unsigned int width;
> struct i915_engine_class_instance engines[GEM_MAX_ENGINES];
> } intel_ctx_cfg_t;
>
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index c447525a0..44b0d480f 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2642,6 +2642,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>
> #define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16))
>
> +/* Atomics */
> +#define MI_ATOMIC ((0x2f << 23) | 2)
> +#define MI_ATOMIC_INLINE_DATA (1 << 18)
> +#define MI_ATOMIC_ADD (0x7 << 8)
> +
> /* Batch */
> #define MI_BATCH_BUFFER ((0x30 << 23) | 1)
> #define MI_BATCH_BUFFER_START (0x31 << 23)
> diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
> index e4e5cda4a..0e7703a0d 100644
> --- a/tests/i915/gem_exec_balancer.c
> +++ b/tests/i915/gem_exec_balancer.c
> @@ -25,8 +25,10 @@
> #include <sched.h>
> #include <sys/ioctl.h>
> #include <sys/signal.h>
> +#include <poll.h>
>
> #include "i915/gem.h"
> +#include "i915/gem_engine_topology.h"
> #include "i915/gem_create.h"
> #include "i915/gem_vm.h"
> #include "igt.h"
> @@ -2752,6 +2754,403 @@ static void nohangcheck(int i915)
> close(params);
> }
>
> +static void check_bo(int i915, uint32_t handle, unsigned int expected,
> + bool wait)
> +{
> + uint32_t *map;
> +
> + map = gem_mmap__cpu(i915, handle, 0, 4096, PROT_READ);
> + if (wait)
> + gem_set_domain(i915, handle, I915_GEM_DOMAIN_CPU,
> + I915_GEM_DOMAIN_CPU);
> + igt_assert_eq(map[0], expected);
> + munmap(map, 4096);
> +}
> +
> +static struct drm_i915_query_engine_info *query_engine_info(int i915)
> +{
> + struct drm_i915_query_engine_info *engines;
> +
> +#define QUERY_SIZE 0x4000
> + engines = malloc(QUERY_SIZE);
> + igt_assert(engines);
> + memset(engines, 0, QUERY_SIZE);
> + igt_assert(!__gem_query_engines(i915, engines, QUERY_SIZE));
> +#undef QUERY_SIZE
> +
> + return engines;
> +}
> +
> +/* This function only works if siblings contains all instances of a class */
> +static void logical_sort_siblings(int i915,
> + struct i915_engine_class_instance *siblings,
> + unsigned int count)
> +{
> + struct i915_engine_class_instance *sorted;
> + struct drm_i915_query_engine_info *engines;
> + unsigned int i, j;
> +
> + sorted = calloc(count, sizeof(*sorted));
> + igt_assert(sorted);
> +
> + engines = query_engine_info(i915);
> +
> + for (j = 0; j < count; ++j) {
> + for (i = 0; i < engines->num_engines; ++i) {
> + if (siblings[j].engine_class ==
> + engines->engines[i].engine.engine_class &&
> + siblings[j].engine_instance ==
> + engines->engines[i].engine.engine_instance) {
> + uint16_t logical_instance =
> + engines->engines[i].logical_instance;
> +
> + igt_assert(logical_instance < count);
> + igt_assert(!sorted[logical_instance].engine_class);
> + igt_assert(!sorted[logical_instance].engine_instance);
> +
> + sorted[logical_instance] = siblings[j];
> + break;
> + }
> + }
> + igt_assert(i != engines->num_engines);
> + }
> +
> + memcpy(siblings, sorted, sizeof(*sorted) * count);
> + free(sorted);
> + free(engines);
> +}
> +
> +#define PARALLEL_BB_FIRST (0x1 << 0)
> +#define PARALLEL_OUT_FENCE (0x1 << 1)
> +#define PARALLEL_IN_FENCE (0x1 << 2)
> +#define PARALLEL_SUBMIT_FENCE (0x1 << 3)
> +#define PARALLEL_CONTEXTS (0x1 << 4)
> +#define PARALLEL_VIRTUAL (0x1 << 5)
> +
> +static void parallel_thread(int i915, unsigned int flags,
> + struct i915_engine_class_instance *siblings,
> + unsigned int count, unsigned int bb_per_execbuf)
> +{
> + const intel_ctx_t *ctx = NULL;
> + int n, i, j, fence = 0;
> + uint32_t batch[16];
> + struct drm_i915_gem_execbuffer2 execbuf;
> + struct drm_i915_gem_exec_object2 obj[32];
> +#define PARALLEL_BB_LOOP_COUNT 512
> + const intel_ctx_t *ctxs[PARALLEL_BB_LOOP_COUNT];
> + uint32_t target_bo_idx = 0;
> + uint32_t first_bb_idx = 1;
> + intel_ctx_cfg_t cfg;
> +
> + igt_assert(bb_per_execbuf < 32);
> +
> + if (flags & PARALLEL_BB_FIRST) {
> + target_bo_idx = bb_per_execbuf;
> + first_bb_idx = 0;
> + }
> +
> + igt_assert(count >= bb_per_execbuf &&
> + count % bb_per_execbuf == 0);
As we've already discussed offline the count % bb_per_execbuf == 0
should be removed because we can have valid cases that fail that assert
(e.g. two 3-wide parallel engines with 8 total engines).
> + memset(&cfg, 0, sizeof(cfg));
> + cfg.parallel = true;
> + cfg.num_engines = count / bb_per_execbuf;
> + cfg.width = bb_per_execbuf;
> + if (flags & PARALLEL_VIRTUAL) {
> + for (i = 0; i < cfg.width; ++i)
> + for (j = 0; j < cfg.num_engines; ++j)
> + memcpy(cfg.engines + i * cfg.num_engines + j,
> + siblings + j * cfg.width + i,
> + sizeof(*siblings));
> + } else {
> + memcpy(cfg.engines, siblings, sizeof(*siblings) * count);
> + }
> + ctx = intel_ctx_create(i915, &cfg);
> +
> + i = 0;
> + batch[i] = MI_ATOMIC | MI_ATOMIC_INLINE_DATA |
> + MI_ATOMIC_ADD;
> +#define TARGET_BO_OFFSET (0x1 << 16)
> + batch[++i] = TARGET_BO_OFFSET;
> + batch[++i] = 0;
> + batch[++i] = 1;
> + batch[++i] = MI_BATCH_BUFFER_END;
> +
> + memset(obj, 0, sizeof(obj));
> + obj[target_bo_idx].offset = TARGET_BO_OFFSET;
> + obj[target_bo_idx].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> + obj[target_bo_idx].handle = gem_create(i915, 4096);
> +
> + for (i = first_bb_idx; i < bb_per_execbuf + first_bb_idx; ++i) {
> + obj[i].handle = gem_create(i915, 4096);
> + gem_write(i915, obj[i].handle, 0, batch,
> + sizeof(batch));
> + }
> +
> + memset(&execbuf, 0, sizeof(execbuf));
> + execbuf.buffers_ptr = to_user_pointer(obj);
> + execbuf.buffer_count = bb_per_execbuf + 1;
> + execbuf.flags |= I915_EXEC_HANDLE_LUT;
> + if (flags & PARALLEL_BB_FIRST)
> + execbuf.flags |= I915_EXEC_BATCH_FIRST;
> + if (flags & PARALLEL_OUT_FENCE)
> + execbuf.flags |= I915_EXEC_FENCE_OUT;
> + execbuf.buffers_ptr = to_user_pointer(obj);
> + execbuf.rsvd1 = ctx->id;
> +
> + for (n = 0; n < PARALLEL_BB_LOOP_COUNT; ++n) {
> + execbuf.flags &= ~0x3full;
> + gem_execbuf_wr(i915, &execbuf);
> +
> + if (flags & PARALLEL_OUT_FENCE) {
> + igt_assert_eq(sync_fence_wait(execbuf.rsvd2 >> 32,
> + 1000), 0);
> + igt_assert_eq(sync_fence_status(execbuf.rsvd2 >> 32), 1);
> +
> + if (fence)
> + close(fence);
> + fence = execbuf.rsvd2 >> 32;
> +
> + if (flags & PARALLEL_SUBMIT_FENCE) {
> + execbuf.flags |=
> + I915_EXEC_FENCE_SUBMIT;
> + execbuf.rsvd2 >>= 32;
> + } else if (flags & PARALLEL_IN_FENCE) {
> + execbuf.flags |=
> + I915_EXEC_FENCE_IN;
> + execbuf.rsvd2 >>= 32;
> + } else {
> + execbuf.rsvd2 = 0;
> + }
> + }
> +
> + if (flags & PARALLEL_CONTEXTS) {
> + ctxs[n] = ctx;
> + ctx = intel_ctx_create(i915, &cfg);
> + execbuf.rsvd1 = ctx->id;
> + }
> + }
> + if (fence)
> + close(fence);
> +
> + check_bo(i915, obj[target_bo_idx].handle,
> + bb_per_execbuf * PARALLEL_BB_LOOP_COUNT, true);
> +
> + intel_ctx_destroy(i915, ctx);
> + for (i = 0; flags & PARALLEL_CONTEXTS &&
> + i < PARALLEL_BB_LOOP_COUNT; ++i) {
> + intel_ctx_destroy(i915, ctxs[i]);
> + }
> + for (i = 0; i < bb_per_execbuf + 1; ++i)
> + gem_close(i915, obj[i].handle);
> +}
> +
> +static void parallel(int i915, unsigned int flags)
> +{
> + int class;
> +
> + for (class = 0; class < 32; class++) {
> + struct i915_engine_class_instance *siblings;
> + unsigned int count, bb_per_execbuf;
> +
> + siblings = list_engines(i915, 1u << class, &count);
> + if (!siblings)
> + continue;
> +
> + if (count < 2) {
> + free(siblings);
> + continue;
> + }
> +
> + logical_sort_siblings(i915, siblings, count);
> + bb_per_execbuf = count;
> +
> + parallel_thread(i915, flags, siblings,
> + count, bb_per_execbuf);
> +
> + free(siblings);
> + }
> +}
> +
> +static void parallel_balancer(int i915, unsigned int flags)
> +{
> + int class;
> +
> + for (class = 0; class < 32; class++) {
> + struct i915_engine_class_instance *siblings;
> + unsigned int bb_per_execbuf;
> + unsigned int count;
> +
> + siblings = list_engines(i915, 1u << class, &count);
> + if (!siblings)
> + continue;
> +
> + if (count < 4) {
> + free(siblings);
> + continue;
> + }
> +
> + logical_sort_siblings(i915, siblings, count);
> +
> + for (bb_per_execbuf = 2; count / bb_per_execbuf > 1;
> + ++bb_per_execbuf) {
> + igt_fork(child, count / bb_per_execbuf)
> + parallel_thread(i915,
> + flags | PARALLEL_VIRTUAL,
> + siblings,
> + count,
> + bb_per_execbuf);
> + igt_waitchildren();
> + }
> +
> + free(siblings);
> + }
> +}
> +
> +static bool fence_busy(int fence)
> +{
> + return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
> +}
> +
> +static unsigned int get_timeslice(int i915,
> + struct i915_engine_class_instance engine)
> +{
> + unsigned int val;
> +
> + switch (engine.engine_class) {
> + case I915_ENGINE_CLASS_RENDER:
> + gem_engine_property_scanf(i915, "rcs0", "timeslice_duration_ms",
> + "%d", &val);
> + break;
> + case I915_ENGINE_CLASS_COPY:
> + gem_engine_property_scanf(i915, "bcs0", "timeslice_duration_ms",
> + "%d", &val);
> + break;
> + case I915_ENGINE_CLASS_VIDEO:
> + gem_engine_property_scanf(i915, "vcs0", "timeslice_duration_ms",
> + "%d", &val);
> + break;
> + case I915_ENGINE_CLASS_VIDEO_ENHANCE:
> + gem_engine_property_scanf(i915, "vecs0", "timeslice_duration_ms",
> + "%d", &val);
This assumes all engines of the same class have the same timeout, which
is guaranteed for GuC but not for execlists. IMO a fair assumption to
make because I'm pretty sure a lot of tests would have issues with
non-default timeslice/preempt values, but maybe worth a comment on top
of the function?
Anyway, with the assert removed:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> + break;
> + }
> +
> + return val;
> +}
> +
> +/*
> + * Ensure a parallel submit actually runs on HW in parallel by putting on a
> + * spinner on 1 engine, doing a parallel submit, and parallel submit is blocked
> + * behind spinner.
> + */
> +static void parallel_ordering(int i915, unsigned int flags)
> +{
> + int class;
> +
> + for (class = 0; class < 32; class++) {
> + const intel_ctx_t *ctx = NULL, *spin_ctx = NULL;
> + struct i915_engine_class_instance *siblings;
> + unsigned int count;
> + int i = 0, fence = 0;
> + uint32_t batch[16];
> + struct drm_i915_gem_execbuffer2 execbuf;
> + struct drm_i915_gem_exec_object2 obj[32];
> + igt_spin_t *spin;
> + intel_ctx_cfg_t cfg;
> +
> + siblings = list_engines(i915, 1u << class, &count);
> + if (!siblings)
> + continue;
> +
> + if (count < 2) {
> + free(siblings);
> + continue;
> + }
> +
> + logical_sort_siblings(i915, siblings, count);
> +
> + memset(&cfg, 0, sizeof(cfg));
> + cfg.parallel = true;
> + cfg.num_engines = 1;
> + cfg.width = count;
> + memcpy(cfg.engines, siblings, sizeof(*siblings) * count);
> +
> + ctx = intel_ctx_create(i915, &cfg);
> +
> + batch[i] = MI_ATOMIC | MI_ATOMIC_INLINE_DATA |
> + MI_ATOMIC_ADD;
> + batch[++i] = TARGET_BO_OFFSET;
> + batch[++i] = 0;
> + batch[++i] = 1;
> + batch[++i] = MI_BATCH_BUFFER_END;
> +
> + memset(obj, 0, sizeof(obj));
> + obj[0].offset = TARGET_BO_OFFSET;
> + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> + obj[0].handle = gem_create(i915, 4096);
> +
> + for (i = 1; i < count + 1; ++i) {
> + obj[i].handle = gem_create(i915, 4096);
> + gem_write(i915, obj[i].handle, 0, batch,
> + sizeof(batch));
> + }
> +
> + memset(&execbuf, 0, sizeof(execbuf));
> + execbuf.buffers_ptr = to_user_pointer(obj);
> + execbuf.buffer_count = count + 1;
> + execbuf.flags |= I915_EXEC_HANDLE_LUT;
> + execbuf.flags |= I915_EXEC_NO_RELOC;
> + execbuf.flags |= I915_EXEC_FENCE_OUT;
> + execbuf.buffers_ptr = to_user_pointer(obj);
> + execbuf.rsvd1 = ctx->id;
> +
> + /* Block parallel submission */
> + spin_ctx = ctx_create_engines(i915, siblings, count);
> + spin = __igt_spin_new(i915,
> + .ctx = spin_ctx,
> + .engine = 0,
> + .flags = IGT_SPIN_FENCE_OUT |
> + IGT_SPIN_NO_PREEMPTION);
> +
> + /* Wait for spinners to start */
> + usleep(5 * 10000);
> + igt_assert(fence_busy(spin->out_fence));
> +
> + /* Submit parallel execbuf */
> + gem_execbuf_wr(i915, &execbuf);
> + fence = execbuf.rsvd2 >> 32;
> +
> + /*
> + * Wait long enough for timeslcing to kick in but not
> + * preemption. Spinner + parallel execbuf should be
> + * active. Assuming default timeslice / preemption values, if
> + * these are changed it is possible for the test to fail.
> + */
> + usleep(get_timeslice(i915, siblings[0]) * 2);
> + igt_assert(fence_busy(spin->out_fence));
> + igt_assert(fence_busy(fence));
> + check_bo(i915, obj[0].handle, 0, false);
> +
> + /*
> + * End spinner and wait for spinner + parallel execbuf
> + * to compelte.
> + */
> + igt_spin_end(spin);
> + igt_assert_eq(sync_fence_wait(fence, 1000), 0);
> + igt_assert_eq(sync_fence_status(fence), 1);
> + check_bo(i915, obj[0].handle, count, true);
> + close(fence);
> +
> + /* Clean up */
> + intel_ctx_destroy(i915, ctx);
> + intel_ctx_destroy(i915, spin_ctx);
> + for (i = 0; i < count + 1; ++i)
> + gem_close(i915, obj[i].handle);
> + free(siblings);
> + igt_spin_free(i915, spin);
> + }
> +}
> +
> static bool has_persistence(int i915)
> {
> struct drm_i915_gem_context_param p = {
> @@ -2786,6 +3185,61 @@ static bool has_load_balancer(int i915)
> return err == 0;
> }
>
> +static bool has_logical_mapping(int i915)
> +{
> + struct drm_i915_query_engine_info *engines;
> + unsigned int i;
> +
> + engines = query_engine_info(i915);
> +
> + for (i = 0; i < engines->num_engines; ++i)
> + if (!(engines->engines[i].flags &
> + I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE)) {
> + free(engines);
> + return false;
> + }
> +
> + free(engines);
> + return true;
> +}
> +
> +static bool has_parallel_execbuf(int i915)
> +{
> + intel_ctx_cfg_t cfg = {
> + .parallel = true,
> + .num_engines = 1,
> + };
> + const intel_ctx_t *ctx = NULL;
> + int err;
> +
> + for (int class = 0; class < 32; class++) {
> + struct i915_engine_class_instance *siblings;
> + unsigned int count;
> +
> + siblings = list_engines(i915, 1u << class, &count);
> + if (!siblings)
> + continue;
> +
> + if (count < 2) {
> + free(siblings);
> + continue;
> + }
> +
> + logical_sort_siblings(i915, siblings, count);
> +
> + cfg.width = count;
> + memcpy(cfg.engines, siblings, sizeof(*siblings) * count);
> + free(siblings);
> +
> + err = __intel_ctx_create(i915, &cfg, &ctx);
> + intel_ctx_destroy(i915, ctx);
> +
> + return err == 0;
> + }
> +
> + return false;
> +}
> +
> igt_main
> {
> int i915 = -1;
> @@ -2886,6 +3340,38 @@ igt_main
> igt_stop_hang_detector();
> }
>
> + igt_subtest_group {
> + igt_fixture {
> + igt_require(has_logical_mapping(i915));
> + igt_require(has_parallel_execbuf(i915));
> + }
> +
> + igt_subtest("parallel-ordering")
> + parallel_ordering(i915, 0);
> +
> + igt_subtest("parallel")
> + parallel(i915, 0);
> +
> + igt_subtest("parallel-bb-first")
> + parallel(i915, PARALLEL_BB_FIRST);
> +
> + igt_subtest("parallel-out-fence")
> + parallel(i915, PARALLEL_OUT_FENCE);
> +
> + igt_subtest("parallel-keep-in-fence")
> + parallel(i915, PARALLEL_OUT_FENCE | PARALLEL_IN_FENCE);
> +
> + igt_subtest("parallel-keep-submit-fence")
> + parallel(i915, PARALLEL_OUT_FENCE |
> + PARALLEL_SUBMIT_FENCE);
> +
> + igt_subtest("parallel-contexts")
> + parallel(i915, PARALLEL_CONTEXTS);
> +
> + igt_subtest("parallel-balancer")
> + parallel_balancer(i915, 0);
> + }
> +
> igt_subtest_group {
> igt_hang_t hang;
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH 0/2] Test parallel execbuf
@ 2021-11-12 0:24 Matthew Brost
0 siblings, 0 replies; 9+ messages in thread
From: Matthew Brost @ 2021-11-12 0:24 UTC (permalink / raw)
To: igt-dev
v2:
(Daniele)
- Sync i915_drm.h
- Address comments in test
v3:
(Daniele)
- Read timeslice from sysfs
v4:
(Daniele)
- Add comment in timeslice sysfs read function
v5:
- Rebase
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Matthew Brost (2):
i915_drm.h sync with drm-next
i915/gem_exec_balancer: Test parallel execbuf
include/drm-uapi/i915_drm.h | 242 +++++++++++++++-
lib/i915/i915_drm_local.h | 23 --
lib/intel_ctx.c | 30 +-
lib/intel_ctx.h | 2 +
lib/intel_reg.h | 5 +
tests/i915/gem_exec_balancer.c | 490 +++++++++++++++++++++++++++++++++
6 files changed, 767 insertions(+), 25 deletions(-)
--
2.33.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH 0/2] Test parallel execbuf
@ 2021-11-11 21:31 Matthew Brost
0 siblings, 0 replies; 9+ messages in thread
From: Matthew Brost @ 2021-11-11 21:31 UTC (permalink / raw)
To: igt-dev
v2:
(Daniele)
- Sync i915_drm.h
- Address comments in test
v3:
(Daniele)
- Read timeslice from sysfs
v4:
(Daniele)
- Add comment in timeslice sysfs read function
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Matthew Brost (2):
i915_drm.h sync with drm-next
i915/gem_exec_balancer: Test parallel execbuf
include/drm-uapi/i915_drm.h | 242 +++++++++++++++-
lib/i915/i915_drm_local.h | 13 -
lib/intel_ctx.c | 30 +-
lib/intel_ctx.h | 2 +
lib/intel_reg.h | 5 +
tests/i915/gem_exec_balancer.c | 490 +++++++++++++++++++++++++++++++++
6 files changed, 767 insertions(+), 15 deletions(-)
--
2.33.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH 0/2] Test parallel execbuf
@ 2021-11-08 19:04 Matthew Brost
0 siblings, 0 replies; 9+ messages in thread
From: Matthew Brost @ 2021-11-08 19:04 UTC (permalink / raw)
To: igt-dev
v2:
(Daniele)
- Sync i915_drm.h
- Address comments in test
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Matthew Brost (2):
i915_drm.h sync with drm-next
i915/gem_exec_balancer: Test parallel execbuf
include/drm-uapi/i915_drm.h | 242 ++++++++++++++++-
lib/i915/i915_drm_local.h | 13 -
lib/intel_ctx.c | 30 ++-
lib/intel_ctx.h | 2 +
lib/intel_reg.h | 5 +
tests/i915/gem_exec_balancer.c | 459 +++++++++++++++++++++++++++++++++
6 files changed, 736 insertions(+), 15 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-11-12 0:30 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-09 22:59 [igt-dev] [PATCH 0/2] Test parallel execbuf Matthew Brost
2021-11-09 22:59 ` [igt-dev] [PATCH 1/2] i915_drm.h sync with drm-next Matthew Brost
2021-11-09 22:59 ` [igt-dev] [PATCH 2/2] i915/gem_exec_balancer: Test parallel execbuf Matthew Brost
2021-11-11 18:56 ` Daniele Ceraolo Spurio
2021-11-10 1:45 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2021-11-10 4:06 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
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2021-11-12 0:24 [igt-dev] [PATCH 0/2] " Matthew Brost
2021-11-11 21:31 Matthew Brost
2021-11-08 19:04 Matthew Brost
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