* [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema
@ 2021-11-12 12:05 Thierry Reding
2021-11-12 12:05 ` [PATCH 01/15] dt-bindings: misc: Convert Tegra MISC " Thierry Reding
` (14 more replies)
0 siblings, 15 replies; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Hi,
this set of patches converts some Tegra-specific DT bindings to
json-schema and, where appropriate, adds Tegra234 compatible strings.
The goal is to prepare existing schemas to allow validation of the
existing Tegra234 device tree files.
I've got a follow-up series that adds more Tegra234 support and will
extend/convert bindings along the way to keep things validatable.
Rob, since all of these are Tegra-specific and given that I have some
follow-up work based on these, I think it'd be best if I picked these
up into the Tegra tree once you're happy with them.
Thierry
Thierry Reding (15):
dt-bindings: misc: Convert Tegra MISC to json-schema
dt-bindings: mmc: tegra: Convert to json-schema
dt-bindings: mailbox: tegra: Convert to json-schema
dt-bindings: mailbox: tegra: Document Tegra234 HSP
dt-bindings: rtc: tegra: Convert to json-schema
dt-bindings: rtc: tegra: Document Tegra234 RTC
dt-bindings: fuse: tegra: Convert to json-schema
dt-bindings: fuse: tegra: Document Tegra234 FUSE
dt-bindings: mmc: tegra: Document Tegra234 SDHCI
dt-bindings: serial: 8250: Document Tegra234 UART
dt-bindings: tegra: pmc: Convert to json-schema
dt-bindings: firmware: tegra: Convert to json-schema
dt-bindings: i2c: tegra-bpmp: Convert to json-schema
dt-bindings: serial: tegra-tcu: Convert to json-schema
dt-bindings: serial: Document Tegra234 TCU
.../arm/tegra/nvidia,tegra186-pmc.txt | 133 --------
.../arm/tegra/nvidia,tegra186-pmc.yaml | 199 ++++++++++++
.../firmware/nvidia,tegra186-bpmp.txt | 107 -------
.../firmware/nvidia,tegra186-bpmp.yaml | 161 ++++++++++
.../bindings/fuse/nvidia,tegra20-fuse.txt | 42 ---
.../bindings/fuse/nvidia,tegra20-fuse.yaml | 80 +++++
.../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 ---
.../i2c/nvidia,tegra186-bpmp-i2c.yaml | 40 +++
.../bindings/mailbox/nvidia,tegra186-hsp.txt | 72 -----
.../bindings/mailbox/nvidia,tegra186-hsp.yaml | 112 +++++++
.../bindings/misc/nvidia,tegra186-misc.txt | 14 -
.../bindings/misc/nvidia,tegra186-misc.yaml | 43 +++
.../bindings/misc/nvidia,tegra20-apbmisc.txt | 17 -
.../bindings/misc/nvidia,tegra20-apbmisc.yaml | 51 +++
.../bindings/mmc/nvidia,tegra20-sdhci.txt | 143 ---------
.../bindings/mmc/nvidia,tegra20-sdhci.yaml | 300 ++++++++++++++++++
.../bindings/rtc/nvidia,tegra20-rtc.txt | 24 --
.../bindings/rtc/nvidia,tegra20-rtc.yaml | 55 ++++
.../devicetree/bindings/serial/8250.yaml | 3 +-
.../bindings/serial/nvidia,tegra194-tcu.txt | 35 --
.../bindings/serial/nvidia,tegra194-tcu.yaml | 61 ++++
21 files changed, 1104 insertions(+), 630 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
delete mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
delete mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
delete mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
delete mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt
create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml
delete mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
create mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
delete mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
create mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
delete mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt
create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
--
2.33.1
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 01/15] dt-bindings: misc: Convert Tegra MISC to json-schema
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 12:05 ` [PATCH 02/15] dt-bindings: mmc: tegra: Convert " Thierry Reding
` (13 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the device tree bindings for the MISC register block found on
NVIDIA Tegra SoCs from plain text to json-schema format.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../bindings/misc/nvidia,tegra186-misc.txt | 14 -----
.../bindings/misc/nvidia,tegra186-misc.yaml | 43 ++++++++++++++++
.../bindings/misc/nvidia,tegra20-apbmisc.txt | 17 -------
.../bindings/misc/nvidia,tegra20-apbmisc.yaml | 51 +++++++++++++++++++
4 files changed, 94 insertions(+), 31 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
deleted file mode 100644
index 43d777ed8316..000000000000
--- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-NVIDIA Tegra186 (and later) MISC register block
-
-The MISC register block found on Tegra186 and later SoCs contains registers
-that can be used to identify a given chip and various strapping options.
-
-Required properties:
-- compatible: Must be:
- - Tegra186: "nvidia,tegra186-misc"
- - Tegra194: "nvidia,tegra194-misc"
- - Tegra234: "nvidia,tegra234-misc"
-- reg: Should contain 2 entries: The first entry gives the physical address
- and length of the register region which contains revision and debug
- features. The second entry specifies the physical address and length
- of the register region indicating the strapping options.
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
new file mode 100644
index 000000000000..cacb845868f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra186 (and later) MISC register block
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: The MISC register block found on Tegra186 and later SoCs contains
+ registers that can be used to identify a given chip and various strapping
+ options.
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra186-misc
+ - nvidia,tegra194-misc
+ - nvidia,tegra234-misc
+
+ reg:
+ items:
+ - description: physical address and length of the registers which
+ contain revision and debug features
+ - description: physical address and length of the registers which
+ indicate strapping options
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ misc@100000 {
+ compatible = "nvidia,tegra186-misc";
+ reg = <0x00100000 0xf000>,
+ <0x0010f000 0x1000>;
+ };
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
deleted file mode 100644
index 83f6a251ba3e..000000000000
--- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-NVIDIA Tegra APBMISC block
-
-Required properties:
-- compatible: Must be:
- - Tegra20: "nvidia,tegra20-apbmisc"
- - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"
- - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"
- - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
- - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
- - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"
-- reg: Should contain 2 entries: the first entry gives the physical address
- and length of the registers which contain revision and debug features.
- The second entry gives the physical address and length of the
- registers indicating the strapping options.
-
-Optional properties:
-- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml
new file mode 100644
index 000000000000..6f504fa74007
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra APBMISC block
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - nvidia,tegra210-apbmisc
+ - nvidia,tegra124-apbmisc
+ - nvidia,tegra114-apbmisc
+ - nvidia,tegra30-apbmisc
+ - const: nvidia,tegra20-apbmisc
+
+ - items:
+ - const: nvidia,tegra20-apbmisc
+
+ reg:
+ items:
+ - description: physical address and length of the registers which
+ contain revision and debug features
+ - description: physical address and length of the registers which
+ indicate strapping options
+
+ nvidia,long-ram-code:
+ description: If present, the RAM code is long (4 bit). If not, short
+ (2 bit).
+ type: boolean
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ apbmisc@70000800 {
+ compatible = "nvidia,tegra20-apbmisc";
+ reg = <0x70000800 0x64>, /* Chip revision */
+ <0x70000008 0x04>; /* Strapping options */
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 02/15] dt-bindings: mmc: tegra: Convert to json-schema
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
2021-11-12 12:05 ` [PATCH 01/15] dt-bindings: misc: Convert Tegra MISC " Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 13:48 ` Rob Herring
2021-11-12 12:05 ` [PATCH 03/15] dt-bindings: mailbox: " Thierry Reding
` (12 subsequent siblings)
14 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra SDHCI bindings from the free-form text format
to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- drop redundant $ref properties, add missing maxItems
.../bindings/mmc/nvidia,tegra20-sdhci.txt | 143 ---------
.../bindings/mmc/nvidia,tegra20-sdhci.yaml | 294 ++++++++++++++++++
2 files changed, 294 insertions(+), 143 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
create mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
deleted file mode 100644
index 96c0b1440c9c..000000000000
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ /dev/null
@@ -1,143 +0,0 @@
-* NVIDIA Tegra Secure Digital Host Controller
-
-This controller on Tegra family SoCs provides an interface for MMC, SD,
-and SDIO types of memory cards.
-
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the sdhci-tegra driver.
-
-Required properties:
-- compatible : should be one of:
- - "nvidia,tegra20-sdhci": for Tegra20
- - "nvidia,tegra30-sdhci": for Tegra30
- - "nvidia,tegra114-sdhci": for Tegra114
- - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
- - "nvidia,tegra210-sdhci": for Tegra210
- - "nvidia,tegra186-sdhci": for Tegra186
- - "nvidia,tegra194-sdhci": for Tegra194
-- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
- One for the module clock and one for the timeout clock.
- For all other Tegra devices, must contain a single entry for
- the module clock. See ../clocks/clock-bindings.txt for details.
-- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the
- strings 'sdhci' and 'tmclk' to represent the module and
- the timeout clocks, respectively.
- For all other Tegra devices must contain the string 'sdhci'
- to represent the module clock.
-- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names : Must include the following entries:
- - sdhci
-
-Optional properties:
-- power-gpios : Specify GPIOs for power control
-
-Example:
-
-sdhci@c8000200 {
- compatible = "nvidia,tegra20-sdhci";
- reg = <0xc8000200 0x200>;
- interrupts = <47>;
- clocks = <&tegra_car 14>;
- resets = <&tegra_car 14>;
- reset-names = "sdhci";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 155 0>; /* gpio PT3 */
- bus-width = <8>;
-};
-
-Optional properties for Tegra210, Tegra186 and Tegra194:
-- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
- configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
- for controllers supporting multiple voltage levels. The order of names
- should correspond to the pin configuration states in pinctrl-0 and
- pinctrl-1.
-- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
- Tegra210 where pad config registers are in the pinmux register domain
- for pull-up-strength and pull-down-strength values configuration when
- using pads at 3V3 and 1V8 levels.
-- nvidia,only-1-8-v : The presence of this property indicates that the
- controller operates at a 1.8 V fixed I/O voltage.
-- nvidia,pad-autocal-pull-up-offset-3v3,
- nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
- calibration offsets for 3.3 V signaling modes.
-- nvidia,pad-autocal-pull-up-offset-1v8,
- nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
- calibration offsets for 1.8 V signaling modes.
-- nvidia,pad-autocal-pull-up-offset-3v3-timeout,
- nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
- strength used as a fallback in case the automatic calibration times
- out on a 3.3 V signaling mode.
-- nvidia,pad-autocal-pull-up-offset-1v8-timeout,
- nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
- strength used as a fallback in case the automatic calibration times
- out on a 1.8 V signaling mode.
-- nvidia,pad-autocal-pull-up-offset-sdr104,
- nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength
- calibration offsets for SDR104 mode.
-- nvidia,pad-autocal-pull-up-offset-hs400,
- nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
- calibration offsets for HS400 mode.
-- nvidia,default-tap : Specify the default inbound sampling clock
- trimmer value for non-tunable modes.
-- nvidia,default-trim : Specify the default outbound clock trimmer
- value.
-- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
-
- Notes on the pad calibration pull up and pulldown offset values:
- - The property values are drive codes which are programmed into the
- PD_OFFSET and PU_OFFSET sections of the
- SDHCI_TEGRA_AUTO_CAL_CONFIG register.
- - A higher value corresponds to higher drive strength. Please refer
- to the reference manual of the SoC for correct values.
- - The SDR104 and HS400 timing specific values are used in
- corresponding modes if specified.
-
- Notes on tap and trim values:
- - The values are used for compensating trace length differences
- by adjusting the sampling point.
- - The values are programmed to the Vendor Clock Control Register.
- Please refer to the reference manual of the SoC for correct
- values.
- - The DQS trim values are only used on controllers which support
- HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
- HS400.
-
-Example:
-sdhci@700b0000 {
- compatible = "nvidia,tegra124-sdhci";
- reg = <0x0 0x700b0000 0x0 0x200>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
- clock-names = "sdhci";
- resets = <&tegra_car 14>;
- reset-names = "sdhci";
- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
- pinctrl-0 = <&sdmmc1_3v3>;
- pinctrl-1 = <&sdmmc1_1v8>;
- nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
- nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
- nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
- nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
- status = "disabled";
-};
-
-sdhci@700b0000 {
- compatible = "nvidia,tegra210-sdhci";
- reg = <0x0 0x700b0000 0x0 0x200>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
- <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
- clock-names = "sdhci", "tmclk";
- resets = <&tegra_car 14>;
- reset-names = "sdhci";
- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
- pinctrl-0 = <&sdmmc1_3v3>;
- pinctrl-1 = <&sdmmc1_1v8>;
- nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
- nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
- nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
- nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
- status = "disabled";
-};
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
new file mode 100644
index 000000000000..1c3b9bbea6b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
@@ -0,0 +1,294 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Secure Digital Host Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ This controller on Tegra family SoCs provides an interface for MMC, SD, and
+ SDIO types of memory cards.
+
+ This file documents differences between the core properties described by
+ mmc-controller.yaml and the properties for the Tegra SDHCI controller.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nvidia,tegra20-sdhci
+ - nvidia,tegra30-sdhci
+ - nvidia,tegra114-sdhci
+ - nvidia,tegra124-sdhci
+ - nvidia,tegra210-sdhci
+ - nvidia,tegra186-sdhci
+ - nvidia,tegra194-sdhci
+
+ - items:
+ - const: nvidia,tegra132-sdhci
+ - const: nvidia,tegra124-sdhci
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ assigned-clocks: true
+ assigned-clock-parents: true
+ assigned-clock-rates: true
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+
+ resets:
+ items:
+ - description: module reset
+
+ reset-names:
+ items:
+ - const: sdhci
+
+ power-gpios:
+ description: specify GPIOs for power control
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ nvidia,default-tap:
+ description: Specify the default inbound sampling clock trimmer value for
+ non-tunable modes.
+
+ The values are used for compensating trace length differences by
+ adjusting the sampling point. The values are programmed to the Vendor
+ Clock Control Register. Please refer to the reference manual of the SoC
+ for correct values.
+
+ The DQS trim values are only used on controllers which support HS400
+ timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,default-trim:
+ description: Specify the default outbound clock trimmer value.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,dqs-trim:
+ description: Specify DQS trim value for HS400 timing.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-1v8:
+ description: Specify drive strength calibration offsets for 1.8 V
+ signaling modes.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-1v8-timeout:
+ description: Specify drive strength used as a fallback in case the
+ automatic calibration times out on a 1.8 V signaling mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-3v3:
+ description: Specify drive strength calibration offsets for 3.3 V
+ signaling modes.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-3v3-timeout:
+ description: Specify drive strength used as a fallback in case the
+ automatic calibration times out on a 3.3 V signaling mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-sdr104:
+ description: Specify drive strength calibration offsets for SDR104 mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-hs400:
+ description: Specify drive strength calibration offsets for HS400 mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-1v8:
+ description: Specify drive strength calibration offsets for 1.8 V
+ signaling modes.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-1v8-timeout:
+ description: Specify drive strength used as a fallback in case the
+ automatic calibration times out on a 1.8 V signaling mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-3v3:
+ description: Specify drive strength calibration offsets for 3.3 V
+ signaling modes.
+
+ The property values are drive codes which are programmed into the
+ PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG
+ register. A higher value corresponds to higher drive strength. Please
+ refer to the reference manual of the SoC for correct values. The SDR104
+ and HS400 timing specific values are used in corresponding modes if
+ specified.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-3v3-timeout:
+ description: Specify drive strength used as a fallback in case the
+ automatic calibration times out on a 3.3 V signaling mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-sdr104:
+ description: Specify drive strength calibration offsets for SDR104 mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-hs400:
+ description: Specify drive strength calibration offsets for HS400 mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,only-1-8v:
+ description: The presence of this property indicates that the controller
+ operates at a 1.8 V fixed I/O voltage.
+ $ref: "/schemas/types.yaml#/definitions/flag"
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra20-sdhci
+ - nvidia,tegra30-sdhci
+ - nvidia,tegra114-sdhci
+ - nvidia,tegra124-sdhci
+ clocks:
+ items:
+ - description: module clock
+ minItems: 1
+ maxItems: 1
+ else:
+ properties:
+ clocks:
+ items:
+ - description: module clock
+ - description: timeout clock
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: sdhci
+ - const: tmclk
+ minItems: 2
+ maxItems: 2
+ required:
+ - clock-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra210-sdhci
+ then:
+ properties:
+ pinctrl-names:
+ oneOf:
+ - items:
+ - const: sdmmc-3v3
+ description: pad configuration for 3.3 V
+ - const: sdmmc-1v8
+ description: pad configuration for 1.8 V
+ - const: sdmmc-3v3-drv
+ description: pull-up/down configuration for 3.3 V
+ - const: sdmmc-1v8-drv
+ description: pull-up/down configuration for 1.8 V
+ - items:
+ - const: sdmmc-3v3-drv
+ description: pull-up/down configuration for 3.3 V
+ - const: sdmmc-1v8-drv
+ description: pull-up/down configuration for 1.8 V
+ - items:
+ - const: sdmmc-1v8-drv
+ description: pull-up/down configuration for 1.8 V
+ required:
+ - clock-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra186-sdhci
+ - nvidia,tegra194-sdhci
+ then:
+ properties:
+ pinctrl-names:
+ items:
+ - const: sdmmc-3v3
+ description: pad configuration for 3.3 V
+ - const: sdmmc-1v8
+ description: pad configuration for 1.8 V
+ required:
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mmc@c8000200 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000200 0x200>;
+ interrupts = <47>;
+ clocks = <&tegra_car 14>;
+ resets = <&tegra_car 14>;
+ reset-names = "sdhci";
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+ power-gpios = <&gpio 155 0>; /* gpio PT3 */
+ bus-width = <8>;
+ };
+
+ - |
+ #include <dt-bindings/clock/tegra210-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mmc@700b0000 {
+ compatible = "nvidia,tegra210-sdhci";
+ reg = <0x700b0000 0x200>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
+ <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+ clock-names = "sdhci", "tmclk";
+ resets = <&tegra_car 14>;
+ reset-names = "sdhci";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
+ "sdmmc-3v3-drv", "sdmmc-1v8-drv";
+ pinctrl-0 = <&sdmmc1_3v3>;
+ pinctrl-1 = <&sdmmc1_1v8>;
+ pinctrl-2 = <&sdmmc1_3v3_drv>;
+ pinctrl-3 = <&sdmmc1_1v8_drv>;
+ nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
+ nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
+ nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
+ nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
+ nvidia,default-tap = <0x2>;
+ nvidia,default-trim = <0x4>;
+ assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+ <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
+ <&tegra_car TEGRA210_CLK_PLL_C4>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+ assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 03/15] dt-bindings: mailbox: tegra: Convert to json-schema
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
2021-11-12 12:05 ` [PATCH 01/15] dt-bindings: misc: Convert Tegra MISC " Thierry Reding
2021-11-12 12:05 ` [PATCH 02/15] dt-bindings: mmc: tegra: Convert " Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 13:48 ` Rob Herring
2021-11-12 12:05 ` [PATCH 04/15] dt-bindings: mailbox: tegra: Document Tegra234 HSP Thierry Reding
` (11 subsequent siblings)
14 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra HSP bindings from the free-form text format to
json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../bindings/mailbox/nvidia,tegra186-hsp.txt | 72 ------------
.../bindings/mailbox/nvidia,tegra186-hsp.yaml | 109 ++++++++++++++++++
2 files changed, 109 insertions(+), 72 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt
create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt
deleted file mode 100644
index ff3eafc5a882..000000000000
--- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-NVIDIA Tegra Hardware Synchronization Primitives (HSP)
-
-The HSP modules are used for the processors to share resources and communicate
-together. It provides a set of hardware synchronization primitives for
-interprocessor communication. So the interprocessor communication (IPC)
-protocols can use hardware synchronization primitives, when operating between
-two processors not in an SMP relationship.
-
-The features that HSP supported are shared mailboxes, shared semaphores,
-arbitrated semaphores and doorbells.
-
-Required properties:
-- name : Should be hsp
-- compatible
- Array of strings.
- one of:
- - "nvidia,tegra186-hsp"
- - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"
-- reg : Offset and length of the register set for the device.
-- interrupt-names
- Array of strings.
- Contains a list of names for the interrupts described by the interrupt
- property. May contain the following entries, in any order:
- - "doorbell"
- - "sharedN", where 'N' is a number from zero up to the number of
- external interrupts supported by the HSP instance minus one.
- Users of this binding MUST look up entries in the interrupt property
- by name, using this interrupt-names property to do so.
-- interrupts
- Array of interrupt specifiers.
- Must contain one entry per entry in the interrupt-names property,
- in a matching order.
-- #mbox-cells : Should be 2.
-
-The mbox specifier of the "mboxes" property in the client node should contain
-two cells. The first cell determines the HSP type and the second cell is used
-to identify the mailbox that the client is going to use.
-
-For doorbells, the second cell specifies the index of the doorbell to use.
-
-For shared mailboxes, the second cell is composed of two fields:
-- bits 31..24:
- A bit mask of flags that further specify how the shared mailbox will be
- used. Valid flags are:
- - bit 31:
- Defines the direction of the mailbox. If set, the mailbox will be used
- as a producer (i.e. used to send data). If cleared, the mailbox is the
- consumer of data sent by a producer.
-
-- bits 23.. 0:
- The index of the shared mailbox to use. The number of available mailboxes
- may vary by instance of the HSP block and SoC generation.
-
-The following file contains definitions that can be used to construct mailbox
-specifiers:
-
- <dt-bindings/mailbox/tegra186-hsp.h>
-
-Example:
-
-hsp_top0: hsp@3c00000 {
- compatible = "nvidia,tegra186-hsp";
- reg = <0x0 0x03c00000 0x0 0xa0000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "doorbell";
- #mbox-cells = <2>;
-};
-
-client {
- ...
- mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>;
-};
diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
new file mode 100644
index 000000000000..f5319f4e4393
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Hardware Synchronization Primitives (HSP)
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ The HSP modules are used for the processors to share resources and
+ communicate together. It provides a set of hardware synchronization
+ primitives for interprocessor communication. So the interprocessor
+ communication (IPC) protocols can use hardware synchronization
+ primitives, when operating between two processors not in an SMP
+ relationship.
+
+ The features that HSP supported are shared mailboxes, shared
+ semaphores, arbitrated semaphores and doorbells.
+
+ The mbox specifier of the "mboxes" property in the client node should
+ contain two cells. The first cell determines the HSP type and the
+ second cell is used to identify the mailbox that the client is going
+ to use.
+
+ For doorbells, the second cell specifies the index of the doorbell to
+ use.
+
+ For shared mailboxes, the second cell is composed of two fields:
+ - bits 31..24:
+ A bit mask of flags that further specify how the shared mailbox
+ will be used. Valid flags are:
+ - bit 31:
+ Defines the direction of the mailbox. If set, the mailbox
+ will be used as a producer (i.e. used to send data). If
+ cleared, the mailbox is the consumer of data sent by a
+ producer.
+
+ - bits 23..0:
+ The index of the shared mailbox to use. The number of available
+ mailboxes may vary by instance of the HSP block and SoC
+ generation.
+
+ The following file contains definitions that can be used to
+ construct mailbox specifiers:
+
+ <dt-bindings/mailbox/tegra186-hsp.h>
+
+properties:
+ $nodename:
+ pattern: "^hsp@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - const: nvidia,tegra186-hsp
+ - const: nvidia,tegra194-hsp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 9
+
+ interrupt-names:
+ oneOf:
+ # shared interrupts are optional
+ - items:
+ - const: doorbell
+
+ - items:
+ - const: doorbell
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+
+ - items:
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+
+ "#mbox-cells":
+ const: 2
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/mailbox/tegra186-hsp.h>
+
+ hsp_top0: hsp@3c00000 {
+ compatible = "nvidia,tegra186-hsp";
+ reg = <0x03c00000 0xa0000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "doorbell";
+ #mbox-cells = <2>;
+ };
+
+ client {
+ mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>;
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 04/15] dt-bindings: mailbox: tegra: Document Tegra234 HSP
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (2 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 03/15] dt-bindings: mailbox: " Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 12:05 ` [PATCH 05/15] dt-bindings: rtc: tegra: Convert to json-schema Thierry Reding
` (10 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the HSP block found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
index f5319f4e4393..a270dd6ddac5 100644
--- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
+++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
@@ -57,6 +57,9 @@ properties:
oneOf:
- const: nvidia,tegra186-hsp
- const: nvidia,tegra194-hsp
+ - items:
+ - const: nvidia,tegra234-hsp
+ - const: nvidia,tegra194-hsp
reg:
maxItems: 1
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 05/15] dt-bindings: rtc: tegra: Convert to json-schema
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (3 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 04/15] dt-bindings: mailbox: tegra: Document Tegra234 HSP Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 13:48 ` Rob Herring
2021-11-12 12:05 ` [PATCH 06/15] dt-bindings: rtc: tegra: Document Tegra234 RTC Thierry Reding
` (9 subsequent siblings)
14 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra RTC bindings from the free-form text format to
json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../bindings/rtc/nvidia,tegra20-rtc.txt | 24 ---------
.../bindings/rtc/nvidia,tegra20-rtc.yaml | 54 +++++++++++++++++++
2 files changed, 54 insertions(+), 24 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
create mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
deleted file mode 100644
index b7d98ed3e098..000000000000
--- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-NVIDIA Tegra20 real-time clock
-
-The Tegra RTC maintains seconds and milliseconds counters, and five alarm
-registers. The alarms and other interrupts may wake the system from low-power
-state.
-
-Required properties:
-
-- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise,
- must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip>
- can be tegra30, tegra114, tegra124, or tegra132.
-- reg : Specifies base physical address and size of the registers.
-- interrupts : A single interrupt specifier.
-- clocks : Must contain one entry, for the module clock.
- See ../clocks/clock-bindings.txt for details.
-
-Example:
-
-timer {
- compatible = "nvidia,tegra20-rtc";
- reg = <0x7000e000 0x100>;
- interrupts = <0 2 0x04>;
- clocks = <&tegra_car 4>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
new file mode 100644
index 000000000000..a96154882161
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra real-time clock
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ The Tegra RTC maintains seconds and milliseconds counters, and five
+ alarm registers. The alarms and other interrupts may wake the system
+ from low-power state.
+
+properties:
+ compatible:
+ oneOf:
+ - const: nvidia,tegra20-rtc
+ - items:
+ - enum:
+ - nvidia,tegra30-rtc
+ - nvidia,tegra114-rtc
+ - nvidia,tegra124-rtc
+ - nvidia,tegra210-rtc
+ - nvidia,tegra186-rtc
+ - nvidia,tegra194-rtc
+ - const: nvidia,tegra20-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ timer@7000e000 {
+ compatible = "nvidia,tegra20-rtc";
+ reg = <0x7000e000 0x100>;
+ interrupts = <0 2 0x04>;
+ clocks = <&tegra_car 4>;
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 06/15] dt-bindings: rtc: tegra: Document Tegra234 RTC
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (4 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 05/15] dt-bindings: rtc: tegra: Convert to json-schema Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 12:05 ` [PATCH 07/15] dt-bindings: fuse: tegra: Convert to json-schema Thierry Reding
` (8 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the RTC block found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
index a96154882161..f2d33ab23966 100644
--- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
@@ -27,6 +27,7 @@ properties:
- nvidia,tegra210-rtc
- nvidia,tegra186-rtc
- nvidia,tegra194-rtc
+ - nvidia,tegra234-rtc
- const: nvidia,tegra20-rtc
reg:
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 07/15] dt-bindings: fuse: tegra: Convert to json-schema
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (5 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 06/15] dt-bindings: rtc: tegra: Document Tegra234 RTC Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 12:05 ` [PATCH 08/15] dt-bindings: fuse: tegra: Document Tegra234 FUSE Thierry Reding
` (7 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra FUSE bindings from the free-form text format to
json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../bindings/fuse/nvidia,tegra20-fuse.txt | 42 ----------
.../bindings/fuse/nvidia,tegra20-fuse.yaml | 79 +++++++++++++++++++
2 files changed, 79 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
deleted file mode 100644
index b109911669e4..000000000000
--- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
-
-Required properties:
-- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
- must contain "nvidia,tegra30-efuse". For Tegra114, must contain
- "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
- For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
- For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
- "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
- For Tegra234 must contain "nvidia,tegra234-efuse".
- Details:
- nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
- due to a hardware bug. Tegra20 also lacks certain information which is
- available in later generations such as fab code, lot code, wafer id,..
- nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
- The differences between these SoCs are the size of the efuse array,
- the location of the spare (OEM programmable) bits and the location of
- the speedo data.
-- reg: Should contain 1 entry: the entry gives the physical address and length
- of the fuse registers.
-- clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - fuse
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - fuse
-
-Example:
-
- fuse@7000f800 {
- compatible = "nvidia,tegra20-efuse";
- reg = <0x7000f800 0x400>,
- <0x70000000 0x400>;
- clocks = <&tegra_car TEGRA20_CLK_FUSE>;
- clock-names = "fuse";
- resets = <&tegra_car 39>;
- reset-names = "fuse";
- };
-
-
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
new file mode 100644
index 000000000000..9389be60c198
--- /dev/null
+++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra FUSE block
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nvidia,tegra20-efuse
+ - nvidia,tegra30-efuse
+ - nvidia,tegra114-efuse
+ - nvidia,tegra124-efuse
+ - nvidia,tegra210-efuse
+ - nvidia,tegra186-efuse
+ - nvidia,tegra194-efuse
+
+ - items:
+ - const: nvidia,tegra132-efuse
+ - const: nvidia,tegra124-efuse
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: fuse
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: fuse
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra20-efuse
+ - nvidia,tegra30-efuse
+ - nvidia,tegra114-efuse
+ - nvidia,tegra124-efuse
+ - nvidia,tegra132-efuse
+ - nvidia,tegra210-efuse
+then:
+ required:
+ - resets
+ - reset-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra20-car.h>
+
+ fuse@7000f800 {
+ compatible = "nvidia,tegra20-efuse";
+ reg = <0x7000f800 0x400>;
+ clocks = <&tegra_car TEGRA20_CLK_FUSE>;
+ clock-names = "fuse";
+ resets = <&tegra_car 39>;
+ reset-names = "fuse";
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 08/15] dt-bindings: fuse: tegra: Document Tegra234 FUSE
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (6 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 07/15] dt-bindings: fuse: tegra: Convert to json-schema Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 12:05 ` [PATCH 09/15] dt-bindings: mmc: tegra: Document Tegra234 SDHCI Thierry Reding
` (6 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the FUSE block found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
index 9389be60c198..dbf3b554bf63 100644
--- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
+++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
@@ -21,6 +21,7 @@ properties:
- nvidia,tegra210-efuse
- nvidia,tegra186-efuse
- nvidia,tegra194-efuse
+ - nvidia,tegra234-efuse
- items:
- const: nvidia,tegra132-efuse
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 09/15] dt-bindings: mmc: tegra: Document Tegra234 SDHCI
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (7 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 08/15] dt-bindings: fuse: tegra: Document Tegra234 FUSE Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 12:05 ` [PATCH 10/15] dt-bindings: serial: 8250: Document Tegra234 UART Thierry Reding
` (5 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the SDHCI block found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
index 1c3b9bbea6b4..a361896323d0 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
@@ -33,6 +33,12 @@ properties:
- const: nvidia,tegra132-sdhci
- const: nvidia,tegra124-sdhci
+ - items:
+ - enum:
+ - nvidia,tegra194-sdhci
+ - nvidia,tegra234-sdhci
+ - const: nvidia,tegra186-sdhci
+
reg:
maxItems: 1
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 10/15] dt-bindings: serial: 8250: Document Tegra234 UART
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (8 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 09/15] dt-bindings: mmc: tegra: Document Tegra234 SDHCI Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 15:01 ` Rob Herring
2021-11-12 12:05 ` [PATCH 11/15] dt-bindings: tegra: pmc: Convert to json-schema Thierry Reding
` (4 subsequent siblings)
14 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the UART found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Documentation/devicetree/bindings/serial/8250.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index fa767440f281..3bab2f27b970 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -113,9 +113,10 @@ properties:
- nvidia,tegra30-uart
- nvidia,tegra114-uart
- nvidia,tegra124-uart
+ - nvidia,tegra210-uart
- nvidia,tegra186-uart
- nvidia,tegra194-uart
- - nvidia,tegra210-uart
+ - nvidia,tegra234-uart
- const: nvidia,tegra20-uart
reg:
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 11/15] dt-bindings: tegra: pmc: Convert to json-schema
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (9 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 10/15] dt-bindings: serial: 8250: Document Tegra234 UART Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 15:01 ` Rob Herring
2021-11-12 12:05 ` [PATCH 12/15] dt-bindings: firmware: tegra: " Thierry Reding
` (3 subsequent siblings)
14 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra186 (and later) PMC bindings from the free-form
text format to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../arm/tegra/nvidia,tegra186-pmc.txt | 133 ------------
.../arm/tegra/nvidia,tegra186-pmc.yaml | 199 ++++++++++++++++++
2 files changed, 199 insertions(+), 133 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
deleted file mode 100644
index 576462fae27f..000000000000
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
+++ /dev/null
@@ -1,133 +0,0 @@
-NVIDIA Tegra Power Management Controller (PMC)
-
-Required properties:
-- compatible: Should contain one of the following:
- - "nvidia,tegra186-pmc": for Tegra186
- - "nvidia,tegra194-pmc": for Tegra194
- - "nvidia,tegra234-pmc": for Tegra234
-- reg: Must contain an (offset, length) pair of the register set for each
- entry in reg-names.
-- reg-names: Must include the following entries:
- - "pmc"
- - "wake"
- - "aotag"
- - "scratch"
- - "misc" (Only for Tegra194 and later)
-
-Optional properties:
-- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
-- interrupt-controller: Identifies the node as an interrupt controller.
-- #interrupt-cells: Specifies the number of cells needed to encode an
- interrupt source. The value must be 2.
-
-Example:
-
-SoC DTSI:
-
- pmc@c3600000 {
- compatible = "nvidia,tegra186-pmc";
- reg = <0 0x0c360000 0 0x10000>,
- <0 0x0c370000 0 0x10000>,
- <0 0x0c380000 0 0x10000>,
- <0 0x0c390000 0 0x10000>;
- reg-names = "pmc", "wake", "aotag", "scratch";
- };
-
-Board DTS:
-
- pmc@c360000 {
- nvidia,invert-interrupt;
- };
-
-== Pad Control ==
-
-On Tegra SoCs a pad is a set of pins which are configured as a group.
-The pin grouping is a fixed attribute of the hardware. The PMC can be
-used to set pad power state and signaling voltage. A pad can be either
-in active or power down mode. The support for power state and signaling
-voltage configuration varies depending on the pad in question. 3.3 V and
-1.8 V signaling voltages are supported on pins where software
-controllable signaling voltage switching is available.
-
-Pad configurations are described with pin configuration nodes which
-are placed under the pmc node and they are referred to by the pinctrl
-client properties. For more information see
-Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
-
-The following pads are present on Tegra186:
-csia csib dsi mipi-bias
-pex-clk-bias pex-clk3 pex-clk2 pex-clk1
-usb0 usb1 usb2 usb-bias
-uart audio hsic dbg
-hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
-sdmmc4 cam dsib dsic
-dsid csic csid csie
-dsif spi ufs dmic-hv
-edp sdmmc1-hv sdmmc3-hv conn
-audio-hv ao-hv
-
-Required pin configuration properties:
- - pins: A list of strings, each of which contains the name of a pad
- to be configured.
-
-Optional pin configuration properties:
- - low-power-enable: Configure the pad into power down mode
- - low-power-disable: Configure the pad into active mode
- - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
- TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
- The values are defined in
- include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
-
-Note: The power state can be configured on all of the above pads except
- for ao-hv. Following pads have software configurable signaling
- voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
- ao-hv.
-
-Pad configuration state example:
- pmc: pmc@7000e400 {
- compatible = "nvidia,tegra186-pmc";
- reg = <0 0x0c360000 0 0x10000>,
- <0 0x0c370000 0 0x10000>,
- <0 0x0c380000 0 0x10000>,
- <0 0x0c390000 0 0x10000>;
- reg-names = "pmc", "wake", "aotag", "scratch";
-
- ...
-
- sdmmc1_3v3: sdmmc1-3v3 {
- pins = "sdmmc1-hv";
- power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
- };
-
- sdmmc1_1v8: sdmmc1-1v8 {
- pins = "sdmmc1-hv";
- power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
- };
-
- hdmi_off: hdmi-off {
- pins = "hdmi";
- low-power-enable;
- }
-
- hdmi_on: hdmi-on {
- pins = "hdmi";
- low-power-disable;
- }
- };
-
-Pinctrl client example:
- sdmmc1: sdhci@3400000 {
- ...
- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
- pinctrl-0 = <&sdmmc1_3v3>;
- pinctrl-1 = <&sdmmc1_1v8>;
- };
-
- ...
-
- sor0: sor@15540000 {
- ...
- pinctrl-0 = <&hdmi_off>;
- pinctrl-1 = <&hdmi_on>;
- pinctrl-names = "hdmi-on", "hdmi-off";
- };
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
new file mode 100644
index 000000000000..6946df96ec81
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
@@ -0,0 +1,199 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Power Management Controller (PMC)
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra186-pmc
+ - nvidia,tegra194-pmc
+ - nvidia,tegra234-pmc
+
+ reg:
+ minItems: 4
+ maxItems: 5
+
+ reg-names:
+ minItems: 4
+ maxItems: 5
+ items:
+ - const: pmc
+ - const: wake
+ - const: aotag
+ - const: scratch
+ - const: misc
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ description: Specifies the number of cells needed to encode an
+ interrupt source. The value must be 2.
+ const: 2
+
+ nvidia,invert-interrupt:
+ description: If present, inverts the PMU interrupt signal.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra186-pmc
+then:
+ properties:
+ reg:
+ maxItems: 4
+
+ reg-names:
+ maxItems: 4
+else:
+ properties:
+ reg:
+ minItems: 5
+
+ reg-names:
+ minItems: 5
+
+patternProperties:
+ "^[a-z0-9]+-[a-z0-9]+$":
+ if:
+ type: object
+ then:
+ description: |
+ These are pad configuration nodes. On Tegra SoCs a pad is a set of
+ pins which are configured as a group. The pin grouping is a fixed
+ attribute of the hardware. The PMC can be used to set pad power
+ state and signaling voltage. A pad can be either in active or
+ power down mode. The support for power state and signaling voltage
+ configuration varies depending on the pad in question. 3.3 V and
+ 1.8 V signaling voltages are supported on pins where software
+ controllable signaling voltage switching is available.
+
+ Pad configurations are described with pin configuration nodes
+ which are placed under the pmc node and they are referred to by
+ the pinctrl client properties. For more information see
+
+ Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+ The following pads are present on Tegra186:
+
+ csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
+ pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
+ hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
+ dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
+ sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
+
+ The following pads are present on Tegra194:
+
+ csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
+ pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
+ pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
+ soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
+ hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
+ pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
+ spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
+ audio-hv, ao-hv
+
+ properties:
+ pins:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: Must contain the name of the pad(s) to be
+ configured.
+
+ low-power-enable:
+ description: Configure the pad into power down mode.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ low-power-disable:
+ description: Configure the pad into active mode.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ power-source:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
+ TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
+ voltages.
+
+ The values are defined in
+
+ include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
+
+ The power state can be configured on all of the above pads
+ except for ao-hv. Following pads have software configurable
+ signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
+ audio-hv, ao-hv.
+
+ phandle: true
+
+ required:
+ - pins
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+additionalProperties: false
+
+dependencies:
+ interrupt-controller: ['#interrupt-cells']
+ "#interrupt-cells":
+ required:
+ - interrupt-controller
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra186-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
+ #include <dt-bindings/memory/tegra186-mc.h>
+ #include <dt-bindings/reset/tegra186-reset.h>
+
+ pmc@c3600000 {
+ compatible = "nvidia,tegra186-pmc";
+ reg = <0x0c360000 0x10000>,
+ <0x0c370000 0x10000>,
+ <0x0c380000 0x10000>,
+ <0x0c390000 0x10000>;
+ reg-names = "pmc", "wake", "aotag", "scratch";
+ nvidia,invert-interrupt;
+
+ sdmmc1_3v3: sdmmc1-3v3 {
+ pins = "sdmmc1-hv";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+ };
+
+ sdmmc1_1v8: sdmmc1-1v8 {
+ pins = "sdmmc1-hv";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+ };
+ };
+
+ sdmmc1: mmc@3400000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x03400000 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
+ <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
+ clock-names = "sdhci", "tmclk";
+ resets = <&bpmp TEGRA186_RESET_SDMMC1>;
+ reset-names = "sdhci";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA186_SID_SDMMC1>;
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-0 = <&sdmmc1_3v3>;
+ pinctrl-1 = <&sdmmc1_1v8>;
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 12/15] dt-bindings: firmware: tegra: Convert to json-schema
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (10 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 11/15] dt-bindings: tegra: pmc: Convert to json-schema Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 15:01 ` Rob Herring
2021-11-12 12:05 ` [PATCH 13/15] dt-bindings: i2c: tegra-bpmp: " Thierry Reding
` (2 subsequent siblings)
14 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra186 (and later) BPMP bindings from the free-form
text format to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../firmware/nvidia,tegra186-bpmp.txt | 107 ------------
.../firmware/nvidia,tegra186-bpmp.yaml | 161 ++++++++++++++++++
2 files changed, 161 insertions(+), 107 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
deleted file mode 100644
index e44a13bc06ed..000000000000
--- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-NVIDIA Tegra Boot and Power Management Processor (BPMP)
-
-The BPMP is a specific processor in Tegra chip, which is designed for
-booting process handling and offloading the power management, clock
-management, and reset control tasks from the CPU. The binding document
-defines the resources that would be used by the BPMP firmware driver,
-which can create the interprocessor communication (IPC) between the CPU
-and BPMP.
-
-Required properties:
-- compatible
- Array of strings
- One of:
- - "nvidia,tegra186-bpmp"
-- mboxes : The phandle of mailbox controller and the mailbox specifier.
-- shmem : List of the phandle of the TX and RX shared memory area that
- the IPC between CPU and BPMP is based on.
-- #clock-cells : Should be 1.
-- #power-domain-cells : Should be 1.
-- #reset-cells : Should be 1.
-
-This node is a mailbox consumer. See the following files for details of
-the mailbox subsystem, and the specifiers implemented by the relevant
-provider(s):
-
-- .../mailbox/mailbox.txt
-- .../mailbox/nvidia,tegra186-hsp.txt
-
-This node is a clock, power domain, and reset provider. See the following
-files for general documentation of those features, and the specifiers
-implemented by this node:
-
-- .../clock/clock-bindings.txt
-- <dt-bindings/clock/tegra186-clock.h>
-- ../power/power-domain.yaml
-- <dt-bindings/power/tegra186-powergate.h>
-- .../reset/reset.txt
-- <dt-bindings/reset/tegra186-reset.h>
-
-The BPMP implements some services which must be represented by separate nodes.
-For example, it can provide access to certain I2C controllers, and the I2C
-bindings represent each I2C controller as a device tree node. Such nodes should
-be nested directly inside the main BPMP node.
-
-Software can determine whether a child node of the BPMP node represents a device
-by checking for a compatible property. Any node with a compatible property
-represents a device that can be instantiated. Nodes without a compatible
-property may be used to provide configuration information regarding the BPMP
-itself, although no such configuration nodes are currently defined by this
-binding.
-
-The BPMP firmware defines no single global name-/numbering-space for such
-services. Put another way, the numbering scheme for I2C buses is distinct from
-the numbering scheme for any other service the BPMP may provide (e.g. a future
-hypothetical SPI bus service). As such, child device nodes will have no reg
-property, and the BPMP node will have no #address-cells or #size-cells property.
-
-The shared memory bindings for BPMP
------------------------------------
-
-The shared memory area for the IPC TX and RX between CPU and BPMP are
-predefined and work on top of sysram, which is an SRAM inside the chip.
-
-See ".../sram/sram.txt" for the bindings.
-
-Example:
-
-hsp_top0: hsp@3c00000 {
- ...
- #mbox-cells = <2>;
-};
-
-sysram@30000000 {
- compatible = "nvidia,tegra186-sysram", "mmio-sram";
- reg = <0x0 0x30000000 0x0 0x50000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
-
- cpu_bpmp_tx: shmem@4e000 {
- compatible = "nvidia,tegra186-bpmp-shmem";
- reg = <0x0 0x4e000 0x0 0x1000>;
- label = "cpu-bpmp-tx";
- pool;
- };
-
- cpu_bpmp_rx: shmem@4f000 {
- compatible = "nvidia,tegra186-bpmp-shmem";
- reg = <0x0 0x4f000 0x0 0x1000>;
- label = "cpu-bpmp-rx";
- pool;
- };
-};
-
-bpmp {
- compatible = "nvidia,tegra186-bpmp";
- mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
- shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
- #clock-cells = <1>;
- #power-domain-cells = <1>;
- #reset-cells = <1>;
-
- i2c {
- compatible = "...";
- ...
- };
-};
diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
new file mode 100644
index 000000000000..b1dacb8953cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
@@ -0,0 +1,161 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ The BPMP is a specific processor in Tegra chip, which is designed for
+ booting process handling and offloading the power management, clock
+ management, and reset control tasks from the CPU. The binding document
+ defines the resources that would be used by the BPMP firmware driver,
+ which can create the interprocessor communication (IPC) between the
+ CPU and BPMP.
+
+ This node is a mailbox consumer. See the following files for details
+ of the mailbox subsystem, and the specifiers implemented by the
+ relevant provider(s):
+
+ - .../mailbox/mailbox.txt
+ - .../mailbox/nvidia,tegra186-hsp.yaml
+
+ This node is a clock, power domain, and reset provider. See the
+ following files for general documentation of those features, and the
+ specifiers implemented by this node:
+
+ - .../clock/clock-bindings.txt
+ - <dt-bindings/clock/tegra186-clock.h>
+ - ../power/power-domain.yaml
+ - <dt-bindings/power/tegra186-powergate.h>
+ - .../reset/reset.txt
+ - <dt-bindings/reset/tegra186-reset.h>
+
+ The BPMP implements some services which must be represented by
+ separate nodes. For example, it can provide access to certain I2C
+ controllers, and the I2C bindings represent each I2C controller as a
+ device tree node. Such nodes should be nested directly inside the main
+ BPMP node.
+
+ Software can determine whether a child node of the BPMP node
+ represents a device by checking for a compatible property. Any node
+ with a compatible property represents a device that can be
+ instantiated. Nodes without a compatible property may be used to
+ provide configuration information regarding the BPMP itself, although
+ no such configuration nodes are currently defined by this binding.
+
+ The BPMP firmware defines no single global name-/numbering-space for
+ such services. Put another way, the numbering scheme for I2C buses is
+ distinct from the numbering scheme for any other service the BPMP may
+ provide (e.g. a future hypothetical SPI bus service). As such, child
+ device nodes will have no reg property, and the BPMP node will have no
+ "#address-cells" or "#size-cells" property.
+
+ The shared memory area for the IPC TX and RX between CPU and BPMP are
+ predefined and work on top of sysram, which is an SRAM inside the
+ chip. See ".../sram/sram.yaml" for the bindings.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - nvidia,tegra194-bpmp
+ - nvidia,tegra234-bpmp
+ - const: nvidia,tegra186-bpmp
+ - const: nvidia,tegra186-bpmp
+
+ mboxes:
+ description: A phandle and channel specifier for the mailbox used to
+ communicate with the BPMP.
+ maxItems: 1
+
+ shmem:
+ description: List of the phandle to the TX and RX shared memory area
+ that the IPC between CPU and BPMP is based on.
+ minItems: 2
+ maxItems: 2
+
+ "#clock-cells":
+ const: 1
+
+ "#power-domain-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - mboxes
+ - shmem
+ - "#clock-cells"
+ - "#power-domain-cells"
+ - "#reset-cells"
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/mailbox/tegra186-hsp.h>
+ #include <dt-bindings/memory/tegra186-mc.h>
+
+ hsp_top0: hsp@3c00000 {
+ compatible = "nvidia,tegra186-hsp";
+ reg = <0x03c00000 0xa0000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "doorbell";
+ #mbox-cells = <2>;
+ };
+
+ sram@30000000 {
+ compatible = "nvidia,tegra186-sysram", "mmio-sram";
+ reg = <0x30000000 0x50000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000000 0x50000>;
+
+ cpu_bpmp_tx: sram@4e000 {
+ reg = <0x4e000 0x1000>;
+ label = "cpu-bpmp-tx";
+ pool;
+ };
+
+ cpu_bpmp_rx: sram@4f000 {
+ reg = <0x4f000 0x1000>;
+ label = "cpu-bpmp-rx";
+ pool;
+ };
+ };
+
+ bpmp {
+ compatible = "nvidia,tegra186-bpmp";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
+ interconnect-names = "read", "write", "dma-mem", "dma-write";
+ iommus = <&smmu TEGRA186_SID_BPMP>;
+ mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
+ TEGRA_HSP_DB_MASTER_BPMP>;
+ shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+
+ i2c {
+ compatible = "nvidia,tegra186-bpmp-i2c";
+ nvidia,bpmp-bus-id = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ thermal {
+ compatible = "nvidia,tegra186-bpmp-thermal";
+ #thermal-sensor-cells = <1>;
+ };
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 13/15] dt-bindings: i2c: tegra-bpmp: Convert to json-schema
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (11 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 12/15] dt-bindings: firmware: tegra: " Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 15:01 ` Rob Herring
2021-11-12 12:05 ` [PATCH 14/15] dt-bindings: serial: tegra-tcu: " Thierry Reding
2021-11-12 12:05 ` [PATCH 15/15] dt-bindings: serial: Document Tegra234 TCU Thierry Reding
14 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra186 (and later) BPMP I2C bindings from the
free-form text format to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 -------------------
.../i2c/nvidia,tegra186-bpmp-i2c.yaml | 40 ++++++++++++++++++
2 files changed, 40 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
deleted file mode 100644
index ab240e10debc..000000000000
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-NVIDIA Tegra186 BPMP I2C controller
-
-In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
-devices, such as the I2C controller for the power management I2C bus. Software
-running on other CPUs must perform IPC to the BPMP in order to execute
-transactions on that I2C bus. This binding describes an I2C bus that is
-accessed in such a fashion.
-
-The BPMP I2C node must be located directly inside the main BPMP node. See
-../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
-
-This node represents an I2C controller. See ../i2c/i2c.txt for details of the
-core I2C binding.
-
-Required properties:
-- compatible:
- Array of strings.
- One of:
- - "nvidia,tegra186-bpmp-i2c".
-- #address-cells: Address cells for I2C device address.
- Single-cell integer.
- Must be <1>.
-- #size-cells:
- Single-cell integer.
- Must be <0>.
-- nvidia,bpmp-bus-id:
- Single-cell integer.
- Indicates the I2C bus number this DT node represent, as defined by the
- BPMP firmware.
-
-Example:
-
-bpmp {
- ...
-
- i2c {
- compatible = "nvidia,tegra186-bpmp-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- nvidia,bpmp-bus-id = <5>;
- };
-};
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
new file mode 100644
index 000000000000..f3a68097dd6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra186 (and later) BPMP I2C controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ In Tegra186 and later, the BPMP (Boot and Power Management Processor)
+ owns certain HW devices, such as the I2C controller for the power
+ management I2C bus. Software running on other CPUs must perform IPC to
+ the BPMP in order to execute transactions on that I2C bus. This
+ binding describes an I2C bus that is accessed in such a fashion.
+
+ The BPMP I2C node must be located directly inside the main BPMP node.
+ See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
+ binding.
+
+ This node represents an I2C controller. See ../i2c/i2c.txt for details
+ of the core I2C binding.
+
+properties:
+ compatible:
+ const: nvidia,tegra186-bpmp-i2c
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ nvidia,bpmp-bus-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Indicates the I2C bus number this DT node represents,
+ as defined by the BPMP firmware.
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 14/15] dt-bindings: serial: tegra-tcu: Convert to json-schema
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (12 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 13/15] dt-bindings: i2c: tegra-bpmp: " Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 15:01 ` Rob Herring
2021-11-12 12:05 ` [PATCH 15/15] dt-bindings: serial: Document Tegra234 TCU Thierry Reding
14 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the Tegra TCU device tree bindings to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../bindings/serial/nvidia,tegra194-tcu.txt | 35 ------------
.../bindings/serial/nvidia,tegra194-tcu.yaml | 56 +++++++++++++++++++
2 files changed, 56 insertions(+), 35 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt
create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt
deleted file mode 100644
index 085a8591accd..000000000000
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-NVIDIA Tegra Combined UART (TCU)
-
-The TCU is a system for sharing a hardware UART instance among multiple
-systems within the Tegra SoC. It is implemented through a mailbox-
-based protocol where each "virtual UART" has a pair of mailboxes, one
-for transmitting and one for receiving, that is used to communicate
-with the hardware implementing the TCU.
-
-Required properties:
-- name : Should be tcu
-- compatible
- Array of strings
- One of:
- - "nvidia,tegra194-tcu"
-- mbox-names:
- "rx" - Mailbox for receiving data from hardware UART
- "tx" - Mailbox for transmitting data to hardware UART
-- mboxes: Mailboxes corresponding to the mbox-names.
-
-This node is a mailbox consumer. See the following files for details of
-the mailbox subsystem, and the specifiers implemented by the relevant
-provider(s):
-
-- .../mailbox/mailbox.txt
-- .../mailbox/nvidia,tegra186-hsp.txt
-
-Example bindings:
------------------
-
-tcu: tcu {
- compatible = "nvidia,tegra194-tcu";
- mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
- <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
- mbox-names = "rx", "tx";
-};
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
new file mode 100644
index 000000000000..7987eca0bb52
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Combined UART (TCU)
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jonathan Hunter <jonathanh@nvidia.com>
+
+description:
+ The TCU is a system for sharing a hardware UART instance among multiple
+ systems within the Tegra SoC. It is implemented through a mailbox-
+ based protocol where each "virtual UART" has a pair of mailboxes, one
+ for transmitting and one for receiving, that is used to communicate
+ with the hardware implementing the TCU.
+
+properties:
+ $nodename:
+ pattern: "^serial(@.*)?$"
+
+ compatible:
+ const: nvidia,tegra194-tcu
+
+ mbox-names:
+ items:
+ - const: rx
+ - const: tx
+
+ mboxes:
+ description: |
+ List of phandles to mailbox channels used for receiving and
+ transmitting data from and to the hardware UART.
+ items:
+ - description: mailbox for receiving data from hardware UART
+ - description: mailbox for transmitting data to hardware UART
+
+required:
+ - compatible
+ - mbox-names
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/mailbox/tegra186-hsp.h>
+
+ tcu: serial {
+ compatible = "nvidia,tegra194-tcu";
+ mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
+ <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
+ mbox-names = "rx", "tx";
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 15/15] dt-bindings: serial: Document Tegra234 TCU
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (13 preceding siblings ...)
2021-11-12 12:05 ` [PATCH 14/15] dt-bindings: serial: tegra-tcu: " Thierry Reding
@ 2021-11-12 12:05 ` Thierry Reding
2021-11-12 15:01 ` Rob Herring
14 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2021-11-12 12:05 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the TCU found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../devicetree/bindings/serial/nvidia,tegra194-tcu.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
index 7987eca0bb52..e2d111b3e0b0 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
@@ -22,7 +22,12 @@ properties:
pattern: "^serial(@.*)?$"
compatible:
- const: nvidia,tegra194-tcu
+ oneOf:
+ - const: nvidia,tegra194-tcu
+ - items:
+ - enum:
+ - nvidia,tegra234-tcu
+ - const: nvidia,tegra194-tcu
mbox-names:
items:
--
2.33.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH 03/15] dt-bindings: mailbox: tegra: Convert to json-schema
2021-11-12 12:05 ` [PATCH 03/15] dt-bindings: mailbox: " Thierry Reding
@ 2021-11-12 13:48 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2021-11-12 13:48 UTC (permalink / raw)
To: Thierry Reding; +Cc: Rob Herring, Jon Hunter, devicetree, linux-tegra
On Fri, 12 Nov 2021 13:05:06 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra HSP bindings from the free-form text format to
> json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/mailbox/nvidia,tegra186-hsp.txt | 72 ------------
> .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 109 ++++++++++++++++++
> 2 files changed, 109 insertions(+), 72 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt
> create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml: properties:compatible:oneOf: [{'const': 'nvidia,tegra186-hsp'}, {'const': 'nvidia,tegra194-hsp'}] should not be valid under {'items': {'propertyNames': {'const': 'const'}, 'required': ['const']}}
hint: Use 'enum' rather than 'oneOf' + 'const' entries
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml: 'additionalProperties' is a required property
hint: A schema without a "$ref" to another schema must define all properties and use "additionalProperties"
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml: ignoring, error in schema: properties: compatible: oneOf
warning: no schema found in file: ./Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.example.dt.yaml:0:0: /example-0/hsp@3c00000: failed to match any schema with compatible: ['nvidia,tegra186-hsp']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1554298
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 02/15] dt-bindings: mmc: tegra: Convert to json-schema
2021-11-12 12:05 ` [PATCH 02/15] dt-bindings: mmc: tegra: Convert " Thierry Reding
@ 2021-11-12 13:48 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2021-11-12 13:48 UTC (permalink / raw)
To: Thierry Reding; +Cc: Jon Hunter, Rob Herring, linux-tegra, devicetree
On Fri, 12 Nov 2021 13:05:05 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra SDHCI bindings from the free-form text format
> to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - drop redundant $ref properties, add missing maxItems
>
> .../bindings/mmc/nvidia,tegra20-sdhci.txt | 143 ---------
> .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 294 ++++++++++++++++++
> 2 files changed, 294 insertions(+), 143 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> create mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1554296
mmc@3460000: clock-names: ['sdhci'] is too short
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dt.yaml
mmc@3460000: clocks: [[2, 123]] is too short
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dt.yaml
mmc@3460000: compatible: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dt.yaml
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 05/15] dt-bindings: rtc: tegra: Convert to json-schema
2021-11-12 12:05 ` [PATCH 05/15] dt-bindings: rtc: tegra: Convert to json-schema Thierry Reding
@ 2021-11-12 13:48 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2021-11-12 13:48 UTC (permalink / raw)
To: Thierry Reding; +Cc: Rob Herring, devicetree, linux-tegra, Jon Hunter
On Fri, 12 Nov 2021 13:05:08 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra RTC bindings from the free-form text format to
> json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/rtc/nvidia,tegra20-rtc.txt | 24 ---------
> .../bindings/rtc/nvidia,tegra20-rtc.yaml | 54 +++++++++++++++++++
> 2 files changed, 54 insertions(+), 24 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
> create mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml: 'additionalProperties' is a required property
hint: A schema without a "$ref" to another schema must define all properties and use "additionalProperties"
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml: ignoring, error in schema:
warning: no schema found in file: ./Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.example.dt.yaml:0:0: /example-0/timer@7000e000: failed to match any schema with compatible: ['nvidia,tegra20-rtc']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1554301
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 11/15] dt-bindings: tegra: pmc: Convert to json-schema
2021-11-12 12:05 ` [PATCH 11/15] dt-bindings: tegra: pmc: Convert to json-schema Thierry Reding
@ 2021-11-12 15:01 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2021-11-12 15:01 UTC (permalink / raw)
To: Thierry Reding; +Cc: Rob Herring, devicetree, linux-tegra, Jon Hunter
On Fri, 12 Nov 2021 13:05:14 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra186 (and later) PMC bindings from the free-form
> text format to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../arm/tegra/nvidia,tegra186-pmc.txt | 133 ------------
> .../arm/tegra/nvidia,tegra186-pmc.yaml | 199 ++++++++++++++++++
> 2 files changed, 199 insertions(+), 133 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml: properties:reg-names: {'minItems': 4, 'maxItems': 5, 'items': [{'const': 'pmc'}, {'const': 'wake'}, {'const': 'aotag'}, {'const': 'scratch'}, {'const': 'misc'}]} should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml: ignoring, error in schema: properties: reg-names
warning: no schema found in file: ./Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.example.dt.yaml:0:0: /example-0/pmc@c3600000: failed to match any schema with compatible: ['nvidia,tegra186-pmc']
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.example.dt.yaml:0:0: /example-0/mmc@3400000: failed to match any schema with compatible: ['nvidia,tegra186-sdhci']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1554314
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 10/15] dt-bindings: serial: 8250: Document Tegra234 UART
2021-11-12 12:05 ` [PATCH 10/15] dt-bindings: serial: 8250: Document Tegra234 UART Thierry Reding
@ 2021-11-12 15:01 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2021-11-12 15:01 UTC (permalink / raw)
To: Thierry Reding; +Cc: Rob Herring, devicetree, Jon Hunter, linux-tegra
On Fri, 12 Nov 2021 13:05:13 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Add the compatible string for the UART found on the Tegra234 SoC.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Documentation/devicetree/bindings/serial/8250.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1554312
serial@2f8: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/hisilicon/hip06-d03.dt.yaml
serial@40081000: clocks: [[4, 1280], [2, 1288]] is too long
arch/arm/boot/dts/lpc4337-ciaa.dt.yaml
serial@40081000: clocks: [[5, 1280], [2, 1288]] is too long
arch/arm/boot/dts/lpc4350-hitex-eval.dt.yaml
arch/arm/boot/dts/lpc4357-ea4357-devkit.dt.yaml
arch/arm/boot/dts/lpc4357-myd-lpc4357.dt.yaml
serial@40082000: clocks: [[4, 1024], [2, 1296]] is too long
arch/arm/boot/dts/lpc4337-ciaa.dt.yaml
serial@40082000: clocks: [[5, 1024], [2, 1296]] is too long
arch/arm/boot/dts/lpc4350-hitex-eval.dt.yaml
arch/arm/boot/dts/lpc4357-ea4357-devkit.dt.yaml
arch/arm/boot/dts/lpc4357-myd-lpc4357.dt.yaml
serial@400c1000: clocks: [[4, 768], [2, 1544]] is too long
arch/arm/boot/dts/lpc4337-ciaa.dt.yaml
serial@400c1000: clocks: [[5, 768], [2, 1544]] is too long
arch/arm/boot/dts/lpc4350-hitex-eval.dt.yaml
arch/arm/boot/dts/lpc4357-ea4357-devkit.dt.yaml
arch/arm/boot/dts/lpc4357-myd-lpc4357.dt.yaml
serial@400c2000: clocks: [[4, 512], [2, 1552]] is too long
arch/arm/boot/dts/lpc4337-ciaa.dt.yaml
serial@400c2000: clocks: [[5, 512], [2, 1552]] is too long
arch/arm/boot/dts/lpc4350-hitex-eval.dt.yaml
arch/arm/boot/dts/lpc4357-ea4357-devkit.dt.yaml
arch/arm/boot/dts/lpc4357-myd-lpc4357.dt.yaml
uart@221000: $nodename:0: 'uart@221000' does not match '^serial(@.*)?$'
arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dt.yaml
arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dt.yaml
arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dt.yaml
arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dt.yaml
arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dt.yaml
uart@3,0: $nodename:0: 'uart@3,0' does not match '^serial(@.*)?$'
arch/arm/boot/dts/omap3-zoom3.dt.yaml
uart@3,0: Unevaluated properties are not allowed ('bank-width', 'gpmc,mux-add-data', 'gpmc,device-width', 'gpmc,wait-pin', 'gpmc,cycle2cycle-samecsen', 'gpmc,cycle2cycle-diffcsen', 'gpmc,cs-on-ns', 'gpmc,cs-rd-off-ns', 'gpmc,cs-wr-off-ns', 'gpmc,adv-on-ns', 'gpmc,adv-rd-off-ns', 'gpmc,adv-wr-off-ns', 'gpmc,oe-on-ns', 'gpmc,oe-off-ns', 'gpmc,we-on-ns', 'gpmc,we-off-ns', 'gpmc,rd-cycle-ns', 'gpmc,wr-cycle-ns', 'gpmc,access-ns', 'gpmc,page-burst-access-ns', 'gpmc,bus-turnaround-ns', 'gpmc,cycle2cycle-delay-ns', 'gpmc,wait-monitoring-ns', 'gpmc,clk-activation-ns', 'gpmc,wr-data-mux-bus-ns', 'gpmc,wr-access-ns' were unexpected)
arch/arm/boot/dts/omap3-zoom3.dt.yaml
uart@3,1: $nodename:0: 'uart@3,1' does not match '^serial(@.*)?$'
arch/arm/boot/dts/omap3-zoom3.dt.yaml
uart@3,1: Unevaluated properties are not allowed ('bank-width' was unexpected)
arch/arm/boot/dts/omap3-zoom3.dt.yaml
uart@3,2: $nodename:0: 'uart@3,2' does not match '^serial(@.*)?$'
arch/arm/boot/dts/omap3-zoom3.dt.yaml
uart@3,2: Unevaluated properties are not allowed ('bank-width' was unexpected)
arch/arm/boot/dts/omap3-zoom3.dt.yaml
uart@3,3: $nodename:0: 'uart@3,3' does not match '^serial(@.*)?$'
arch/arm/boot/dts/omap3-zoom3.dt.yaml
uart@3,3: Unevaluated properties are not allowed ('bank-width' was unexpected)
arch/arm/boot/dts/omap3-zoom3.dt.yaml
uart8250@3,1000000: $nodename:0: 'uart8250@3,1000000' does not match '^serial(@.*)?$'
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dt.yaml
uart8250@3,1000000: Unevaluated properties are not allowed ('fsl,weim-cs-timing' was unexpected)
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dt.yaml
uart8250@3,200000: $nodename:0: 'uart8250@3,200000' does not match '^serial(@.*)?$'
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dt.yaml
uart8250@3,200000: Unevaluated properties are not allowed ('fsl,weim-cs-timing' was unexpected)
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dt.yaml
uart8250@3,400000: $nodename:0: 'uart8250@3,400000' does not match '^serial(@.*)?$'
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dt.yaml
uart8250@3,400000: Unevaluated properties are not allowed ('fsl,weim-cs-timing' was unexpected)
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dt.yaml
uart8250@3,800000: $nodename:0: 'uart8250@3,800000' does not match '^serial(@.*)?$'
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dt.yaml
uart8250@3,800000: Unevaluated properties are not allowed ('fsl,weim-cs-timing' was unexpected)
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dt.yaml
uart@98200000: $nodename:0: 'uart@98200000' does not match '^serial(@.*)?$'
arch/arm/boot/dts/moxart-uc7112lx.dt.yaml
uart@fd883000: $nodename:0: 'uart@fd883000' does not match '^serial(@.*)?$'
arch/arm/boot/dts/alpine-db.dt.yaml
uart@fd884000: $nodename:0: 'uart@fd884000' does not match '^serial(@.*)?$'
arch/arm/boot/dts/alpine-db.dt.yaml
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 13/15] dt-bindings: i2c: tegra-bpmp: Convert to json-schema
2021-11-12 12:05 ` [PATCH 13/15] dt-bindings: i2c: tegra-bpmp: " Thierry Reding
@ 2021-11-12 15:01 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2021-11-12 15:01 UTC (permalink / raw)
To: Thierry Reding; +Cc: Jon Hunter, devicetree, Rob Herring, linux-tegra
On Fri, 12 Nov 2021 13:05:16 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra186 (and later) BPMP I2C bindings from the
> free-form text format to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 -------------------
> .../i2c/nvidia,tegra186-bpmp-i2c.yaml | 40 ++++++++++++++++++
> 2 files changed, 40 insertions(+), 42 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml: 'additionalProperties' is a required property
hint: A schema without a "$ref" to another schema must define all properties and use "additionalProperties"
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml: ignoring, error in schema:
warning: no schema found in file: ./Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1554317
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 12/15] dt-bindings: firmware: tegra: Convert to json-schema
2021-11-12 12:05 ` [PATCH 12/15] dt-bindings: firmware: tegra: " Thierry Reding
@ 2021-11-12 15:01 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2021-11-12 15:01 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Rob Herring, devicetree, Jon Hunter
On Fri, 12 Nov 2021 13:05:15 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra186 (and later) BPMP bindings from the free-form
> text format to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../firmware/nvidia,tegra186-bpmp.txt | 107 ------------
> .../firmware/nvidia,tegra186-bpmp.yaml | 161 ++++++++++++++++++
> 2 files changed, 161 insertions(+), 107 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
> create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml: 'additionalProperties' is a required property
hint: A schema without a "$ref" to another schema must define all properties and use "additionalProperties"
from schema $id: http://devicetree.org/meta-schemas/base.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml: ignoring, error in schema:
warning: no schema found in file: ./Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.example.dt.yaml:0:0: /example-0/hsp@3c00000: failed to match any schema with compatible: ['nvidia,tegra186-hsp']
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.example.dt.yaml:0:0: /example-0/sram@30000000: failed to match any schema with compatible: ['nvidia,tegra186-sysram', 'mmio-sram']
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.example.dt.yaml:0:0: /example-0/bpmp: failed to match any schema with compatible: ['nvidia,tegra186-bpmp']
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.example.dt.yaml:0:0: /example-0/bpmp/i2c: failed to match any schema with compatible: ['nvidia,tegra186-bpmp-i2c']
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.example.dt.yaml:0:0: /example-0/bpmp/thermal: failed to match any schema with compatible: ['nvidia,tegra186-bpmp-thermal']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1554316
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 14/15] dt-bindings: serial: tegra-tcu: Convert to json-schema
2021-11-12 12:05 ` [PATCH 14/15] dt-bindings: serial: tegra-tcu: " Thierry Reding
@ 2021-11-12 15:01 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2021-11-12 15:01 UTC (permalink / raw)
To: Thierry Reding; +Cc: Rob Herring, devicetree, Jon Hunter, linux-tegra
On Fri, 12 Nov 2021 13:05:17 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the Tegra TCU device tree bindings to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/serial/nvidia,tegra194-tcu.txt | 35 ------------
> .../bindings/serial/nvidia,tegra194-tcu.yaml | 56 +++++++++++++++++++
> 2 files changed, 56 insertions(+), 35 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt
> create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1554320
tcu: $nodename:0: 'tcu' does not match '^serial(@.*)?$'
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 15/15] dt-bindings: serial: Document Tegra234 TCU
2021-11-12 12:05 ` [PATCH 15/15] dt-bindings: serial: Document Tegra234 TCU Thierry Reding
@ 2021-11-12 15:01 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2021-11-12 15:01 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Jon Hunter, devicetree, Rob Herring
On Fri, 12 Nov 2021 13:05:18 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Add the compatible string for the TCU found on the Tegra234 SoC.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../devicetree/bindings/serial/nvidia,tegra194-tcu.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1554322
tcu: $nodename:0: 'tcu' does not match '^serial(@.*)?$'
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2021-11-12 15:02 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-12 12:05 [PATCH 00/15] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
2021-11-12 12:05 ` [PATCH 01/15] dt-bindings: misc: Convert Tegra MISC " Thierry Reding
2021-11-12 12:05 ` [PATCH 02/15] dt-bindings: mmc: tegra: Convert " Thierry Reding
2021-11-12 13:48 ` Rob Herring
2021-11-12 12:05 ` [PATCH 03/15] dt-bindings: mailbox: " Thierry Reding
2021-11-12 13:48 ` Rob Herring
2021-11-12 12:05 ` [PATCH 04/15] dt-bindings: mailbox: tegra: Document Tegra234 HSP Thierry Reding
2021-11-12 12:05 ` [PATCH 05/15] dt-bindings: rtc: tegra: Convert to json-schema Thierry Reding
2021-11-12 13:48 ` Rob Herring
2021-11-12 12:05 ` [PATCH 06/15] dt-bindings: rtc: tegra: Document Tegra234 RTC Thierry Reding
2021-11-12 12:05 ` [PATCH 07/15] dt-bindings: fuse: tegra: Convert to json-schema Thierry Reding
2021-11-12 12:05 ` [PATCH 08/15] dt-bindings: fuse: tegra: Document Tegra234 FUSE Thierry Reding
2021-11-12 12:05 ` [PATCH 09/15] dt-bindings: mmc: tegra: Document Tegra234 SDHCI Thierry Reding
2021-11-12 12:05 ` [PATCH 10/15] dt-bindings: serial: 8250: Document Tegra234 UART Thierry Reding
2021-11-12 15:01 ` Rob Herring
2021-11-12 12:05 ` [PATCH 11/15] dt-bindings: tegra: pmc: Convert to json-schema Thierry Reding
2021-11-12 15:01 ` Rob Herring
2021-11-12 12:05 ` [PATCH 12/15] dt-bindings: firmware: tegra: " Thierry Reding
2021-11-12 15:01 ` Rob Herring
2021-11-12 12:05 ` [PATCH 13/15] dt-bindings: i2c: tegra-bpmp: " Thierry Reding
2021-11-12 15:01 ` Rob Herring
2021-11-12 12:05 ` [PATCH 14/15] dt-bindings: serial: tegra-tcu: " Thierry Reding
2021-11-12 15:01 ` Rob Herring
2021-11-12 12:05 ` [PATCH 15/15] dt-bindings: serial: Document Tegra234 TCU Thierry Reding
2021-11-12 15:01 ` Rob Herring
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