[PATCH v4 0/4] arm64: dts: renesas: r8a779a0 DU support

[PATCH v4 0/4] arm64: dts: renesas: r8a779a0 DU support

[Kieran Bingham]

Provide the DT nodes for the DU, and DSI found on the r8a779a0, and
extend the falcon-cpu board add on with the TI SN65DSI86 bridge which is
used to connect the DSI output to the mini display-port connector on the
Falcon CPU board.

This has been successfully tested on a Falcon-V3U with patches to the
rcar_du and sn65dsi86 which will be sent separately.

Patch 4 could be expected to be merged with patch 2, but I have kept it
separate for specific review. It can stay separate or be squashed if the
change itself is approved.

Kieran Bingham (4):
  arm64: dts: renesas: r8a779a0: Add DU support
  arm64: dts: renesas: r8a779a0: Add DSI encoders
  arm64: dts: renesas: r8a779a0: falcon-cpu: Add DSI display output
  arm64: dts: renesas: r8a779a0: Provide default DSI data-lanes

 .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 79 +++++++++++++++
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi     | 99 +++++++++++++++++++
 2 files changed, 178 insertions(+)

-- 
2.30.2

[PATCH v4 1/4] arm64: dts: renesas: r8a779a0: Add DU support

[Kieran Bingham]

Provide the device nodes for the DU on the V3U platforms.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
v2
 - Use a single clock specification for the whole DU.

v3:
 - Use 'du.0' clock name instead of 'du'

v4:
 - Add in missing reset-names
 - Use full renesas,vsps


 arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 9e085d635100..483bb971c3ca 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -2601,6 +2601,38 @@ isp3vin31: endpoint {
 			};
 		};
 
+		du: display@feb00000 {
+			compatible = "renesas,du-r8a779a0";
+			reg = <0 0xfeb00000 0 0x40000>;
+			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 411>;
+			clock-names = "du.0";
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets = <&cpg 411>;
+			reset-names = "du.0";
+			renesas,vsps = <&vspd0 0>, <&vspd1 0>;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					du_out_dsi0: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					du_out_dsi1: endpoint {
+					};
+				};
+			};
+		};
+
 		prr: chipid@fff00044 {
 			compatible = "renesas,prr";
 			reg = <0 0xfff00044 0 4>;
-- 
2.30.2

Re: [PATCH v4 1/4] arm64: dts: renesas: r8a779a0: Add DU support

[Geert Uytterhoeven]

Hi Kieran,

On Fri, Nov 26, 2021 at 10:54 AM Kieran Bingham
<kieran.bingham+renesas@ideasonboard.com> wrote:
> Provide the device nodes for the DU on the V3U platforms.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> ---
> v2
>  - Use a single clock specification for the whole DU.
>
> v3:
>  - Use 'du.0' clock name instead of 'du'
>
> v4:
>  - Add in missing reset-names
>  - Use full renesas,vsps

Thanks for the update!
Will queue in renesas-devel for v5.17, with the du-node relocated to its
final resting place.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v4 2/4] arm64: dts: renesas: r8a779a0: Add DSI encoders

[Kieran Bingham]

Provide the two MIPI DSI encoders on the V3U and connect them to the DU
accordingly.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
v2
 - Fixup indentation

v3
 - Fix the clock references
 - Fixup dsi1 as well

-v4:
 - Use the correct pll clocks.


This is still pending approval/integration of the DSI encoder bindings
at [0]

[0] https://lore.kernel.org/all/YQGFP%2FcFoSksPyn+@pendragon.ideasonboard.com/

 arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 64 +++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 483bb971c3ca..fdad8bc4a069 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -2622,12 +2622,76 @@ ports {
 				port@0 {
 					reg = <0>;
 					du_out_dsi0: endpoint {
+						remote-endpoint = <&dsi0_in>;
 					};
 				};
 
 				port@1 {
 					reg = <1>;
 					du_out_dsi1: endpoint {
+						remote-endpoint = <&dsi1_in>;
+					};
+				};
+			};
+		};
+
+		dsi0: dsi-encoder@fed80000 {
+			compatible = "renesas,r8a779a0-dsi-csi2-tx";
+			reg = <0 0xfed80000 0 0x10000>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 415>,
+				 <&cpg CPG_CORE R8A779A0_CLK_DSI>,
+				 <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>;
+			clock-names = "fck", "dsi", "pll";
+
+			resets = <&cpg 415>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dsi0_in: endpoint {
+						remote-endpoint = <&du_out_dsi0>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dsi0_out: endpoint {
+					};
+				};
+			};
+		};
+
+		dsi1: dsi-encoder@fed90000 {
+			compatible = "renesas,r8a779a0-dsi-csi2-tx";
+			reg = <0 0xfed90000 0 0x10000>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			clocks = <&cpg CPG_MOD 415>,
+				 <&cpg CPG_CORE R8A779A0_CLK_DSI>,
+				 <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>;
+			clock-names = "fck", "dsi", "pll";
+
+			resets = <&cpg 416>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dsi1_in: endpoint {
+						remote-endpoint = <&du_out_dsi1>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dsi1_out: endpoint {
 					};
 				};
 			};
-- 
2.30.2

[PATCH v4 3/4] arm64: dts: renesas: r8a779a0: falcon-cpu: Add DSI display output

[Kieran Bingham]

Provide the display output using the sn65dsi86 MIPI DSI bridge

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
v3:
 - Fix the voltage regulator values
 - No longer override the clocks
 - use clk-x6 as clock node name

 .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
index cd2f0d60f21a..62b62656b486 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
@@ -98,6 +98,15 @@ memory@700000000 {
 		reg = <0x7 0x00000000 0x0 0x80000000>;
 	};
 
+	reg_1p2v: regulator-1p2v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.2V";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
@@ -115,6 +124,41 @@ reg_3p3v: regulator-3p3v {
 		regulator-boot-on;
 		regulator-always-on;
 	};
+
+	mini-dp-con {
+		compatible = "dp-connector";
+		label = "CN5";
+		type = "mini";
+
+		port {
+			mini_dp_con_in: endpoint {
+				remote-endpoint = <&sn65dsi86_out>;
+			};
+		};
+	};
+
+	sn65dsi86_refclk: clk-x6 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <38400000>;
+	};
+};
+
+&dsi0 {
+	status = "okay";
+
+	ports {
+		port@1 {
+			endpoint {
+				remote-endpoint = <&sn65dsi86_in>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&du {
+	status = "okay";
 };
 
 &extal_clk {
@@ -146,6 +190,41 @@ &i2c1 {
 
 	status = "okay";
 	clock-frequency = <400000>;
+
+	sn65dsi86@2c {
+		compatible = "ti,sn65dsi86";
+		reg = <0x2c>;
+
+		clocks = <&sn65dsi86_refclk>;
+		clock-names = "refclk";
+
+		interrupt-parent = <&gpio1>;
+		interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+
+		vccio-supply = <&reg_1p8v>;
+		vpll-supply = <&reg_1p8v>;
+		vcca-supply = <&reg_1p2v>;
+		vcc-supply = <&reg_1p2v>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				sn65dsi86_in: endpoint {
+					remote-endpoint = <&dsi0_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				sn65dsi86_out: endpoint {
+					remote-endpoint = <&mini_dp_con_in>;
+				};
+			};
+		};
+	};
 };
 
 &i2c6 {
-- 
2.30.2

[PATCH v4 4/4] arm64: dts: renesas: r8a779a0: Provide default DSI data-lanes

[Kieran Bingham]

The data-lanes is a mandatory property for the endpoints.
Provide a default when not connected that represents the maximum
lanes supported by the device.

A connected device should override the data-lanes if it uses a lower
number of lanes.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---

This patch is split from 2/4 to keep it's change for distinct review.
The data-lanes is marked as a mandatory property in the DSI bindings
(which are out of tree, most recent posting at [0])

[0] https://lore.kernel.org/all/YQGFP%2FcFoSksPyn+@pendragon.ideasonboard.com/

The data-lanes property is marked as mandatory, which means it needs to
be provided even when supplying the port templates which get overridden
later. Is this expected behaviour?

Does this have sufficient meaning? Or will it always have to be
specified by any node overriding anyway...?


 arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index fdad8bc4a069..7322c4628e2b 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -2661,6 +2661,7 @@ dsi0_in: endpoint {
 				port@1 {
 					reg = <1>;
 					dsi0_out: endpoint {
+						data-lanes = <1 2 3 4>;
 					};
 				};
 			};
@@ -2691,7 +2692,9 @@ dsi1_in: endpoint {
 
 				port@1 {
 					reg = <1>;
+
 					dsi1_out: endpoint {
+						data-lanes = <1 2 3 4>;
 					};
 				};
 			};
-- 
2.30.2

Re: [PATCH v4 4/4] arm64: dts: renesas: r8a779a0: Provide default DSI data-lanes

[Laurent Pinchart]

Hi Kieran,

Thank you for the patch.

On Fri, Nov 26, 2021 at 09:54:45AM +0000, Kieran Bingham wrote:
> The data-lanes is a mandatory property for the endpoints.
> Provide a default when not connected that represents the maximum
> lanes supported by the device.
> 
> A connected device should override the data-lanes if it uses a lower
> number of lanes.
> 
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> ---
> 
> This patch is split from 2/4 to keep it's change for distinct review.
> The data-lanes is marked as a mandatory property in the DSI bindings
> (which are out of tree, most recent posting at [0])
> 
> [0] https://lore.kernel.org/all/YQGFP%2FcFoSksPyn+@pendragon.ideasonboard.com/
> 
> The data-lanes property is marked as mandatory, which means it needs to
> be provided even when supplying the port templates which get overridden
> later. Is this expected behaviour?
> 
> Does this have sufficient meaning? Or will it always have to be
> specified by any node overriding anyway...?

Isn't the remote-endpoint also mandatory ?

Given that there's no real good default value for data-lanes that is
significantly more likely than others, I'd prefer dropping the endpoints
from r8a779a0.dtsi and adding them in board files.

>  arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> index fdad8bc4a069..7322c4628e2b 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -2661,6 +2661,7 @@ dsi0_in: endpoint {
>  				port@1 {
>  					reg = <1>;
>  					dsi0_out: endpoint {
> +						data-lanes = <1 2 3 4>;
>  					};
>  				};
>  			};
> @@ -2691,7 +2692,9 @@ dsi1_in: endpoint {
>  
>  				port@1 {
>  					reg = <1>;
> +
>  					dsi1_out: endpoint {
> +						data-lanes = <1 2 3 4>;
>  					};
>  				};
>  			};

-- 
Regards,

Laurent Pinchart