From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
To: Rob Herring <robh+dt@kernel.org>, Heiko Stuebner <heiko@sntech.de>
Cc: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A
Date: Fri, 26 Nov 2021 16:43:44 +0100 [thread overview]
Message-ID: <20211126154344.724316-4-frattaroli.nicolas@gmail.com> (raw)
In-Reply-To: <20211126154344.724316-1-frattaroli.nicolas@gmail.com>
The Quartz64 Model A has the SPI pins broken out on its pin
header. The actual pins being used though are not the m0
variant, but the m1 variant, which also lacks the cs1 pin.
This commit overrides pinctrl-0 accordingly for this board.
spi1 is intentionally left disabled, as anyone wishing to add
SPI devices needs to edit the dts anyway, and the pins are more
useful as GPIOs for the rest of the users.
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 4d4b2a301b1a..166399b7f13f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -509,6 +509,11 @@ &spdif {
status = "okay";
};
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+};
+
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
--
2.34.0
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID (diff)
From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
To: Rob Herring <robh+dt@kernel.org>, Heiko Stuebner <heiko@sntech.de>
Cc: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A
Date: Fri, 26 Nov 2021 16:43:44 +0100 [thread overview]
Message-ID: <20211126154344.724316-4-frattaroli.nicolas@gmail.com> (raw)
In-Reply-To: <20211126154344.724316-1-frattaroli.nicolas@gmail.com>
The Quartz64 Model A has the SPI pins broken out on its pin
header. The actual pins being used though are not the m0
variant, but the m1 variant, which also lacks the cs1 pin.
This commit overrides pinctrl-0 accordingly for this board.
spi1 is intentionally left disabled, as anyone wishing to add
SPI devices needs to edit the dts anyway, and the pins are more
useful as GPIOs for the rest of the users.
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 4d4b2a301b1a..166399b7f13f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -509,6 +509,11 @@ &spdif {
status = "okay";
};
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+};
+
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
--
2.34.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
To: Rob Herring <robh+dt@kernel.org>, Heiko Stuebner <heiko@sntech.de>
Cc: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A
Date: Fri, 26 Nov 2021 16:43:44 +0100 [thread overview]
Message-ID: <20211126154344.724316-4-frattaroli.nicolas@gmail.com> (raw)
In-Reply-To: <20211126154344.724316-1-frattaroli.nicolas@gmail.com>
The Quartz64 Model A has the SPI pins broken out on its pin
header. The actual pins being used though are not the m0
variant, but the m1 variant, which also lacks the cs1 pin.
This commit overrides pinctrl-0 accordingly for this board.
spi1 is intentionally left disabled, as anyone wishing to add
SPI devices needs to edit the dts anyway, and the pins are more
useful as GPIOs for the rest of the users.
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 4d4b2a301b1a..166399b7f13f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -509,6 +509,11 @@ &spdif {
status = "okay";
};
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+};
+
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
--
2.34.0
next prev parent reply other threads:[~2021-11-26 15:44 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-26 15:43 [PATCH 0/3] RK356x/Quartz64 Model A SPI Nicolas Frattaroli
2021-11-26 15:43 ` Nicolas Frattaroli
2021-11-26 15:43 ` Nicolas Frattaroli
2021-11-26 15:43 ` [PATCH 1/3] dt-bindings: spi: spi-rockchip: Add rk3568-spi compatible Nicolas Frattaroli
2021-11-26 15:43 ` Nicolas Frattaroli
2021-11-26 15:43 ` Nicolas Frattaroli
2021-11-26 15:43 ` [PATCH 2/3] arm64: dts: rockchip: Add spi nodes on rk356x Nicolas Frattaroli
2021-11-26 15:43 ` Nicolas Frattaroli
2021-11-26 15:43 ` Nicolas Frattaroli
2021-11-26 17:51 ` Johan Jonker
2021-11-26 17:51 ` Johan Jonker
2021-11-26 17:51 ` Johan Jonker
2021-11-26 18:59 ` Heiko Stübner
2021-11-26 18:59 ` Heiko Stübner
2021-11-26 18:59 ` Heiko Stübner
2021-11-26 15:43 ` Nicolas Frattaroli [this message]
2021-11-26 15:43 ` [PATCH 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A Nicolas Frattaroli
2021-11-26 15:43 ` Nicolas Frattaroli
2021-11-29 16:45 ` (subset) [PATCH 0/3] RK356x/Quartz64 Model A SPI Mark Brown
2021-11-29 16:45 ` Mark Brown
2021-11-29 16:45 ` Mark Brown
2022-01-25 10:20 ` Mark Brown
2022-01-25 10:20 ` Mark Brown
2022-01-25 10:20 ` Mark Brown
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