From: Jisheng Zhang <jszhang@kernel.org> To: wefu@redhat.com Cc: anup.patel@wdc.com, atishp04@gmail.com, palmer@dabbelt.com, guoren@kernel.org, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, hch@lst.de, liush@allwinnertech.com, lazyparser@gmail.com, drew@beagleboard.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, taiten.peng@canonical.com, aniket.ponkshe@canonical.com, heinrich.schuchardt@canonical.com, gordan.markus@canonical.com, guoren@linux.alibaba.com, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com Subject: Re: [PATCH V4 0/2] riscv: add RISC-V Svpbmt Standard Extension supports Date: Mon, 29 Nov 2021 21:33:18 +0800 [thread overview] Message-ID: <20211129213309.40673113@xhacker> (raw) In-Reply-To: <20211129014007.286478-1-wefu@redhat.com> On Mon, 29 Nov 2021 09:40:05 +0800 wefu@redhat.com wrote: > From: Fu Wei <wefu@redhat.com> > > This patch follows the RISC-V standard Svpbmt extension in > privilege spec to solve the non-coherent SOC DMA synchronization > issues. > > The svpbmt PTE format: > | 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 > N MT RSW D A G U X W R V > ^ > > Of the Reserved bits [63:54] in a leaf PTE, the bits [62:61] are used as > the MT (aka MemType) field. This field specifies one of three memory types > as shown in the following table: > MemType RISC-V Description > ---------- ------------------------------------------------ > 00 - PMA Normal Cacheable, No change to implied PMA memory type > 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory > 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory > 11 - Rsvd Reserved for future standard use > > The standard protection_map[] needn't be modified because the "PMA" > type keeps the highest bits zero. > And the whole modification is limited in the arch/riscv/* and using > a global variable(__svpbmt) as _PAGE_MASK/IO/NOCACHE for pgprot_noncached > (&writecombine) in pgtable.h. We also add _PAGE_CHG_MASK to filter > PFN than before. > > Enable it in devicetree - (Add "riscv,svpbmt" in the mmu of cpu node) > - mmu: > riscv,svpmbt > I noticed that this series goes up to v4 but changes history is missing. Will you add it? > Wei Fu (2): > dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt > riscv: add RISC-V Svpbmt extension supports > > .../devicetree/bindings/riscv/cpus.yaml | 10 +++++ > arch/riscv/include/asm/fixmap.h | 2 +- > arch/riscv/include/asm/pgtable-64.h | 21 ++++++++-- > arch/riscv/include/asm/pgtable-bits.h | 39 ++++++++++++++++++- > arch/riscv/include/asm/pgtable.h | 39 ++++++++++++++----- > arch/riscv/kernel/cpufeature.c | 35 +++++++++++++++++ > arch/riscv/mm/init.c | 5 +++ > 7 files changed, 136 insertions(+), 15 deletions(-) > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org> To: wefu@redhat.com Cc: anup.patel@wdc.com, atishp04@gmail.com, palmer@dabbelt.com, guoren@kernel.org, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, hch@lst.de, liush@allwinnertech.com, lazyparser@gmail.com, drew@beagleboard.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, taiten.peng@canonical.com, aniket.ponkshe@canonical.com, heinrich.schuchardt@canonical.com, gordan.markus@canonical.com, guoren@linux.alibaba.com, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com Subject: Re: [PATCH V4 0/2] riscv: add RISC-V Svpbmt Standard Extension supports Date: Mon, 29 Nov 2021 21:33:18 +0800 [thread overview] Message-ID: <20211129213309.40673113@xhacker> (raw) In-Reply-To: <20211129014007.286478-1-wefu@redhat.com> On Mon, 29 Nov 2021 09:40:05 +0800 wefu@redhat.com wrote: > From: Fu Wei <wefu@redhat.com> > > This patch follows the RISC-V standard Svpbmt extension in > privilege spec to solve the non-coherent SOC DMA synchronization > issues. > > The svpbmt PTE format: > | 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 > N MT RSW D A G U X W R V > ^ > > Of the Reserved bits [63:54] in a leaf PTE, the bits [62:61] are used as > the MT (aka MemType) field. This field specifies one of three memory types > as shown in the following table: > MemType RISC-V Description > ---------- ------------------------------------------------ > 00 - PMA Normal Cacheable, No change to implied PMA memory type > 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory > 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory > 11 - Rsvd Reserved for future standard use > > The standard protection_map[] needn't be modified because the "PMA" > type keeps the highest bits zero. > And the whole modification is limited in the arch/riscv/* and using > a global variable(__svpbmt) as _PAGE_MASK/IO/NOCACHE for pgprot_noncached > (&writecombine) in pgtable.h. We also add _PAGE_CHG_MASK to filter > PFN than before. > > Enable it in devicetree - (Add "riscv,svpbmt" in the mmu of cpu node) > - mmu: > riscv,svpmbt > I noticed that this series goes up to v4 but changes history is missing. Will you add it? > Wei Fu (2): > dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt > riscv: add RISC-V Svpbmt extension supports > > .../devicetree/bindings/riscv/cpus.yaml | 10 +++++ > arch/riscv/include/asm/fixmap.h | 2 +- > arch/riscv/include/asm/pgtable-64.h | 21 ++++++++-- > arch/riscv/include/asm/pgtable-bits.h | 39 ++++++++++++++++++- > arch/riscv/include/asm/pgtable.h | 39 ++++++++++++++----- > arch/riscv/kernel/cpufeature.c | 35 +++++++++++++++++ > arch/riscv/mm/init.c | 5 +++ > 7 files changed, 136 insertions(+), 15 deletions(-) >
next prev parent reply other threads:[~2021-11-29 13:40 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-29 1:40 [PATCH V4 0/2] riscv: add RISC-V Svpbmt Standard Extension supports wefu 2021-11-29 1:40 ` wefu 2021-11-29 1:40 ` [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt wefu 2021-11-29 1:40 ` wefu 2021-11-29 8:54 ` Heinrich Schuchardt 2021-11-29 8:54 ` Heinrich Schuchardt 2021-11-29 12:06 ` Heiko Stübner 2021-11-29 12:06 ` Heiko Stübner 2021-11-30 12:07 ` Heiko Stübner 2021-11-30 12:07 ` Heiko Stübner 2021-11-30 13:17 ` Jessica Clarke 2021-11-30 13:17 ` Jessica Clarke 2021-11-30 13:27 ` Heiko Stübner 2021-11-30 13:27 ` Heiko Stübner 2021-11-30 13:59 ` Jessica Clarke 2021-11-30 13:59 ` Jessica Clarke 2021-11-30 15:01 ` Philipp Tomsich 2021-11-30 15:01 ` Philipp Tomsich 2021-11-30 16:12 ` Jessica Clarke 2021-11-30 16:12 ` Jessica Clarke 2021-12-01 1:21 ` Atish Patra 2021-12-01 1:21 ` Atish Patra 2021-12-01 3:06 ` Tsukasa OI 2021-12-01 3:06 ` Tsukasa OI 2021-12-01 8:15 ` Atish Patra 2021-12-01 8:15 ` Atish Patra 2021-12-01 8:30 ` Heiko Stübner 2021-12-01 8:30 ` Heiko Stübner [not found] ` <CAELrHRDb9oeu_FokyhUFQ+Yu27=4xqvPdz4=08MXQzh3Bj2Myw@mail.gmail.com> 2021-12-01 10:20 ` Heiko Stübner 2021-12-01 10:20 ` Heiko Stübner 2021-12-01 11:05 ` Philipp Tomsich 2021-12-01 11:05 ` Philipp Tomsich 2021-12-01 13:39 ` Jessica Clarke 2021-12-01 13:39 ` Jessica Clarke 2021-12-02 1:31 ` Tsukasa OI 2021-12-02 1:31 ` Tsukasa OI 2021-12-02 1:55 ` Atish Patra 2021-12-02 1:55 ` Atish Patra 2021-12-01 13:28 ` Heiko Stübner 2021-12-01 13:28 ` Heiko Stübner 2021-12-02 1:59 ` Atish Patra 2021-12-02 1:59 ` Atish Patra 2021-11-30 18:45 ` Heiko Stübner 2021-11-30 18:45 ` Heiko Stübner 2021-12-01 2:58 ` Wei Fu 2021-12-01 2:58 ` Wei Fu 2021-11-29 1:40 ` [PATCH V4 2/2] riscv: add RISC-V Svpbmt extension supports wefu 2021-11-29 1:40 ` wefu 2021-11-29 3:57 ` kernel test robot 2021-11-29 4:17 ` kernel test robot 2021-11-29 10:48 ` Alexandre Ghiti 2021-11-29 10:48 ` Alexandre Ghiti 2021-11-29 13:36 ` Jisheng Zhang 2021-11-29 13:36 ` Jisheng Zhang 2021-12-01 5:05 ` Wei Fu 2021-12-01 5:05 ` Wei Fu 2021-12-01 6:18 ` Anup Patel 2021-12-01 6:18 ` Anup Patel 2021-12-01 13:29 ` Jisheng Zhang 2021-12-01 13:29 ` Jisheng Zhang 2021-12-03 9:12 ` Wei Fu 2021-12-03 9:12 ` Wei Fu 2021-11-30 10:18 ` Guo Ren 2021-11-30 10:18 ` Guo Ren 2021-12-01 3:03 ` Wei Fu 2021-12-01 3:03 ` Wei Fu 2021-11-30 18:46 ` Heiko Stübner 2021-11-30 18:46 ` Heiko Stübner 2021-12-01 3:00 ` Wei Fu 2021-12-01 3:00 ` Wei Fu 2021-11-29 13:33 ` Jisheng Zhang [this message] 2021-11-29 13:33 ` [PATCH V4 0/2] riscv: add RISC-V Svpbmt Standard Extension supports Jisheng Zhang
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