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From: "Stefan Mätje" <stefan.maetje@esd.eu>
To: Jagan Teki <jagan@amarulasolutions.com>, u-boot@lists.denx.de
Cc: "Tom Rini" <trini@konsulko.com>, "Stefan Mätje" <stefan.maetje@esd.eu>
Subject: [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372
Date: Tue, 30 Nov 2021 01:06:56 +0100	[thread overview]
Message-ID: <20211130000656.1837826-2-stefan.maetje@esd.eu> (raw)
In-Reply-To: <20211130000656.1837826-1-stefan.maetje@esd.eu>

On AM4372 the SPI_GCLK input gets its clock from the PRCM module which
divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4.
See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration.

The QSPI_FCLK therefore needs to take this factor into account and
becomes (192000000 / 4).

Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
---
 drivers/spi/ti_qspi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 664b9cad79..bccdeeaf82 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* ti qpsi register bit masks */
 #define QSPI_TIMEOUT                    2000000
-#define QSPI_FCLK			192000000
+/* AM4372: QSPI gets SPI_GCLK from PRCM unit as PER_CLKOUTM2 divided by 4. */
+#define QSPI_FCLK                       (192000000 / 4)
 #define QSPI_DRA7XX_FCLK                76800000
 #define QSPI_WLEN_MAX_BITS		128
 #define QSPI_WLEN_MAX_BYTES		(QSPI_WLEN_MAX_BITS >> 3)
-- 
2.25.1


  reply	other threads:[~2021-11-30 13:33 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-30  0:06 [PATCH 0/1] Provide a fix for wrong QSPI clock calculation on AM4372 Stefan Mätje
2021-11-30  0:06 ` Stefan Mätje [this message]
2021-11-30  3:58   ` [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372 Tom Rini
2021-11-30 12:14     ` Stefan Mätje
2021-11-30 12:51       ` Tom Rini
2022-01-17 18:36   ` Tom Rini

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