Re: [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372

From: Tom Rini <trini@konsulko.com>
To: "Stefan Mätje" <stefan.maetje@esd.eu>
Cc: Jagan Teki <jagan@amarulasolutions.com>, u-boot@lists.denx.de
Subject: Re: [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372
Date: Mon, 29 Nov 2021 22:58:41 -0500	[thread overview]
Message-ID: <20211130035841.GV24579@bill-the-cat> (raw)
In-Reply-To: <20211130000656.1837826-2-stefan.maetje@esd.eu>

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On Tue, Nov 30, 2021 at 01:06:56AM +0100, Stefan Mätje wrote:

> On AM4372 the SPI_GCLK input gets its clock from the PRCM module which
> divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4.
> See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration.
> 
> The QSPI_FCLK therefore needs to take this factor into account and
> becomes (192000000 / 4).
> 
> Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
> ---
>  drivers/spi/ti_qspi.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> index 664b9cad79..bccdeeaf82 100644
> --- a/drivers/spi/ti_qspi.c
> +++ b/drivers/spi/ti_qspi.c
> @@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR;
>  
>  /* ti qpsi register bit masks */
>  #define QSPI_TIMEOUT                    2000000
> -#define QSPI_FCLK			192000000
> +/* AM4372: QSPI gets SPI_GCLK from PRCM unit as PER_CLKOUTM2 divided by 4. */
> +#define QSPI_FCLK                       (192000000 / 4)
>  #define QSPI_DRA7XX_FCLK                76800000
>  #define QSPI_WLEN_MAX_BITS		128
>  #define QSPI_WLEN_MAX_BYTES		(QSPI_WLEN_MAX_BITS >> 3)

How is this treated in the kernel?  Thanks.

-- 
Tom

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