From: Nancy.Lin <nancy.lin@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
"Nancy . Lin" <nancy.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<singo.chang@mediatek.com>, <srv_heupstream@mediatek.com>
Subject: [PATCH v9 09/22] soc: mediatek: change the mutex defines and the mutex_mod type
Date: Tue, 30 Nov 2021 11:35:06 +0800 [thread overview]
Message-ID: <20211130033519.26086-10-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20211130033519.26086-1-nancy.lin@mediatek.com>
This is a preparation for adding support for mt8195 vdosys1 mutex.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 242 +++++++++++++++----------------
1 file changed, 121 insertions(+), 121 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 36502b27fe20..ff2f74668e8a 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,113 +29,113 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8192_MUTEX_MOD_DISP_OVL0 0
-#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
-#define MT8192_MUTEX_MOD_DISP_RDMA0 2
-#define MT8192_MUTEX_MOD_DISP_COLOR0 4
-#define MT8192_MUTEX_MOD_DISP_CCORR0 5
-#define MT8192_MUTEX_MOD_DISP_AAL0 6
-#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
-#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
-#define MT8192_MUTEX_MOD_DISP_DITHER0 9
-#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
-#define MT8192_MUTEX_MOD_DISP_RDMA4 17
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8192_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L BIT(1)
+#define MT8192_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8192_MUTEX_MOD_DISP_COLOR0 BIT(4)
+#define MT8192_MUTEX_MOD_DISP_CCORR0 BIT(5)
+#define MT8192_MUTEX_MOD_DISP_AAL0 BIT(6)
+#define MT8192_MUTEX_MOD_DISP_GAMMA0 BIT(7)
+#define MT8192_MUTEX_MOD_DISP_POSTMASK0 BIT(8)
+#define MT8192_MUTEX_MOD_DISP_DITHER0 BIT(9)
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L BIT(16)
+#define MT8192_MUTEX_MOD_DISP_RDMA4 BIT(17)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -183,7 +183,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -198,7 +198,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -207,7 +207,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -227,7 +227,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -242,7 +242,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -260,7 +260,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -274,7 +274,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
@@ -288,7 +288,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -467,16 +467,16 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
sof_id = MUTEX_SOF_DP_INTF0;
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -512,16 +512,16 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Nancy.Lin <nancy.lin@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
srv_heupstream@mediatek.com, devicetree@vger.kernel.org,
David Airlie <airlied@linux.ie>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
singo.chang@mediatek.com, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
"Nancy . Lin" <nancy.lin@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v9 09/22] soc: mediatek: change the mutex defines and the mutex_mod type
Date: Tue, 30 Nov 2021 11:35:06 +0800 [thread overview]
Message-ID: <20211130033519.26086-10-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20211130033519.26086-1-nancy.lin@mediatek.com>
This is a preparation for adding support for mt8195 vdosys1 mutex.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 242 +++++++++++++++----------------
1 file changed, 121 insertions(+), 121 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 36502b27fe20..ff2f74668e8a 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,113 +29,113 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8192_MUTEX_MOD_DISP_OVL0 0
-#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
-#define MT8192_MUTEX_MOD_DISP_RDMA0 2
-#define MT8192_MUTEX_MOD_DISP_COLOR0 4
-#define MT8192_MUTEX_MOD_DISP_CCORR0 5
-#define MT8192_MUTEX_MOD_DISP_AAL0 6
-#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
-#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
-#define MT8192_MUTEX_MOD_DISP_DITHER0 9
-#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
-#define MT8192_MUTEX_MOD_DISP_RDMA4 17
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8192_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L BIT(1)
+#define MT8192_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8192_MUTEX_MOD_DISP_COLOR0 BIT(4)
+#define MT8192_MUTEX_MOD_DISP_CCORR0 BIT(5)
+#define MT8192_MUTEX_MOD_DISP_AAL0 BIT(6)
+#define MT8192_MUTEX_MOD_DISP_GAMMA0 BIT(7)
+#define MT8192_MUTEX_MOD_DISP_POSTMASK0 BIT(8)
+#define MT8192_MUTEX_MOD_DISP_DITHER0 BIT(9)
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L BIT(16)
+#define MT8192_MUTEX_MOD_DISP_RDMA4 BIT(17)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -183,7 +183,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -198,7 +198,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -207,7 +207,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -227,7 +227,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -242,7 +242,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -260,7 +260,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -274,7 +274,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
@@ -288,7 +288,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -467,16 +467,16 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
sof_id = MUTEX_SOF_DP_INTF0;
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -512,16 +512,16 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Nancy.Lin <nancy.lin@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
"Nancy . Lin" <nancy.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<singo.chang@mediatek.com>, <srv_heupstream@mediatek.com>
Subject: [PATCH v9 09/22] soc: mediatek: change the mutex defines and the mutex_mod type
Date: Tue, 30 Nov 2021 11:35:06 +0800 [thread overview]
Message-ID: <20211130033519.26086-10-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20211130033519.26086-1-nancy.lin@mediatek.com>
This is a preparation for adding support for mt8195 vdosys1 mutex.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 242 +++++++++++++++----------------
1 file changed, 121 insertions(+), 121 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 36502b27fe20..ff2f74668e8a 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,113 +29,113 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8192_MUTEX_MOD_DISP_OVL0 0
-#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
-#define MT8192_MUTEX_MOD_DISP_RDMA0 2
-#define MT8192_MUTEX_MOD_DISP_COLOR0 4
-#define MT8192_MUTEX_MOD_DISP_CCORR0 5
-#define MT8192_MUTEX_MOD_DISP_AAL0 6
-#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
-#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
-#define MT8192_MUTEX_MOD_DISP_DITHER0 9
-#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
-#define MT8192_MUTEX_MOD_DISP_RDMA4 17
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8192_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L BIT(1)
+#define MT8192_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8192_MUTEX_MOD_DISP_COLOR0 BIT(4)
+#define MT8192_MUTEX_MOD_DISP_CCORR0 BIT(5)
+#define MT8192_MUTEX_MOD_DISP_AAL0 BIT(6)
+#define MT8192_MUTEX_MOD_DISP_GAMMA0 BIT(7)
+#define MT8192_MUTEX_MOD_DISP_POSTMASK0 BIT(8)
+#define MT8192_MUTEX_MOD_DISP_DITHER0 BIT(9)
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L BIT(16)
+#define MT8192_MUTEX_MOD_DISP_RDMA4 BIT(17)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -183,7 +183,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -198,7 +198,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -207,7 +207,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -227,7 +227,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -242,7 +242,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -260,7 +260,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -274,7 +274,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
@@ -288,7 +288,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -467,16 +467,16 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
sof_id = MUTEX_SOF_DP_INTF0;
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -512,16 +512,16 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-11-30 3:36 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 3:34 [PATCH v9 00/22] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-11-30 3:34 ` Nancy.Lin
2021-11-30 3:34 ` Nancy.Lin
2021-11-30 3:34 ` [PATCH v9 01/22] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2021-11-30 3:34 ` Nancy.Lin
2021-11-30 3:34 ` Nancy.Lin
2021-11-30 3:34 ` [PATCH v9 02/22] dt-bindings: mediatek: add vdosys1 MERGE property " Nancy.Lin
2021-11-30 3:34 ` Nancy.Lin
2021-11-30 3:34 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 03/22] dt-bindings: mediatek: add ethdr definition " Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 04/22] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 05/22] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 06/22] soc: mediatek: add mtk-mmsys config API " Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 07/22] soc: mediatek: add cmdq support of " Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 08/22] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin [this message]
2021-11-30 3:35 ` [PATCH v9 09/22] soc: mediatek: change the mutex defines and the mutex_mod type Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 10/22] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 11/22] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 12/22] drm/mediatek: add display merge advance config API " Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 13/22] drm/mediatek: add display merge start/stop API for cmdq support Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 14/22] drm/mediatek: add display merge mute/unmute support for MT8195 Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 15/22] drm/mediatek: add display merge async reset control Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 16/22] drm/mediatek: add ETHDR support for MT8195 Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 9:46 ` Philipp Zabel
2021-11-30 9:46 ` Philipp Zabel
2021-11-30 9:46 ` Philipp Zabel
2021-11-30 9:46 ` Philipp Zabel
2021-12-08 1:53 ` Nancy.Lin
2021-12-08 1:53 ` Nancy.Lin
2021-12-08 1:53 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 17/22] drm/mediatek: add mediatek-drm plane color encoding info Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 18/22] drm/mediatek: add ovl_adaptor support for MT8195 Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 19/22] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 20/22] drm/mediatek: add drm ovl_adaptor sub driver for MT8195 Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 21/22] drm/mediatek: add mediatek-drm of vdosys1 support " Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` [PATCH v9 22/22] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
2021-11-30 3:35 ` Nancy.Lin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211130033519.26086-10-nancy.lin@mediatek.com \
--to=nancy.lin@mediatek.com \
--cc=airlied@linux.ie \
--cc=chunkuang.hu@kernel.org \
--cc=ck.hu@mediatek.com \
--cc=daniel@ffwll.ch \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=jason-jh.lin@mediatek.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=singo.chang@mediatek.com \
--cc=srv_heupstream@mediatek.com \
--cc=yongqiang.niu@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.