[igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay

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* [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay
@ 2021-11-30  8:34 Stylon Wang
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 01/11] tests/amdgpu/amd_plane: Introduced 4K MPO test Stylon Wang
                   ` (13 more replies)
  0 siblings, 14 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:34 UTC (permalink / raw)
  To: igt-dev; +Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

A series of new tests on MPO is added to tests/amdgpu/amd_plane.

Currently most of the sub-tests are AMD-specific and concerns with
video use cases from projects.

Ahmad Othman (1):
  tests/amdgpu/amd_plane: fixes for test-4k-mpo

Anson Jacob (1):
  tests/amdgpu/amd_plane: Ensure pipes are enabled before accessing

Bhawanpreet Lakha (4):
  tests/amdgpu/amd_plane: Create mpo panning test
  tests/amdgpu/amd_plane: Create mpo swap between 2 displays test
  tests/amdgpu/amd_plane: Create mpo scaling tests
  tests/amdgpu/amd_plane: Add full screen scaling test case

Nicholas Kazlauskas (1):
  tests/amdgpu/amd_plane: Add MPO swizzle mode toggle test

Stylon Wang (1):
  tests/amdgpu/amd_plane: Add P010 format to MPO tests and add test
    descriptions

Victor Lu (3):
  tests/amdgpu/amd_plane: Introduced 4K MPO test
  tests/amdgpu/amd_plane: Switch mpo-swizzle-toggle to single-head
  tests/amdgpu/amd_plane: Add MPO scale and pan subtest single display
    option

 tests/amdgpu/amd_plane.c | 805 +++++++++++++++++++++++++++++++++++++++
 tests/amdgpu/meson.build |   1 +
 2 files changed, 806 insertions(+)
 create mode 100644 tests/amdgpu/amd_plane.c

-- 
2.33.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t 01/11] tests/amdgpu/amd_plane: Introduced 4K MPO test
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
@ 2021-11-30  8:34 ` Stylon Wang
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 02/11] tests/amdgpu/amd_plane: Add MPO swizzle mode toggle test Stylon Wang
                   ` (12 subsequent siblings)
  13 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:34 UTC (permalink / raw)
  To: igt-dev
  Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad.Othman, Victor Lu,
	Hayden.Goodfellow

From: Victor Lu <victorchengchi.lu@amd.com>

Tests MPO using a primary plane and an overlay plane with a transparent
cutout.

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
---
 tests/amdgpu/amd_plane.c | 158 +++++++++++++++++++++++++++++++++++++++
 tests/amdgpu/meson.build |   1 +
 2 files changed, 159 insertions(+)
 create mode 100644 tests/amdgpu/amd_plane.c

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
new file mode 100644
index 00000000..64273330
--- /dev/null
+++ b/tests/amdgpu/amd_plane.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+
+/* Common test data. */
+typedef struct data {
+	igt_display_t display;
+	igt_plane_t *primary;
+	igt_plane_t *overlay;
+	igt_output_t *output;
+	igt_pipe_t *pipe;
+	igt_pipe_crc_t *pipe_crc;
+	drmModeModeInfo *mode;
+	enum pipe pipe_id;
+	int fd;
+	int w;
+	int h;
+} data_t;
+
+static void test_init(data_t *data)
+{
+	igt_display_t *display = &data->display;
+
+	/* It doesn't matter which pipe we choose on amdpgu. */
+	data->pipe_id = PIPE_A;
+	data->pipe = &data->display.pipes[data->pipe_id];
+
+	igt_display_reset(display);
+
+	data->output = igt_get_single_output_for_pipe(display, data->pipe_id);
+	igt_require(data->output);
+
+	data->mode = igt_output_get_mode(data->output);
+	igt_assert(data->mode);
+
+	data->primary =
+		igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_PRIMARY);
+	data->overlay =
+		igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_OVERLAY);
+
+	data->pipe_crc = igt_pipe_crc_new(data->fd, data->pipe_id,
+					  INTEL_PIPE_CRC_SOURCE_AUTO);
+
+	igt_output_set_pipe(data->output, data->pipe_id);
+
+	data->w = data->mode->hdisplay;
+	data->h = data->mode->vdisplay;
+}
+
+static void test_fini(data_t *data)
+{
+	igt_pipe_crc_free(data->pipe_crc);
+	igt_display_reset(&data->display);
+}
+
+static void draw_color_alpha(igt_fb_t *fb, int x, int y, int w, int h,
+		             double r, double g, double b, double a)
+{
+	cairo_t *cr = igt_get_cairo_ctx(fb->fd, fb);
+	igt_paint_color_alpha(cr, x, y, w, h, r, g, b, a);
+	igt_put_cairo_ctx(cr);
+}
+
+/*
+ * Compares a white 4K reference FB against a white 4K primary FB and a
+ * white 4K overlay with an RGBA (0, 0, 0, 0) cutout in the center.
+ */
+static void test_mpo_4k(data_t *data)
+{
+	igt_fb_t r_fb, p_fb, o_fb;
+	igt_crc_t ref_crc, new_crc;
+	igt_display_t *display = &data->display;
+	int cutout_x, cutout_y, cutout_w, cutout_h;
+
+	test_init(data);
+
+	/* Skip if not 4K resolution. */
+	igt_skip_on(!(data->mode->hdisplay == 3840 &&
+		    data->mode->vdisplay == 2160));
+
+	cutout_x = cutout_w = 1280;
+	cutout_y = cutout_h = 720;
+
+	igt_create_color_fb(data->fd, data->w, data->h, DRM_FORMAT_XRGB8888,
+			    0, 1.00, 1.00, 1.00, &r_fb);
+	igt_create_color_fb(data->fd, data->w, data->h, DRM_FORMAT_XRGB8888,
+			    0, 1.00, 1.00, 1.00, &p_fb);
+	igt_create_fb(data->fd, data->w, data->h, DRM_FORMAT_ARGB8888,
+		      0, &o_fb);
+	draw_color_alpha(&o_fb, 0, 0, o_fb.width, o_fb.height, 1.00, 1.00, 1.00, 1.00);
+	draw_color_alpha(&o_fb, cutout_x, cutout_y, cutout_w, cutout_h,
+			 0.00, 0.00, 0.00, 0.00);
+
+	igt_plane_set_fb(data->primary, &r_fb);
+	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+	igt_pipe_crc_collect_crc(data->pipe_crc, &ref_crc);
+
+	igt_plane_set_fb(data->primary, &p_fb);
+	igt_plane_set_fb(data->overlay, &o_fb);
+	igt_display_commit_atomic(display, 0, NULL);
+
+	igt_pipe_crc_collect_crc(data->pipe_crc, &new_crc);
+
+	igt_assert_crc_equal(&ref_crc, &new_crc);
+
+	test_fini(data);
+	igt_remove_fb(data->fd, &o_fb);
+	igt_remove_fb(data->fd, &p_fb);
+	igt_remove_fb(data->fd, &r_fb);
+}
+
+igt_main
+{
+	data_t data;
+
+	igt_skip_on_simulation();
+
+	memset(&data, 0, sizeof(data));
+
+	igt_fixture
+	{
+		data.fd = drm_open_driver_master(DRIVER_AMDGPU);
+
+		kmstest_set_vt_graphics_mode();
+
+		igt_display_require(&data.display, data.fd);
+		igt_require(data.display.is_atomic);
+		igt_display_require_output(&data.display);
+	}
+
+	igt_subtest("test-mpo-4k") test_mpo_4k(&data);
+
+	igt_fixture
+	{
+		igt_display_fini(&data.display);
+	}
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index b736c456..e1e342f7 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -16,6 +16,7 @@ if libdrm_amdgpu.found()
 			  'amd_mem_leak',
 			  'amd_link_settings',
 			  'amd_vrr_range',
+			  'amd_plane',
 			]
 	amdgpu_deps += libdrm_amdgpu
 endif
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t 02/11] tests/amdgpu/amd_plane: Add MPO swizzle mode toggle test
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 01/11] tests/amdgpu/amd_plane: Introduced 4K MPO test Stylon Wang
@ 2021-11-30  8:34 ` Stylon Wang
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 03/11] tests/amdgpu/amd_plane: fixes for test-4k-mpo Stylon Wang
                   ` (11 subsequent siblings)
  13 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:34 UTC (permalink / raw)
  To: igt-dev; +Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Sequence captured on ChromeOS - we experience underflow when toggling
between swizzle modes on the primary plane with MPO enabled.

Add a new subtest replicating that sequence, "mpo-swizzle-toggle".

Converts the existing framework over to the new multi-display framework
since that's the configuration where this was found.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 tests/amdgpu/amd_plane.c | 260 ++++++++++++++++++++++++++++++++-------
 1 file changed, 217 insertions(+), 43 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 64273330..09fd3b08 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -21,56 +21,153 @@
  */
 
 #include "igt.h"
+#include "libdrm/amdgpu.h"
+#include "libdrm/amdgpu_drm.h"
+
+/* Maximum pipes on any AMD ASIC. */
+#define MAX_PIPES 6
 
 /* Common test data. */
 typedef struct data {
-	igt_display_t display;
-	igt_plane_t *primary;
-	igt_plane_t *overlay;
-	igt_output_t *output;
-	igt_pipe_t *pipe;
-	igt_pipe_crc_t *pipe_crc;
-	drmModeModeInfo *mode;
-	enum pipe pipe_id;
-	int fd;
-	int w;
-	int h;
+        igt_display_t display;
+        igt_plane_t *primary[MAX_PIPES];
+        igt_plane_t *cursor[MAX_PIPES];
+	igt_plane_t *overlay[MAX_PIPES];
+        igt_output_t *output[MAX_PIPES];
+        igt_pipe_t *pipe[MAX_PIPES];
+        igt_pipe_crc_t *pipe_crc[MAX_PIPES];
+        drmModeModeInfo mode[MAX_PIPES];
+        enum pipe pipe_id[MAX_PIPES];
+        int w[MAX_PIPES];
+        int h[MAX_PIPES];
+        int fd;
 } data_t;
 
+static const drmModeModeInfo test_mode_1 = {
+	.name = "1920x1080 Test",
+	.vrefresh = 60,
+	.clock = 148500,
+	.hdisplay = 1920,
+	.hsync_start = 2008,
+	.hsync_end = 2052,
+	.htotal = 2200,
+	.vdisplay = 1080,
+	.vsync_start = 1084,
+	.vsync_end = 1089,
+	.vtotal = 1125,
+	.type = 0x40,
+	.flags = DRM_MODE_FLAG_NHSYNC,
+	.hskew = 0,
+	.vscan = 0,
+};
+
+static const drmModeModeInfo test_mode_2 = {
+	.name = "1280x1024 Test",
+	.vrefresh = 60,
+	.clock = 148500,
+	.hdisplay = 1280,
+	.hsync_start = 2008,
+	.hsync_end = 2052,
+	.htotal = 2200,
+	.vdisplay = 1024,
+	.vsync_start = 1084,
+	.vsync_end = 1089,
+	.vtotal = 1125,
+	.type = DRM_MODE_TYPE_DRIVER,
+	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+	.hskew = 0,
+	.vscan = 0,
+};
+
 static void test_init(data_t *data)
 {
 	igt_display_t *display = &data->display;
+	int i, n, max_pipes = display->n_pipes;
+
+	for (i = 0; i < max_pipes; ++i) {
+		data->pipe_id[i] = PIPE_A + i;
+		data->pipe[i] = &data->display.pipes[data->pipe_id[i]];
+		data->primary[i] = igt_pipe_get_plane_type(
+			data->pipe[i], DRM_PLANE_TYPE_PRIMARY);
+		data->overlay[i] = igt_pipe_get_plane_type_index(
+			data->pipe[i], DRM_PLANE_TYPE_OVERLAY, 0);
+		data->cursor[i] = igt_pipe_get_plane_type(
+			data->pipe[i], DRM_PLANE_TYPE_CURSOR);
+		data->pipe_crc[i] =
+			igt_pipe_crc_new(data->fd, data->pipe_id[i], "auto");
+	}
+
+	for (i = 0, n = 0; i < display->n_outputs && n < max_pipes; ++i) {
+		igt_output_t *output = &display->outputs[i];
+
+		data->output[n] = output;
+
+		/* Only allow physically connected displays for the tests. */
+		if (!igt_output_is_connected(output))
+			continue;
 
-	/* It doesn't matter which pipe we choose on amdpgu. */
-	data->pipe_id = PIPE_A;
-	data->pipe = &data->display.pipes[data->pipe_id];
+		igt_assert(kmstest_get_connector_default_mode(
+			data->fd, output->config.connector, &data->mode[n]));
 
+		data->w[n] = data->mode[n].hdisplay;
+		data->h[n] = data->mode[n].vdisplay;
+
+		n += 1;
+	}
+
+	igt_require(data->output[0]);
 	igt_display_reset(display);
+}
 
-	data->output = igt_get_single_output_for_pipe(display, data->pipe_id);
-	igt_require(data->output);
+static void test_fini(data_t *data)
+{
+	igt_display_t *display = &data->display;
+	int i, max_pipes = display->n_pipes;
 
-	data->mode = igt_output_get_mode(data->output);
-	igt_assert(data->mode);
+	for (i = 0; i < max_pipes; ++i) {
+		igt_pipe_crc_free(data->pipe_crc[i]);
+	}
 
-	data->primary =
-		igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_PRIMARY);
-	data->overlay =
-		igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_OVERLAY);
+	igt_display_reset(display);
+	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+}
 
-	data->pipe_crc = igt_pipe_crc_new(data->fd, data->pipe_id,
-					  INTEL_PIPE_CRC_SOURCE_AUTO);
+/* Forces a mode for a connector. */
+static void force_output_mode(data_t *data, igt_output_t *output,
+			      drmModeModeInfo const *mode)
+{
+	/* This allows us to create a virtual sink. */
+	if (!igt_output_is_connected(output)) {
+		kmstest_force_edid(data->fd, output->config.connector,
+				   igt_kms_get_4k_edid());
 
-	igt_output_set_pipe(data->output, data->pipe_id);
+		kmstest_force_connector(data->fd, output->config.connector,
+					FORCE_CONNECTOR_DIGITAL);
+	}
 
-	data->w = data->mode->hdisplay;
-	data->h = data->mode->vdisplay;
+	igt_output_override_mode(output, mode);
 }
 
-static void test_fini(data_t *data)
+
+static int set_metadata(data_t *data, igt_fb_t *fb, struct amdgpu_bo_metadata *info)
 {
-	igt_pipe_crc_free(data->pipe_crc);
-	igt_display_reset(&data->display);
+	struct drm_amdgpu_gem_metadata args = {};
+
+	args.handle = fb->gem_handle;
+	args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
+	args.data.flags = info->flags;
+	args.data.tiling_info = info->tiling_info;
+
+	if (info->size_metadata > sizeof(args.data.data))
+		return -EINVAL;
+
+	if (info->size_metadata) {
+		args.data.data_size_bytes = info->size_metadata;
+		memcpy(args.data.data, info->umd_metadata, info->size_metadata);
+	}
+
+	return drmCommandWriteRead(data->fd, DRM_AMDGPU_GEM_METADATA, &args,
+				   sizeof(args));
 }
 
 static void draw_color_alpha(igt_fb_t *fb, int x, int y, int w, int h,
@@ -91,36 +188,38 @@ static void test_mpo_4k(data_t *data)
 	igt_crc_t ref_crc, new_crc;
 	igt_display_t *display = &data->display;
 	int cutout_x, cutout_y, cutout_w, cutout_h;
+	int w, h;
 
 	test_init(data);
 
 	/* Skip if not 4K resolution. */
-	igt_skip_on(!(data->mode->hdisplay == 3840 &&
-		    data->mode->vdisplay == 2160));
+	igt_skip_on(!(data->mode[0].hdisplay == 3840
+		      && data->mode[0].vdisplay == 2160));
 
+	w = data->w[0];
+	h = data->h[0];
 	cutout_x = cutout_w = 1280;
 	cutout_y = cutout_h = 720;
 
-	igt_create_color_fb(data->fd, data->w, data->h, DRM_FORMAT_XRGB8888,
-			    0, 1.00, 1.00, 1.00, &r_fb);
-	igt_create_color_fb(data->fd, data->w, data->h, DRM_FORMAT_XRGB8888,
-			    0, 1.00, 1.00, 1.00, &p_fb);
-	igt_create_fb(data->fd, data->w, data->h, DRM_FORMAT_ARGB8888,
-		      0, &o_fb);
+	igt_create_color_fb(data->fd, w, h, DRM_FORMAT_XRGB8888, 0, 1.00, 1.00,
+			    1.00, &r_fb);
+	igt_create_color_fb(data->fd, w, h, DRM_FORMAT_XRGB8888, 0, 1.00, 1.00,
+			    1.00, &p_fb);
+	igt_create_fb(data->fd, w, h, DRM_FORMAT_ARGB8888, 0, &o_fb);
 	draw_color_alpha(&o_fb, 0, 0, o_fb.width, o_fb.height, 1.00, 1.00, 1.00, 1.00);
 	draw_color_alpha(&o_fb, cutout_x, cutout_y, cutout_w, cutout_h,
 			 0.00, 0.00, 0.00, 0.00);
 
-	igt_plane_set_fb(data->primary, &r_fb);
+	igt_plane_set_fb(data->primary[0], &r_fb);
 	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
 
-	igt_pipe_crc_collect_crc(data->pipe_crc, &ref_crc);
+	igt_pipe_crc_collect_crc(data->pipe_crc[0], &ref_crc);
 
-	igt_plane_set_fb(data->primary, &p_fb);
-	igt_plane_set_fb(data->overlay, &o_fb);
+	igt_plane_set_fb(data->primary[0], &p_fb);
+	igt_plane_set_fb(data->overlay[0], &o_fb);
 	igt_display_commit_atomic(display, 0, NULL);
 
-	igt_pipe_crc_collect_crc(data->pipe_crc, &new_crc);
+	igt_pipe_crc_collect_crc(data->pipe_crc[0], &new_crc);
 
 	igt_assert_crc_equal(&ref_crc, &new_crc);
 
@@ -130,6 +229,80 @@ static void test_mpo_4k(data_t *data)
 	igt_remove_fb(data->fd, &r_fb);
 }
 
+static void test_mpo_swizzle_toggle(data_t *data)
+{
+	struct amdgpu_bo_metadata meta = {};
+	igt_display_t *display = &data->display;
+	igt_fb_t fb_1280_xr24_tiled, fb_1280_ar24_tiled, fb_1920_xb24_tiled,
+		fb_1920_xb24_linear, fb_1920_xr24_tiled;
+	int w, h;
+
+	w = 2400;
+	h = 1350;
+
+	igt_create_pattern_fb(data->fd, 1280, 1024, DRM_FORMAT_XRGB8888, 0,
+			      &fb_1280_xr24_tiled);
+	igt_create_pattern_fb(data->fd, 1280, 1024, DRM_FORMAT_ARGB8888, 0,
+			      &fb_1280_ar24_tiled);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XBGR8888, 0,
+			      &fb_1920_xb24_tiled);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XBGR8888, 0,
+			      &fb_1920_xb24_linear);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XRGB8888, 0,
+			      &fb_1920_xr24_tiled);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1280_xr24_tiled, &meta);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1280_ar24_tiled, &meta);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1920_xb24_tiled, &meta);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1920_xr24_tiled, &meta);
+
+	test_init(data);
+
+	/* Initial modeset */
+	igt_output_set_pipe(data->output[0], data->pipe_id[0]);
+	igt_output_set_pipe(data->output[1], data->pipe_id[1]);
+	force_output_mode(data, data->output[0], &test_mode_1);
+	force_output_mode(data, data->output[1], &test_mode_2);
+
+	igt_plane_set_fb(data->primary[0], &fb_1920_xr24_tiled);
+	igt_plane_set_fb(data->primary[1], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[1], w, h);
+
+	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+	/* Enable overlay plane. */
+	igt_plane_set_fb(data->overlay[1], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[1], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[1], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	/* Switch to tiled. */
+	igt_plane_set_fb(data->overlay[1], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[1], &fb_1920_xb24_tiled);
+	igt_plane_set_size(data->primary[1], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	/* Switch to linear. */
+	igt_plane_set_fb(data->overlay[1], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[1], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[1], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	test_fini(data);
+	igt_remove_fb(data->fd, &fb_1280_xr24_tiled);
+	igt_remove_fb(data->fd, &fb_1280_ar24_tiled);
+	igt_remove_fb(data->fd, &fb_1920_xb24_tiled);
+	igt_remove_fb(data->fd, &fb_1920_xb24_linear);
+	igt_remove_fb(data->fd, &fb_1920_xr24_tiled);
+}
+
 igt_main
 {
 	data_t data;
@@ -150,6 +323,7 @@ igt_main
 	}
 
 	igt_subtest("test-mpo-4k") test_mpo_4k(&data);
+	igt_subtest("mpo-swizzle-toggle") test_mpo_swizzle_toggle(&data);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t 03/11] tests/amdgpu/amd_plane: fixes for test-4k-mpo
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 01/11] tests/amdgpu/amd_plane: Introduced 4K MPO test Stylon Wang
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 02/11] tests/amdgpu/amd_plane: Add MPO swizzle mode toggle test Stylon Wang
@ 2021-11-30  8:34 ` Stylon Wang
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 04/11] tests/amdgpu/amd_plane: Switch mpo-swizzle-toggle to single-head Stylon Wang
                   ` (10 subsequent siblings)
  13 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:34 UTC (permalink / raw)
  To: igt-dev; +Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad Othman, Hayden.Goodfellow

From: Ahmad Othman <ahmad.othman@amd.com>

[Why]
The test wasn't working on some setups and needs fixing

[How]
Added output pipe initialization
Added checks for both 4k and 2160p

Signed-off-by: Ahmad Othman <ahmad.othman@amd.com>
---
 tests/amdgpu/amd_plane.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 09fd3b08..ba29bdd4 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -193,8 +193,10 @@ static void test_mpo_4k(data_t *data)
 	test_init(data);
 
 	/* Skip if not 4K resolution. */
-	igt_skip_on(!(data->mode[0].hdisplay == 3840
-		      && data->mode[0].vdisplay == 2160));
+	igt_skip_on(!((data->mode[0].hdisplay == 4096
+		      && data->mode[0].vdisplay == 2160)||
+		      (data->mode[0].hdisplay == 3840
+		      && data->mode[0].vdisplay == 2160)));
 
 	w = data->w[0];
 	h = data->h[0];
@@ -210,6 +212,7 @@ static void test_mpo_4k(data_t *data)
 	draw_color_alpha(&o_fb, cutout_x, cutout_y, cutout_w, cutout_h,
 			 0.00, 0.00, 0.00, 0.00);
 
+	igt_output_set_pipe(data->output[0], data->pipe_id[0]);
 	igt_plane_set_fb(data->primary[0], &r_fb);
 	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
 
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t 04/11] tests/amdgpu/amd_plane: Switch mpo-swizzle-toggle to single-head
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
                   ` (2 preceding siblings ...)
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 03/11] tests/amdgpu/amd_plane: fixes for test-4k-mpo Stylon Wang
@ 2021-11-30  8:34 ` Stylon Wang
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 05/11] tests/amdgpu/amd_plane: Create mpo panning test Stylon Wang
                   ` (9 subsequent siblings)
  13 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:34 UTC (permalink / raw)
  To: igt-dev
  Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad.Othman, Victor Lu,
	Hayden.Goodfellow

From: Victor Lu <victorchengchi.lu@amd.com>

[why]
Older ASIC does not support multi-head MPO

[how]
Rename current mpo-swizzle-toggle subtest to
mpo-swizzle-toggle-multihead. Change mpo-swizzle-toggle to only use one
output.

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
---
 tests/amdgpu/amd_plane.c | 70 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 69 insertions(+), 1 deletion(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index ba29bdd4..5666b9e7 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -232,7 +232,7 @@ static void test_mpo_4k(data_t *data)
 	igt_remove_fb(data->fd, &r_fb);
 }
 
-static void test_mpo_swizzle_toggle(data_t *data)
+static void test_mpo_swizzle_toggle_multihead(data_t *data)
 {
 	struct amdgpu_bo_metadata meta = {};
 	igt_display_t *display = &data->display;
@@ -306,6 +306,72 @@ static void test_mpo_swizzle_toggle(data_t *data)
 	igt_remove_fb(data->fd, &fb_1920_xr24_tiled);
 }
 
+static void test_mpo_swizzle_toggle(data_t *data)
+{
+	struct amdgpu_bo_metadata meta = {};
+	igt_display_t *display = &data->display;
+	igt_fb_t fb_1280_ar24_tiled, fb_1920_xb24_tiled, fb_1920_xb24_linear,
+		 fb_1920_xr24_tiled;
+	int w, h;
+
+	w = 2400;
+	h = 1350;
+
+	igt_create_pattern_fb(data->fd, 1280, 1024, DRM_FORMAT_ARGB8888, 0,
+			      &fb_1280_ar24_tiled);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XBGR8888, 0,
+			      &fb_1920_xb24_tiled);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XBGR8888, 0,
+			      &fb_1920_xb24_linear);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XRGB8888, 0,
+			      &fb_1920_xr24_tiled);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1280_ar24_tiled, &meta);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1920_xb24_tiled, &meta);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1920_xr24_tiled, &meta);
+
+	test_init(data);
+
+	/* Initial modeset */
+	igt_output_set_pipe(data->output[0], data->pipe_id[0]);
+	force_output_mode(data, data->output[0], &test_mode_1);
+
+	igt_plane_set_fb(data->primary[0], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[0], w, h);
+
+	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+	/* Enable overlay plane. */
+	igt_plane_set_fb(data->overlay[0], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[0], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[0], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	/* Switch to tiled. */
+	igt_plane_set_fb(data->overlay[0], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[0], &fb_1920_xb24_tiled);
+	igt_plane_set_size(data->primary[0], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	/* Switch to linear. */
+	igt_plane_set_fb(data->overlay[0], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[0], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[0], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	test_fini(data);
+	igt_remove_fb(data->fd, &fb_1280_ar24_tiled);
+	igt_remove_fb(data->fd, &fb_1920_xb24_tiled);
+	igt_remove_fb(data->fd, &fb_1920_xb24_linear);
+	igt_remove_fb(data->fd, &fb_1920_xr24_tiled);
+}
+
+
 igt_main
 {
 	data_t data;
@@ -327,6 +393,8 @@ igt_main
 
 	igt_subtest("test-mpo-4k") test_mpo_4k(&data);
 	igt_subtest("mpo-swizzle-toggle") test_mpo_swizzle_toggle(&data);
+	igt_subtest("mpo-swizzle-toggle-multihead")
+		test_mpo_swizzle_toggle_multihead(&data);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t 05/11] tests/amdgpu/amd_plane: Create mpo panning test
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
                   ` (3 preceding siblings ...)
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 04/11] tests/amdgpu/amd_plane: Switch mpo-swizzle-toggle to single-head Stylon Wang
@ 2021-11-30  8:34 ` Stylon Wang
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 06/11] tests/amdgpu/amd_plane: Create mpo swap between 2 displays test Stylon Wang
                   ` (8 subsequent siblings)
  13 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:34 UTC (permalink / raw)
  To: igt-dev; +Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

[Why]
Moving the MPO window is a common usecase (video window being moved).
This test creates a MPO window and moves it horizontally, vertically and
diagonally

[How]
Create common video resolution windows and move them across the
displays. Test pass is determined by getting a crc of window location
using a single plane, then recreating this scenario using overlay.

Test panes from Start->End1, Start->End2 and Start->End3

                  CRTC#1
    Start
    +--------+--------+--------+
    |Primary |  -->   |Primary | End1
    +--------+        +--------+
    |  |      \      Overlay   |
    |  v        *              |
    +--------+    \   +--------+
    |Primary |        |Primary | End2
    +--------+--------+--------+
     End3

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 tests/amdgpu/amd_plane.c | 261 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 261 insertions(+)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 5666b9e7..09fcf3eb 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -26,6 +26,13 @@
 
 /* Maximum pipes on any AMD ASIC. */
 #define MAX_PIPES 6
+#define DISPLAYS_TO_TEST 2
+
+/* (De)gamma LUT. */
+typedef struct lut {
+	struct drm_color_lut *data;
+	uint32_t size;
+} lut_t;
 
 /* Common test data. */
 typedef struct data {
@@ -79,6 +86,63 @@ static const drmModeModeInfo test_mode_2 = {
 	.vscan = 0,
 };
 
+static const drmModeModeInfo test_mode_3 = {
+	.name = "3840x2160 Test",
+	.vrefresh = 60,
+	.clock = 594000,
+	.hdisplay = 3840,
+	.hsync_start = 4016,
+	.hsync_end = 4104,
+	.htotal = 4400,
+	.vdisplay = 2160,
+	.vsync_start = 2168,
+	.vsync_end = 2178,
+	.vtotal = 2250,
+	.type = DRM_MODE_TYPE_DRIVER,
+	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+	.hskew = 0,
+	.vscan = 0,
+};
+
+static void lut_init(lut_t *lut, uint32_t size)
+{
+	igt_assert(size > 0);
+	lut->size = size;
+	lut->data = malloc(size * sizeof(struct drm_color_lut));
+	igt_assert(lut);
+}
+static void lut_gen(lut_t *lut)
+{
+	uint32_t i;
+	/* 10% threshold */
+	uint32_t threshold = (256 * 10) / 100;
+
+	for (i = 0; i < threshold; ++i) {
+		uint32_t v = 0;
+		lut->data[i].red = v;
+		lut->data[i].blue = v;
+		lut->data[i].green = v;
+	}
+	for (i = threshold; i < lut->size; ++i) {
+		uint32_t v = 0xffff;
+		lut->data[i].red = v;
+		lut->data[i].blue = v;
+		lut->data[i].green = v;
+	}
+}
+static void lut_free(lut_t *lut)
+{
+	if (lut->data) {
+		free(lut->data);
+		lut->data = NULL;
+	}
+	lut->size = 0;
+}
+
+enum test {
+	MPO_SINGLE_PAN
+};
+
 static void test_init(data_t *data)
 {
 	igt_display_t *display = &data->display;
@@ -174,10 +238,205 @@ static void draw_color_alpha(igt_fb_t *fb, int x, int y, int w, int h,
 		             double r, double g, double b, double a)
 {
 	cairo_t *cr = igt_get_cairo_ctx(fb->fd, fb);
+	cairo_set_operator(cr, CAIRO_OPERATOR_SOURCE);
 	igt_paint_color_alpha(cr, x, y, w, h, r, g, b, a);
 	igt_put_cairo_ctx(cr);
 }
 
+struct fbc {
+	igt_fb_t ref_primary;
+	igt_fb_t test_primary;
+	igt_fb_t test_overlay;
+	igt_crc_t ref_crc;
+};
+
+/* Sets the regamma LUT. */
+static void set_regamma_lut(data_t *data, lut_t const *lut, int n)
+{
+	size_t size = lut ? sizeof(lut->data) * lut->size : 0;
+	const void *ptr = lut ? lut->data : NULL;
+	igt_pipe_obj_replace_prop_blob(data->pipe[n], IGT_CRTC_GAMMA_LUT, ptr,
+				       size);
+}
+
+/*
+ * Compares the result of white backgroud with white window with and without MPO
+ *
+ * Reference crc:
+ * Draws a White background of size (pw,ph).
+ *
+ * Test crc:
+ * Draws a White Overlay of size (pw,ph) then creates a cutout of size (p,w) at location (x,y)
+ * Draws a White Primary plane of size (p,w) at location (x,y) (under the overlay)
+ *
+ * NOTE: The reason for using White+White is to speed up the crc (reuse the ref crc for all cases vs taking
+ * a ref crc per flip)
+ */
+static void test_plane(data_t *data, int n, int x, int y, int w, int h, int pw, int ph, struct fbc *fbc){
+
+	igt_crc_t test_crc;
+	igt_display_t *display = &data->display;
+
+	/* Reference: */
+
+	igt_plane_set_fb(data->primary[n], &fbc[n].ref_primary);
+
+	igt_plane_set_position(data->primary[n], 0, 0);
+	igt_plane_set_size(data->primary[n], pw, ph);
+
+	igt_display_commit_atomic(display, 0, 0);
+
+	/* Test: */
+	/* Draw a white overlay with a cutout */
+	draw_color_alpha(&fbc[n].test_overlay, 0, 0, pw, ph, 1.0, 1.0, 1.0, 1.00);
+	draw_color_alpha(&fbc[n].test_overlay, x, y, w, h, 0.0, 0.0, 0.0, 0.0);
+
+	igt_plane_set_fb(data->primary[n], &fbc[n].test_primary);
+	igt_plane_set_fb(data->overlay[n], &fbc[n].test_overlay);
+
+	/* Move the overlay to cover the cutout */
+	igt_plane_set_position(data->primary[n], x, y);
+	igt_plane_set_size(data->primary[n], w, h);
+
+	igt_display_commit_atomic(display, 0, 0);
+	igt_pipe_crc_collect_crc(data->pipe_crc[n], &test_crc);
+	igt_plane_set_fb(data->overlay[n], NULL);
+
+	igt_assert_crc_equal(&fbc[n].ref_crc, &test_crc);
+
+	/* Set window to white, this is to avoid flashing between black/white after each flip */
+	draw_color_alpha(&fbc[n].ref_primary, 0, 0, pw, ph, 1.0, 1.0, 1.0, 1.00);
+	igt_plane_set_fb(data->primary[n], &fbc[n].ref_primary);
+	igt_plane_set_position(data->primary[n], 0, 0);
+	igt_plane_set_size(data->primary[n], pw, ph);
+	igt_display_commit_atomic(display, 0, 0);
+
+
+}
+/*
+ * MPO_SINGLE_PAN: This test moves the window (w,h) horizontally, vertically and diagonally
+ * Horizontal: from top-left (0,0) to top-right (pw-w,0)
+ * Vertical: from top-left (0,0) to bottom-left (0,ph-h)
+ * Diagonal: from top-left (0,0) to bottom-right (pw-w, ph-h)
+ */
+static void test_panning_1_display(data_t *data, int display_count, int w, int h, struct fbc *fb)
+{
+	/* x and y movements */
+	int dir[3][2]= {
+		{0,1}, /* Only Y */
+		{1,0}, /* Only X */
+		{1,1}, /* Both X and Y */
+
+	};
+
+	/* # of iterations to use to move from one side to the other */
+	int it = 3;
+
+	for (int n = 0; n < display_count; n++) {
+
+		int pw = data->w[n];
+		int ph = data->h[n];
+		int dx = (pw-w)/it;
+		int dy = (ph-h)/it;
+
+		for (int i = 0; i < ARRAY_SIZE(dir); i++){
+			for (int j = 0; j <= it; j++){
+
+				int x = dx*j*dir[i][0];
+				int y = dy*j*dir[i][1];
+
+				/* No need to pan a overley that is bigger than the display */
+				if (pw <= w && ph <= h)
+					break;
+
+				test_plane(data, n, x, y, w, h, pw, ph, fb);
+
+			}
+		}
+	}
+
+	return;
+
+
+}
+
+
+/*
+ * Setup and runner for panning test. Creates common video sizes and pans them across the display
+ */
+static void test_display_mpo(data_t *data, enum test test, uint32_t format, int display_count)
+{
+
+	igt_display_t *display = &data->display;
+	uint32_t regamma_lut_size;
+	lut_t lut;
+	struct fbc fb[4];
+	int videos[][2]= {
+		{426, 240},
+		{640, 360},
+		{854, 480},
+		{1280, 720},
+		{1920, 1080},
+		{2560, 1440},
+		{3840, 2160},
+	};
+
+	test_init(data);
+
+	regamma_lut_size = igt_pipe_obj_get_prop(data->pipe[0], IGT_CRTC_GAMMA_LUT_SIZE);
+	igt_assert_lt(0, regamma_lut_size);
+	lut_init(&lut, regamma_lut_size);
+	lut_gen(&lut);
+
+	for (int n = 0; n < display_count;  n++) {
+		int w = data->w[n];
+		int h = data->h[n];
+
+		if (w == 0) {
+			force_output_mode(data, data->output[n], &test_mode_3);
+			w = data->w[n] = test_mode_3.hdisplay;
+			h = data->h[n] = test_mode_3.vdisplay;
+		}
+
+		igt_output_set_pipe(data->output[n], data->pipe_id[n]);
+
+		igt_create_fb(data->fd, w, h, DRM_FORMAT_XRGB8888, 0, &fb[n].ref_primary);
+		igt_create_color_fb(data->fd, w, h, DRM_FORMAT_XRGB8888, 0, 1.0, 1.0, 1.0, &fb[n].ref_primary);
+		igt_create_fb(data->fd, w, h, DRM_FORMAT_ARGB8888, 0, &fb[n].test_overlay);
+
+		igt_plane_set_fb(data->primary[n], &fb[n].ref_primary);
+
+		if (format == DRM_FORMAT_NV12)
+			set_regamma_lut(data, &lut,  n);
+	}
+
+	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+	for (int n = 0; n < display_count; n++)
+		igt_pipe_crc_collect_crc(data->pipe_crc[n], &fb[n].ref_crc);
+
+	for (int i = 0; i < ARRAY_SIZE(videos); ++i) {
+
+		for (int n = 0; n < display_count; n++)
+			igt_create_color_fb(data->fd, videos[i][0], videos[i][1],
+					    format, 0, 1.0, 1.0, 1.0, &fb[n].test_primary);
+
+		if (test == MPO_SINGLE_PAN)
+			test_panning_1_display(data, display_count, videos[i][0], videos[i][1], fb);
+
+		for (int n = 0; n < display_count; n++)
+			igt_remove_fb(data->fd, &fb[n].test_primary);
+	}
+
+	test_fini(data);
+
+	lut_free(&lut);
+
+	for (int n = 0; n < display_count; n++) {
+		igt_remove_fb(data->fd, &fb[n].ref_primary);
+		igt_remove_fb(data->fd, &fb[n].test_overlay);
+	}
+}
 /*
  * Compares a white 4K reference FB against a white 4K primary FB and a
  * white 4K overlay with an RGBA (0, 0, 0, 0) cutout in the center.
@@ -395,6 +654,8 @@ igt_main
 	igt_subtest("mpo-swizzle-toggle") test_mpo_swizzle_toggle(&data);
 	igt_subtest("mpo-swizzle-toggle-multihead")
 		test_mpo_swizzle_toggle_multihead(&data);
+	igt_subtest("mpo-pan-rgb") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t 06/11] tests/amdgpu/amd_plane: Create mpo swap between 2 displays test
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
                   ` (4 preceding siblings ...)
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 05/11] tests/amdgpu/amd_plane: Create mpo panning test Stylon Wang
@ 2021-11-30  8:34 ` Stylon Wang
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 07/11] tests/amdgpu/amd_plane: Create mpo scaling tests Stylon Wang
                   ` (7 subsequent siblings)
  13 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:34 UTC (permalink / raw)
  To: igt-dev; +Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

[Why]
In a multi display MPO config the MPO window is dragged from one display
to the other. In this usecase there is an instance when the overlay is
moved from one display to the next. This test recreates the scenario
(MPO swap)

[How]
Overlay should switch to the display that has >50% of the video. This
test was created with this asumption.

The test creates common video sizes and swaps a window of size (w/2,h)
between 2 displays bezzels at the top,middle and bottom of the display.

CRTC#1           CRTC#2                CRTC#1           CRTC#2
+-------------+------------+           +-------------+------------+
|             |            |           |             |            |
|    +--------+            |           |             +--------+   |
|    |Primary |   Primary  |    <=>    |   Primary   |Primary |   |
|    |        |            |   Swap    |             |        |   |
|    +--------+            |           |             +--------+   |
|overlay      |            |           |             |Overlay     |
+-------------+------------+           +-------------+------------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 tests/amdgpu/amd_plane.c | 53 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 52 insertions(+), 1 deletion(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 09fcf3eb..fe2389df 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -140,7 +140,8 @@ static void lut_free(lut_t *lut)
 }
 
 enum test {
-	MPO_SINGLE_PAN
+	MPO_SINGLE_PAN,
+	MPO_MULTI_PAN
 };
 
 static void test_init(data_t *data)
@@ -360,6 +361,46 @@ static void test_panning_1_display(data_t *data, int display_count, int w, int h
 
 }
 
+/*
+ * MPO_MULTI_PAN: Requires 2 displays. This test swaps a window (w,h) between 2 displays at 3 different
+ * vertical locations (top, middle, bottom)
+ *
+ * MPO will usually be the 'largest' part of the video window. Which means when a window is
+ * being dragged between 2 displays there is a instance where the MPO will jump between the displays.
+ * This test should be called with w/2 to emulate the behaviour of MPO switching between displays
+ */
+static void test_panning_2_display(data_t *data, int w, int h, struct fbc *fbc)
+{
+	bool toggle = true;
+	int pw =  data->w[0];
+	int ph =  data->h[0];
+	int pw2 =  data->w[1];
+	int ph2 =  data->h[1];
+	int smallest_h = min(ph, ph2);
+	int y[] = {0, smallest_h/2-h/2, smallest_h-h};
+	int it = 3; /* # of times to swap */
+
+	/* Set y to 0 if window is bigger than one of the displays
+	 * beacause y will be negative in that case
+	 */
+	if (h >= smallest_h)
+		y[0] = y[1] = y[2] = 0;
+
+
+	for (int j = 0; j < ARRAY_SIZE(y); j++){
+		for (int i = 0; i < it; i++){
+			if (toggle)
+				test_plane(data, 0, pw-w, y[j], w, h, pw, ph, fbc);
+			else
+				test_plane(data, 1, 0, y[j], w, h, pw2, ph2, fbc);
+
+			toggle = !toggle;
+		}
+	}
+
+	return;
+
+}
 
 /*
  * Setup and runner for panning test. Creates common video sizes and pans them across the display
@@ -417,12 +458,20 @@ static void test_display_mpo(data_t *data, enum test test, uint32_t format, int
 
 	for (int i = 0; i < ARRAY_SIZE(videos); ++i) {
 
+		/* Video(mpo) should be in the middle when it transitions between displays. This
+		 * means MPO plane will be w/2
+		 */
+		if (test == MPO_MULTI_PAN)
+			videos[i][0] = videos[i][0]/2;
+
 		for (int n = 0; n < display_count; n++)
 			igt_create_color_fb(data->fd, videos[i][0], videos[i][1],
 					    format, 0, 1.0, 1.0, 1.0, &fb[n].test_primary);
 
 		if (test == MPO_SINGLE_PAN)
 			test_panning_1_display(data, display_count, videos[i][0], videos[i][1], fb);
+		if (test == MPO_MULTI_PAN)
+			test_panning_2_display(data, videos[i][0], videos[i][1], fb);
 
 		for (int n = 0; n < display_count; n++)
 			igt_remove_fb(data->fd, &fb[n].test_primary);
@@ -656,6 +705,8 @@ igt_main
 		test_mpo_swizzle_toggle_multihead(&data);
 	igt_subtest("mpo-pan-rgb") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
 	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-pan-multi-rgb") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-pan-multi-nv12") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t 07/11] tests/amdgpu/amd_plane: Create mpo scaling tests
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
                   ` (5 preceding siblings ...)
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 06/11] tests/amdgpu/amd_plane: Create mpo swap between 2 displays test Stylon Wang
@ 2021-11-30  8:34 ` Stylon Wang
  2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 08/11] tests/amdgpu/amd_plane: Add MPO scale and pan subtest single display option Stylon Wang
                   ` (6 subsequent siblings)
  13 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:34 UTC (permalink / raw)
  To: igt-dev; +Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

[Why]
Resizing MPO window is a common usecase (video in windowed mode)

Our MPO feature has scaling limitations (0.25x -> 16x). So this test
creates a window of various reolutions and scales them between 0.25x -> 16x

[How]
The test creates common video sizes and scales them from (0.30x->16x).
The lower limit is 0.25 but some combination of configs fail at 0.25x so
0.30 is used as the starting point.

CRTC#1                            CRTC#1
+--------------------+           +---------------------+
| +-------+          |           | +------------+      |
| |Primary|          |           | |Primary     |      |
| +-------+          |    -->    | |            |      |
|                    |   scale   | |            |      |
|                    |           | +------------+      |
|overlay             |           |Overlay              |
+--------------------+           +---------------------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 tests/amdgpu/amd_plane.c | 53 ++++++++++++++++++++++++++++++++++------
 1 file changed, 46 insertions(+), 7 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index fe2389df..9506421d 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -141,7 +141,8 @@ static void lut_free(lut_t *lut)
 
 enum test {
 	MPO_SINGLE_PAN,
-	MPO_MULTI_PAN
+	MPO_MULTI_PAN,
+	MPO_SCALE
 };
 
 static void test_init(data_t *data)
@@ -273,7 +274,7 @@ static void set_regamma_lut(data_t *data, lut_t const *lut, int n)
  * NOTE: The reason for using White+White is to speed up the crc (reuse the ref crc for all cases vs taking
  * a ref crc per flip)
  */
-static void test_plane(data_t *data, int n, int x, int y, int w, int h, int pw, int ph, struct fbc *fbc){
+static void test_plane(data_t *data, int n, int x, int y, double w, double h, double scale, int pw, int ph, struct fbc *fbc){
 
 	igt_crc_t test_crc;
 	igt_display_t *display = &data->display;
@@ -290,14 +291,14 @@ static void test_plane(data_t *data, int n, int x, int y, int w, int h, int pw,
 	/* Test: */
 	/* Draw a white overlay with a cutout */
 	draw_color_alpha(&fbc[n].test_overlay, 0, 0, pw, ph, 1.0, 1.0, 1.0, 1.00);
-	draw_color_alpha(&fbc[n].test_overlay, x, y, w, h, 0.0, 0.0, 0.0, 0.0);
+	draw_color_alpha(&fbc[n].test_overlay, x, y, w*scale, h*scale, 0.0, 0.0, 0.0, 0.0);
 
 	igt_plane_set_fb(data->primary[n], &fbc[n].test_primary);
 	igt_plane_set_fb(data->overlay[n], &fbc[n].test_overlay);
 
 	/* Move the overlay to cover the cutout */
 	igt_plane_set_position(data->primary[n], x, y);
-	igt_plane_set_size(data->primary[n], w, h);
+	igt_plane_set_size(data->primary[n], w*scale, h*scale);
 
 	igt_display_commit_atomic(display, 0, 0);
 	igt_pipe_crc_collect_crc(data->pipe_crc[n], &test_crc);
@@ -350,7 +351,7 @@ static void test_panning_1_display(data_t *data, int display_count, int w, int h
 				if (pw <= w && ph <= h)
 					break;
 
-				test_plane(data, n, x, y, w, h, pw, ph, fb);
+				test_plane(data, n, x, y, w, h, 1.0, pw, ph, fb);
 
 			}
 		}
@@ -361,6 +362,40 @@ static void test_panning_1_display(data_t *data, int display_count, int w, int h
 
 }
 
+ /* MPO_SCALE: This test scales a window of size (w,h) from x1/4->x16.
+  */
+static void test_scaling_planes(data_t *data, int display_count, int w, int h, struct fbc *fb)
+{
+
+	/* Scale limit is x1/4 -> x16
+	 * some combinations of mode/window sizes fail for x0.25 so start from 0.30 -> 16
+	 */
+	double scale[]= {
+		0.30,
+		0.50,
+		0.75,
+		1.50,
+		3.00,
+		6.00,
+		12.00,
+		16.00
+
+	};
+
+	for (int n = 0; n < display_count; n++) {
+		int pw = data->w[n];
+		int ph = data->h[n];
+
+		for (int i=0;i<ARRAY_SIZE(scale);i++) {
+			/* No need to scale a overley that is bigger than the display */
+			if (pw <= w*scale[i] && ph <= h*scale[i])
+				break;
+			test_plane(data, n, 0, 0, w, h, scale[i], pw, ph, fb);
+		}
+	}
+
+	return;
+}
 /*
  * MPO_MULTI_PAN: Requires 2 displays. This test swaps a window (w,h) between 2 displays at 3 different
  * vertical locations (top, middle, bottom)
@@ -390,9 +425,9 @@ static void test_panning_2_display(data_t *data, int w, int h, struct fbc *fbc)
 	for (int j = 0; j < ARRAY_SIZE(y); j++){
 		for (int i = 0; i < it; i++){
 			if (toggle)
-				test_plane(data, 0, pw-w, y[j], w, h, pw, ph, fbc);
+				test_plane(data, 0, pw-w, y[j], w, h, 1.0, pw, ph, fbc);
 			else
-				test_plane(data, 1, 0, y[j], w, h, pw2, ph2, fbc);
+				test_plane(data, 1, 0, y[j], w, h, 1.0, pw2, ph2, fbc);
 
 			toggle = !toggle;
 		}
@@ -472,6 +507,8 @@ static void test_display_mpo(data_t *data, enum test test, uint32_t format, int
 			test_panning_1_display(data, display_count, videos[i][0], videos[i][1], fb);
 		if (test == MPO_MULTI_PAN)
 			test_panning_2_display(data, videos[i][0], videos[i][1], fb);
+		if(test == MPO_SCALE)
+			test_scaling_planes(data, display_count, videos[i][0], videos[i][1], fb);
 
 		for (int n = 0; n < display_count; n++)
 			igt_remove_fb(data->fd, &fb[n].test_primary);
@@ -707,6 +744,8 @@ igt_main
 	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 	igt_subtest("mpo-pan-multi-rgb") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
 	igt_subtest("mpo-pan-multi-nv12") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-scale-rgb") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-scale-nv12") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t 08/11] tests/amdgpu/amd_plane: Add MPO scale and pan subtest single display option
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
                   ` (6 preceding siblings ...)
  2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 07/11] tests/amdgpu/amd_plane: Create mpo scaling tests Stylon Wang
@ 2021-11-30  8:35 ` Stylon Wang
  2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 09/11] tests/amdgpu/amd_plane: Add full screen scaling test case Stylon Wang
                   ` (5 subsequent siblings)
  13 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:35 UTC (permalink / raw)
  To: igt-dev
  Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad.Othman, Victor Lu,
	Hayden.Goodfellow

From: Victor Lu <victorchengchi.lu@amd.com>

[Why]
The MPO scale and pan subtests is valid with one display and our current
CI setup only has one display.

[How]
Change the MPO scale and pan subtests to be single display and add
"-multihead" subtests for the two for the original dual display config

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
---
 tests/amdgpu/amd_plane.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 9506421d..12669239 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -740,12 +740,16 @@ igt_main
 	igt_subtest("mpo-swizzle-toggle") test_mpo_swizzle_toggle(&data);
 	igt_subtest("mpo-swizzle-toggle-multihead")
 		test_mpo_swizzle_toggle_multihead(&data);
-	igt_subtest("mpo-pan-rgb") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-pan-rgb") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, 1);
+	igt_subtest("mpo-pan-rgb-multihead") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, 1);
+	igt_subtest("mpo-pan-nv12-multihead") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 	igt_subtest("mpo-pan-multi-rgb") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
 	igt_subtest("mpo-pan-multi-nv12") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-scale-rgb") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-scale-nv12") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-scale-rgb") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, 1);
+	igt_subtest("mpo-scale-rgb-multihead") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-scale-nv12") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, 1);
+	igt_subtest("mpo-scale-nv12-multihead") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t 09/11] tests/amdgpu/amd_plane: Add full screen scaling test case
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
                   ` (7 preceding siblings ...)
  2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 08/11] tests/amdgpu/amd_plane: Add MPO scale and pan subtest single display option Stylon Wang
@ 2021-11-30  8:35 ` Stylon Wang
  2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 10/11] tests/amdgpu/amd_plane: Ensure pipes are enabled before accessing Stylon Wang
                   ` (4 subsequent siblings)
  13 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:35 UTC (permalink / raw)
  To: igt-dev; +Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

[Why]
Full screen scaling is a common usecase

[How]
Rework the scaling tests to add a 'fullscreen' test case. Change the
test_plane function to use "dst_w/h" instead of a scale multiplier. This
way we can easily add a full screen scale multiplier.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 tests/amdgpu/amd_plane.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 12669239..66302ebf 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -274,7 +274,7 @@ static void set_regamma_lut(data_t *data, lut_t const *lut, int n)
  * NOTE: The reason for using White+White is to speed up the crc (reuse the ref crc for all cases vs taking
  * a ref crc per flip)
  */
-static void test_plane(data_t *data, int n, int x, int y, double w, double h, double scale, int pw, int ph, struct fbc *fbc){
+static void test_plane(data_t *data, int n, int x, int y, double w, double h, double dw, double dh, int pw, int ph, struct fbc *fbc){
 
 	igt_crc_t test_crc;
 	igt_display_t *display = &data->display;
@@ -291,14 +291,14 @@ static void test_plane(data_t *data, int n, int x, int y, double w, double h, do
 	/* Test: */
 	/* Draw a white overlay with a cutout */
 	draw_color_alpha(&fbc[n].test_overlay, 0, 0, pw, ph, 1.0, 1.0, 1.0, 1.00);
-	draw_color_alpha(&fbc[n].test_overlay, x, y, w*scale, h*scale, 0.0, 0.0, 0.0, 0.0);
+	draw_color_alpha(&fbc[n].test_overlay, x, y, dw, dh, 0.0, 0.0, 0.0, 0.0);
 
 	igt_plane_set_fb(data->primary[n], &fbc[n].test_primary);
 	igt_plane_set_fb(data->overlay[n], &fbc[n].test_overlay);
 
 	/* Move the overlay to cover the cutout */
 	igt_plane_set_position(data->primary[n], x, y);
-	igt_plane_set_size(data->primary[n], w*scale, h*scale);
+	igt_plane_set_size(data->primary[n], dw, dh);
 
 	igt_display_commit_atomic(display, 0, 0);
 	igt_pipe_crc_collect_crc(data->pipe_crc[n], &test_crc);
@@ -351,7 +351,7 @@ static void test_panning_1_display(data_t *data, int display_count, int w, int h
 				if (pw <= w && ph <= h)
 					break;
 
-				test_plane(data, n, x, y, w, h, 1.0, pw, ph, fb);
+				test_plane(data, n, x, y, w, h, w, h, pw, ph, fb);
 
 			}
 		}
@@ -390,8 +390,11 @@ static void test_scaling_planes(data_t *data, int display_count, int w, int h, s
 			/* No need to scale a overley that is bigger than the display */
 			if (pw <= w*scale[i] && ph <= h*scale[i])
 				break;
-			test_plane(data, n, 0, 0, w, h, scale[i], pw, ph, fb);
+			test_plane(data, n, 0, 0, w, h, w*scale[i], h*scale[i], pw, ph, fb);
 		}
+
+		/* Test Fullscreen scale*/
+		test_plane(data, n, 0, 0, w, h, pw, ph, pw, ph, fb);
 	}
 
 	return;
@@ -425,9 +428,9 @@ static void test_panning_2_display(data_t *data, int w, int h, struct fbc *fbc)
 	for (int j = 0; j < ARRAY_SIZE(y); j++){
 		for (int i = 0; i < it; i++){
 			if (toggle)
-				test_plane(data, 0, pw-w, y[j], w, h, 1.0, pw, ph, fbc);
+				test_plane(data, 0, pw-w, y[j], w, h, w, h, pw, ph, fbc);
 			else
-				test_plane(data, 1, 0, y[j], w, h, 1.0, pw2, ph2, fbc);
+				test_plane(data, 1, 0, y[j], w, h, w, h, pw2, ph2, fbc);
 
 			toggle = !toggle;
 		}
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t 10/11] tests/amdgpu/amd_plane: Ensure pipes are enabled before accessing
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
                   ` (8 preceding siblings ...)
  2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 09/11] tests/amdgpu/amd_plane: Add full screen scaling test case Stylon Wang
@ 2021-11-30  8:35 ` Stylon Wang
  2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 11/11] tests/amdgpu/amd_plane: Add P010 format to MPO tests and add test descriptions Stylon Wang
                   ` (3 subsequent siblings)
  13 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:35 UTC (permalink / raw)
  To: igt-dev; +Cc: Anson Jacob, Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

From: Anson Jacob <Anson.Jacob@amd.com>

Couple of tests were accessing pipe's without ensuring if they are
enabled or not. Using for_each_pipe macro to do so.

Signed-off-by: Anson Jacob <Anson.Jacob@amd.com>
---
 tests/amdgpu/amd_plane.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 66302ebf..e4c7dca3 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -150,9 +150,9 @@ static void test_init(data_t *data)
 	igt_display_t *display = &data->display;
 	int i, n, max_pipes = display->n_pipes;
 
-	for (i = 0; i < max_pipes; ++i) {
+	for_each_pipe(display, i) {
 		data->pipe_id[i] = PIPE_A + i;
-		data->pipe[i] = &data->display.pipes[data->pipe_id[i]];
+		data->pipe[i] = &display->pipes[data->pipe_id[i]];
 		data->primary[i] = igt_pipe_get_plane_type(
 			data->pipe[i], DRM_PLANE_TYPE_PRIMARY);
 		data->overlay[i] = igt_pipe_get_plane_type_index(
@@ -188,9 +188,9 @@ static void test_init(data_t *data)
 static void test_fini(data_t *data)
 {
 	igt_display_t *display = &data->display;
-	int i, max_pipes = display->n_pipes;
+	int i;
 
-	for (i = 0; i < max_pipes; ++i) {
+	for_each_pipe(display, i) {
 		igt_pipe_crc_free(data->pipe_crc[i]);
 	}
 
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t 11/11] tests/amdgpu/amd_plane: Add P010 format to MPO tests and add test descriptions
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
                   ` (9 preceding siblings ...)
  2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 10/11] tests/amdgpu/amd_plane: Ensure pipes are enabled before accessing Stylon Wang
@ 2021-11-30  8:35 ` Stylon Wang
  2021-11-30 11:10 ` [igt-dev] ✗ Fi.CI.BUILD: failure for Create tests for multi-plane overlay Patchwork
                   ` (2 subsequent siblings)
  13 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-11-30  8:35 UTC (permalink / raw)
  To: igt-dev; +Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

Signed-off-by: Stylon Wang <stylon.wang@amd.com>
---
 tests/amdgpu/amd_plane.c | 64 +++++++++++++++++++++++++++++++++-------
 1 file changed, 54 insertions(+), 10 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index e4c7dca3..faaa1b87 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -24,6 +24,8 @@
 #include "libdrm/amdgpu.h"
 #include "libdrm/amdgpu_drm.h"
 
+IGT_TEST_DESCRIPTION("Tests for Multi Plane Overlay for single and dual displays");
+
 /* Maximum pipes on any AMD ASIC. */
 #define MAX_PIPES 6
 #define DISPLAYS_TO_TEST 2
@@ -485,7 +487,7 @@ static void test_display_mpo(data_t *data, enum test test, uint32_t format, int
 
 		igt_plane_set_fb(data->primary[n], &fb[n].ref_primary);
 
-		if (format == DRM_FORMAT_NV12)
+		if (format == DRM_FORMAT_NV12 || format == DRM_FORMAT_P010)
 			set_regamma_lut(data, &lut,  n);
 	}
 
@@ -739,20 +741,62 @@ igt_main
 		igt_display_require_output(&data.display);
 	}
 
+	igt_describe("MPO with 4K planes");
 	igt_subtest("test-mpo-4k") test_mpo_4k(&data);
+	igt_describe("MPO with tiled and linear buffers");
 	igt_subtest("mpo-swizzle-toggle") test_mpo_swizzle_toggle(&data);
+	igt_describe("MPO with tiled and linear buffers on dual displays");
 	igt_subtest("mpo-swizzle-toggle-multihead")
 		test_mpo_swizzle_toggle_multihead(&data);
-	igt_subtest("mpo-pan-rgb") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, 1);
-	igt_subtest("mpo-pan-rgb-multihead") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, 1);
-	igt_subtest("mpo-pan-nv12-multihead") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-pan-multi-rgb") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-pan-multi-nv12") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-scale-rgb") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, 1);
-	igt_subtest("mpo-scale-rgb-multihead") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-scale-nv12") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, 1);
+
+	igt_describe("MPO and moving RGB primary plane around");
+	igt_subtest("mpo-pan-rgb")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, 1);
+	igt_describe("MPO and moving RGB primary plane around with dual displays");
+	igt_subtest("mpo-pan-rgb-multihead")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+
+	igt_describe("MPO and moving NV12 primary plane around");
+	igt_subtest("mpo-pan-nv12")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, 1);
+	igt_describe("MPO and moving NV12 primary plane around with dual displays");
+	igt_subtest("mpo-pan-nv12-multihead")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+
+	igt_describe("MPO and moving P010 primary plane around");
+	igt_subtest("mpo-pan-p010")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_P010, 1);
+	igt_describe("MPO and moving P010 primary plane around with dual displays");
+	igt_subtest("mpo-pan-p010-multihead")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_P010, DISPLAYS_TO_TEST);
+
+	igt_describe("MPO and moving RGB primary plane between 2 displays");
+	igt_subtest("mpo-pan-multi-rgb")
+		test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_describe("MPO and moving NV12 primary plane between 2 displays");
+	igt_subtest("mpo-pan-multi-nv12")
+		test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_describe("MPO and moving P010 primary plane between 2 displays");
+	igt_subtest("mpo-pan-multi-p010")
+		test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_P010, DISPLAYS_TO_TEST);
+
+	igt_describe("MPO and scaling RGB primary plane");
+	igt_subtest("mpo-scale-rgb")
+		test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, 1);
+	igt_describe("MPO and scaling RGB primary plane with 2 displays");
+	igt_subtest("mpo-scale-rgb-multihead")
+		test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_describe("MPO and scaling NV12 primary plane");
+	igt_subtest("mpo-scale-nv12")
+		test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, 1);
+	igt_describe("MPO and scaling NV12 primary plane with 2 displays");
 	igt_subtest("mpo-scale-nv12-multihead") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_describe("MPO and scaling P010 primary plane");
+	igt_subtest("mpo-scale-p010")
+		test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_P010, 1);
+	igt_describe("MPO and scaling P010 primary plane with 2 displays");
+	igt_subtest("mpo-scale-p010-multihead")
+		test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_P010, DISPLAYS_TO_TEST);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] ✗ Fi.CI.BUILD: failure for Create tests for multi-plane overlay
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
                   ` (10 preceding siblings ...)
  2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 11/11] tests/amdgpu/amd_plane: Add P010 format to MPO tests and add test descriptions Stylon Wang
@ 2021-11-30 11:10 ` Patchwork
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
  2021-12-01 22:09 ` [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Rodrigo Siqueira Jordao
  13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2021-11-30 11:10 UTC (permalink / raw)
  To: Stylon Wang; +Cc: igt-dev

== Series Details ==

Series: Create tests for multi-plane overlay
URL   : https://patchwork.freedesktop.org/series/97398/
State : failure

== Summary ==

Applying: tests/amdgpu/amd_plane: Introduced 4K MPO test
Using index info to reconstruct a base tree...
M	tests/amdgpu/meson.build
Falling back to patching base and 3-way merge...
Auto-merging tests/amdgpu/meson.build
CONFLICT (content): Merge conflict in tests/amdgpu/meson.build
Patch failed at 0001 tests/amdgpu/amd_plane: Introduced 4K MPO test
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 00/11] Create tests for multi-plane overlay
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
                   ` (11 preceding siblings ...)
  2021-11-30 11:10 ` [igt-dev] ✗ Fi.CI.BUILD: failure for Create tests for multi-plane overlay Patchwork
@ 2021-12-01  6:54 ` Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 01/11] tests/amdgpu/amd_plane: Introduced 4K MPO test Stylon Wang
                     ` (10 more replies)
  2021-12-01 22:09 ` [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Rodrigo Siqueira Jordao
  13 siblings, 11 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

A series of new tests on MPO is added to tests/amdgpu/amd_plane.

Currently most of the sub-tests are AMD-specific and concerns with
video use cases from projects.

Changes from prior rev1 to now:

v2: Fix conflict in meson.build

Ahmad Othman (1):
  tests/amdgpu/amd_plane: fixes for test-4k-mpo

Anson Jacob (1):
  tests/amdgpu/amd_plane: Ensure pipes are enabled before accessing

Bhawanpreet Lakha (4):
  tests/amdgpu/amd_plane: Create mpo panning test
  tests/amdgpu/amd_plane: Create mpo swap between 2 displays test
  tests/amdgpu/amd_plane: Create mpo scaling tests
  tests/amdgpu/amd_plane: Add full screen scaling test case

Nicholas Kazlauskas (1):
  tests/amdgpu/amd_plane: Add MPO swizzle mode toggle test

Stylon Wang (1):
  tests/amdgpu/amd_plane: Add P010 format to MPO tests and add test
    descriptions

Victor Lu (3):
  tests/amdgpu/amd_plane: Introduced 4K MPO test
  tests/amdgpu/amd_plane: Switch mpo-swizzle-toggle to single-head
  tests/amdgpu/amd_plane: Add MPO scale and pan subtest single display
    option

 tests/amdgpu/amd_plane.c | 805 +++++++++++++++++++++++++++++++++++++++
 tests/amdgpu/meson.build |   1 +
 2 files changed, 806 insertions(+)
 create mode 100644 tests/amdgpu/amd_plane.c

-- 
2.33.1

^ permalink raw reply	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 01/11] tests/amdgpu/amd_plane: Introduced 4K MPO test
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
@ 2021-12-01  6:54   ` Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 02/11] tests/amdgpu/amd_plane: Add MPO swizzle mode toggle test Stylon Wang
                     ` (9 subsequent siblings)
  10 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad.Othman, Victor Lu, Hayden.Goodfellow

From: Victor Lu <victorchengchi.lu@amd.com>

Tests MPO using a primary plane and an overlay plane with a transparent
cutout.

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
---
 tests/amdgpu/amd_plane.c | 158 +++++++++++++++++++++++++++++++++++++++
 tests/amdgpu/meson.build |   1 +
 2 files changed, 159 insertions(+)
 create mode 100644 tests/amdgpu/amd_plane.c

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
new file mode 100644
index 00000000..64273330
--- /dev/null
+++ b/tests/amdgpu/amd_plane.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+
+/* Common test data. */
+typedef struct data {
+	igt_display_t display;
+	igt_plane_t *primary;
+	igt_plane_t *overlay;
+	igt_output_t *output;
+	igt_pipe_t *pipe;
+	igt_pipe_crc_t *pipe_crc;
+	drmModeModeInfo *mode;
+	enum pipe pipe_id;
+	int fd;
+	int w;
+	int h;
+} data_t;
+
+static void test_init(data_t *data)
+{
+	igt_display_t *display = &data->display;
+
+	/* It doesn't matter which pipe we choose on amdpgu. */
+	data->pipe_id = PIPE_A;
+	data->pipe = &data->display.pipes[data->pipe_id];
+
+	igt_display_reset(display);
+
+	data->output = igt_get_single_output_for_pipe(display, data->pipe_id);
+	igt_require(data->output);
+
+	data->mode = igt_output_get_mode(data->output);
+	igt_assert(data->mode);
+
+	data->primary =
+		igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_PRIMARY);
+	data->overlay =
+		igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_OVERLAY);
+
+	data->pipe_crc = igt_pipe_crc_new(data->fd, data->pipe_id,
+					  INTEL_PIPE_CRC_SOURCE_AUTO);
+
+	igt_output_set_pipe(data->output, data->pipe_id);
+
+	data->w = data->mode->hdisplay;
+	data->h = data->mode->vdisplay;
+}
+
+static void test_fini(data_t *data)
+{
+	igt_pipe_crc_free(data->pipe_crc);
+	igt_display_reset(&data->display);
+}
+
+static void draw_color_alpha(igt_fb_t *fb, int x, int y, int w, int h,
+		             double r, double g, double b, double a)
+{
+	cairo_t *cr = igt_get_cairo_ctx(fb->fd, fb);
+	igt_paint_color_alpha(cr, x, y, w, h, r, g, b, a);
+	igt_put_cairo_ctx(cr);
+}
+
+/*
+ * Compares a white 4K reference FB against a white 4K primary FB and a
+ * white 4K overlay with an RGBA (0, 0, 0, 0) cutout in the center.
+ */
+static void test_mpo_4k(data_t *data)
+{
+	igt_fb_t r_fb, p_fb, o_fb;
+	igt_crc_t ref_crc, new_crc;
+	igt_display_t *display = &data->display;
+	int cutout_x, cutout_y, cutout_w, cutout_h;
+
+	test_init(data);
+
+	/* Skip if not 4K resolution. */
+	igt_skip_on(!(data->mode->hdisplay == 3840 &&
+		    data->mode->vdisplay == 2160));
+
+	cutout_x = cutout_w = 1280;
+	cutout_y = cutout_h = 720;
+
+	igt_create_color_fb(data->fd, data->w, data->h, DRM_FORMAT_XRGB8888,
+			    0, 1.00, 1.00, 1.00, &r_fb);
+	igt_create_color_fb(data->fd, data->w, data->h, DRM_FORMAT_XRGB8888,
+			    0, 1.00, 1.00, 1.00, &p_fb);
+	igt_create_fb(data->fd, data->w, data->h, DRM_FORMAT_ARGB8888,
+		      0, &o_fb);
+	draw_color_alpha(&o_fb, 0, 0, o_fb.width, o_fb.height, 1.00, 1.00, 1.00, 1.00);
+	draw_color_alpha(&o_fb, cutout_x, cutout_y, cutout_w, cutout_h,
+			 0.00, 0.00, 0.00, 0.00);
+
+	igt_plane_set_fb(data->primary, &r_fb);
+	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+	igt_pipe_crc_collect_crc(data->pipe_crc, &ref_crc);
+
+	igt_plane_set_fb(data->primary, &p_fb);
+	igt_plane_set_fb(data->overlay, &o_fb);
+	igt_display_commit_atomic(display, 0, NULL);
+
+	igt_pipe_crc_collect_crc(data->pipe_crc, &new_crc);
+
+	igt_assert_crc_equal(&ref_crc, &new_crc);
+
+	test_fini(data);
+	igt_remove_fb(data->fd, &o_fb);
+	igt_remove_fb(data->fd, &p_fb);
+	igt_remove_fb(data->fd, &r_fb);
+}
+
+igt_main
+{
+	data_t data;
+
+	igt_skip_on_simulation();
+
+	memset(&data, 0, sizeof(data));
+
+	igt_fixture
+	{
+		data.fd = drm_open_driver_master(DRIVER_AMDGPU);
+
+		kmstest_set_vt_graphics_mode();
+
+		igt_display_require(&data.display, data.fd);
+		igt_require(data.display.is_atomic);
+		igt_display_require_output(&data.display);
+	}
+
+	igt_subtest("test-mpo-4k") test_mpo_4k(&data);
+
+	igt_fixture
+	{
+		igt_display_fini(&data.display);
+	}
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 5216e194..3531151b 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -17,6 +17,7 @@ if libdrm_amdgpu.found()
 			  'amd_link_settings',
 			  'amd_vrr_range',
 			  'amd_mode_switch',
+			  'amd_plane',
 			]
 	amdgpu_deps += libdrm_amdgpu
 endif
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 02/11] tests/amdgpu/amd_plane: Add MPO swizzle mode toggle test
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 01/11] tests/amdgpu/amd_plane: Introduced 4K MPO test Stylon Wang
@ 2021-12-01  6:54   ` Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 03/11] tests/amdgpu/amd_plane: fixes for test-4k-mpo Stylon Wang
                     ` (8 subsequent siblings)
  10 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Sequence captured on ChromeOS - we experience underflow when toggling
between swizzle modes on the primary plane with MPO enabled.

Add a new subtest replicating that sequence, "mpo-swizzle-toggle".

Converts the existing framework over to the new multi-display framework
since that's the configuration where this was found.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 tests/amdgpu/amd_plane.c | 260 ++++++++++++++++++++++++++++++++-------
 1 file changed, 217 insertions(+), 43 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 64273330..09fd3b08 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -21,56 +21,153 @@
  */
 
 #include "igt.h"
+#include "libdrm/amdgpu.h"
+#include "libdrm/amdgpu_drm.h"
+
+/* Maximum pipes on any AMD ASIC. */
+#define MAX_PIPES 6
 
 /* Common test data. */
 typedef struct data {
-	igt_display_t display;
-	igt_plane_t *primary;
-	igt_plane_t *overlay;
-	igt_output_t *output;
-	igt_pipe_t *pipe;
-	igt_pipe_crc_t *pipe_crc;
-	drmModeModeInfo *mode;
-	enum pipe pipe_id;
-	int fd;
-	int w;
-	int h;
+        igt_display_t display;
+        igt_plane_t *primary[MAX_PIPES];
+        igt_plane_t *cursor[MAX_PIPES];
+	igt_plane_t *overlay[MAX_PIPES];
+        igt_output_t *output[MAX_PIPES];
+        igt_pipe_t *pipe[MAX_PIPES];
+        igt_pipe_crc_t *pipe_crc[MAX_PIPES];
+        drmModeModeInfo mode[MAX_PIPES];
+        enum pipe pipe_id[MAX_PIPES];
+        int w[MAX_PIPES];
+        int h[MAX_PIPES];
+        int fd;
 } data_t;
 
+static const drmModeModeInfo test_mode_1 = {
+	.name = "1920x1080 Test",
+	.vrefresh = 60,
+	.clock = 148500,
+	.hdisplay = 1920,
+	.hsync_start = 2008,
+	.hsync_end = 2052,
+	.htotal = 2200,
+	.vdisplay = 1080,
+	.vsync_start = 1084,
+	.vsync_end = 1089,
+	.vtotal = 1125,
+	.type = 0x40,
+	.flags = DRM_MODE_FLAG_NHSYNC,
+	.hskew = 0,
+	.vscan = 0,
+};
+
+static const drmModeModeInfo test_mode_2 = {
+	.name = "1280x1024 Test",
+	.vrefresh = 60,
+	.clock = 148500,
+	.hdisplay = 1280,
+	.hsync_start = 2008,
+	.hsync_end = 2052,
+	.htotal = 2200,
+	.vdisplay = 1024,
+	.vsync_start = 1084,
+	.vsync_end = 1089,
+	.vtotal = 1125,
+	.type = DRM_MODE_TYPE_DRIVER,
+	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+	.hskew = 0,
+	.vscan = 0,
+};
+
 static void test_init(data_t *data)
 {
 	igt_display_t *display = &data->display;
+	int i, n, max_pipes = display->n_pipes;
+
+	for (i = 0; i < max_pipes; ++i) {
+		data->pipe_id[i] = PIPE_A + i;
+		data->pipe[i] = &data->display.pipes[data->pipe_id[i]];
+		data->primary[i] = igt_pipe_get_plane_type(
+			data->pipe[i], DRM_PLANE_TYPE_PRIMARY);
+		data->overlay[i] = igt_pipe_get_plane_type_index(
+			data->pipe[i], DRM_PLANE_TYPE_OVERLAY, 0);
+		data->cursor[i] = igt_pipe_get_plane_type(
+			data->pipe[i], DRM_PLANE_TYPE_CURSOR);
+		data->pipe_crc[i] =
+			igt_pipe_crc_new(data->fd, data->pipe_id[i], "auto");
+	}
+
+	for (i = 0, n = 0; i < display->n_outputs && n < max_pipes; ++i) {
+		igt_output_t *output = &display->outputs[i];
+
+		data->output[n] = output;
+
+		/* Only allow physically connected displays for the tests. */
+		if (!igt_output_is_connected(output))
+			continue;
 
-	/* It doesn't matter which pipe we choose on amdpgu. */
-	data->pipe_id = PIPE_A;
-	data->pipe = &data->display.pipes[data->pipe_id];
+		igt_assert(kmstest_get_connector_default_mode(
+			data->fd, output->config.connector, &data->mode[n]));
 
+		data->w[n] = data->mode[n].hdisplay;
+		data->h[n] = data->mode[n].vdisplay;
+
+		n += 1;
+	}
+
+	igt_require(data->output[0]);
 	igt_display_reset(display);
+}
 
-	data->output = igt_get_single_output_for_pipe(display, data->pipe_id);
-	igt_require(data->output);
+static void test_fini(data_t *data)
+{
+	igt_display_t *display = &data->display;
+	int i, max_pipes = display->n_pipes;
 
-	data->mode = igt_output_get_mode(data->output);
-	igt_assert(data->mode);
+	for (i = 0; i < max_pipes; ++i) {
+		igt_pipe_crc_free(data->pipe_crc[i]);
+	}
 
-	data->primary =
-		igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_PRIMARY);
-	data->overlay =
-		igt_pipe_get_plane_type(data->pipe, DRM_PLANE_TYPE_OVERLAY);
+	igt_display_reset(display);
+	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+}
 
-	data->pipe_crc = igt_pipe_crc_new(data->fd, data->pipe_id,
-					  INTEL_PIPE_CRC_SOURCE_AUTO);
+/* Forces a mode for a connector. */
+static void force_output_mode(data_t *data, igt_output_t *output,
+			      drmModeModeInfo const *mode)
+{
+	/* This allows us to create a virtual sink. */
+	if (!igt_output_is_connected(output)) {
+		kmstest_force_edid(data->fd, output->config.connector,
+				   igt_kms_get_4k_edid());
 
-	igt_output_set_pipe(data->output, data->pipe_id);
+		kmstest_force_connector(data->fd, output->config.connector,
+					FORCE_CONNECTOR_DIGITAL);
+	}
 
-	data->w = data->mode->hdisplay;
-	data->h = data->mode->vdisplay;
+	igt_output_override_mode(output, mode);
 }
 
-static void test_fini(data_t *data)
+
+static int set_metadata(data_t *data, igt_fb_t *fb, struct amdgpu_bo_metadata *info)
 {
-	igt_pipe_crc_free(data->pipe_crc);
-	igt_display_reset(&data->display);
+	struct drm_amdgpu_gem_metadata args = {};
+
+	args.handle = fb->gem_handle;
+	args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
+	args.data.flags = info->flags;
+	args.data.tiling_info = info->tiling_info;
+
+	if (info->size_metadata > sizeof(args.data.data))
+		return -EINVAL;
+
+	if (info->size_metadata) {
+		args.data.data_size_bytes = info->size_metadata;
+		memcpy(args.data.data, info->umd_metadata, info->size_metadata);
+	}
+
+	return drmCommandWriteRead(data->fd, DRM_AMDGPU_GEM_METADATA, &args,
+				   sizeof(args));
 }
 
 static void draw_color_alpha(igt_fb_t *fb, int x, int y, int w, int h,
@@ -91,36 +188,38 @@ static void test_mpo_4k(data_t *data)
 	igt_crc_t ref_crc, new_crc;
 	igt_display_t *display = &data->display;
 	int cutout_x, cutout_y, cutout_w, cutout_h;
+	int w, h;
 
 	test_init(data);
 
 	/* Skip if not 4K resolution. */
-	igt_skip_on(!(data->mode->hdisplay == 3840 &&
-		    data->mode->vdisplay == 2160));
+	igt_skip_on(!(data->mode[0].hdisplay == 3840
+		      && data->mode[0].vdisplay == 2160));
 
+	w = data->w[0];
+	h = data->h[0];
 	cutout_x = cutout_w = 1280;
 	cutout_y = cutout_h = 720;
 
-	igt_create_color_fb(data->fd, data->w, data->h, DRM_FORMAT_XRGB8888,
-			    0, 1.00, 1.00, 1.00, &r_fb);
-	igt_create_color_fb(data->fd, data->w, data->h, DRM_FORMAT_XRGB8888,
-			    0, 1.00, 1.00, 1.00, &p_fb);
-	igt_create_fb(data->fd, data->w, data->h, DRM_FORMAT_ARGB8888,
-		      0, &o_fb);
+	igt_create_color_fb(data->fd, w, h, DRM_FORMAT_XRGB8888, 0, 1.00, 1.00,
+			    1.00, &r_fb);
+	igt_create_color_fb(data->fd, w, h, DRM_FORMAT_XRGB8888, 0, 1.00, 1.00,
+			    1.00, &p_fb);
+	igt_create_fb(data->fd, w, h, DRM_FORMAT_ARGB8888, 0, &o_fb);
 	draw_color_alpha(&o_fb, 0, 0, o_fb.width, o_fb.height, 1.00, 1.00, 1.00, 1.00);
 	draw_color_alpha(&o_fb, cutout_x, cutout_y, cutout_w, cutout_h,
 			 0.00, 0.00, 0.00, 0.00);
 
-	igt_plane_set_fb(data->primary, &r_fb);
+	igt_plane_set_fb(data->primary[0], &r_fb);
 	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
 
-	igt_pipe_crc_collect_crc(data->pipe_crc, &ref_crc);
+	igt_pipe_crc_collect_crc(data->pipe_crc[0], &ref_crc);
 
-	igt_plane_set_fb(data->primary, &p_fb);
-	igt_plane_set_fb(data->overlay, &o_fb);
+	igt_plane_set_fb(data->primary[0], &p_fb);
+	igt_plane_set_fb(data->overlay[0], &o_fb);
 	igt_display_commit_atomic(display, 0, NULL);
 
-	igt_pipe_crc_collect_crc(data->pipe_crc, &new_crc);
+	igt_pipe_crc_collect_crc(data->pipe_crc[0], &new_crc);
 
 	igt_assert_crc_equal(&ref_crc, &new_crc);
 
@@ -130,6 +229,80 @@ static void test_mpo_4k(data_t *data)
 	igt_remove_fb(data->fd, &r_fb);
 }
 
+static void test_mpo_swizzle_toggle(data_t *data)
+{
+	struct amdgpu_bo_metadata meta = {};
+	igt_display_t *display = &data->display;
+	igt_fb_t fb_1280_xr24_tiled, fb_1280_ar24_tiled, fb_1920_xb24_tiled,
+		fb_1920_xb24_linear, fb_1920_xr24_tiled;
+	int w, h;
+
+	w = 2400;
+	h = 1350;
+
+	igt_create_pattern_fb(data->fd, 1280, 1024, DRM_FORMAT_XRGB8888, 0,
+			      &fb_1280_xr24_tiled);
+	igt_create_pattern_fb(data->fd, 1280, 1024, DRM_FORMAT_ARGB8888, 0,
+			      &fb_1280_ar24_tiled);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XBGR8888, 0,
+			      &fb_1920_xb24_tiled);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XBGR8888, 0,
+			      &fb_1920_xb24_linear);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XRGB8888, 0,
+			      &fb_1920_xr24_tiled);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1280_xr24_tiled, &meta);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1280_ar24_tiled, &meta);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1920_xb24_tiled, &meta);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1920_xr24_tiled, &meta);
+
+	test_init(data);
+
+	/* Initial modeset */
+	igt_output_set_pipe(data->output[0], data->pipe_id[0]);
+	igt_output_set_pipe(data->output[1], data->pipe_id[1]);
+	force_output_mode(data, data->output[0], &test_mode_1);
+	force_output_mode(data, data->output[1], &test_mode_2);
+
+	igt_plane_set_fb(data->primary[0], &fb_1920_xr24_tiled);
+	igt_plane_set_fb(data->primary[1], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[1], w, h);
+
+	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+	/* Enable overlay plane. */
+	igt_plane_set_fb(data->overlay[1], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[1], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[1], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	/* Switch to tiled. */
+	igt_plane_set_fb(data->overlay[1], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[1], &fb_1920_xb24_tiled);
+	igt_plane_set_size(data->primary[1], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	/* Switch to linear. */
+	igt_plane_set_fb(data->overlay[1], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[1], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[1], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	test_fini(data);
+	igt_remove_fb(data->fd, &fb_1280_xr24_tiled);
+	igt_remove_fb(data->fd, &fb_1280_ar24_tiled);
+	igt_remove_fb(data->fd, &fb_1920_xb24_tiled);
+	igt_remove_fb(data->fd, &fb_1920_xb24_linear);
+	igt_remove_fb(data->fd, &fb_1920_xr24_tiled);
+}
+
 igt_main
 {
 	data_t data;
@@ -150,6 +323,7 @@ igt_main
 	}
 
 	igt_subtest("test-mpo-4k") test_mpo_4k(&data);
+	igt_subtest("mpo-swizzle-toggle") test_mpo_swizzle_toggle(&data);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 03/11] tests/amdgpu/amd_plane: fixes for test-4k-mpo
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 01/11] tests/amdgpu/amd_plane: Introduced 4K MPO test Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 02/11] tests/amdgpu/amd_plane: Add MPO swizzle mode toggle test Stylon Wang
@ 2021-12-01  6:54   ` Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 04/11] tests/amdgpu/amd_plane: Switch mpo-swizzle-toggle to single-head Stylon Wang
                     ` (7 subsequent siblings)
  10 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad Othman, Hayden.Goodfellow

From: Ahmad Othman <ahmad.othman@amd.com>

[Why]
The test wasn't working on some setups and needs fixing

[How]
Added output pipe initialization
Added checks for both 4k and 2160p

Signed-off-by: Ahmad Othman <ahmad.othman@amd.com>
---
 tests/amdgpu/amd_plane.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 09fd3b08..ba29bdd4 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -193,8 +193,10 @@ static void test_mpo_4k(data_t *data)
 	test_init(data);
 
 	/* Skip if not 4K resolution. */
-	igt_skip_on(!(data->mode[0].hdisplay == 3840
-		      && data->mode[0].vdisplay == 2160));
+	igt_skip_on(!((data->mode[0].hdisplay == 4096
+		      && data->mode[0].vdisplay == 2160)||
+		      (data->mode[0].hdisplay == 3840
+		      && data->mode[0].vdisplay == 2160)));
 
 	w = data->w[0];
 	h = data->h[0];
@@ -210,6 +212,7 @@ static void test_mpo_4k(data_t *data)
 	draw_color_alpha(&o_fb, cutout_x, cutout_y, cutout_w, cutout_h,
 			 0.00, 0.00, 0.00, 0.00);
 
+	igt_output_set_pipe(data->output[0], data->pipe_id[0]);
 	igt_plane_set_fb(data->primary[0], &r_fb);
 	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
 
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 04/11] tests/amdgpu/amd_plane: Switch mpo-swizzle-toggle to single-head
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
                     ` (2 preceding siblings ...)
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 03/11] tests/amdgpu/amd_plane: fixes for test-4k-mpo Stylon Wang
@ 2021-12-01  6:54   ` Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 05/11] tests/amdgpu/amd_plane: Create mpo panning test Stylon Wang
                     ` (6 subsequent siblings)
  10 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad.Othman, Victor Lu, Hayden.Goodfellow

From: Victor Lu <victorchengchi.lu@amd.com>

[why]
Older ASIC does not support multi-head MPO

[how]
Rename current mpo-swizzle-toggle subtest to
mpo-swizzle-toggle-multihead. Change mpo-swizzle-toggle to only use one
output.

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
---
 tests/amdgpu/amd_plane.c | 70 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 69 insertions(+), 1 deletion(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index ba29bdd4..5666b9e7 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -232,7 +232,7 @@ static void test_mpo_4k(data_t *data)
 	igt_remove_fb(data->fd, &r_fb);
 }
 
-static void test_mpo_swizzle_toggle(data_t *data)
+static void test_mpo_swizzle_toggle_multihead(data_t *data)
 {
 	struct amdgpu_bo_metadata meta = {};
 	igt_display_t *display = &data->display;
@@ -306,6 +306,72 @@ static void test_mpo_swizzle_toggle(data_t *data)
 	igt_remove_fb(data->fd, &fb_1920_xr24_tiled);
 }
 
+static void test_mpo_swizzle_toggle(data_t *data)
+{
+	struct amdgpu_bo_metadata meta = {};
+	igt_display_t *display = &data->display;
+	igt_fb_t fb_1280_ar24_tiled, fb_1920_xb24_tiled, fb_1920_xb24_linear,
+		 fb_1920_xr24_tiled;
+	int w, h;
+
+	w = 2400;
+	h = 1350;
+
+	igt_create_pattern_fb(data->fd, 1280, 1024, DRM_FORMAT_ARGB8888, 0,
+			      &fb_1280_ar24_tiled);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XBGR8888, 0,
+			      &fb_1920_xb24_tiled);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XBGR8888, 0,
+			      &fb_1920_xb24_linear);
+	igt_create_pattern_fb(data->fd, 1920, 1080, DRM_FORMAT_XRGB8888, 0,
+			      &fb_1920_xr24_tiled);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1280_ar24_tiled, &meta);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1920_xb24_tiled, &meta);
+
+	meta.tiling_info = AMDGPU_TILING_SET(SWIZZLE_MODE, 0x19);
+	set_metadata(data, &fb_1920_xr24_tiled, &meta);
+
+	test_init(data);
+
+	/* Initial modeset */
+	igt_output_set_pipe(data->output[0], data->pipe_id[0]);
+	force_output_mode(data, data->output[0], &test_mode_1);
+
+	igt_plane_set_fb(data->primary[0], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[0], w, h);
+
+	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+	/* Enable overlay plane. */
+	igt_plane_set_fb(data->overlay[0], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[0], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[0], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	/* Switch to tiled. */
+	igt_plane_set_fb(data->overlay[0], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[0], &fb_1920_xb24_tiled);
+	igt_plane_set_size(data->primary[0], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	/* Switch to linear. */
+	igt_plane_set_fb(data->overlay[0], &fb_1280_ar24_tiled);
+	igt_plane_set_fb(data->primary[0], &fb_1920_xb24_linear);
+	igt_plane_set_size(data->primary[0], w, h);
+	igt_display_commit_atomic(display, 0, 0);
+
+	test_fini(data);
+	igt_remove_fb(data->fd, &fb_1280_ar24_tiled);
+	igt_remove_fb(data->fd, &fb_1920_xb24_tiled);
+	igt_remove_fb(data->fd, &fb_1920_xb24_linear);
+	igt_remove_fb(data->fd, &fb_1920_xr24_tiled);
+}
+
+
 igt_main
 {
 	data_t data;
@@ -327,6 +393,8 @@ igt_main
 
 	igt_subtest("test-mpo-4k") test_mpo_4k(&data);
 	igt_subtest("mpo-swizzle-toggle") test_mpo_swizzle_toggle(&data);
+	igt_subtest("mpo-swizzle-toggle-multihead")
+		test_mpo_swizzle_toggle_multihead(&data);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 05/11] tests/amdgpu/amd_plane: Create mpo panning test
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
                     ` (3 preceding siblings ...)
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 04/11] tests/amdgpu/amd_plane: Switch mpo-swizzle-toggle to single-head Stylon Wang
@ 2021-12-01  6:54   ` Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 06/11] tests/amdgpu/amd_plane: Create mpo swap between 2 displays test Stylon Wang
                     ` (5 subsequent siblings)
  10 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

[Why]
Moving the MPO window is a common usecase (video window being moved).
This test creates a MPO window and moves it horizontally, vertically and
diagonally

[How]
Create common video resolution windows and move them across the
displays. Test pass is determined by getting a crc of window location
using a single plane, then recreating this scenario using overlay.

Test panes from Start->End1, Start->End2 and Start->End3

                  CRTC#1
    Start
    +--------+--------+--------+
    |Primary |  -->   |Primary | End1
    +--------+        +--------+
    |  |      \      Overlay   |
    |  v        *              |
    +--------+    \   +--------+
    |Primary |        |Primary | End2
    +--------+--------+--------+
     End3

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 tests/amdgpu/amd_plane.c | 261 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 261 insertions(+)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 5666b9e7..09fcf3eb 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -26,6 +26,13 @@
 
 /* Maximum pipes on any AMD ASIC. */
 #define MAX_PIPES 6
+#define DISPLAYS_TO_TEST 2
+
+/* (De)gamma LUT. */
+typedef struct lut {
+	struct drm_color_lut *data;
+	uint32_t size;
+} lut_t;
 
 /* Common test data. */
 typedef struct data {
@@ -79,6 +86,63 @@ static const drmModeModeInfo test_mode_2 = {
 	.vscan = 0,
 };
 
+static const drmModeModeInfo test_mode_3 = {
+	.name = "3840x2160 Test",
+	.vrefresh = 60,
+	.clock = 594000,
+	.hdisplay = 3840,
+	.hsync_start = 4016,
+	.hsync_end = 4104,
+	.htotal = 4400,
+	.vdisplay = 2160,
+	.vsync_start = 2168,
+	.vsync_end = 2178,
+	.vtotal = 2250,
+	.type = DRM_MODE_TYPE_DRIVER,
+	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+	.hskew = 0,
+	.vscan = 0,
+};
+
+static void lut_init(lut_t *lut, uint32_t size)
+{
+	igt_assert(size > 0);
+	lut->size = size;
+	lut->data = malloc(size * sizeof(struct drm_color_lut));
+	igt_assert(lut);
+}
+static void lut_gen(lut_t *lut)
+{
+	uint32_t i;
+	/* 10% threshold */
+	uint32_t threshold = (256 * 10) / 100;
+
+	for (i = 0; i < threshold; ++i) {
+		uint32_t v = 0;
+		lut->data[i].red = v;
+		lut->data[i].blue = v;
+		lut->data[i].green = v;
+	}
+	for (i = threshold; i < lut->size; ++i) {
+		uint32_t v = 0xffff;
+		lut->data[i].red = v;
+		lut->data[i].blue = v;
+		lut->data[i].green = v;
+	}
+}
+static void lut_free(lut_t *lut)
+{
+	if (lut->data) {
+		free(lut->data);
+		lut->data = NULL;
+	}
+	lut->size = 0;
+}
+
+enum test {
+	MPO_SINGLE_PAN
+};
+
 static void test_init(data_t *data)
 {
 	igt_display_t *display = &data->display;
@@ -174,10 +238,205 @@ static void draw_color_alpha(igt_fb_t *fb, int x, int y, int w, int h,
 		             double r, double g, double b, double a)
 {
 	cairo_t *cr = igt_get_cairo_ctx(fb->fd, fb);
+	cairo_set_operator(cr, CAIRO_OPERATOR_SOURCE);
 	igt_paint_color_alpha(cr, x, y, w, h, r, g, b, a);
 	igt_put_cairo_ctx(cr);
 }
 
+struct fbc {
+	igt_fb_t ref_primary;
+	igt_fb_t test_primary;
+	igt_fb_t test_overlay;
+	igt_crc_t ref_crc;
+};
+
+/* Sets the regamma LUT. */
+static void set_regamma_lut(data_t *data, lut_t const *lut, int n)
+{
+	size_t size = lut ? sizeof(lut->data) * lut->size : 0;
+	const void *ptr = lut ? lut->data : NULL;
+	igt_pipe_obj_replace_prop_blob(data->pipe[n], IGT_CRTC_GAMMA_LUT, ptr,
+				       size);
+}
+
+/*
+ * Compares the result of white backgroud with white window with and without MPO
+ *
+ * Reference crc:
+ * Draws a White background of size (pw,ph).
+ *
+ * Test crc:
+ * Draws a White Overlay of size (pw,ph) then creates a cutout of size (p,w) at location (x,y)
+ * Draws a White Primary plane of size (p,w) at location (x,y) (under the overlay)
+ *
+ * NOTE: The reason for using White+White is to speed up the crc (reuse the ref crc for all cases vs taking
+ * a ref crc per flip)
+ */
+static void test_plane(data_t *data, int n, int x, int y, int w, int h, int pw, int ph, struct fbc *fbc){
+
+	igt_crc_t test_crc;
+	igt_display_t *display = &data->display;
+
+	/* Reference: */
+
+	igt_plane_set_fb(data->primary[n], &fbc[n].ref_primary);
+
+	igt_plane_set_position(data->primary[n], 0, 0);
+	igt_plane_set_size(data->primary[n], pw, ph);
+
+	igt_display_commit_atomic(display, 0, 0);
+
+	/* Test: */
+	/* Draw a white overlay with a cutout */
+	draw_color_alpha(&fbc[n].test_overlay, 0, 0, pw, ph, 1.0, 1.0, 1.0, 1.00);
+	draw_color_alpha(&fbc[n].test_overlay, x, y, w, h, 0.0, 0.0, 0.0, 0.0);
+
+	igt_plane_set_fb(data->primary[n], &fbc[n].test_primary);
+	igt_plane_set_fb(data->overlay[n], &fbc[n].test_overlay);
+
+	/* Move the overlay to cover the cutout */
+	igt_plane_set_position(data->primary[n], x, y);
+	igt_plane_set_size(data->primary[n], w, h);
+
+	igt_display_commit_atomic(display, 0, 0);
+	igt_pipe_crc_collect_crc(data->pipe_crc[n], &test_crc);
+	igt_plane_set_fb(data->overlay[n], NULL);
+
+	igt_assert_crc_equal(&fbc[n].ref_crc, &test_crc);
+
+	/* Set window to white, this is to avoid flashing between black/white after each flip */
+	draw_color_alpha(&fbc[n].ref_primary, 0, 0, pw, ph, 1.0, 1.0, 1.0, 1.00);
+	igt_plane_set_fb(data->primary[n], &fbc[n].ref_primary);
+	igt_plane_set_position(data->primary[n], 0, 0);
+	igt_plane_set_size(data->primary[n], pw, ph);
+	igt_display_commit_atomic(display, 0, 0);
+
+
+}
+/*
+ * MPO_SINGLE_PAN: This test moves the window (w,h) horizontally, vertically and diagonally
+ * Horizontal: from top-left (0,0) to top-right (pw-w,0)
+ * Vertical: from top-left (0,0) to bottom-left (0,ph-h)
+ * Diagonal: from top-left (0,0) to bottom-right (pw-w, ph-h)
+ */
+static void test_panning_1_display(data_t *data, int display_count, int w, int h, struct fbc *fb)
+{
+	/* x and y movements */
+	int dir[3][2]= {
+		{0,1}, /* Only Y */
+		{1,0}, /* Only X */
+		{1,1}, /* Both X and Y */
+
+	};
+
+	/* # of iterations to use to move from one side to the other */
+	int it = 3;
+
+	for (int n = 0; n < display_count; n++) {
+
+		int pw = data->w[n];
+		int ph = data->h[n];
+		int dx = (pw-w)/it;
+		int dy = (ph-h)/it;
+
+		for (int i = 0; i < ARRAY_SIZE(dir); i++){
+			for (int j = 0; j <= it; j++){
+
+				int x = dx*j*dir[i][0];
+				int y = dy*j*dir[i][1];
+
+				/* No need to pan a overley that is bigger than the display */
+				if (pw <= w && ph <= h)
+					break;
+
+				test_plane(data, n, x, y, w, h, pw, ph, fb);
+
+			}
+		}
+	}
+
+	return;
+
+
+}
+
+
+/*
+ * Setup and runner for panning test. Creates common video sizes and pans them across the display
+ */
+static void test_display_mpo(data_t *data, enum test test, uint32_t format, int display_count)
+{
+
+	igt_display_t *display = &data->display;
+	uint32_t regamma_lut_size;
+	lut_t lut;
+	struct fbc fb[4];
+	int videos[][2]= {
+		{426, 240},
+		{640, 360},
+		{854, 480},
+		{1280, 720},
+		{1920, 1080},
+		{2560, 1440},
+		{3840, 2160},
+	};
+
+	test_init(data);
+
+	regamma_lut_size = igt_pipe_obj_get_prop(data->pipe[0], IGT_CRTC_GAMMA_LUT_SIZE);
+	igt_assert_lt(0, regamma_lut_size);
+	lut_init(&lut, regamma_lut_size);
+	lut_gen(&lut);
+
+	for (int n = 0; n < display_count;  n++) {
+		int w = data->w[n];
+		int h = data->h[n];
+
+		if (w == 0) {
+			force_output_mode(data, data->output[n], &test_mode_3);
+			w = data->w[n] = test_mode_3.hdisplay;
+			h = data->h[n] = test_mode_3.vdisplay;
+		}
+
+		igt_output_set_pipe(data->output[n], data->pipe_id[n]);
+
+		igt_create_fb(data->fd, w, h, DRM_FORMAT_XRGB8888, 0, &fb[n].ref_primary);
+		igt_create_color_fb(data->fd, w, h, DRM_FORMAT_XRGB8888, 0, 1.0, 1.0, 1.0, &fb[n].ref_primary);
+		igt_create_fb(data->fd, w, h, DRM_FORMAT_ARGB8888, 0, &fb[n].test_overlay);
+
+		igt_plane_set_fb(data->primary[n], &fb[n].ref_primary);
+
+		if (format == DRM_FORMAT_NV12)
+			set_regamma_lut(data, &lut,  n);
+	}
+
+	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+	for (int n = 0; n < display_count; n++)
+		igt_pipe_crc_collect_crc(data->pipe_crc[n], &fb[n].ref_crc);
+
+	for (int i = 0; i < ARRAY_SIZE(videos); ++i) {
+
+		for (int n = 0; n < display_count; n++)
+			igt_create_color_fb(data->fd, videos[i][0], videos[i][1],
+					    format, 0, 1.0, 1.0, 1.0, &fb[n].test_primary);
+
+		if (test == MPO_SINGLE_PAN)
+			test_panning_1_display(data, display_count, videos[i][0], videos[i][1], fb);
+
+		for (int n = 0; n < display_count; n++)
+			igt_remove_fb(data->fd, &fb[n].test_primary);
+	}
+
+	test_fini(data);
+
+	lut_free(&lut);
+
+	for (int n = 0; n < display_count; n++) {
+		igt_remove_fb(data->fd, &fb[n].ref_primary);
+		igt_remove_fb(data->fd, &fb[n].test_overlay);
+	}
+}
 /*
  * Compares a white 4K reference FB against a white 4K primary FB and a
  * white 4K overlay with an RGBA (0, 0, 0, 0) cutout in the center.
@@ -395,6 +654,8 @@ igt_main
 	igt_subtest("mpo-swizzle-toggle") test_mpo_swizzle_toggle(&data);
 	igt_subtest("mpo-swizzle-toggle-multihead")
 		test_mpo_swizzle_toggle_multihead(&data);
+	igt_subtest("mpo-pan-rgb") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 06/11] tests/amdgpu/amd_plane: Create mpo swap between 2 displays test
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
                     ` (4 preceding siblings ...)
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 05/11] tests/amdgpu/amd_plane: Create mpo panning test Stylon Wang
@ 2021-12-01  6:54   ` Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 07/11] tests/amdgpu/amd_plane: Create mpo scaling tests Stylon Wang
                     ` (4 subsequent siblings)
  10 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

[Why]
In a multi display MPO config the MPO window is dragged from one display
to the other. In this usecase there is an instance when the overlay is
moved from one display to the next. This test recreates the scenario
(MPO swap)

[How]
Overlay should switch to the display that has >50% of the video. This
test was created with this asumption.

The test creates common video sizes and swaps a window of size (w/2,h)
between 2 displays bezzels at the top,middle and bottom of the display.

CRTC#1           CRTC#2                CRTC#1           CRTC#2
+-------------+------------+           +-------------+------------+
|             |            |           |             |            |
|    +--------+            |           |             +--------+   |
|    |Primary |   Primary  |    <=>    |   Primary   |Primary |   |
|    |        |            |   Swap    |             |        |   |
|    +--------+            |           |             +--------+   |
|overlay      |            |           |             |Overlay     |
+-------------+------------+           +-------------+------------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 tests/amdgpu/amd_plane.c | 53 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 52 insertions(+), 1 deletion(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 09fcf3eb..fe2389df 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -140,7 +140,8 @@ static void lut_free(lut_t *lut)
 }
 
 enum test {
-	MPO_SINGLE_PAN
+	MPO_SINGLE_PAN,
+	MPO_MULTI_PAN
 };
 
 static void test_init(data_t *data)
@@ -360,6 +361,46 @@ static void test_panning_1_display(data_t *data, int display_count, int w, int h
 
 }
 
+/*
+ * MPO_MULTI_PAN: Requires 2 displays. This test swaps a window (w,h) between 2 displays at 3 different
+ * vertical locations (top, middle, bottom)
+ *
+ * MPO will usually be the 'largest' part of the video window. Which means when a window is
+ * being dragged between 2 displays there is a instance where the MPO will jump between the displays.
+ * This test should be called with w/2 to emulate the behaviour of MPO switching between displays
+ */
+static void test_panning_2_display(data_t *data, int w, int h, struct fbc *fbc)
+{
+	bool toggle = true;
+	int pw =  data->w[0];
+	int ph =  data->h[0];
+	int pw2 =  data->w[1];
+	int ph2 =  data->h[1];
+	int smallest_h = min(ph, ph2);
+	int y[] = {0, smallest_h/2-h/2, smallest_h-h};
+	int it = 3; /* # of times to swap */
+
+	/* Set y to 0 if window is bigger than one of the displays
+	 * beacause y will be negative in that case
+	 */
+	if (h >= smallest_h)
+		y[0] = y[1] = y[2] = 0;
+
+
+	for (int j = 0; j < ARRAY_SIZE(y); j++){
+		for (int i = 0; i < it; i++){
+			if (toggle)
+				test_plane(data, 0, pw-w, y[j], w, h, pw, ph, fbc);
+			else
+				test_plane(data, 1, 0, y[j], w, h, pw2, ph2, fbc);
+
+			toggle = !toggle;
+		}
+	}
+
+	return;
+
+}
 
 /*
  * Setup and runner for panning test. Creates common video sizes and pans them across the display
@@ -417,12 +458,20 @@ static void test_display_mpo(data_t *data, enum test test, uint32_t format, int
 
 	for (int i = 0; i < ARRAY_SIZE(videos); ++i) {
 
+		/* Video(mpo) should be in the middle when it transitions between displays. This
+		 * means MPO plane will be w/2
+		 */
+		if (test == MPO_MULTI_PAN)
+			videos[i][0] = videos[i][0]/2;
+
 		for (int n = 0; n < display_count; n++)
 			igt_create_color_fb(data->fd, videos[i][0], videos[i][1],
 					    format, 0, 1.0, 1.0, 1.0, &fb[n].test_primary);
 
 		if (test == MPO_SINGLE_PAN)
 			test_panning_1_display(data, display_count, videos[i][0], videos[i][1], fb);
+		if (test == MPO_MULTI_PAN)
+			test_panning_2_display(data, videos[i][0], videos[i][1], fb);
 
 		for (int n = 0; n < display_count; n++)
 			igt_remove_fb(data->fd, &fb[n].test_primary);
@@ -656,6 +705,8 @@ igt_main
 		test_mpo_swizzle_toggle_multihead(&data);
 	igt_subtest("mpo-pan-rgb") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
 	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-pan-multi-rgb") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-pan-multi-nv12") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 07/11] tests/amdgpu/amd_plane: Create mpo scaling tests
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
                     ` (5 preceding siblings ...)
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 06/11] tests/amdgpu/amd_plane: Create mpo swap between 2 displays test Stylon Wang
@ 2021-12-01  6:54   ` Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 08/11] tests/amdgpu/amd_plane: Add MPO scale and pan subtest single display option Stylon Wang
                     ` (3 subsequent siblings)
  10 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

[Why]
Resizing MPO window is a common usecase (video in windowed mode)

Our MPO feature has scaling limitations (0.25x -> 16x). So this test
creates a window of various reolutions and scales them between 0.25x -> 16x

[How]
The test creates common video sizes and scales them from (0.30x->16x).
The lower limit is 0.25 but some combination of configs fail at 0.25x so
0.30 is used as the starting point.

CRTC#1                            CRTC#1
+--------------------+           +---------------------+
| +-------+          |           | +------------+      |
| |Primary|          |           | |Primary     |      |
| +-------+          |    -->    | |            |      |
|                    |   scale   | |            |      |
|                    |           | +------------+      |
|overlay             |           |Overlay              |
+--------------------+           +---------------------+

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 tests/amdgpu/amd_plane.c | 53 ++++++++++++++++++++++++++++++++++------
 1 file changed, 46 insertions(+), 7 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index fe2389df..9506421d 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -141,7 +141,8 @@ static void lut_free(lut_t *lut)
 
 enum test {
 	MPO_SINGLE_PAN,
-	MPO_MULTI_PAN
+	MPO_MULTI_PAN,
+	MPO_SCALE
 };
 
 static void test_init(data_t *data)
@@ -273,7 +274,7 @@ static void set_regamma_lut(data_t *data, lut_t const *lut, int n)
  * NOTE: The reason for using White+White is to speed up the crc (reuse the ref crc for all cases vs taking
  * a ref crc per flip)
  */
-static void test_plane(data_t *data, int n, int x, int y, int w, int h, int pw, int ph, struct fbc *fbc){
+static void test_plane(data_t *data, int n, int x, int y, double w, double h, double scale, int pw, int ph, struct fbc *fbc){
 
 	igt_crc_t test_crc;
 	igt_display_t *display = &data->display;
@@ -290,14 +291,14 @@ static void test_plane(data_t *data, int n, int x, int y, int w, int h, int pw,
 	/* Test: */
 	/* Draw a white overlay with a cutout */
 	draw_color_alpha(&fbc[n].test_overlay, 0, 0, pw, ph, 1.0, 1.0, 1.0, 1.00);
-	draw_color_alpha(&fbc[n].test_overlay, x, y, w, h, 0.0, 0.0, 0.0, 0.0);
+	draw_color_alpha(&fbc[n].test_overlay, x, y, w*scale, h*scale, 0.0, 0.0, 0.0, 0.0);
 
 	igt_plane_set_fb(data->primary[n], &fbc[n].test_primary);
 	igt_plane_set_fb(data->overlay[n], &fbc[n].test_overlay);
 
 	/* Move the overlay to cover the cutout */
 	igt_plane_set_position(data->primary[n], x, y);
-	igt_plane_set_size(data->primary[n], w, h);
+	igt_plane_set_size(data->primary[n], w*scale, h*scale);
 
 	igt_display_commit_atomic(display, 0, 0);
 	igt_pipe_crc_collect_crc(data->pipe_crc[n], &test_crc);
@@ -350,7 +351,7 @@ static void test_panning_1_display(data_t *data, int display_count, int w, int h
 				if (pw <= w && ph <= h)
 					break;
 
-				test_plane(data, n, x, y, w, h, pw, ph, fb);
+				test_plane(data, n, x, y, w, h, 1.0, pw, ph, fb);
 
 			}
 		}
@@ -361,6 +362,40 @@ static void test_panning_1_display(data_t *data, int display_count, int w, int h
 
 }
 
+ /* MPO_SCALE: This test scales a window of size (w,h) from x1/4->x16.
+  */
+static void test_scaling_planes(data_t *data, int display_count, int w, int h, struct fbc *fb)
+{
+
+	/* Scale limit is x1/4 -> x16
+	 * some combinations of mode/window sizes fail for x0.25 so start from 0.30 -> 16
+	 */
+	double scale[]= {
+		0.30,
+		0.50,
+		0.75,
+		1.50,
+		3.00,
+		6.00,
+		12.00,
+		16.00
+
+	};
+
+	for (int n = 0; n < display_count; n++) {
+		int pw = data->w[n];
+		int ph = data->h[n];
+
+		for (int i=0;i<ARRAY_SIZE(scale);i++) {
+			/* No need to scale a overley that is bigger than the display */
+			if (pw <= w*scale[i] && ph <= h*scale[i])
+				break;
+			test_plane(data, n, 0, 0, w, h, scale[i], pw, ph, fb);
+		}
+	}
+
+	return;
+}
 /*
  * MPO_MULTI_PAN: Requires 2 displays. This test swaps a window (w,h) between 2 displays at 3 different
  * vertical locations (top, middle, bottom)
@@ -390,9 +425,9 @@ static void test_panning_2_display(data_t *data, int w, int h, struct fbc *fbc)
 	for (int j = 0; j < ARRAY_SIZE(y); j++){
 		for (int i = 0; i < it; i++){
 			if (toggle)
-				test_plane(data, 0, pw-w, y[j], w, h, pw, ph, fbc);
+				test_plane(data, 0, pw-w, y[j], w, h, 1.0, pw, ph, fbc);
 			else
-				test_plane(data, 1, 0, y[j], w, h, pw2, ph2, fbc);
+				test_plane(data, 1, 0, y[j], w, h, 1.0, pw2, ph2, fbc);
 
 			toggle = !toggle;
 		}
@@ -472,6 +507,8 @@ static void test_display_mpo(data_t *data, enum test test, uint32_t format, int
 			test_panning_1_display(data, display_count, videos[i][0], videos[i][1], fb);
 		if (test == MPO_MULTI_PAN)
 			test_panning_2_display(data, videos[i][0], videos[i][1], fb);
+		if(test == MPO_SCALE)
+			test_scaling_planes(data, display_count, videos[i][0], videos[i][1], fb);
 
 		for (int n = 0; n < display_count; n++)
 			igt_remove_fb(data->fd, &fb[n].test_primary);
@@ -707,6 +744,8 @@ igt_main
 	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 	igt_subtest("mpo-pan-multi-rgb") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
 	igt_subtest("mpo-pan-multi-nv12") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-scale-rgb") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-scale-nv12") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 08/11] tests/amdgpu/amd_plane: Add MPO scale and pan subtest single display option
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
                     ` (6 preceding siblings ...)
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 07/11] tests/amdgpu/amd_plane: Create mpo scaling tests Stylon Wang
@ 2021-12-01  6:54   ` Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 09/11] tests/amdgpu/amd_plane: Add full screen scaling test case Stylon Wang
                     ` (2 subsequent siblings)
  10 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad.Othman, Victor Lu, Hayden.Goodfellow

From: Victor Lu <victorchengchi.lu@amd.com>

[Why]
The MPO scale and pan subtests is valid with one display and our current
CI setup only has one display.

[How]
Change the MPO scale and pan subtests to be single display and add
"-multihead" subtests for the two for the original dual display config

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
---
 tests/amdgpu/amd_plane.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 9506421d..12669239 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -740,12 +740,16 @@ igt_main
 	igt_subtest("mpo-swizzle-toggle") test_mpo_swizzle_toggle(&data);
 	igt_subtest("mpo-swizzle-toggle-multihead")
 		test_mpo_swizzle_toggle_multihead(&data);
-	igt_subtest("mpo-pan-rgb") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-pan-rgb") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, 1);
+	igt_subtest("mpo-pan-rgb-multihead") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, 1);
+	igt_subtest("mpo-pan-nv12-multihead") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 	igt_subtest("mpo-pan-multi-rgb") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
 	igt_subtest("mpo-pan-multi-nv12") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-scale-rgb") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-scale-nv12") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-scale-rgb") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, 1);
+	igt_subtest("mpo-scale-rgb-multihead") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_subtest("mpo-scale-nv12") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, 1);
+	igt_subtest("mpo-scale-nv12-multihead") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 09/11] tests/amdgpu/amd_plane: Add full screen scaling test case
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
                     ` (7 preceding siblings ...)
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 08/11] tests/amdgpu/amd_plane: Add MPO scale and pan subtest single display option Stylon Wang
@ 2021-12-01  6:54   ` Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 10/11] tests/amdgpu/amd_plane: Ensure pipes are enabled before accessing Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 11/11] tests/amdgpu/amd_plane: Add P010 format to MPO tests and add test descriptions Stylon Wang
  10 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

[Why]
Full screen scaling is a common usecase

[How]
Rework the scaling tests to add a 'fullscreen' test case. Change the
test_plane function to use "dst_w/h" instead of a scale multiplier. This
way we can easily add a full screen scale multiplier.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 tests/amdgpu/amd_plane.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 12669239..66302ebf 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -274,7 +274,7 @@ static void set_regamma_lut(data_t *data, lut_t const *lut, int n)
  * NOTE: The reason for using White+White is to speed up the crc (reuse the ref crc for all cases vs taking
  * a ref crc per flip)
  */
-static void test_plane(data_t *data, int n, int x, int y, double w, double h, double scale, int pw, int ph, struct fbc *fbc){
+static void test_plane(data_t *data, int n, int x, int y, double w, double h, double dw, double dh, int pw, int ph, struct fbc *fbc){
 
 	igt_crc_t test_crc;
 	igt_display_t *display = &data->display;
@@ -291,14 +291,14 @@ static void test_plane(data_t *data, int n, int x, int y, double w, double h, do
 	/* Test: */
 	/* Draw a white overlay with a cutout */
 	draw_color_alpha(&fbc[n].test_overlay, 0, 0, pw, ph, 1.0, 1.0, 1.0, 1.00);
-	draw_color_alpha(&fbc[n].test_overlay, x, y, w*scale, h*scale, 0.0, 0.0, 0.0, 0.0);
+	draw_color_alpha(&fbc[n].test_overlay, x, y, dw, dh, 0.0, 0.0, 0.0, 0.0);
 
 	igt_plane_set_fb(data->primary[n], &fbc[n].test_primary);
 	igt_plane_set_fb(data->overlay[n], &fbc[n].test_overlay);
 
 	/* Move the overlay to cover the cutout */
 	igt_plane_set_position(data->primary[n], x, y);
-	igt_plane_set_size(data->primary[n], w*scale, h*scale);
+	igt_plane_set_size(data->primary[n], dw, dh);
 
 	igt_display_commit_atomic(display, 0, 0);
 	igt_pipe_crc_collect_crc(data->pipe_crc[n], &test_crc);
@@ -351,7 +351,7 @@ static void test_panning_1_display(data_t *data, int display_count, int w, int h
 				if (pw <= w && ph <= h)
 					break;
 
-				test_plane(data, n, x, y, w, h, 1.0, pw, ph, fb);
+				test_plane(data, n, x, y, w, h, w, h, pw, ph, fb);
 
 			}
 		}
@@ -390,8 +390,11 @@ static void test_scaling_planes(data_t *data, int display_count, int w, int h, s
 			/* No need to scale a overley that is bigger than the display */
 			if (pw <= w*scale[i] && ph <= h*scale[i])
 				break;
-			test_plane(data, n, 0, 0, w, h, scale[i], pw, ph, fb);
+			test_plane(data, n, 0, 0, w, h, w*scale[i], h*scale[i], pw, ph, fb);
 		}
+
+		/* Test Fullscreen scale*/
+		test_plane(data, n, 0, 0, w, h, pw, ph, pw, ph, fb);
 	}
 
 	return;
@@ -425,9 +428,9 @@ static void test_panning_2_display(data_t *data, int w, int h, struct fbc *fbc)
 	for (int j = 0; j < ARRAY_SIZE(y); j++){
 		for (int i = 0; i < it; i++){
 			if (toggle)
-				test_plane(data, 0, pw-w, y[j], w, h, 1.0, pw, ph, fbc);
+				test_plane(data, 0, pw-w, y[j], w, h, w, h, pw, ph, fbc);
 			else
-				test_plane(data, 1, 0, y[j], w, h, 1.0, pw2, ph2, fbc);
+				test_plane(data, 1, 0, y[j], w, h, w, h, pw2, ph2, fbc);
 
 			toggle = !toggle;
 		}
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 10/11] tests/amdgpu/amd_plane: Ensure pipes are enabled before accessing
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
                     ` (8 preceding siblings ...)
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 09/11] tests/amdgpu/amd_plane: Add full screen scaling test case Stylon Wang
@ 2021-12-01  6:54   ` Stylon Wang
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 11/11] tests/amdgpu/amd_plane: Add P010 format to MPO tests and add test descriptions Stylon Wang
  10 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad.Othman, Anson Jacob, Hayden.Goodfellow

From: Anson Jacob <Anson.Jacob@amd.com>

Couple of tests were accessing pipe's without ensuring if they are
enabled or not. Using for_each_pipe macro to do so.

Signed-off-by: Anson Jacob <Anson.Jacob@amd.com>
---
 tests/amdgpu/amd_plane.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index 66302ebf..e4c7dca3 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -150,9 +150,9 @@ static void test_init(data_t *data)
 	igt_display_t *display = &data->display;
 	int i, n, max_pipes = display->n_pipes;
 
-	for (i = 0; i < max_pipes; ++i) {
+	for_each_pipe(display, i) {
 		data->pipe_id[i] = PIPE_A + i;
-		data->pipe[i] = &data->display.pipes[data->pipe_id[i]];
+		data->pipe[i] = &display->pipes[data->pipe_id[i]];
 		data->primary[i] = igt_pipe_get_plane_type(
 			data->pipe[i], DRM_PLANE_TYPE_PRIMARY);
 		data->overlay[i] = igt_pipe_get_plane_type_index(
@@ -188,9 +188,9 @@ static void test_init(data_t *data)
 static void test_fini(data_t *data)
 {
 	igt_display_t *display = &data->display;
-	int i, max_pipes = display->n_pipes;
+	int i;
 
-	for (i = 0; i < max_pipes; ++i) {
+	for_each_pipe(display, i) {
 		igt_pipe_crc_free(data->pipe_crc[i]);
 	}
 
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* [igt-dev] [PATCH i-g-t v2 11/11] tests/amdgpu/amd_plane: Add P010 format to MPO tests and add test descriptions
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
                     ` (9 preceding siblings ...)
  2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 10/11] tests/amdgpu/amd_plane: Ensure pipes are enabled before accessing Stylon Wang
@ 2021-12-01  6:54   ` Stylon Wang
  10 siblings, 0 replies; 26+ messages in thread
From: Stylon Wang @ 2021-12-01  6:54 UTC (permalink / raw)
  To: igt-dev; +Cc: Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

Signed-off-by: Stylon Wang <stylon.wang@amd.com>
---
 tests/amdgpu/amd_plane.c | 64 +++++++++++++++++++++++++++++++++-------
 1 file changed, 54 insertions(+), 10 deletions(-)

diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c
index e4c7dca3..faaa1b87 100644
--- a/tests/amdgpu/amd_plane.c
+++ b/tests/amdgpu/amd_plane.c
@@ -24,6 +24,8 @@
 #include "libdrm/amdgpu.h"
 #include "libdrm/amdgpu_drm.h"
 
+IGT_TEST_DESCRIPTION("Tests for Multi Plane Overlay for single and dual displays");
+
 /* Maximum pipes on any AMD ASIC. */
 #define MAX_PIPES 6
 #define DISPLAYS_TO_TEST 2
@@ -485,7 +487,7 @@ static void test_display_mpo(data_t *data, enum test test, uint32_t format, int
 
 		igt_plane_set_fb(data->primary[n], &fb[n].ref_primary);
 
-		if (format == DRM_FORMAT_NV12)
+		if (format == DRM_FORMAT_NV12 || format == DRM_FORMAT_P010)
 			set_regamma_lut(data, &lut,  n);
 	}
 
@@ -739,20 +741,62 @@ igt_main
 		igt_display_require_output(&data.display);
 	}
 
+	igt_describe("MPO with 4K planes");
 	igt_subtest("test-mpo-4k") test_mpo_4k(&data);
+	igt_describe("MPO with tiled and linear buffers");
 	igt_subtest("mpo-swizzle-toggle") test_mpo_swizzle_toggle(&data);
+	igt_describe("MPO with tiled and linear buffers on dual displays");
 	igt_subtest("mpo-swizzle-toggle-multihead")
 		test_mpo_swizzle_toggle_multihead(&data);
-	igt_subtest("mpo-pan-rgb") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, 1);
-	igt_subtest("mpo-pan-rgb-multihead") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-pan-nv12") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, 1);
-	igt_subtest("mpo-pan-nv12-multihead") test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-pan-multi-rgb") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-pan-multi-nv12") test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-scale-rgb") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, 1);
-	igt_subtest("mpo-scale-rgb-multihead") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
-	igt_subtest("mpo-scale-nv12") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, 1);
+
+	igt_describe("MPO and moving RGB primary plane around");
+	igt_subtest("mpo-pan-rgb")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, 1);
+	igt_describe("MPO and moving RGB primary plane around with dual displays");
+	igt_subtest("mpo-pan-rgb-multihead")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+
+	igt_describe("MPO and moving NV12 primary plane around");
+	igt_subtest("mpo-pan-nv12")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, 1);
+	igt_describe("MPO and moving NV12 primary plane around with dual displays");
+	igt_subtest("mpo-pan-nv12-multihead")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+
+	igt_describe("MPO and moving P010 primary plane around");
+	igt_subtest("mpo-pan-p010")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_P010, 1);
+	igt_describe("MPO and moving P010 primary plane around with dual displays");
+	igt_subtest("mpo-pan-p010-multihead")
+		test_display_mpo(&data, MPO_SINGLE_PAN, DRM_FORMAT_P010, DISPLAYS_TO_TEST);
+
+	igt_describe("MPO and moving RGB primary plane between 2 displays");
+	igt_subtest("mpo-pan-multi-rgb")
+		test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_describe("MPO and moving NV12 primary plane between 2 displays");
+	igt_subtest("mpo-pan-multi-nv12")
+		test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_describe("MPO and moving P010 primary plane between 2 displays");
+	igt_subtest("mpo-pan-multi-p010")
+		test_display_mpo(&data, MPO_MULTI_PAN, DRM_FORMAT_P010, DISPLAYS_TO_TEST);
+
+	igt_describe("MPO and scaling RGB primary plane");
+	igt_subtest("mpo-scale-rgb")
+		test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, 1);
+	igt_describe("MPO and scaling RGB primary plane with 2 displays");
+	igt_subtest("mpo-scale-rgb-multihead")
+		test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_XRGB8888, DISPLAYS_TO_TEST);
+	igt_describe("MPO and scaling NV12 primary plane");
+	igt_subtest("mpo-scale-nv12")
+		test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, 1);
+	igt_describe("MPO and scaling NV12 primary plane with 2 displays");
 	igt_subtest("mpo-scale-nv12-multihead") test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_NV12, DISPLAYS_TO_TEST);
+	igt_describe("MPO and scaling P010 primary plane");
+	igt_subtest("mpo-scale-p010")
+		test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_P010, 1);
+	igt_describe("MPO and scaling P010 primary plane with 2 displays");
+	igt_subtest("mpo-scale-p010-multihead")
+		test_display_mpo(&data, MPO_SCALE, DRM_FORMAT_P010, DISPLAYS_TO_TEST);
 
 	igt_fixture
 	{
-- 
2.33.1

^ permalink raw reply related	[flat|nested] 26+ messages in thread

* Re: [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay
  2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
                   ` (12 preceding siblings ...)
  2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
@ 2021-12-01 22:09 ` Rodrigo Siqueira Jordao
  13 siblings, 0 replies; 26+ messages in thread
From: Rodrigo Siqueira Jordao @ 2021-12-01 22:09 UTC (permalink / raw)
  To: Stylon Wang, igt-dev
  Cc: anson.jacob, Bhawanpreet.Lakha, Ahmad.Othman, Hayden.Goodfellow

Hi Stylon,

I think your patch need has merge conflict in the upstream.

Maybe rebase your change in the latest code from the master, and resend 
it as a V2.

Thanks
Siqueira

On 2021-11-30 3:34 a.m., Stylon Wang wrote:
> A series of new tests on MPO is added to tests/amdgpu/amd_plane.
> 
> Currently most of the sub-tests are AMD-specific and concerns with
> video use cases from projects.
> 
> Ahmad Othman (1):
>    tests/amdgpu/amd_plane: fixes for test-4k-mpo
> 
> Anson Jacob (1):
>    tests/amdgpu/amd_plane: Ensure pipes are enabled before accessing
> 
> Bhawanpreet Lakha (4):
>    tests/amdgpu/amd_plane: Create mpo panning test
>    tests/amdgpu/amd_plane: Create mpo swap between 2 displays test
>    tests/amdgpu/amd_plane: Create mpo scaling tests
>    tests/amdgpu/amd_plane: Add full screen scaling test case
> 
> Nicholas Kazlauskas (1):
>    tests/amdgpu/amd_plane: Add MPO swizzle mode toggle test
> 
> Stylon Wang (1):
>    tests/amdgpu/amd_plane: Add P010 format to MPO tests and add test
>      descriptions
> 
> Victor Lu (3):
>    tests/amdgpu/amd_plane: Introduced 4K MPO test
>    tests/amdgpu/amd_plane: Switch mpo-swizzle-toggle to single-head
>    tests/amdgpu/amd_plane: Add MPO scale and pan subtest single display
>      option
> 
>   tests/amdgpu/amd_plane.c | 805 +++++++++++++++++++++++++++++++++++++++
>   tests/amdgpu/meson.build |   1 +
>   2 files changed, 806 insertions(+)
>   create mode 100644 tests/amdgpu/amd_plane.c
> 

^ permalink raw reply	[flat|nested] 26+ messages in thread

end of thread, other threads:[~2021-12-01 22:09 UTC | newest]

Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-30  8:34 [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Stylon Wang
2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 01/11] tests/amdgpu/amd_plane: Introduced 4K MPO test Stylon Wang
2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 02/11] tests/amdgpu/amd_plane: Add MPO swizzle mode toggle test Stylon Wang
2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 03/11] tests/amdgpu/amd_plane: fixes for test-4k-mpo Stylon Wang
2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 04/11] tests/amdgpu/amd_plane: Switch mpo-swizzle-toggle to single-head Stylon Wang
2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 05/11] tests/amdgpu/amd_plane: Create mpo panning test Stylon Wang
2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 06/11] tests/amdgpu/amd_plane: Create mpo swap between 2 displays test Stylon Wang
2021-11-30  8:34 ` [igt-dev] [PATCH i-g-t 07/11] tests/amdgpu/amd_plane: Create mpo scaling tests Stylon Wang
2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 08/11] tests/amdgpu/amd_plane: Add MPO scale and pan subtest single display option Stylon Wang
2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 09/11] tests/amdgpu/amd_plane: Add full screen scaling test case Stylon Wang
2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 10/11] tests/amdgpu/amd_plane: Ensure pipes are enabled before accessing Stylon Wang
2021-11-30  8:35 ` [igt-dev] [PATCH i-g-t 11/11] tests/amdgpu/amd_plane: Add P010 format to MPO tests and add test descriptions Stylon Wang
2021-11-30 11:10 ` [igt-dev] ✗ Fi.CI.BUILD: failure for Create tests for multi-plane overlay Patchwork
2021-12-01  6:54 ` [igt-dev] [PATCH i-g-t v2 00/11] " Stylon Wang
2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 01/11] tests/amdgpu/amd_plane: Introduced 4K MPO test Stylon Wang
2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 02/11] tests/amdgpu/amd_plane: Add MPO swizzle mode toggle test Stylon Wang
2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 03/11] tests/amdgpu/amd_plane: fixes for test-4k-mpo Stylon Wang
2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 04/11] tests/amdgpu/amd_plane: Switch mpo-swizzle-toggle to single-head Stylon Wang
2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 05/11] tests/amdgpu/amd_plane: Create mpo panning test Stylon Wang
2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 06/11] tests/amdgpu/amd_plane: Create mpo swap between 2 displays test Stylon Wang
2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 07/11] tests/amdgpu/amd_plane: Create mpo scaling tests Stylon Wang
2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 08/11] tests/amdgpu/amd_plane: Add MPO scale and pan subtest single display option Stylon Wang
2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 09/11] tests/amdgpu/amd_plane: Add full screen scaling test case Stylon Wang
2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 10/11] tests/amdgpu/amd_plane: Ensure pipes are enabled before accessing Stylon Wang
2021-12-01  6:54   ` [igt-dev] [PATCH i-g-t v2 11/11] tests/amdgpu/amd_plane: Add P010 format to MPO tests and add test descriptions Stylon Wang
2021-12-01 22:09 ` [igt-dev] [PATCH i-g-t 00/11] Create tests for multi-plane overlay Rodrigo Siqueira Jordao

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