* [linux-next:master 2889/4301] arch/powerpc/kvm/book3s_hv_p9_entry.c:771:14: error: variable 'ri_set' set but not used
@ 2021-12-01 0:22 kernel test robot
0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2021-12-01 0:22 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 16514 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: 34f255a1e91ab44ff8926cf8294ff9144e62e861
commit: f08cbf5c7d1f86f12143a1dce23740411b03a807 [2889/4301] KVM: PPC: Book3S HV P9: Avoid changing MSR[RI] in entry and exit
config: powerpc64-defconfig (https://download.01.org/0day-ci/archive/20211201/202112010857.asG6G5sT-lkp(a)intel.com/config)
compiler: powerpc64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=f08cbf5c7d1f86f12143a1dce23740411b03a807
git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
git fetch --no-tags linux-next master
git checkout f08cbf5c7d1f86f12143a1dce23740411b03a807
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=powerpc SHELL=/bin/bash arch/powerpc/kvm/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
arch/powerpc/kvm/book3s_hv_p9_entry.c: In function 'kvmhv_vcpu_entry_p9':
>> arch/powerpc/kvm/book3s_hv_p9_entry.c:771:14: error: variable 'ri_set' set but not used [-Werror=unused-but-set-variable]
771 | bool ri_set;
| ^~~~~~
cc1: all warnings being treated as errors
vim +/ri_set +771 arch/powerpc/kvm/book3s_hv_p9_entry.c
b49c65c5f9f1da Nicholas Piggin 2021-11-23 761
cb2553a093093a Nicholas Piggin 2021-11-23 762 int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr, u64 *tb)
c00366e2375408 Nicholas Piggin 2021-05-28 763 {
d5f48019457742 Nicholas Piggin 2021-11-23 764 struct p9_host_os_sprs host_os_sprs;
c00366e2375408 Nicholas Piggin 2021-05-28 765 struct kvm *kvm = vcpu->kvm;
079a09a500c399 Nicholas Piggin 2021-05-28 766 struct kvm_nested_guest *nested = vcpu->arch.nested;
c00366e2375408 Nicholas Piggin 2021-05-28 767 struct kvmppc_vcore *vc = vcpu->arch.vcore;
3c1a4322bba79a Nicholas Piggin 2021-11-23 768 s64 hdec, dec;
cb2553a093093a Nicholas Piggin 2021-11-23 769 u64 purr, spurr;
89d35b23910158 Nicholas Piggin 2021-05-28 770 u64 *exsave;
6d770e3fe9a120 Nicholas Piggin 2021-05-28 @771 bool ri_set;
89d35b23910158 Nicholas Piggin 2021-05-28 772 int trap;
68e3baaca8c56b Nicholas Piggin 2021-05-28 773 unsigned long msr;
68e3baaca8c56b Nicholas Piggin 2021-05-28 774 unsigned long host_hfscr;
68e3baaca8c56b Nicholas Piggin 2021-05-28 775 unsigned long host_ciabr;
68e3baaca8c56b Nicholas Piggin 2021-05-28 776 unsigned long host_dawr0;
68e3baaca8c56b Nicholas Piggin 2021-05-28 777 unsigned long host_dawrx0;
68e3baaca8c56b Nicholas Piggin 2021-05-28 778 unsigned long host_psscr;
a089a6869e7f61 Nicholas Piggin 2021-11-23 779 unsigned long host_hpsscr;
68e3baaca8c56b Nicholas Piggin 2021-05-28 780 unsigned long host_pidr;
68e3baaca8c56b Nicholas Piggin 2021-05-28 781 unsigned long host_dawr1;
68e3baaca8c56b Nicholas Piggin 2021-05-28 782 unsigned long host_dawrx1;
c00366e2375408 Nicholas Piggin 2021-05-28 783
cb2553a093093a Nicholas Piggin 2021-11-23 784 hdec = time_limit - *tb;
c00366e2375408 Nicholas Piggin 2021-05-28 785 if (hdec < 0)
c00366e2375408 Nicholas Piggin 2021-05-28 786 return BOOK3S_INTERRUPT_HV_DECREMENTER;
c00366e2375408 Nicholas Piggin 2021-05-28 787
41f779917669fc Nicholas Piggin 2021-05-28 788 WARN_ON_ONCE(vcpu->arch.shregs.msr & MSR_HV);
41f779917669fc Nicholas Piggin 2021-05-28 789 WARN_ON_ONCE(!(vcpu->arch.shregs.msr & MSR_ME));
41f779917669fc Nicholas Piggin 2021-05-28 790
a32ed1bb70723e Nicholas Piggin 2021-05-28 791 start_timing(vcpu, &vcpu->arch.rm_entry);
a32ed1bb70723e Nicholas Piggin 2021-05-28 792
41f779917669fc Nicholas Piggin 2021-05-28 793 vcpu->arch.ceded = 0;
41f779917669fc Nicholas Piggin 2021-05-28 794
b49c65c5f9f1da Nicholas Piggin 2021-11-23 795 /* Save MSR for restore, with EE clear. */
b49c65c5f9f1da Nicholas Piggin 2021-11-23 796 msr = mfmsr() & ~MSR_EE;
b49c65c5f9f1da Nicholas Piggin 2021-11-23 797
68e3baaca8c56b Nicholas Piggin 2021-05-28 798 host_hfscr = mfspr(SPRN_HFSCR);
68e3baaca8c56b Nicholas Piggin 2021-05-28 799 host_ciabr = mfspr(SPRN_CIABR);
a089a6869e7f61 Nicholas Piggin 2021-11-23 800 host_psscr = mfspr(SPRN_PSSCR_PR);
a089a6869e7f61 Nicholas Piggin 2021-11-23 801 if (cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
a089a6869e7f61 Nicholas Piggin 2021-11-23 802 host_hpsscr = mfspr(SPRN_PSSCR);
68e3baaca8c56b Nicholas Piggin 2021-05-28 803 host_pidr = mfspr(SPRN_PID);
9c75f65f3583b0 Nicholas Piggin 2021-11-23 804
9c75f65f3583b0 Nicholas Piggin 2021-11-23 805 if (dawr_enabled()) {
9c75f65f3583b0 Nicholas Piggin 2021-11-23 806 host_dawr0 = mfspr(SPRN_DAWR0);
9c75f65f3583b0 Nicholas Piggin 2021-11-23 807 host_dawrx0 = mfspr(SPRN_DAWRX0);
68e3baaca8c56b Nicholas Piggin 2021-05-28 808 if (cpu_has_feature(CPU_FTR_DAWR1)) {
68e3baaca8c56b Nicholas Piggin 2021-05-28 809 host_dawr1 = mfspr(SPRN_DAWR1);
68e3baaca8c56b Nicholas Piggin 2021-05-28 810 host_dawrx1 = mfspr(SPRN_DAWRX1);
68e3baaca8c56b Nicholas Piggin 2021-05-28 811 }
9c75f65f3583b0 Nicholas Piggin 2021-11-23 812 }
68e3baaca8c56b Nicholas Piggin 2021-05-28 813
9a1e530bbbdaa2 Nicholas Piggin 2021-11-23 814 local_paca->kvm_hstate.host_purr = mfspr(SPRN_PURR);
9a1e530bbbdaa2 Nicholas Piggin 2021-11-23 815 local_paca->kvm_hstate.host_spurr = mfspr(SPRN_SPURR);
9a1e530bbbdaa2 Nicholas Piggin 2021-11-23 816
d5f48019457742 Nicholas Piggin 2021-11-23 817 save_p9_host_os_sprs(&host_os_sprs);
d5f48019457742 Nicholas Piggin 2021-11-23 818
b49c65c5f9f1da Nicholas Piggin 2021-11-23 819 msr = kvmppc_msr_hard_disable_set_facilities(vcpu, msr);
d5f48019457742 Nicholas Piggin 2021-11-23 820 if (lazy_irq_pending()) {
d5f48019457742 Nicholas Piggin 2021-11-23 821 trap = 0;
d5f48019457742 Nicholas Piggin 2021-11-23 822 goto out;
d5f48019457742 Nicholas Piggin 2021-11-23 823 }
d5f48019457742 Nicholas Piggin 2021-11-23 824
d5f48019457742 Nicholas Piggin 2021-11-23 825 if (unlikely(load_vcpu_state(vcpu, &host_os_sprs)))
d5f48019457742 Nicholas Piggin 2021-11-23 826 msr = mfmsr(); /* MSR may have been updated */
d5f48019457742 Nicholas Piggin 2021-11-23 827
6547af3eba88e4 Nicholas Piggin 2021-11-23 828 if (vc->tb_offset) {
cb2553a093093a Nicholas Piggin 2021-11-23 829 u64 new_tb = *tb + vc->tb_offset;
6547af3eba88e4 Nicholas Piggin 2021-11-23 830 mtspr(SPRN_TBU40, new_tb);
cb2553a093093a Nicholas Piggin 2021-11-23 831 if ((mftb() & 0xffffff) < (new_tb & 0xffffff)) {
cb2553a093093a Nicholas Piggin 2021-11-23 832 new_tb += 0x1000000;
cb2553a093093a Nicholas Piggin 2021-11-23 833 mtspr(SPRN_TBU40, new_tb);
cb2553a093093a Nicholas Piggin 2021-11-23 834 }
cb2553a093093a Nicholas Piggin 2021-11-23 835 *tb = new_tb;
6547af3eba88e4 Nicholas Piggin 2021-11-23 836 vc->tb_offset_applied = vc->tb_offset;
6547af3eba88e4 Nicholas Piggin 2021-11-23 837 }
6547af3eba88e4 Nicholas Piggin 2021-11-23 838
c00366e2375408 Nicholas Piggin 2021-05-28 839 mtspr(SPRN_VTB, vc->vtb);
c00366e2375408 Nicholas Piggin 2021-05-28 840 mtspr(SPRN_PURR, vcpu->arch.purr);
c00366e2375408 Nicholas Piggin 2021-05-28 841 mtspr(SPRN_SPURR, vcpu->arch.spurr);
c00366e2375408 Nicholas Piggin 2021-05-28 842
34e02d555d8fa3 Nicholas Piggin 2021-11-23 843 if (vc->pcr)
34e02d555d8fa3 Nicholas Piggin 2021-11-23 844 mtspr(SPRN_PCR, vc->pcr | PCR_MASK);
34e02d555d8fa3 Nicholas Piggin 2021-11-23 845 if (vc->dpdes)
34e02d555d8fa3 Nicholas Piggin 2021-11-23 846 mtspr(SPRN_DPDES, vc->dpdes);
34e02d555d8fa3 Nicholas Piggin 2021-11-23 847
c00366e2375408 Nicholas Piggin 2021-05-28 848 if (dawr_enabled()) {
34e02d555d8fa3 Nicholas Piggin 2021-11-23 849 if (vcpu->arch.dawr0 != host_dawr0)
c00366e2375408 Nicholas Piggin 2021-05-28 850 mtspr(SPRN_DAWR0, vcpu->arch.dawr0);
34e02d555d8fa3 Nicholas Piggin 2021-11-23 851 if (vcpu->arch.dawrx0 != host_dawrx0)
c00366e2375408 Nicholas Piggin 2021-05-28 852 mtspr(SPRN_DAWRX0, vcpu->arch.dawrx0);
c00366e2375408 Nicholas Piggin 2021-05-28 853 if (cpu_has_feature(CPU_FTR_DAWR1)) {
34e02d555d8fa3 Nicholas Piggin 2021-11-23 854 if (vcpu->arch.dawr1 != host_dawr1)
c00366e2375408 Nicholas Piggin 2021-05-28 855 mtspr(SPRN_DAWR1, vcpu->arch.dawr1);
34e02d555d8fa3 Nicholas Piggin 2021-11-23 856 if (vcpu->arch.dawrx1 != host_dawrx1)
c00366e2375408 Nicholas Piggin 2021-05-28 857 mtspr(SPRN_DAWRX1, vcpu->arch.dawrx1);
c00366e2375408 Nicholas Piggin 2021-05-28 858 }
c00366e2375408 Nicholas Piggin 2021-05-28 859 }
34e02d555d8fa3 Nicholas Piggin 2021-11-23 860 if (vcpu->arch.ciabr != host_ciabr)
c00366e2375408 Nicholas Piggin 2021-05-28 861 mtspr(SPRN_CIABR, vcpu->arch.ciabr);
c00366e2375408 Nicholas Piggin 2021-05-28 862
a089a6869e7f61 Nicholas Piggin 2021-11-23 863
a089a6869e7f61 Nicholas Piggin 2021-11-23 864 if (cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST)) {
c00366e2375408 Nicholas Piggin 2021-05-28 865 mtspr(SPRN_PSSCR, vcpu->arch.psscr | PSSCR_EC |
c00366e2375408 Nicholas Piggin 2021-05-28 866 (local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG));
a089a6869e7f61 Nicholas Piggin 2021-11-23 867 } else {
a089a6869e7f61 Nicholas Piggin 2021-11-23 868 if (vcpu->arch.psscr != host_psscr)
a089a6869e7f61 Nicholas Piggin 2021-11-23 869 mtspr(SPRN_PSSCR_PR, vcpu->arch.psscr);
a089a6869e7f61 Nicholas Piggin 2021-11-23 870 }
c00366e2375408 Nicholas Piggin 2021-05-28 871
c00366e2375408 Nicholas Piggin 2021-05-28 872 mtspr(SPRN_HFSCR, vcpu->arch.hfscr);
c00366e2375408 Nicholas Piggin 2021-05-28 873
89d35b23910158 Nicholas Piggin 2021-05-28 874 mtspr(SPRN_HSRR0, vcpu->arch.regs.nip);
89d35b23910158 Nicholas Piggin 2021-05-28 875 mtspr(SPRN_HSRR1, (vcpu->arch.shregs.msr & ~MSR_HV) | MSR_ME);
89d35b23910158 Nicholas Piggin 2021-05-28 876
89d35b23910158 Nicholas Piggin 2021-05-28 877 /*
89d35b23910158 Nicholas Piggin 2021-05-28 878 * On POWER9 DD2.1 and below, sometimes on a Hypervisor Data Storage
89d35b23910158 Nicholas Piggin 2021-05-28 879 * Interrupt (HDSI) the HDSISR is not be updated at all.
89d35b23910158 Nicholas Piggin 2021-05-28 880 *
89d35b23910158 Nicholas Piggin 2021-05-28 881 * To work around this we put a canary value into the HDSISR before
89d35b23910158 Nicholas Piggin 2021-05-28 882 * returning to a guest and then check for this canary when we take a
89d35b23910158 Nicholas Piggin 2021-05-28 883 * HDSI. If we find the canary on a HDSI, we know the hardware didn't
89d35b23910158 Nicholas Piggin 2021-05-28 884 * update the HDSISR. In this case we return to the guest to retake the
89d35b23910158 Nicholas Piggin 2021-05-28 885 * HDSI which should correctly update the HDSISR the second time HDSI
89d35b23910158 Nicholas Piggin 2021-05-28 886 * entry.
89d35b23910158 Nicholas Piggin 2021-05-28 887 *
d55b1eccc7aa14 Nicholas Piggin 2021-11-23 888 * The "radix prefetch bug" test can be used to test for this bug, as
d55b1eccc7aa14 Nicholas Piggin 2021-11-23 889 * it also exists fo DD2.1 and below.
89d35b23910158 Nicholas Piggin 2021-05-28 890 */
d55b1eccc7aa14 Nicholas Piggin 2021-11-23 891 if (cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG))
89d35b23910158 Nicholas Piggin 2021-05-28 892 mtspr(SPRN_HDSISR, HDSISR_CANARY);
89d35b23910158 Nicholas Piggin 2021-05-28 893
41f779917669fc Nicholas Piggin 2021-05-28 894 mtspr(SPRN_SPRG0, vcpu->arch.shregs.sprg0);
41f779917669fc Nicholas Piggin 2021-05-28 895 mtspr(SPRN_SPRG1, vcpu->arch.shregs.sprg1);
41f779917669fc Nicholas Piggin 2021-05-28 896 mtspr(SPRN_SPRG2, vcpu->arch.shregs.sprg2);
41f779917669fc Nicholas Piggin 2021-05-28 897 mtspr(SPRN_SPRG3, vcpu->arch.shregs.sprg3);
41f779917669fc Nicholas Piggin 2021-05-28 898
d5f48019457742 Nicholas Piggin 2021-11-23 899 /*
d5f48019457742 Nicholas Piggin 2021-11-23 900 * It might be preferable to load_vcpu_state here, in order to get the
d5f48019457742 Nicholas Piggin 2021-11-23 901 * GPR/FP register loads executing in parallel with the previous mtSPR
d5f48019457742 Nicholas Piggin 2021-11-23 902 * instructions, but for now that can't be done because the TM handling
d5f48019457742 Nicholas Piggin 2021-11-23 903 * in load_vcpu_state can change some SPRs and vcpu state (nip, msr).
d5f48019457742 Nicholas Piggin 2021-11-23 904 * But TM could be split out if this would be a significant benefit.
d5f48019457742 Nicholas Piggin 2021-11-23 905 */
d5f48019457742 Nicholas Piggin 2021-11-23 906
f08cbf5c7d1f86 Nicholas Piggin 2021-11-23 907 /*
f08cbf5c7d1f86 Nicholas Piggin 2021-11-23 908 * MSR[RI] does not need to be cleared (and is not, for radix guests
f08cbf5c7d1f86 Nicholas Piggin 2021-11-23 909 * with no prefetch bug), because in_guest is set. If we take a SRESET
f08cbf5c7d1f86 Nicholas Piggin 2021-11-23 910 * or MCE with in_guest set but still in HV mode, then
f08cbf5c7d1f86 Nicholas Piggin 2021-11-23 911 * kvmppc_p9_bad_interrupt handles the interrupt, which effectively
f08cbf5c7d1f86 Nicholas Piggin 2021-11-23 912 * clears MSR[RI] and doesn't return.
f08cbf5c7d1f86 Nicholas Piggin 2021-11-23 913 */
f08cbf5c7d1f86 Nicholas Piggin 2021-11-23 914 WRITE_ONCE(local_paca->kvm_hstate.in_guest, KVM_GUEST_MODE_HV_P9);
f08cbf5c7d1f86 Nicholas Piggin 2021-11-23 915 barrier(); /* Open in_guest critical section */
0bf7e1b2e9a496 Nicholas Piggin 2021-05-28 916
0bf7e1b2e9a496 Nicholas Piggin 2021-05-28 917 /*
0bf7e1b2e9a496 Nicholas Piggin 2021-05-28 918 * Hash host, hash guest, or radix guest with prefetch bug, all have
0bf7e1b2e9a496 Nicholas Piggin 2021-05-28 919 * to disable the MMU before switching to guest MMU state.
0bf7e1b2e9a496 Nicholas Piggin 2021-05-28 920 */
0bf7e1b2e9a496 Nicholas Piggin 2021-05-28 921 if (!radix_enabled() || !kvm_is_radix(kvm) ||
0bf7e1b2e9a496 Nicholas Piggin 2021-05-28 922 cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG))
2e1ae9cd56f861 Nicholas Piggin 2021-05-28 923 __mtmsrd(msr & ~(MSR_IR|MSR_DR|MSR_RI), 0);
0bf7e1b2e9a496 Nicholas Piggin 2021-05-28 924
0bf7e1b2e9a496 Nicholas Piggin 2021-05-28 925 save_clear_host_mmu(kvm);
0bf7e1b2e9a496 Nicholas Piggin 2021-05-28 926
f08cbf5c7d1f86 Nicholas Piggin 2021-11-23 927 if (kvm_is_radix(kvm))
41f779917669fc Nicholas Piggin 2021-05-28 928 switch_mmu_to_guest_radix(kvm, vcpu, lpcr);
f08cbf5c7d1f86 Nicholas Piggin 2021-11-23 929 else
079a09a500c399 Nicholas Piggin 2021-05-28 930 switch_mmu_to_guest_hpt(kvm, vcpu, lpcr);
079a09a500c399 Nicholas Piggin 2021-05-28 931
079a09a500c399 Nicholas Piggin 2021-05-28 932 /* TLBIEL uses LPID=LPIDR, so run this after setting guest LPID */
0ba0e5d5a69180 Nicholas Piggin 2021-11-23 933 check_need_tlb_flush(kvm, vc->pcpu, nested);
41f779917669fc Nicholas Piggin 2021-05-28 934
41f779917669fc Nicholas Piggin 2021-05-28 935 /*
41f779917669fc Nicholas Piggin 2021-05-28 936 * P9 suppresses the HDEC exception when LPCR[HDICE] = 0,
41f779917669fc Nicholas Piggin 2021-05-28 937 * so set guest LPCR (with HDICE) before writing HDEC.
41f779917669fc Nicholas Piggin 2021-05-28 938 */
41f779917669fc Nicholas Piggin 2021-05-28 939 mtspr(SPRN_HDEC, hdec);
41f779917669fc Nicholas Piggin 2021-05-28 940
cb2553a093093a Nicholas Piggin 2021-11-23 941 mtspr(SPRN_DEC, vcpu->arch.dec_expires - *tb);
3c1a4322bba79a Nicholas Piggin 2021-11-23 942
:::::: The code at line 771 was first introduced by commit
:::::: 6d770e3fe9a120560cda66331ce5faa363400e97 KVM: PPC: Book3S HV P9: Read machine check registers while MSR[RI] is 0
:::::: TO: Nicholas Piggin <npiggin@gmail.com>
:::::: CC: Michael Ellerman <mpe@ellerman.id.au>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2021-12-01 0:22 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-01 0:22 [linux-next:master 2889/4301] arch/powerpc/kvm/book3s_hv_p9_entry.c:771:14: error: variable 'ri_set' set but not used kernel test robot
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.