* [PATCH v2 0/6] Expand display core documentation
@ 2021-12-02 16:01 ` Rodrigo Siqueira
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
Display Core (DC) is one of the components under amdgpu, and it has
multiple features directly related to the KMS API. Unfortunately, we
don't have enough documentation about DC in the upstream, which makes
the life of some external contributors a little bit more challenging.
For these reasons, this patchset reworks part of the DC documentation
and introduces a new set of details on how the display core works on DCN
IP. Another improvement that this documentation effort tries to bring is
making explicit some of our hardware-specific details to guide
user-space developers better.
In my view, it is easier to review this series if you apply it in your
local kernel and build the HTML version (make htmldocs). I'm suggesting
this approach because I added a few SVG diagrams that will be easier to
see in the HTML version. If you cannot build the documentation, try to
open the SVG images while reviewing the content. In summary, in this
series, you will find:
1. Patch 1: Re-arrange of display core documentation. This is
preparation work for the other patches, but it is also a way to expand
this documentation.
2. Patch 2 to 4: Document some common debug options related to display.
3. Patch 5: This patch provides an overview of how our display core next
works and a brief explanation of each component.
4. Patch 6: We use a lot of acronyms in our driver; for this reason, we
exposed a glossary with common terms used by display core.
Please let us know what you think we can improve in this series and what
kind of content you want to see for the next series.
Changes since V1:
- Group amdgpu documentation together.
- Create index pages.
- Mirror display folder in the documentation.
- Divide glossary based on driver context.
- Make terms more consistent and update CPLIB
- Add new acronyms to the glossary
Thanks
Siqueira
Rodrigo Siqueira (6):
Documentation/gpu: Reorganize DC documentation
Documentation/gpu: Document amdgpu_dm_visual_confirm debugfs entry
Documentation/gpu: Document pipe split visual confirmation
Documentation/gpu: How to collect DTN log
Documentation/gpu: Add basic overview of DC pipeline
Documentation/gpu: Add amdgpu and dc glossary
Documentation/gpu/amdgpu-dc.rst | 74 --
Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 +
.../gpu/amdgpu/display/config_example.svg | 414 ++++++
Documentation/gpu/amdgpu/display/dc-debug.rst | 77 ++
.../gpu/amdgpu/display/dc-glossary.rst | 243 ++++
.../amdgpu/display/dc_pipeline_overview.svg | 1125 +++++++++++++++++
.../gpu/amdgpu/display/dcn-overview.rst | 168 +++
.../gpu/amdgpu/display/display-manager.rst | 42 +
.../gpu/amdgpu/display/global_sync_vblank.svg | 485 +++++++
Documentation/gpu/amdgpu/display/index.rst | 29 +
.../gpu/{amdgpu.rst => amdgpu/index.rst} | 25 +-
Documentation/gpu/drivers.rst | 3 +-
12 files changed, 2653 insertions(+), 79 deletions(-)
delete mode 100644 Documentation/gpu/amdgpu-dc.rst
create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
create mode 100644 Documentation/gpu/amdgpu/display/config_example.svg
create mode 100644 Documentation/gpu/amdgpu/display/dc-debug.rst
create mode 100644 Documentation/gpu/amdgpu/display/dc-glossary.rst
create mode 100644 Documentation/gpu/amdgpu/display/dc_pipeline_overview.svg
create mode 100644 Documentation/gpu/amdgpu/display/dcn-overview.rst
create mode 100644 Documentation/gpu/amdgpu/display/display-manager.rst
create mode 100644 Documentation/gpu/amdgpu/display/global_sync_vblank.svg
create mode 100644 Documentation/gpu/amdgpu/display/index.rst
rename Documentation/gpu/{amdgpu.rst => amdgpu/index.rst} (95%)
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v2 0/6] Expand display core documentation
@ 2021-12-02 16:01 ` Rodrigo Siqueira
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
Display Core (DC) is one of the components under amdgpu, and it has
multiple features directly related to the KMS API. Unfortunately, we
don't have enough documentation about DC in the upstream, which makes
the life of some external contributors a little bit more challenging.
For these reasons, this patchset reworks part of the DC documentation
and introduces a new set of details on how the display core works on DCN
IP. Another improvement that this documentation effort tries to bring is
making explicit some of our hardware-specific details to guide
user-space developers better.
In my view, it is easier to review this series if you apply it in your
local kernel and build the HTML version (make htmldocs). I'm suggesting
this approach because I added a few SVG diagrams that will be easier to
see in the HTML version. If you cannot build the documentation, try to
open the SVG images while reviewing the content. In summary, in this
series, you will find:
1. Patch 1: Re-arrange of display core documentation. This is
preparation work for the other patches, but it is also a way to expand
this documentation.
2. Patch 2 to 4: Document some common debug options related to display.
3. Patch 5: This patch provides an overview of how our display core next
works and a brief explanation of each component.
4. Patch 6: We use a lot of acronyms in our driver; for this reason, we
exposed a glossary with common terms used by display core.
Please let us know what you think we can improve in this series and what
kind of content you want to see for the next series.
Changes since V1:
- Group amdgpu documentation together.
- Create index pages.
- Mirror display folder in the documentation.
- Divide glossary based on driver context.
- Make terms more consistent and update CPLIB
- Add new acronyms to the glossary
Thanks
Siqueira
Rodrigo Siqueira (6):
Documentation/gpu: Reorganize DC documentation
Documentation/gpu: Document amdgpu_dm_visual_confirm debugfs entry
Documentation/gpu: Document pipe split visual confirmation
Documentation/gpu: How to collect DTN log
Documentation/gpu: Add basic overview of DC pipeline
Documentation/gpu: Add amdgpu and dc glossary
Documentation/gpu/amdgpu-dc.rst | 74 --
Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 +
.../gpu/amdgpu/display/config_example.svg | 414 ++++++
Documentation/gpu/amdgpu/display/dc-debug.rst | 77 ++
.../gpu/amdgpu/display/dc-glossary.rst | 243 ++++
.../amdgpu/display/dc_pipeline_overview.svg | 1125 +++++++++++++++++
.../gpu/amdgpu/display/dcn-overview.rst | 168 +++
.../gpu/amdgpu/display/display-manager.rst | 42 +
.../gpu/amdgpu/display/global_sync_vblank.svg | 485 +++++++
Documentation/gpu/amdgpu/display/index.rst | 29 +
.../gpu/{amdgpu.rst => amdgpu/index.rst} | 25 +-
Documentation/gpu/drivers.rst | 3 +-
12 files changed, 2653 insertions(+), 79 deletions(-)
delete mode 100644 Documentation/gpu/amdgpu-dc.rst
create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
create mode 100644 Documentation/gpu/amdgpu/display/config_example.svg
create mode 100644 Documentation/gpu/amdgpu/display/dc-debug.rst
create mode 100644 Documentation/gpu/amdgpu/display/dc-glossary.rst
create mode 100644 Documentation/gpu/amdgpu/display/dc_pipeline_overview.svg
create mode 100644 Documentation/gpu/amdgpu/display/dcn-overview.rst
create mode 100644 Documentation/gpu/amdgpu/display/display-manager.rst
create mode 100644 Documentation/gpu/amdgpu/display/global_sync_vblank.svg
create mode 100644 Documentation/gpu/amdgpu/display/index.rst
rename Documentation/gpu/{amdgpu.rst => amdgpu/index.rst} (95%)
--
2.25.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v2 1/6] Documentation/gpu: Reorganize DC documentation
2021-12-02 16:01 ` Rodrigo Siqueira
@ 2021-12-02 16:01 ` Rodrigo Siqueira
-1 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
Display core documentation is not well organized, and it is hard to find
information due to the lack of sections. This commit reorganizes the
documentation layout, and it is preparation work for future changes.
Changes since V1:
- Christian: Group amdgpu documentation together.
- Daniel: Drop redundant amdgpu prefix.
- Jani: Create index pages.
- Yann: Mirror display folder in the documentation.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu-dc.rst | 74 -------------------
Documentation/gpu/amdgpu/display/dc-debug.rst | 4 +
.../gpu/amdgpu/display/display-manager.rst | 42 +++++++++++
Documentation/gpu/amdgpu/display/index.rst | 29 ++++++++
.../gpu/{amdgpu.rst => amdgpu/index.rst} | 18 ++++-
Documentation/gpu/drivers.rst | 3 +-
6 files changed, 91 insertions(+), 79 deletions(-)
delete mode 100644 Documentation/gpu/amdgpu-dc.rst
create mode 100644 Documentation/gpu/amdgpu/display/dc-debug.rst
create mode 100644 Documentation/gpu/amdgpu/display/display-manager.rst
create mode 100644 Documentation/gpu/amdgpu/display/index.rst
rename Documentation/gpu/{amdgpu.rst => amdgpu/index.rst} (96%)
diff --git a/Documentation/gpu/amdgpu-dc.rst b/Documentation/gpu/amdgpu-dc.rst
deleted file mode 100644
index f7ff7e1309de..000000000000
--- a/Documentation/gpu/amdgpu-dc.rst
+++ /dev/null
@@ -1,74 +0,0 @@
-===================================
-drm/amd/display - Display Core (DC)
-===================================
-
-*placeholder - general description of supported platforms, what dc is, etc.*
-
-Because it is partially shared with other operating systems, the Display Core
-Driver is divided in two pieces.
-
-1. **Display Core (DC)** contains the OS-agnostic components. Things like
- hardware programming and resource management are handled here.
-2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
- amdgpu base driver and DRM are implemented here.
-
-It doesn't help that the entire package is frequently referred to as DC. But
-with the context in mind, it should be clear.
-
-When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default for
-supported ASICs. To force disable, set `amdgpu.dc=0` on kernel command line.
-Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`.
-
-To determine if DC is loaded, search dmesg for the following entry:
-
-``Display Core initialized with <version number here>``
-
-AMDgpu Display Manager
-======================
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :doc: overview
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
- :internal:
-
-Lifecycle
----------
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :doc: DM Lifecycle
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :functions: dm_hw_init dm_hw_fini
-
-Interrupts
-----------
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
- :doc: overview
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
- :internal:
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :functions: register_hpd_handlers dm_crtc_high_irq dm_pflip_high_irq
-
-Atomic Implementation
----------------------
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :doc: atomic
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
-
-Display Core
-============
-
-**WIP**
-
-FreeSync Video
---------------
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :doc: FreeSync Video
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst b/Documentation/gpu/amdgpu/display/dc-debug.rst
new file mode 100644
index 000000000000..bbb8c3fc8eee
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/dc-debug.rst
@@ -0,0 +1,4 @@
+Display Core Debug tools
+========================
+
+TODO
diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
new file mode 100644
index 000000000000..7ce31f89d9a0
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/display-manager.rst
@@ -0,0 +1,42 @@
+======================
+AMDgpu Display Manager
+======================
+
+.. contents:: Table of Contents
+ :depth: 3
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+ :internal:
+
+Lifecycle
+=========
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :doc: DM Lifecycle
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :functions: dm_hw_init dm_hw_fini
+
+Interrupts
+==========
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+ :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+ :internal:
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :functions: register_hpd_handlers dm_crtc_high_irq dm_pflip_high_irq
+
+Atomic Implementation
+=====================
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :doc: atomic
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
new file mode 100644
index 000000000000..a443866332ac
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/index.rst
@@ -0,0 +1,29 @@
+===================================
+drm/amd/display - Display Core (DC)
+===================================
+
+*placeholder - general description of supported platforms, what dc is, etc.*
+
+Because it is partially shared with other operating systems, the Display Core
+Driver is divided in two pieces.
+
+1. **Display Core (DC)** contains the OS-agnostic components. Things like
+ hardware programming and resource management are handled here.
+2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
+ amdgpu base driver and DRM are implemented here.
+
+It doesn't help that the entire package is frequently referred to as DC. But
+with the context in mind, it should be clear.
+
+When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default for
+supported ASICs. To force disable, set `amdgpu.dc=0` on kernel command line.
+Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`.
+
+To determine if DC is loaded, search dmesg for the following entry:
+
+.. toctree::
+
+ display-manager.rst
+ dc-debug.rst
+
+``Display Core initialized with <version number here>``
diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu/index.rst
similarity index 96%
rename from Documentation/gpu/amdgpu.rst
rename to Documentation/gpu/amdgpu/index.rst
index 8ba72e898099..5c8cbf514097 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -1,6 +1,6 @@
-=========================
+==========================
drm/amdgpu AMDgpu driver
-=========================
+==========================
The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
Next (GCN) architecture.
@@ -71,7 +71,7 @@ Interrupt Handling
:internal:
IP Blocks
-------------------
+---------
.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
:doc: IP Blocks
@@ -79,6 +79,18 @@ IP Blocks
.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
:identifiers: amd_ip_block_type amd_ip_funcs
+Display Core
+============
+
+This section covers Display core.
+
+.. toctree::
+
+ display/index
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :doc: overview
+
AMDGPU XGMI Support
===================
diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst
index b4a0ed3ca961..3a52f48215a3 100644
--- a/Documentation/gpu/drivers.rst
+++ b/Documentation/gpu/drivers.rst
@@ -4,8 +4,7 @@ GPU Driver Documentation
.. toctree::
- amdgpu
- amdgpu-dc
+ amdgpu/index
i915
mcde
meson
--
2.25.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 1/6] Documentation/gpu: Reorganize DC documentation
@ 2021-12-02 16:01 ` Rodrigo Siqueira
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
Display core documentation is not well organized, and it is hard to find
information due to the lack of sections. This commit reorganizes the
documentation layout, and it is preparation work for future changes.
Changes since V1:
- Christian: Group amdgpu documentation together.
- Daniel: Drop redundant amdgpu prefix.
- Jani: Create index pages.
- Yann: Mirror display folder in the documentation.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu-dc.rst | 74 -------------------
Documentation/gpu/amdgpu/display/dc-debug.rst | 4 +
.../gpu/amdgpu/display/display-manager.rst | 42 +++++++++++
Documentation/gpu/amdgpu/display/index.rst | 29 ++++++++
.../gpu/{amdgpu.rst => amdgpu/index.rst} | 18 ++++-
Documentation/gpu/drivers.rst | 3 +-
6 files changed, 91 insertions(+), 79 deletions(-)
delete mode 100644 Documentation/gpu/amdgpu-dc.rst
create mode 100644 Documentation/gpu/amdgpu/display/dc-debug.rst
create mode 100644 Documentation/gpu/amdgpu/display/display-manager.rst
create mode 100644 Documentation/gpu/amdgpu/display/index.rst
rename Documentation/gpu/{amdgpu.rst => amdgpu/index.rst} (96%)
diff --git a/Documentation/gpu/amdgpu-dc.rst b/Documentation/gpu/amdgpu-dc.rst
deleted file mode 100644
index f7ff7e1309de..000000000000
--- a/Documentation/gpu/amdgpu-dc.rst
+++ /dev/null
@@ -1,74 +0,0 @@
-===================================
-drm/amd/display - Display Core (DC)
-===================================
-
-*placeholder - general description of supported platforms, what dc is, etc.*
-
-Because it is partially shared with other operating systems, the Display Core
-Driver is divided in two pieces.
-
-1. **Display Core (DC)** contains the OS-agnostic components. Things like
- hardware programming and resource management are handled here.
-2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
- amdgpu base driver and DRM are implemented here.
-
-It doesn't help that the entire package is frequently referred to as DC. But
-with the context in mind, it should be clear.
-
-When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default for
-supported ASICs. To force disable, set `amdgpu.dc=0` on kernel command line.
-Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`.
-
-To determine if DC is loaded, search dmesg for the following entry:
-
-``Display Core initialized with <version number here>``
-
-AMDgpu Display Manager
-======================
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :doc: overview
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
- :internal:
-
-Lifecycle
----------
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :doc: DM Lifecycle
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :functions: dm_hw_init dm_hw_fini
-
-Interrupts
-----------
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
- :doc: overview
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
- :internal:
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :functions: register_hpd_handlers dm_crtc_high_irq dm_pflip_high_irq
-
-Atomic Implementation
----------------------
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :doc: atomic
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
-
-Display Core
-============
-
-**WIP**
-
-FreeSync Video
---------------
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- :doc: FreeSync Video
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst b/Documentation/gpu/amdgpu/display/dc-debug.rst
new file mode 100644
index 000000000000..bbb8c3fc8eee
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/dc-debug.rst
@@ -0,0 +1,4 @@
+Display Core Debug tools
+========================
+
+TODO
diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
new file mode 100644
index 000000000000..7ce31f89d9a0
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/display-manager.rst
@@ -0,0 +1,42 @@
+======================
+AMDgpu Display Manager
+======================
+
+.. contents:: Table of Contents
+ :depth: 3
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+ :internal:
+
+Lifecycle
+=========
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :doc: DM Lifecycle
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :functions: dm_hw_init dm_hw_fini
+
+Interrupts
+==========
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+ :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+ :internal:
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :functions: register_hpd_handlers dm_crtc_high_irq dm_pflip_high_irq
+
+Atomic Implementation
+=====================
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :doc: atomic
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
new file mode 100644
index 000000000000..a443866332ac
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/index.rst
@@ -0,0 +1,29 @@
+===================================
+drm/amd/display - Display Core (DC)
+===================================
+
+*placeholder - general description of supported platforms, what dc is, etc.*
+
+Because it is partially shared with other operating systems, the Display Core
+Driver is divided in two pieces.
+
+1. **Display Core (DC)** contains the OS-agnostic components. Things like
+ hardware programming and resource management are handled here.
+2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
+ amdgpu base driver and DRM are implemented here.
+
+It doesn't help that the entire package is frequently referred to as DC. But
+with the context in mind, it should be clear.
+
+When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default for
+supported ASICs. To force disable, set `amdgpu.dc=0` on kernel command line.
+Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`.
+
+To determine if DC is loaded, search dmesg for the following entry:
+
+.. toctree::
+
+ display-manager.rst
+ dc-debug.rst
+
+``Display Core initialized with <version number here>``
diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu/index.rst
similarity index 96%
rename from Documentation/gpu/amdgpu.rst
rename to Documentation/gpu/amdgpu/index.rst
index 8ba72e898099..5c8cbf514097 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -1,6 +1,6 @@
-=========================
+==========================
drm/amdgpu AMDgpu driver
-=========================
+==========================
The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
Next (GCN) architecture.
@@ -71,7 +71,7 @@ Interrupt Handling
:internal:
IP Blocks
-------------------
+---------
.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
:doc: IP Blocks
@@ -79,6 +79,18 @@ IP Blocks
.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
:identifiers: amd_ip_block_type amd_ip_funcs
+Display Core
+============
+
+This section covers Display core.
+
+.. toctree::
+
+ display/index
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :doc: overview
+
AMDGPU XGMI Support
===================
diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst
index b4a0ed3ca961..3a52f48215a3 100644
--- a/Documentation/gpu/drivers.rst
+++ b/Documentation/gpu/drivers.rst
@@ -4,8 +4,7 @@ GPU Driver Documentation
.. toctree::
- amdgpu
- amdgpu-dc
+ amdgpu/index
i915
mcde
meson
--
2.25.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 2/6] Documentation/gpu: Document amdgpu_dm_visual_confirm debugfs entry
2021-12-02 16:01 ` Rodrigo Siqueira
@ 2021-12-02 16:01 ` Rodrigo Siqueira
-1 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
Display core provides a feature that makes it easy for users to debug
Multiple planes by enabling a visual notification at the bottom of each
plane. This commit introduces how to use such a feature.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 34 ++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst b/Documentation/gpu/amdgpu/display/dc-debug.rst
index bbb8c3fc8eee..532cbbd64863 100644
--- a/Documentation/gpu/amdgpu/display/dc-debug.rst
+++ b/Documentation/gpu/amdgpu/display/dc-debug.rst
@@ -1,4 +1,36 @@
+========================
Display Core Debug tools
========================
-TODO
+DC Debugfs
+==========
+
+Multiple Planes Debug
+---------------------
+
+If you want to enable or debug multiple planes in a specific user-space
+application, you can leverage a debug feature named visual confirm. For
+enabling it, you will need::
+
+ echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
+
+You need to reload your GUI to see the visual confirmation. When the plane
+configuration changes or a full update occurs there will be a colored bar at
+the bottom of each hardware plane being drawn on the screen.
+
+* The color indicates the format - For example, red is AR24 and green is NV12
+* The height of the bar indicates the index of the plane
+* Pipe split can be observed if there are two bars with a difference in height
+ covering the same plane
+
+Consider the video playback case in which a video is played in a specific
+plane, and the desktop is drawn in another plane. The video plane should
+feature one or two green bars at the bottom of the video depending on pipe
+split configuration.
+
+* There should **not** be any visual corruption
+* There should **not** be any underflow or screen flashes
+* There should **not** be any black screens
+* There should **not** be any cursor corruption
+* Multiple plane **may** be briefly disabled during window transitions or
+ resizing but should come back after the action has finished
--
2.25.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 2/6] Documentation/gpu: Document amdgpu_dm_visual_confirm debugfs entry
@ 2021-12-02 16:01 ` Rodrigo Siqueira
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
Display core provides a feature that makes it easy for users to debug
Multiple planes by enabling a visual notification at the bottom of each
plane. This commit introduces how to use such a feature.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 34 ++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst b/Documentation/gpu/amdgpu/display/dc-debug.rst
index bbb8c3fc8eee..532cbbd64863 100644
--- a/Documentation/gpu/amdgpu/display/dc-debug.rst
+++ b/Documentation/gpu/amdgpu/display/dc-debug.rst
@@ -1,4 +1,36 @@
+========================
Display Core Debug tools
========================
-TODO
+DC Debugfs
+==========
+
+Multiple Planes Debug
+---------------------
+
+If you want to enable or debug multiple planes in a specific user-space
+application, you can leverage a debug feature named visual confirm. For
+enabling it, you will need::
+
+ echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
+
+You need to reload your GUI to see the visual confirmation. When the plane
+configuration changes or a full update occurs there will be a colored bar at
+the bottom of each hardware plane being drawn on the screen.
+
+* The color indicates the format - For example, red is AR24 and green is NV12
+* The height of the bar indicates the index of the plane
+* Pipe split can be observed if there are two bars with a difference in height
+ covering the same plane
+
+Consider the video playback case in which a video is played in a specific
+plane, and the desktop is drawn in another plane. The video plane should
+feature one or two green bars at the bottom of the video depending on pipe
+split configuration.
+
+* There should **not** be any visual corruption
+* There should **not** be any underflow or screen flashes
+* There should **not** be any black screens
+* There should **not** be any cursor corruption
+* Multiple plane **may** be briefly disabled during window transitions or
+ resizing but should come back after the action has finished
--
2.25.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 3/6] Documentation/gpu: Document pipe split visual confirmation
2021-12-02 16:01 ` Rodrigo Siqueira
@ 2021-12-02 16:01 ` Rodrigo Siqueira
-1 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
Display core provides a feature that makes it easy for users to debug
Pipe Split. This commit introduces how to use such a debug option.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 28 +++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst b/Documentation/gpu/amdgpu/display/dc-debug.rst
index 532cbbd64863..6dbd21f7f59e 100644
--- a/Documentation/gpu/amdgpu/display/dc-debug.rst
+++ b/Documentation/gpu/amdgpu/display/dc-debug.rst
@@ -2,8 +2,18 @@
Display Core Debug tools
========================
-DC Debugfs
-==========
+DC Visual Confirmation
+======================
+
+Display core provides a feature named visual confirmation, which is a set of
+bars added at the scanout time by the driver to convey some specific
+information. In general, you can enable this debug option by using::
+
+ echo <N> > /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
+
+Where `N` is an integer number for some specific scenarios that the developer
+wants to enable, you will see some of these debug cases in the following
+subsection.
Multiple Planes Debug
---------------------
@@ -34,3 +44,17 @@ split configuration.
* There should **not** be any cursor corruption
* Multiple plane **may** be briefly disabled during window transitions or
resizing but should come back after the action has finished
+
+Pipe Split Debug
+----------------
+
+Sometimes we need to debug if DCN is splitting pipes correctly, and visual
+confirmation is also handy for this case. Similar to the MPO case, you can use
+the below command to enable visual confirmation::
+
+ echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
+
+In this case, if you have a pipe split, you will see one small red bar at the
+bottom of the display covering the entire display width and another bar
+covering the second pipe. In other words, you will see a bit high bar in the
+second pipe.
--
2.25.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 3/6] Documentation/gpu: Document pipe split visual confirmation
@ 2021-12-02 16:01 ` Rodrigo Siqueira
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
Display core provides a feature that makes it easy for users to debug
Pipe Split. This commit introduces how to use such a debug option.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 28 +++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst b/Documentation/gpu/amdgpu/display/dc-debug.rst
index 532cbbd64863..6dbd21f7f59e 100644
--- a/Documentation/gpu/amdgpu/display/dc-debug.rst
+++ b/Documentation/gpu/amdgpu/display/dc-debug.rst
@@ -2,8 +2,18 @@
Display Core Debug tools
========================
-DC Debugfs
-==========
+DC Visual Confirmation
+======================
+
+Display core provides a feature named visual confirmation, which is a set of
+bars added at the scanout time by the driver to convey some specific
+information. In general, you can enable this debug option by using::
+
+ echo <N> > /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
+
+Where `N` is an integer number for some specific scenarios that the developer
+wants to enable, you will see some of these debug cases in the following
+subsection.
Multiple Planes Debug
---------------------
@@ -34,3 +44,17 @@ split configuration.
* There should **not** be any cursor corruption
* Multiple plane **may** be briefly disabled during window transitions or
resizing but should come back after the action has finished
+
+Pipe Split Debug
+----------------
+
+Sometimes we need to debug if DCN is splitting pipes correctly, and visual
+confirmation is also handy for this case. Similar to the MPO case, you can use
+the below command to enable visual confirmation::
+
+ echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
+
+In this case, if you have a pipe split, you will see one small red bar at the
+bottom of the display covering the entire display width and another bar
+covering the second pipe. In other words, you will see a bit high bar in the
+second pipe.
--
2.25.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 4/6] Documentation/gpu: How to collect DTN log
2021-12-02 16:01 ` Rodrigo Siqueira
@ 2021-12-02 16:01 ` Rodrigo Siqueira
-1 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
Introduce how to collect DTN log from debugfs.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst b/Documentation/gpu/amdgpu/display/dc-debug.rst
index 6dbd21f7f59e..40c55a618918 100644
--- a/Documentation/gpu/amdgpu/display/dc-debug.rst
+++ b/Documentation/gpu/amdgpu/display/dc-debug.rst
@@ -58,3 +58,20 @@ In this case, if you have a pipe split, you will see one small red bar at the
bottom of the display covering the entire display width and another bar
covering the second pipe. In other words, you will see a bit high bar in the
second pipe.
+
+DTN Debug
+=========
+
+DC (DCN) provides an extensive log that dumps multiple details from our
+hardware configuration. Via debugfs, you can capture those status values by
+using Display Test Next (DTN) log, which can be captured via debugfs by using::
+
+ cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
+
+Since this log is updated accordingly with DCN status, you can also follow the
+change in real-time by using something like::
+
+ sudo watch -d cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
+
+When reporting a bug related to DC, consider attaching this log before and
+after you reproduce the bug.
--
2.25.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 4/6] Documentation/gpu: How to collect DTN log
@ 2021-12-02 16:01 ` Rodrigo Siqueira
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
Introduce how to collect DTN log from debugfs.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst b/Documentation/gpu/amdgpu/display/dc-debug.rst
index 6dbd21f7f59e..40c55a618918 100644
--- a/Documentation/gpu/amdgpu/display/dc-debug.rst
+++ b/Documentation/gpu/amdgpu/display/dc-debug.rst
@@ -58,3 +58,20 @@ In this case, if you have a pipe split, you will see one small red bar at the
bottom of the display covering the entire display width and another bar
covering the second pipe. In other words, you will see a bit high bar in the
second pipe.
+
+DTN Debug
+=========
+
+DC (DCN) provides an extensive log that dumps multiple details from our
+hardware configuration. Via debugfs, you can capture those status values by
+using Display Test Next (DTN) log, which can be captured via debugfs by using::
+
+ cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
+
+Since this log is updated accordingly with DCN status, you can also follow the
+change in real-time by using something like::
+
+ sudo watch -d cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
+
+When reporting a bug related to DC, consider attaching this log before and
+after you reproduce the bug.
--
2.25.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 5/6] Documentation/gpu: Add basic overview of DC pipeline
2021-12-02 16:01 ` Rodrigo Siqueira
` (4 preceding siblings ...)
(?)
@ 2021-12-02 16:01 ` Rodrigo Siqueira
2021-12-03 21:06 ` Yann Dirson
-1 siblings, 1 reply; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
This commit describes how DCN works by providing high-level diagrams
with an explanation of each component. In particular, it details the
Global Sync signals.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../gpu/amdgpu/display/config_example.svg | 414 ++++++
.../amdgpu/display/dc_pipeline_overview.svg | 1125 +++++++++++++++++
.../gpu/amdgpu/display/dcn-overview.rst | 168 +++
.../gpu/amdgpu/display/global_sync_vblank.svg | 485 +++++++
Documentation/gpu/amdgpu/display/index.rst | 23 +-
5 files changed, 2203 insertions(+), 12 deletions(-)
create mode 100644 Documentation/gpu/amdgpu/display/config_example.svg
create mode 100644 Documentation/gpu/amdgpu/display/dc_pipeline_overview.svg
create mode 100644 Documentation/gpu/amdgpu/display/dcn-overview.rst
create mode 100644 Documentation/gpu/amdgpu/display/global_sync_vblank.svg
diff --git a/Documentation/gpu/amdgpu/display/config_example.svg b/Documentation/gpu/amdgpu/display/config_example.svg
new file mode 100644
index 000000000000..cdac9858601c
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/config_example.svg
@@ -0,0 +1,414 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!-- Created with Inkscape (http://www.inkscape.org/) -->
+
+<svg
+ xmlns:dc="http://purl.org/dc/elements/1.1/"
+ xmlns:cc="http://creativecommons.org/ns#"
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+ xmlns="http://www.w3.org/2000/svg"
+ xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
+ xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
+ width="144.63406mm"
+ height="66.596054mm"
+ viewBox="0 0 144.15195 66.596054"
+ version="1.1"
+ id="svg8"
+ inkscape:version="0.92.5 (2060ec1f9f, 2020-04-08)"
+ sodipodi:docname="config_example.svg">
+ <defs
+ id="defs2">
+ <marker
+ inkscape:stockid="Arrow1Mend"
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+ inkscape:stockid="Arrow1Mend"
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diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst b/Documentation/gpu/amdgpu/display/dcn-overview.rst
new file mode 100644
index 000000000000..47e9a70de8ae
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
@@ -0,0 +1,168 @@
+=======================
+Display Core Next (DCN)
+=======================
+
+To equip our readers with the basic knowledge of how AMD Display Core Next
+(DCN) works, we need to start with an overview of the hardware pipeline. Below
+you can see a picture that provides a DCN overview, keep in mind that this is a
+generic diagram, and we have variations per ASIC.
+
+.. kernel-figure:: dc_pipeline_overview.svg
+
+Based on this diagram, we can pass through each block and briefly describe
+them:
+
+* **Display Controller Hub (DCHUB)**: This is the gateway between the Scalable
+ Data Port (SDP) and DCN. This component has multiple features, such as memory
+ arbitration, rotation, and cursor manipulation.
+
+* **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
+ processing such as color space conversion, linearization of pixel data, tone
+ mapping, and gamut mapping.
+
+* **Multiple Pipe/Plane Combined (MPC)**: This component performs blending of
+ multiple planes, using global or per-pixel alpha.
+
+* **Output Pixel Processing (OPP)**: Process and format pixels to be sent to
+ the display.
+
+* **Output Pipe Timing Combiner (OPTC)**: It generates time output to combine
+ streams or divide capabilities. CRC values are generated in this block.
+
+* **Display Output (DIO)**: Codify the output to the display connected to our
+ GPU.
+
+* **Display Writeback (DWB)**: It provides the ability to write the output of
+ the display pipe back to memory as video frames.
+
+* **DCN Management Unit (DMU)**: It provides registers with access control and
+ interrupts the controller to the SOC host interrupt unit. This block includes
+ the Display Micro-Controller Unit - version B (DMCUB), which is handled via
+ firmware.
+
+* **DCN Clock Generator Block (DCCG)**: It provides the clocks and resets
+ for all of the display controller clock domains.
+
+* **Azalia (AZ)**: Audio engine.
+
+The above diagram is an architecture generalization of DCN, which means that
+every ASIC has variations around this base model. Notice that the display
+pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you can see
+the SDP as the element from our Data Fabric that feeds the display pipe.
+
+Always approach the DCN architecture as something flexible that can be
+configured and reconfigured in multiple ways; in other words, each block can be
+setup or ignored accordingly with userspace demands. For example, if we
+want to drive an 8k@60Hz with a DSC enabled, our DCN may require 4 DPP and 2
+OPP. It is DC's responsibility to drive the best configuration for each
+specific scenario. Orchestrate all of these components together requires a
+sophisticated communication interface which is highlighted in the diagram by
+the edges that connect each block; from the chart, each connection between
+these blocks represents:
+
+1. Pixel data interface (red): Represents the pixel data flow;
+2. Global sync signals (green): It is a set of synchronization signals composed
+ by VStartup, VUpdate, and VReady;
+3. Config interface: Responsible to configure blocks;
+4. Sideband signals: All other signals that do not fit the previous one.
+
+These signals are essential and play an important role in DCN. Nevertheless,
+the Global Sync deserves an extra level of detail described in the next
+section.
+
+All of these components are represented by a data structure named dc_state.
+From DCHUB to MPC, we have a representation called dc_plane; from MPC to OPTC,
+we have dc_stream, and the output (DIO) is handled by dc_link. Keep in mind
+that HUBP accesses a surface using a specific format read from memory, and our
+dc_plane should work to convert all pixels in the plane to something that can
+be sent to the display via dc_stream and dc_link.
+
+Front End and Back End
+----------------------
+
+Display pipeline can be broken down into two components that are usually
+referred as **Front End (FE)** and **Back End (BE)**, where FE consists of:
+
+* DCHUB (Mainly referring to a subcomponent named HUBP)
+* DPP
+* MPC
+
+On the other hand, BE consist of
+
+* OPP
+* OPTC
+* DIO (DP/HDMI stream encoder and link encoder)
+
+OPP and OPTC are two joining blocks between FE and BE. On a side note, this is
+a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
+to choose which link encoder to connect to which PHY. FE's main responsibility
+is to change, blend and compose pixel data, while BE's job is to frame a
+generic pixel stream to a specific display's pixel stream.
+
+Data Flow
+---------
+
+Initially, data is passed in from VRAM through Data Fabric (DF) in native pixel
+formats. Such data format stays through till HUBP in DCHUB, where HUBP unpacks
+different pixel formats and outputs them to DPP in uniform streams through 4
+channels (1 for alpha + 3 for colors).
+
+The Converter and Cursor (CNVC) in DPP would then normalize the data
+representation and convert them to a DCN specific floating-point format (i.e.,
+different from the IEEE floating-point format). In the process, CNVC also
+applies a degamma function to transform the data from non-linear to linear
+space to relax the floating-point calculations following. Data would stay in
+this floating-point format from DPP to OPP.
+
+Starting OPP, because color transformation and blending have been completed
+(i.e alpha can be dropped), and the end sinks do not require the precision and
+dynamic range that floating points provide (i.e. all displays are in integer
+depth format), bit-depth reduction/dithering would kick in. In OPP, we would
+also apply a regamma function to introduce the gamma removed earlier back.
+Eventually, we output data in integer format at DIO.
+
+Global Sync
+-----------
+
+Many DCN registers are double buffered, most importantly the surface address.
+This allows us to updated DCN hardware atomically for page flips, as well as
+for most other updates that don't require enabling or disabling of new pipes.
+
+(Note: There are many scenarios when DC will decide to reserve extra pipes
+in order to support outputs that need a very high pixel clock, or for
+power saving purposes.)
+
+These atomic register updates are driven by global sync signals in DCN. In
+order to understand how atomic updates interact with DCN hardware, and how DCN
+signals page flip and vblank events it is helpful to understand how global sync
+is programmed.
+
+Global sync consists of three signals, VSTARTUP, VUPDATE, and VREADY. These are
+calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml)
+based on a large number of parameters and ensure our hardware is able to feed
+the DCN pipeline without underflows or hangs in any given system configuration.
+The global sync signals always happen during VBlank, are independent from the
+VSync signal, and do not overlap each other.
+
+VUPDATE is the only signal that is of interest to the rest of the driver stack
+or userspace clients as it signals the point at which hardware latches to
+atomically programmed (i.e. double buffered) registers. Even though it is
+independent of the VSync signal we use VUPDATE to signal the VSync event as it
+provides the best indication of how atomic commits and hardware interact.
+
+Since DCN hardware is double-buffered the DC driver is able to program the
+hardware at any point during the frame.
+
+The below picture illustrates the global sync signals:
+
+.. kernel-figure:: global_sync_vblank.svg
+
+These signals affect core DCN behavior. Programming them incorrectly will lead
+to a number of negative consequences, most of them quite catastrophic.
+
+The following picture shows how global sync allows for a mailbox style of
+updates, i.e. it allows for multiple re-configurations between VUpdate
+events where only the last configuration programmed before the VUpdate signal
+becomes effective.
+
+.. kernel-figure:: config_example.svg
diff --git a/Documentation/gpu/amdgpu/display/global_sync_vblank.svg b/Documentation/gpu/amdgpu/display/global_sync_vblank.svg
new file mode 100644
index 000000000000..48f5dc4fd5d3
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/global_sync_vblank.svg
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diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
index a443866332ac..fe2ecad8df81 100644
--- a/Documentation/gpu/amdgpu/display/index.rst
+++ b/Documentation/gpu/amdgpu/display/index.rst
@@ -2,28 +2,27 @@
drm/amd/display - Display Core (DC)
===================================
-*placeholder - general description of supported platforms, what dc is, etc.*
-
-Because it is partially shared with other operating systems, the Display Core
-Driver is divided in two pieces.
+AMD display engine is partially shared with other operating systems; for this
+reason, our Display Core Driver is divided into two pieces:
1. **Display Core (DC)** contains the OS-agnostic components. Things like
hardware programming and resource management are handled here.
2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
amdgpu base driver and DRM are implemented here.
-It doesn't help that the entire package is frequently referred to as DC. But
-with the context in mind, it should be clear.
+The display pipe is responsible for "scanning out" a rendered frame from the
+GPU memory (also called VRAM, FrameBuffer, etc.) to a display. In other words,
+it would:
-When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default for
-supported ASICs. To force disable, set `amdgpu.dc=0` on kernel command line.
-Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`.
+1. Read frame information from memory;
+2. Perform required transformation;
+3. Send pixel data to sink devices.
-To determine if DC is loaded, search dmesg for the following entry:
+If you want to learn more about our driver details, take a look at the below
+table of content:
.. toctree::
display-manager.rst
dc-debug.rst
-
-``Display Core initialized with <version number here>``
+ dcn-overview.rst
--
2.25.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
2021-12-02 16:01 ` Rodrigo Siqueira
@ 2021-12-02 16:01 ` Rodrigo Siqueira
-1 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
In the DC driver, we have multiple acronyms that are not obvious most of
the time; the same idea is valid for amdgpu. This commit introduces a DC
and amdgpu glossary in order to make it easier to navigate through our
driver.
Changes since V1:
- Yann: Divide glossary based on driver context.
- Alex: Make terms more consistent and update CPLIB
- Add new acronyms to the glossary
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
.../gpu/amdgpu/display/dc-glossary.rst | 243 ++++++++++++++++++
Documentation/gpu/amdgpu/display/index.rst | 1 +
Documentation/gpu/amdgpu/index.rst | 7 +
4 files changed, 298 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
create mode 100644 Documentation/gpu/amdgpu/display/dc-glossary.rst
diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
new file mode 100644
index 000000000000..e635851025e7
--- /dev/null
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -0,0 +1,47 @@
+===============
+AMDGPU Glossary
+===============
+
+Here you can find some generic acronyms used in the amdgpu driver. Notice that
+we have a dedicated glossary for Display Core.
+
+.. glossary::
+
+ CPLIB
+ Content Protection Library
+
+ DFS
+ Digital Frequency Synthesizer
+
+ ECP
+ Enhanced Content Protection
+
+ EOP
+ End Of Pipe/Pipeline
+
+ HQD
+ Hardware Queue Descriptor
+
+ KCQ
+ Kernel Compute Queue
+
+ KGQ
+ Kernel Graphics Queue
+
+ KIQ
+ Kernel Interface Queue
+
+ MQD
+ Memory Queue Descriptor
+
+ PPLib
+ PowerPlay Library - PowerPlay is the power management component.
+
+ SMU
+ System Management Unit
+
+ VCE
+ Video Compression Engine
+
+ VCN
+ Video Codec Next
diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst b/Documentation/gpu/amdgpu/display/dc-glossary.rst
new file mode 100644
index 000000000000..547c0bfbb3e2
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
@@ -0,0 +1,243 @@
+===========
+DC Glossary
+===========
+
+On this page, we try to keep track of acronyms related to the display
+component. If you do not find what you are looking for, look at the amdgpu
+glossary; if you cannot find it anywhere, consider asking in the amdgfx and
+update this page.
+
+.. glossary::
+
+ ABM
+ Adaptive Backlight Modulation
+
+ APU
+ Accelerated Processing Unit
+
+ ASIC
+ Application-Specific Integrated Circuit
+
+ ASSR
+ Alternate Scrambler Seed Reset
+
+ AZ
+ Azalia (HD audio DMA engine)
+
+ BPC
+ Bits Per Colour/Component
+
+ BPP
+ Bits Per Pixel
+
+ Clocks
+ * PCLK: Pixel Clock
+ * SYMCLK: Symbol Clock
+ * SOCCLK: GPU Engine Clock
+ * DISPCLK: Display Clock
+ * DPPCLK: DPP Clock
+ * DCFCLK: Display Controller Fabric Clock
+ * REFCLK: Real Time Reference Clock
+ * PPLL: Pixel PLL
+ * FCLK: Fabric Clock
+ * MCLK: Memory Clock
+
+ CRC
+ Cyclic Redundancy Check
+
+ CRTC
+ Cathode Ray Tube Controller - commonly called "Controller" - Generates
+ raw stream of pixels, clocked at pixel clock
+
+ CVT
+ Coordinated Video Timings
+
+ DAL
+ Display Abstraction layer
+
+ DC (Software)
+ Display Core
+
+ DC (Hardware)
+ Display Controller
+
+ DCC
+ Delta Colour Compression
+
+ DCE
+ Display Controller Engine
+
+ DCHUB
+ Display Controller HUB
+
+ ARB
+ Arbiter
+
+ VTG
+ Vertical Timing Generator
+
+ DCN
+ Display Core Next
+
+ DCCG
+ Display Clock Generator block
+
+ DDC
+ Display Data Channel
+
+ DIO
+ Display IO
+
+ DPP
+ Display Pipes and Planes
+
+ DSC
+ Display Stream Compression (Reduce the amount of bits to represent pixel
+ count while at the same pixel clock)
+
+ dGPU
+ discrete GPU
+
+ DMIF
+ Display Memory Interface
+
+ DML
+ Display Mode Library
+
+ DMCU
+ Display Micro-Controller Unit
+
+ DMCUB
+ Display Micro-Controller Unit, version B
+
+ DPCD
+ DisplayPort Configuration Data
+
+ DPM(S)
+ Display Power Management (Signaling)
+
+ DRR
+ Dynamic Refresh Rate
+
+ DWB
+ Display Writeback
+
+ FB
+ Frame Buffer
+
+ FBC
+ Frame Buffer Compression
+
+ FEC
+ Forward Error Correction
+
+ FRL
+ Fixed Rate Link
+
+ GCO
+ Graphical Controller Object
+
+ GMC
+ Graphic Memory Controller
+
+ GSL
+ Global Swap Lock
+
+ iGPU
+ integrated GPU
+
+ IH
+ Interrupt Handler
+
+ ISR
+ Interrupt Service Request
+
+ ISV
+ Independent Software Vendor
+
+ KMD
+ Kernel Mode Driver
+
+ LB
+ Line Buffer
+
+ LFC
+ Low Framerate Compensation
+
+ LTTPR
+ Link Training Tunable Phy Repeater
+
+ LUT
+ Lookup Table
+
+ MALL
+ Memory Access at Last Level
+
+ MC
+ Memory Controller
+
+ MPC
+ Multiple pipes and plane combine
+
+ MPO
+ Multi Plane Overlay
+
+ MST
+ Multi Stream Transport
+
+ NBP State
+ Northbridge Power State
+
+ NBIO
+ North Bridge Input/Output
+
+ ODM
+ Output Data Mapping
+
+ OPM
+ Output Protection Manager
+
+ OPP
+ Output Plane Processor
+
+ OPTC
+ Output Pipe Timing Combiner
+
+ OTG
+ Output Timing Generator
+
+ PCON
+ Power Controller
+
+ PGFSM
+ Power Gate Finite State Machine
+
+ PSR
+ Panel Self Refresh
+
+ SCL
+ Scaler
+
+ SDP
+ Scalable Data Port
+
+ SLS
+ Single Large Surface
+
+ SST
+ Single Stream Transport
+
+ TMDS
+ Transition-Minimized Differential Signaling
+
+ TMZ
+ Trusted Memory Zone
+
+ TTU
+ Time to Underflow
+
+ VRR
+ Variable Refresh Rate
+
+ UVD
+ Unified Video Decoder
diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
index fe2ecad8df81..e23c752ee5f5 100644
--- a/Documentation/gpu/amdgpu/display/index.rst
+++ b/Documentation/gpu/amdgpu/display/index.rst
@@ -26,3 +26,4 @@ table of content:
display-manager.rst
dc-debug.rst
dcn-overview.rst
+ dc-glossary.rst
diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
index 5c8cbf514097..ff38c360b04e 100644
--- a/Documentation/gpu/amdgpu/index.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -334,3 +334,10 @@ smartshift_bias
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
:doc: smartshift_bias
+
+AMDGPU Glossary
+===============
+
+.. toctree::
+
+ amdgpu-glossary.rst
--
2.25.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
@ 2021-12-02 16:01 ` Rodrigo Siqueira
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira @ 2021-12-02 16:01 UTC (permalink / raw)
To: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter
Cc: linux-doc, qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
In the DC driver, we have multiple acronyms that are not obvious most of
the time; the same idea is valid for amdgpu. This commit introduces a DC
and amdgpu glossary in order to make it easier to navigate through our
driver.
Changes since V1:
- Yann: Divide glossary based on driver context.
- Alex: Make terms more consistent and update CPLIB
- Add new acronyms to the glossary
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
.../gpu/amdgpu/display/dc-glossary.rst | 243 ++++++++++++++++++
Documentation/gpu/amdgpu/display/index.rst | 1 +
Documentation/gpu/amdgpu/index.rst | 7 +
4 files changed, 298 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
create mode 100644 Documentation/gpu/amdgpu/display/dc-glossary.rst
diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
new file mode 100644
index 000000000000..e635851025e7
--- /dev/null
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -0,0 +1,47 @@
+===============
+AMDGPU Glossary
+===============
+
+Here you can find some generic acronyms used in the amdgpu driver. Notice that
+we have a dedicated glossary for Display Core.
+
+.. glossary::
+
+ CPLIB
+ Content Protection Library
+
+ DFS
+ Digital Frequency Synthesizer
+
+ ECP
+ Enhanced Content Protection
+
+ EOP
+ End Of Pipe/Pipeline
+
+ HQD
+ Hardware Queue Descriptor
+
+ KCQ
+ Kernel Compute Queue
+
+ KGQ
+ Kernel Graphics Queue
+
+ KIQ
+ Kernel Interface Queue
+
+ MQD
+ Memory Queue Descriptor
+
+ PPLib
+ PowerPlay Library - PowerPlay is the power management component.
+
+ SMU
+ System Management Unit
+
+ VCE
+ Video Compression Engine
+
+ VCN
+ Video Codec Next
diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst b/Documentation/gpu/amdgpu/display/dc-glossary.rst
new file mode 100644
index 000000000000..547c0bfbb3e2
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
@@ -0,0 +1,243 @@
+===========
+DC Glossary
+===========
+
+On this page, we try to keep track of acronyms related to the display
+component. If you do not find what you are looking for, look at the amdgpu
+glossary; if you cannot find it anywhere, consider asking in the amdgfx and
+update this page.
+
+.. glossary::
+
+ ABM
+ Adaptive Backlight Modulation
+
+ APU
+ Accelerated Processing Unit
+
+ ASIC
+ Application-Specific Integrated Circuit
+
+ ASSR
+ Alternate Scrambler Seed Reset
+
+ AZ
+ Azalia (HD audio DMA engine)
+
+ BPC
+ Bits Per Colour/Component
+
+ BPP
+ Bits Per Pixel
+
+ Clocks
+ * PCLK: Pixel Clock
+ * SYMCLK: Symbol Clock
+ * SOCCLK: GPU Engine Clock
+ * DISPCLK: Display Clock
+ * DPPCLK: DPP Clock
+ * DCFCLK: Display Controller Fabric Clock
+ * REFCLK: Real Time Reference Clock
+ * PPLL: Pixel PLL
+ * FCLK: Fabric Clock
+ * MCLK: Memory Clock
+
+ CRC
+ Cyclic Redundancy Check
+
+ CRTC
+ Cathode Ray Tube Controller - commonly called "Controller" - Generates
+ raw stream of pixels, clocked at pixel clock
+
+ CVT
+ Coordinated Video Timings
+
+ DAL
+ Display Abstraction layer
+
+ DC (Software)
+ Display Core
+
+ DC (Hardware)
+ Display Controller
+
+ DCC
+ Delta Colour Compression
+
+ DCE
+ Display Controller Engine
+
+ DCHUB
+ Display Controller HUB
+
+ ARB
+ Arbiter
+
+ VTG
+ Vertical Timing Generator
+
+ DCN
+ Display Core Next
+
+ DCCG
+ Display Clock Generator block
+
+ DDC
+ Display Data Channel
+
+ DIO
+ Display IO
+
+ DPP
+ Display Pipes and Planes
+
+ DSC
+ Display Stream Compression (Reduce the amount of bits to represent pixel
+ count while at the same pixel clock)
+
+ dGPU
+ discrete GPU
+
+ DMIF
+ Display Memory Interface
+
+ DML
+ Display Mode Library
+
+ DMCU
+ Display Micro-Controller Unit
+
+ DMCUB
+ Display Micro-Controller Unit, version B
+
+ DPCD
+ DisplayPort Configuration Data
+
+ DPM(S)
+ Display Power Management (Signaling)
+
+ DRR
+ Dynamic Refresh Rate
+
+ DWB
+ Display Writeback
+
+ FB
+ Frame Buffer
+
+ FBC
+ Frame Buffer Compression
+
+ FEC
+ Forward Error Correction
+
+ FRL
+ Fixed Rate Link
+
+ GCO
+ Graphical Controller Object
+
+ GMC
+ Graphic Memory Controller
+
+ GSL
+ Global Swap Lock
+
+ iGPU
+ integrated GPU
+
+ IH
+ Interrupt Handler
+
+ ISR
+ Interrupt Service Request
+
+ ISV
+ Independent Software Vendor
+
+ KMD
+ Kernel Mode Driver
+
+ LB
+ Line Buffer
+
+ LFC
+ Low Framerate Compensation
+
+ LTTPR
+ Link Training Tunable Phy Repeater
+
+ LUT
+ Lookup Table
+
+ MALL
+ Memory Access at Last Level
+
+ MC
+ Memory Controller
+
+ MPC
+ Multiple pipes and plane combine
+
+ MPO
+ Multi Plane Overlay
+
+ MST
+ Multi Stream Transport
+
+ NBP State
+ Northbridge Power State
+
+ NBIO
+ North Bridge Input/Output
+
+ ODM
+ Output Data Mapping
+
+ OPM
+ Output Protection Manager
+
+ OPP
+ Output Plane Processor
+
+ OPTC
+ Output Pipe Timing Combiner
+
+ OTG
+ Output Timing Generator
+
+ PCON
+ Power Controller
+
+ PGFSM
+ Power Gate Finite State Machine
+
+ PSR
+ Panel Self Refresh
+
+ SCL
+ Scaler
+
+ SDP
+ Scalable Data Port
+
+ SLS
+ Single Large Surface
+
+ SST
+ Single Stream Transport
+
+ TMDS
+ Transition-Minimized Differential Signaling
+
+ TMZ
+ Trusted Memory Zone
+
+ TTU
+ Time to Underflow
+
+ VRR
+ Variable Refresh Rate
+
+ UVD
+ Unified Video Decoder
diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
index fe2ecad8df81..e23c752ee5f5 100644
--- a/Documentation/gpu/amdgpu/display/index.rst
+++ b/Documentation/gpu/amdgpu/display/index.rst
@@ -26,3 +26,4 @@ table of content:
display-manager.rst
dc-debug.rst
dcn-overview.rst
+ dc-glossary.rst
diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
index 5c8cbf514097..ff38c360b04e 100644
--- a/Documentation/gpu/amdgpu/index.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -334,3 +334,10 @@ smartshift_bias
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
:doc: smartshift_bias
+
+AMDGPU Glossary
+===============
+
+.. toctree::
+
+ amdgpu-glossary.rst
--
2.25.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH v2 5/6] Documentation/gpu: Add basic overview of DC pipeline
2021-12-02 16:01 ` [PATCH v2 5/6] Documentation/gpu: Add basic overview of DC pipeline Rodrigo Siqueira
2021-12-03 21:06 ` Yann Dirson
@ 2021-12-03 21:06 ` Yann Dirson
0 siblings, 0 replies; 31+ messages in thread
From: Yann Dirson @ 2021-12-03 21:06 UTC (permalink / raw)
To: Rodrigo Siqueira
Cc: linux-doc, qingqing zhuo, roman li, amd-gfx, aurabindo pillai,
nicholas choi, dri-devel, Alex Deucher, bhawanpreet lakha,
Christian Koenig, Simon Ser, Michel Daenzer, Bas Nieuwenhuizen,
Marek Olsak, Roman Gilg, Nicholas Kazlauskas, Harry Wentland,
Mark Yacoub, Sean Paul, Pekka Paalanen, Daniel Vetter
> De: "Rodrigo Siqueira" <Rodrigo.Siqueira@amd.com>
> Objet: [PATCH v2 5/6] Documentation/gpu: Add basic overview of DC pipeline
>
> This commit describes how DCN works by providing high-level diagrams
> with an explanation of each component. In particular, it details the
> Global Sync signals.
>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
> .../gpu/amdgpu/display/config_example.svg | 414 ++++++
> .../amdgpu/display/dc_pipeline_overview.svg | 1125
> +++++++++++++++++
> .../gpu/amdgpu/display/dcn-overview.rst | 168 +++
> .../gpu/amdgpu/display/global_sync_vblank.svg | 485 +++++++
> Documentation/gpu/amdgpu/display/index.rst | 23 +-
> 5 files changed, 2203 insertions(+), 12 deletions(-)
> create mode 100644
> Documentation/gpu/amdgpu/display/config_example.svg
> create mode 100644
> Documentation/gpu/amdgpu/display/dc_pipeline_overview.svg
> create mode 100644 Documentation/gpu/amdgpu/display/dcn-overview.rst
> create mode 100644
> Documentation/gpu/amdgpu/display/global_sync_vblank.svg
>
...
> diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst
> b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> new file mode 100644
> index 000000000000..47e9a70de8ae
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> @@ -0,0 +1,168 @@
> +=======================
> +Display Core Next (DCN)
> +=======================
> +
> +To equip our readers with the basic knowledge of how AMD Display
> Core Next
> +(DCN) works, we need to start with an overview of the hardware
> pipeline. Below
> +you can see a picture that provides a DCN overview, keep in mind
> that this is a
> +generic diagram, and we have variations per ASIC.
> +
> +.. kernel-figure:: dc_pipeline_overview.svg
> +
> +Based on this diagram, we can pass through each block and briefly
> describe
> +them:
Maybe a note on MMHUBBUB is missing ?
> +
> +* **Display Controller Hub (DCHUB)**: This is the gateway between
> the Scalable
> + Data Port (SDP) and DCN. This component has multiple features,
> such as memory
> + arbitration, rotation, and cursor manipulation.
> +
> +* **Display Pipe and Plane (DPP)**: This block provides pre-blend
> pixel
> + processing such as color space conversion, linearization of pixel
> data, tone
> + mapping, and gamut mapping.
> +
> +* **Multiple Pipe/Plane Combined (MPC)**: This component performs
> blending of
> + multiple planes, using global or per-pixel alpha.
> +
> +* **Output Pixel Processing (OPP)**: Process and format pixels to be
> sent to
> + the display.
> +
> +* **Output Pipe Timing Combiner (OPTC)**: It generates time output
> to combine
> + streams or divide capabilities. CRC values are generated in this
> block.
> +
> +* **Display Output (DIO)**: Codify the output to the display
> connected to our
> + GPU.
> +
> +* **Display Writeback (DWB)**: It provides the ability to write the
> output of
> + the display pipe back to memory as video frames.
> +
> +* **DCN Management Unit (DMU)**: It provides registers with access
> control and
> + interrupts the controller to the SOC host interrupt unit. This
> block includes
> + the Display Micro-Controller Unit - version B (DMCUB), which is
> handled via
> + firmware.
> +
> +* **DCN Clock Generator Block (DCCG)**: It provides the clocks and
> resets
> + for all of the display controller clock domains.
> +
> +* **Azalia (AZ)**: Audio engine.
> +
> +The above diagram is an architecture generalization of DCN, which
> means that
> +every ASIC has variations around this base model. Notice that the
> display
> +pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you
> can see
> +the SDP as the element from our Data Fabric that feeds the display
> pipe.
> +
> +Always approach the DCN architecture as something flexible that can
> be
> +configured and reconfigured in multiple ways; in other words, each
> block can be
> +setup or ignored accordingly with userspace demands. For example, if
> we
> +want to drive an 8k@60Hz with a DSC enabled, our DCN may require 4
> DPP and 2
> +OPP. It is DC's responsibility to drive the best configuration for
> each
> +specific scenario. Orchestrate all of these components together
> requires a
> +sophisticated communication interface which is highlighted in the
> diagram by
> +the edges that connect each block; from the chart, each connection
> between
> +these blocks represents:
> +
> +1. Pixel data interface (red): Represents the pixel data flow;
> +2. Global sync signals (green): It is a set of synchronization
> signals composed
> + by VStartup, VUpdate, and VReady;
> +3. Config interface: Responsible to configure blocks;
> +4. Sideband signals: All other signals that do not fit the previous
> one.
> +
> +These signals are essential and play an important role in DCN.
> Nevertheless,
> +the Global Sync deserves an extra level of detail described in the
> next
> +section.
> +
> +All of these components are represented by a data structure named
> dc_state.
> +From DCHUB to MPC, we have a representation called dc_plane; from
> MPC to OPTC,
> +we have dc_stream, and the output (DIO) is handled by dc_link. Keep
> in mind
> +that HUBP accesses a surface using a specific format read from
> memory, and our
> +dc_plane should work to convert all pixels in the plane to something
> that can
> +be sent to the display via dc_stream and dc_link.
> +
> +Front End and Back End
> +----------------------
> +
> +Display pipeline can be broken down into two components that are
> usually
> +referred as **Front End (FE)** and **Back End (BE)**, where FE
> consists of:
> +
> +* DCHUB (Mainly referring to a subcomponent named HUBP)
> +* DPP
> +* MPC
> +
> +On the other hand, BE consist of
> +
> +* OPP
> +* OPTC
> +* DIO (DP/HDMI stream encoder and link encoder)
> +
> +OPP and OPTC are two joining blocks between FE and BE. On a side
> note, this is
> +a one-to-one mapping of the link encoder to PHY, but we can
> configure the DCN
> +to choose which link encoder to connect to which PHY. FE's main
> responsibility
> +is to change, blend and compose pixel data, while BE's job is to
> frame a
> +generic pixel stream to a specific display's pixel stream.
> +
> +Data Flow
> +---------
> +
> +Initially, data is passed in from VRAM through Data Fabric (DF) in
> native pixel
> +formats. Such data format stays through till HUBP in DCHUB, where
> HUBP unpacks
> +different pixel formats and outputs them to DPP in uniform streams
> through 4
> +channels (1 for alpha + 3 for colors).
> +
> +The Converter and Cursor (CNVC) in DPP would then normalize the data
> +representation and convert them to a DCN specific floating-point
> format (i.e.,
> +different from the IEEE floating-point format). In the process, CNVC
> also
> +applies a degamma function to transform the data from non-linear to
> linear
> +space to relax the floating-point calculations following. Data would
> stay in
> +this floating-point format from DPP to OPP.
> +
> +Starting OPP, because color transformation and blending have been
> completed
> +(i.e alpha can be dropped), and the end sinks do not require the
> precision and
> +dynamic range that floating points provide (i.e. all displays are in
> integer
> +depth format), bit-depth reduction/dithering would kick in. In OPP,
> we would
> +also apply a regamma function to introduce the gamma removed earlier
> back.
> +Eventually, we output data in integer format at DIO.
> +
> +Global Sync
> +-----------
> +
> +Many DCN registers are double buffered, most importantly the surface
> address.
> +This allows us to updated DCN hardware atomically for page flips, as
> well as
to update ?
> +for most other updates that don't require enabling or disabling of
> new pipes.
> +
> +(Note: There are many scenarios when DC will decide to reserve extra
> pipes
> +in order to support outputs that need a very high pixel clock, or
> for
> +power saving purposes.)
> +
> +These atomic register updates are driven by global sync signals in
> DCN. In
> +order to understand how atomic updates interact with DCN hardware,
> and how DCN
> +signals page flip and vblank events it is helpful to understand how
> global sync
> +is programmed.
> +
> +Global sync consists of three signals, VSTARTUP, VUPDATE, and
> VREADY. These are
> +calculated by the Display Mode Library - DML
> (drivers/gpu/drm/amd/display/dc/dml)
> +based on a large number of parameters and ensure our hardware is
> able to feed
> +the DCN pipeline without underflows or hangs in any given system
> configuration.
> +The global sync signals always happen during VBlank, are independent
> from the
> +VSync signal, and do not overlap each other.
> +
> +VUPDATE is the only signal that is of interest to the rest of the
> driver stack
> +or userspace clients as it signals the point at which hardware
> latches to
> +atomically programmed (i.e. double buffered) registers. Even though
> it is
> +independent of the VSync signal we use VUPDATE to signal the VSync
> event as it
> +provides the best indication of how atomic commits and hardware
> interact.
> +
> +Since DCN hardware is double-buffered the DC driver is able to
> program the
> +hardware at any point during the frame.
> +
> +The below picture illustrates the global sync signals:
> +
> +.. kernel-figure:: global_sync_vblank.svg
> +
> +These signals affect core DCN behavior. Programming them incorrectly
> will lead
> +to a number of negative consequences, most of them quite
> catastrophic.
> +
> +The following picture shows how global sync allows for a mailbox
> style of
> +updates, i.e. it allows for multiple re-configurations between
> VUpdate
> +events where only the last configuration programmed before the
> VUpdate signal
> +becomes effective.
> +
> +.. kernel-figure:: config_example.svg
...
> diff --git a/Documentation/gpu/amdgpu/display/index.rst
> b/Documentation/gpu/amdgpu/display/index.rst
> index a443866332ac..fe2ecad8df81 100644
> --- a/Documentation/gpu/amdgpu/display/index.rst
> +++ b/Documentation/gpu/amdgpu/display/index.rst
> @@ -2,28 +2,27 @@
> drm/amd/display - Display Core (DC)
> ===================================
>
> -*placeholder - general description of supported platforms, what dc
> is, etc.*
> -
> -Because it is partially shared with other operating systems, the
> Display Core
> -Driver is divided in two pieces.
> +AMD display engine is partially shared with other operating systems;
> for this
> +reason, our Display Core Driver is divided into two pieces:
>
> 1. **Display Core (DC)** contains the OS-agnostic components. Things
> like
> hardware programming and resource management are handled here.
> 2. **Display Manager (DM)** contains the OS-dependent components.
> Hooks to the
> amdgpu base driver and DRM are implemented here.
>
> -It doesn't help that the entire package is frequently referred to as
> DC. But
> -with the context in mind, it should be clear.
> +The display pipe is responsible for "scanning out" a rendered frame
> from the
> +GPU memory (also called VRAM, FrameBuffer, etc.) to a display. In
> other words,
> +it would:
>
> -When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default
> for
> -supported ASICs. To force disable, set `amdgpu.dc=0` on kernel
> command line.
> -Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`.
> +1. Read frame information from memory;
> +2. Perform required transformation;
> +3. Send pixel data to sink devices.
>
> -To determine if DC is loaded, search dmesg for the following entry:
> +If you want to learn more about our driver details, take a look at
> the below
> +table of content:
>
> .. toctree::
>
> display-manager.rst
> dc-debug.rst
> -
> -``Display Core initialized with <version number here>``
> + dcn-overview.rst
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 5/6] Documentation/gpu: Add basic overview of DC pipeline
@ 2021-12-03 21:06 ` Yann Dirson
0 siblings, 0 replies; 31+ messages in thread
From: Yann Dirson @ 2021-12-03 21:06 UTC (permalink / raw)
To: Rodrigo Siqueira
Cc: Mark Yacoub, linux-doc, qingqing zhuo, Marek Olsak, roman li,
amd-gfx, Roman Gilg, Michel Daenzer, aurabindo pillai,
nicholas choi, dri-devel, Alex Deucher, Sean Paul,
Nicholas Kazlauskas, bhawanpreet lakha, Christian Koenig
> De: "Rodrigo Siqueira" <Rodrigo.Siqueira@amd.com>
> Objet: [PATCH v2 5/6] Documentation/gpu: Add basic overview of DC pipeline
>
> This commit describes how DCN works by providing high-level diagrams
> with an explanation of each component. In particular, it details the
> Global Sync signals.
>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
> .../gpu/amdgpu/display/config_example.svg | 414 ++++++
> .../amdgpu/display/dc_pipeline_overview.svg | 1125
> +++++++++++++++++
> .../gpu/amdgpu/display/dcn-overview.rst | 168 +++
> .../gpu/amdgpu/display/global_sync_vblank.svg | 485 +++++++
> Documentation/gpu/amdgpu/display/index.rst | 23 +-
> 5 files changed, 2203 insertions(+), 12 deletions(-)
> create mode 100644
> Documentation/gpu/amdgpu/display/config_example.svg
> create mode 100644
> Documentation/gpu/amdgpu/display/dc_pipeline_overview.svg
> create mode 100644 Documentation/gpu/amdgpu/display/dcn-overview.rst
> create mode 100644
> Documentation/gpu/amdgpu/display/global_sync_vblank.svg
>
...
> diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst
> b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> new file mode 100644
> index 000000000000..47e9a70de8ae
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> @@ -0,0 +1,168 @@
> +=======================
> +Display Core Next (DCN)
> +=======================
> +
> +To equip our readers with the basic knowledge of how AMD Display
> Core Next
> +(DCN) works, we need to start with an overview of the hardware
> pipeline. Below
> +you can see a picture that provides a DCN overview, keep in mind
> that this is a
> +generic diagram, and we have variations per ASIC.
> +
> +.. kernel-figure:: dc_pipeline_overview.svg
> +
> +Based on this diagram, we can pass through each block and briefly
> describe
> +them:
Maybe a note on MMHUBBUB is missing ?
> +
> +* **Display Controller Hub (DCHUB)**: This is the gateway between
> the Scalable
> + Data Port (SDP) and DCN. This component has multiple features,
> such as memory
> + arbitration, rotation, and cursor manipulation.
> +
> +* **Display Pipe and Plane (DPP)**: This block provides pre-blend
> pixel
> + processing such as color space conversion, linearization of pixel
> data, tone
> + mapping, and gamut mapping.
> +
> +* **Multiple Pipe/Plane Combined (MPC)**: This component performs
> blending of
> + multiple planes, using global or per-pixel alpha.
> +
> +* **Output Pixel Processing (OPP)**: Process and format pixels to be
> sent to
> + the display.
> +
> +* **Output Pipe Timing Combiner (OPTC)**: It generates time output
> to combine
> + streams or divide capabilities. CRC values are generated in this
> block.
> +
> +* **Display Output (DIO)**: Codify the output to the display
> connected to our
> + GPU.
> +
> +* **Display Writeback (DWB)**: It provides the ability to write the
> output of
> + the display pipe back to memory as video frames.
> +
> +* **DCN Management Unit (DMU)**: It provides registers with access
> control and
> + interrupts the controller to the SOC host interrupt unit. This
> block includes
> + the Display Micro-Controller Unit - version B (DMCUB), which is
> handled via
> + firmware.
> +
> +* **DCN Clock Generator Block (DCCG)**: It provides the clocks and
> resets
> + for all of the display controller clock domains.
> +
> +* **Azalia (AZ)**: Audio engine.
> +
> +The above diagram is an architecture generalization of DCN, which
> means that
> +every ASIC has variations around this base model. Notice that the
> display
> +pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you
> can see
> +the SDP as the element from our Data Fabric that feeds the display
> pipe.
> +
> +Always approach the DCN architecture as something flexible that can
> be
> +configured and reconfigured in multiple ways; in other words, each
> block can be
> +setup or ignored accordingly with userspace demands. For example, if
> we
> +want to drive an 8k@60Hz with a DSC enabled, our DCN may require 4
> DPP and 2
> +OPP. It is DC's responsibility to drive the best configuration for
> each
> +specific scenario. Orchestrate all of these components together
> requires a
> +sophisticated communication interface which is highlighted in the
> diagram by
> +the edges that connect each block; from the chart, each connection
> between
> +these blocks represents:
> +
> +1. Pixel data interface (red): Represents the pixel data flow;
> +2. Global sync signals (green): It is a set of synchronization
> signals composed
> + by VStartup, VUpdate, and VReady;
> +3. Config interface: Responsible to configure blocks;
> +4. Sideband signals: All other signals that do not fit the previous
> one.
> +
> +These signals are essential and play an important role in DCN.
> Nevertheless,
> +the Global Sync deserves an extra level of detail described in the
> next
> +section.
> +
> +All of these components are represented by a data structure named
> dc_state.
> +From DCHUB to MPC, we have a representation called dc_plane; from
> MPC to OPTC,
> +we have dc_stream, and the output (DIO) is handled by dc_link. Keep
> in mind
> +that HUBP accesses a surface using a specific format read from
> memory, and our
> +dc_plane should work to convert all pixels in the plane to something
> that can
> +be sent to the display via dc_stream and dc_link.
> +
> +Front End and Back End
> +----------------------
> +
> +Display pipeline can be broken down into two components that are
> usually
> +referred as **Front End (FE)** and **Back End (BE)**, where FE
> consists of:
> +
> +* DCHUB (Mainly referring to a subcomponent named HUBP)
> +* DPP
> +* MPC
> +
> +On the other hand, BE consist of
> +
> +* OPP
> +* OPTC
> +* DIO (DP/HDMI stream encoder and link encoder)
> +
> +OPP and OPTC are two joining blocks between FE and BE. On a side
> note, this is
> +a one-to-one mapping of the link encoder to PHY, but we can
> configure the DCN
> +to choose which link encoder to connect to which PHY. FE's main
> responsibility
> +is to change, blend and compose pixel data, while BE's job is to
> frame a
> +generic pixel stream to a specific display's pixel stream.
> +
> +Data Flow
> +---------
> +
> +Initially, data is passed in from VRAM through Data Fabric (DF) in
> native pixel
> +formats. Such data format stays through till HUBP in DCHUB, where
> HUBP unpacks
> +different pixel formats and outputs them to DPP in uniform streams
> through 4
> +channels (1 for alpha + 3 for colors).
> +
> +The Converter and Cursor (CNVC) in DPP would then normalize the data
> +representation and convert them to a DCN specific floating-point
> format (i.e.,
> +different from the IEEE floating-point format). In the process, CNVC
> also
> +applies a degamma function to transform the data from non-linear to
> linear
> +space to relax the floating-point calculations following. Data would
> stay in
> +this floating-point format from DPP to OPP.
> +
> +Starting OPP, because color transformation and blending have been
> completed
> +(i.e alpha can be dropped), and the end sinks do not require the
> precision and
> +dynamic range that floating points provide (i.e. all displays are in
> integer
> +depth format), bit-depth reduction/dithering would kick in. In OPP,
> we would
> +also apply a regamma function to introduce the gamma removed earlier
> back.
> +Eventually, we output data in integer format at DIO.
> +
> +Global Sync
> +-----------
> +
> +Many DCN registers are double buffered, most importantly the surface
> address.
> +This allows us to updated DCN hardware atomically for page flips, as
> well as
to update ?
> +for most other updates that don't require enabling or disabling of
> new pipes.
> +
> +(Note: There are many scenarios when DC will decide to reserve extra
> pipes
> +in order to support outputs that need a very high pixel clock, or
> for
> +power saving purposes.)
> +
> +These atomic register updates are driven by global sync signals in
> DCN. In
> +order to understand how atomic updates interact with DCN hardware,
> and how DCN
> +signals page flip and vblank events it is helpful to understand how
> global sync
> +is programmed.
> +
> +Global sync consists of three signals, VSTARTUP, VUPDATE, and
> VREADY. These are
> +calculated by the Display Mode Library - DML
> (drivers/gpu/drm/amd/display/dc/dml)
> +based on a large number of parameters and ensure our hardware is
> able to feed
> +the DCN pipeline without underflows or hangs in any given system
> configuration.
> +The global sync signals always happen during VBlank, are independent
> from the
> +VSync signal, and do not overlap each other.
> +
> +VUPDATE is the only signal that is of interest to the rest of the
> driver stack
> +or userspace clients as it signals the point at which hardware
> latches to
> +atomically programmed (i.e. double buffered) registers. Even though
> it is
> +independent of the VSync signal we use VUPDATE to signal the VSync
> event as it
> +provides the best indication of how atomic commits and hardware
> interact.
> +
> +Since DCN hardware is double-buffered the DC driver is able to
> program the
> +hardware at any point during the frame.
> +
> +The below picture illustrates the global sync signals:
> +
> +.. kernel-figure:: global_sync_vblank.svg
> +
> +These signals affect core DCN behavior. Programming them incorrectly
> will lead
> +to a number of negative consequences, most of them quite
> catastrophic.
> +
> +The following picture shows how global sync allows for a mailbox
> style of
> +updates, i.e. it allows for multiple re-configurations between
> VUpdate
> +events where only the last configuration programmed before the
> VUpdate signal
> +becomes effective.
> +
> +.. kernel-figure:: config_example.svg
...
> diff --git a/Documentation/gpu/amdgpu/display/index.rst
> b/Documentation/gpu/amdgpu/display/index.rst
> index a443866332ac..fe2ecad8df81 100644
> --- a/Documentation/gpu/amdgpu/display/index.rst
> +++ b/Documentation/gpu/amdgpu/display/index.rst
> @@ -2,28 +2,27 @@
> drm/amd/display - Display Core (DC)
> ===================================
>
> -*placeholder - general description of supported platforms, what dc
> is, etc.*
> -
> -Because it is partially shared with other operating systems, the
> Display Core
> -Driver is divided in two pieces.
> +AMD display engine is partially shared with other operating systems;
> for this
> +reason, our Display Core Driver is divided into two pieces:
>
> 1. **Display Core (DC)** contains the OS-agnostic components. Things
> like
> hardware programming and resource management are handled here.
> 2. **Display Manager (DM)** contains the OS-dependent components.
> Hooks to the
> amdgpu base driver and DRM are implemented here.
>
> -It doesn't help that the entire package is frequently referred to as
> DC. But
> -with the context in mind, it should be clear.
> +The display pipe is responsible for "scanning out" a rendered frame
> from the
> +GPU memory (also called VRAM, FrameBuffer, etc.) to a display. In
> other words,
> +it would:
>
> -When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default
> for
> -supported ASICs. To force disable, set `amdgpu.dc=0` on kernel
> command line.
> -Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`.
> +1. Read frame information from memory;
> +2. Perform required transformation;
> +3. Send pixel data to sink devices.
>
> -To determine if DC is loaded, search dmesg for the following entry:
> +If you want to learn more about our driver details, take a look at
> the below
> +table of content:
>
> .. toctree::
>
> display-manager.rst
> dc-debug.rst
> -
> -``Display Core initialized with <version number here>``
> + dcn-overview.rst
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 5/6] Documentation/gpu: Add basic overview of DC pipeline
@ 2021-12-03 21:06 ` Yann Dirson
0 siblings, 0 replies; 31+ messages in thread
From: Yann Dirson @ 2021-12-03 21:06 UTC (permalink / raw)
To: Rodrigo Siqueira
Cc: Mark Yacoub, Harry Wentland, linux-doc, Simon Ser, qingqing zhuo,
Marek Olsak, roman li, amd-gfx, Roman Gilg, Michel Daenzer,
Pekka Paalanen, aurabindo pillai, nicholas choi, dri-devel,
Daniel Vetter, Bas Nieuwenhuizen, Alex Deucher, Sean Paul,
Nicholas Kazlauskas, bhawanpreet lakha, Christian Koenig
> De: "Rodrigo Siqueira" <Rodrigo.Siqueira@amd.com>
> Objet: [PATCH v2 5/6] Documentation/gpu: Add basic overview of DC pipeline
>
> This commit describes how DCN works by providing high-level diagrams
> with an explanation of each component. In particular, it details the
> Global Sync signals.
>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
> .../gpu/amdgpu/display/config_example.svg | 414 ++++++
> .../amdgpu/display/dc_pipeline_overview.svg | 1125
> +++++++++++++++++
> .../gpu/amdgpu/display/dcn-overview.rst | 168 +++
> .../gpu/amdgpu/display/global_sync_vblank.svg | 485 +++++++
> Documentation/gpu/amdgpu/display/index.rst | 23 +-
> 5 files changed, 2203 insertions(+), 12 deletions(-)
> create mode 100644
> Documentation/gpu/amdgpu/display/config_example.svg
> create mode 100644
> Documentation/gpu/amdgpu/display/dc_pipeline_overview.svg
> create mode 100644 Documentation/gpu/amdgpu/display/dcn-overview.rst
> create mode 100644
> Documentation/gpu/amdgpu/display/global_sync_vblank.svg
>
...
> diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst
> b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> new file mode 100644
> index 000000000000..47e9a70de8ae
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> @@ -0,0 +1,168 @@
> +=======================
> +Display Core Next (DCN)
> +=======================
> +
> +To equip our readers with the basic knowledge of how AMD Display
> Core Next
> +(DCN) works, we need to start with an overview of the hardware
> pipeline. Below
> +you can see a picture that provides a DCN overview, keep in mind
> that this is a
> +generic diagram, and we have variations per ASIC.
> +
> +.. kernel-figure:: dc_pipeline_overview.svg
> +
> +Based on this diagram, we can pass through each block and briefly
> describe
> +them:
Maybe a note on MMHUBBUB is missing ?
> +
> +* **Display Controller Hub (DCHUB)**: This is the gateway between
> the Scalable
> + Data Port (SDP) and DCN. This component has multiple features,
> such as memory
> + arbitration, rotation, and cursor manipulation.
> +
> +* **Display Pipe and Plane (DPP)**: This block provides pre-blend
> pixel
> + processing such as color space conversion, linearization of pixel
> data, tone
> + mapping, and gamut mapping.
> +
> +* **Multiple Pipe/Plane Combined (MPC)**: This component performs
> blending of
> + multiple planes, using global or per-pixel alpha.
> +
> +* **Output Pixel Processing (OPP)**: Process and format pixels to be
> sent to
> + the display.
> +
> +* **Output Pipe Timing Combiner (OPTC)**: It generates time output
> to combine
> + streams or divide capabilities. CRC values are generated in this
> block.
> +
> +* **Display Output (DIO)**: Codify the output to the display
> connected to our
> + GPU.
> +
> +* **Display Writeback (DWB)**: It provides the ability to write the
> output of
> + the display pipe back to memory as video frames.
> +
> +* **DCN Management Unit (DMU)**: It provides registers with access
> control and
> + interrupts the controller to the SOC host interrupt unit. This
> block includes
> + the Display Micro-Controller Unit - version B (DMCUB), which is
> handled via
> + firmware.
> +
> +* **DCN Clock Generator Block (DCCG)**: It provides the clocks and
> resets
> + for all of the display controller clock domains.
> +
> +* **Azalia (AZ)**: Audio engine.
> +
> +The above diagram is an architecture generalization of DCN, which
> means that
> +every ASIC has variations around this base model. Notice that the
> display
> +pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you
> can see
> +the SDP as the element from our Data Fabric that feeds the display
> pipe.
> +
> +Always approach the DCN architecture as something flexible that can
> be
> +configured and reconfigured in multiple ways; in other words, each
> block can be
> +setup or ignored accordingly with userspace demands. For example, if
> we
> +want to drive an 8k@60Hz with a DSC enabled, our DCN may require 4
> DPP and 2
> +OPP. It is DC's responsibility to drive the best configuration for
> each
> +specific scenario. Orchestrate all of these components together
> requires a
> +sophisticated communication interface which is highlighted in the
> diagram by
> +the edges that connect each block; from the chart, each connection
> between
> +these blocks represents:
> +
> +1. Pixel data interface (red): Represents the pixel data flow;
> +2. Global sync signals (green): It is a set of synchronization
> signals composed
> + by VStartup, VUpdate, and VReady;
> +3. Config interface: Responsible to configure blocks;
> +4. Sideband signals: All other signals that do not fit the previous
> one.
> +
> +These signals are essential and play an important role in DCN.
> Nevertheless,
> +the Global Sync deserves an extra level of detail described in the
> next
> +section.
> +
> +All of these components are represented by a data structure named
> dc_state.
> +From DCHUB to MPC, we have a representation called dc_plane; from
> MPC to OPTC,
> +we have dc_stream, and the output (DIO) is handled by dc_link. Keep
> in mind
> +that HUBP accesses a surface using a specific format read from
> memory, and our
> +dc_plane should work to convert all pixels in the plane to something
> that can
> +be sent to the display via dc_stream and dc_link.
> +
> +Front End and Back End
> +----------------------
> +
> +Display pipeline can be broken down into two components that are
> usually
> +referred as **Front End (FE)** and **Back End (BE)**, where FE
> consists of:
> +
> +* DCHUB (Mainly referring to a subcomponent named HUBP)
> +* DPP
> +* MPC
> +
> +On the other hand, BE consist of
> +
> +* OPP
> +* OPTC
> +* DIO (DP/HDMI stream encoder and link encoder)
> +
> +OPP and OPTC are two joining blocks between FE and BE. On a side
> note, this is
> +a one-to-one mapping of the link encoder to PHY, but we can
> configure the DCN
> +to choose which link encoder to connect to which PHY. FE's main
> responsibility
> +is to change, blend and compose pixel data, while BE's job is to
> frame a
> +generic pixel stream to a specific display's pixel stream.
> +
> +Data Flow
> +---------
> +
> +Initially, data is passed in from VRAM through Data Fabric (DF) in
> native pixel
> +formats. Such data format stays through till HUBP in DCHUB, where
> HUBP unpacks
> +different pixel formats and outputs them to DPP in uniform streams
> through 4
> +channels (1 for alpha + 3 for colors).
> +
> +The Converter and Cursor (CNVC) in DPP would then normalize the data
> +representation and convert them to a DCN specific floating-point
> format (i.e.,
> +different from the IEEE floating-point format). In the process, CNVC
> also
> +applies a degamma function to transform the data from non-linear to
> linear
> +space to relax the floating-point calculations following. Data would
> stay in
> +this floating-point format from DPP to OPP.
> +
> +Starting OPP, because color transformation and blending have been
> completed
> +(i.e alpha can be dropped), and the end sinks do not require the
> precision and
> +dynamic range that floating points provide (i.e. all displays are in
> integer
> +depth format), bit-depth reduction/dithering would kick in. In OPP,
> we would
> +also apply a regamma function to introduce the gamma removed earlier
> back.
> +Eventually, we output data in integer format at DIO.
> +
> +Global Sync
> +-----------
> +
> +Many DCN registers are double buffered, most importantly the surface
> address.
> +This allows us to updated DCN hardware atomically for page flips, as
> well as
to update ?
> +for most other updates that don't require enabling or disabling of
> new pipes.
> +
> +(Note: There are many scenarios when DC will decide to reserve extra
> pipes
> +in order to support outputs that need a very high pixel clock, or
> for
> +power saving purposes.)
> +
> +These atomic register updates are driven by global sync signals in
> DCN. In
> +order to understand how atomic updates interact with DCN hardware,
> and how DCN
> +signals page flip and vblank events it is helpful to understand how
> global sync
> +is programmed.
> +
> +Global sync consists of three signals, VSTARTUP, VUPDATE, and
> VREADY. These are
> +calculated by the Display Mode Library - DML
> (drivers/gpu/drm/amd/display/dc/dml)
> +based on a large number of parameters and ensure our hardware is
> able to feed
> +the DCN pipeline without underflows or hangs in any given system
> configuration.
> +The global sync signals always happen during VBlank, are independent
> from the
> +VSync signal, and do not overlap each other.
> +
> +VUPDATE is the only signal that is of interest to the rest of the
> driver stack
> +or userspace clients as it signals the point at which hardware
> latches to
> +atomically programmed (i.e. double buffered) registers. Even though
> it is
> +independent of the VSync signal we use VUPDATE to signal the VSync
> event as it
> +provides the best indication of how atomic commits and hardware
> interact.
> +
> +Since DCN hardware is double-buffered the DC driver is able to
> program the
> +hardware at any point during the frame.
> +
> +The below picture illustrates the global sync signals:
> +
> +.. kernel-figure:: global_sync_vblank.svg
> +
> +These signals affect core DCN behavior. Programming them incorrectly
> will lead
> +to a number of negative consequences, most of them quite
> catastrophic.
> +
> +The following picture shows how global sync allows for a mailbox
> style of
> +updates, i.e. it allows for multiple re-configurations between
> VUpdate
> +events where only the last configuration programmed before the
> VUpdate signal
> +becomes effective.
> +
> +.. kernel-figure:: config_example.svg
...
> diff --git a/Documentation/gpu/amdgpu/display/index.rst
> b/Documentation/gpu/amdgpu/display/index.rst
> index a443866332ac..fe2ecad8df81 100644
> --- a/Documentation/gpu/amdgpu/display/index.rst
> +++ b/Documentation/gpu/amdgpu/display/index.rst
> @@ -2,28 +2,27 @@
> drm/amd/display - Display Core (DC)
> ===================================
>
> -*placeholder - general description of supported platforms, what dc
> is, etc.*
> -
> -Because it is partially shared with other operating systems, the
> Display Core
> -Driver is divided in two pieces.
> +AMD display engine is partially shared with other operating systems;
> for this
> +reason, our Display Core Driver is divided into two pieces:
>
> 1. **Display Core (DC)** contains the OS-agnostic components. Things
> like
> hardware programming and resource management are handled here.
> 2. **Display Manager (DM)** contains the OS-dependent components.
> Hooks to the
> amdgpu base driver and DRM are implemented here.
>
> -It doesn't help that the entire package is frequently referred to as
> DC. But
> -with the context in mind, it should be clear.
> +The display pipe is responsible for "scanning out" a rendered frame
> from the
> +GPU memory (also called VRAM, FrameBuffer, etc.) to a display. In
> other words,
> +it would:
>
> -When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default
> for
> -supported ASICs. To force disable, set `amdgpu.dc=0` on kernel
> command line.
> -Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`.
> +1. Read frame information from memory;
> +2. Perform required transformation;
> +3. Send pixel data to sink devices.
>
> -To determine if DC is loaded, search dmesg for the following entry:
> +If you want to learn more about our driver details, take a look at
> the below
> +table of content:
>
> .. toctree::
>
> display-manager.rst
> dc-debug.rst
> -
> -``Display Core initialized with <version number here>``
> + dcn-overview.rst
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
2021-12-02 16:01 ` Rodrigo Siqueira
(?)
@ 2021-12-07 18:19 ` Daniel Vetter
-1 siblings, 0 replies; 31+ messages in thread
From: Daniel Vetter @ 2021-12-07 18:19 UTC (permalink / raw)
To: Rodrigo Siqueira
Cc: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Nicholas Kazlauskas, Harry Wentland, Mark Yacoub,
Sean Paul, Pekka Paalanen, Yann Dirson, Daniel Vetter, linux-doc,
qingqing.zhuo, roman.li, amd-gfx, aurabindo.pillai,
nicholas.choi, dri-devel, Alex Deucher, bhawanpreet.lakha,
Christian Koenig
On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
> In the DC driver, we have multiple acronyms that are not obvious most of
> the time; the same idea is valid for amdgpu. This commit introduces a DC
> and amdgpu glossary in order to make it easier to navigate through our
> driver.
>
> Changes since V1:
> - Yann: Divide glossary based on driver context.
> - Alex: Make terms more consistent and update CPLIB
> - Add new acronyms to the glossary
>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
> .../gpu/amdgpu/display/dc-glossary.rst | 243 ++++++++++++++++++
> Documentation/gpu/amdgpu/display/index.rst | 1 +
> Documentation/gpu/amdgpu/index.rst | 7 +
> 4 files changed, 298 insertions(+)
> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
> create mode 100644 Documentation/gpu/amdgpu/display/dc-glossary.rst
>
> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> new file mode 100644
> index 000000000000..e635851025e7
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -0,0 +1,47 @@
> +===============
> +AMDGPU Glossary
> +===============
> +
> +Here you can find some generic acronyms used in the amdgpu driver. Notice that
> +we have a dedicated glossary for Display Core.
Maybe add a link to that here so it's easier to find? sphinx autogenerates
header targets so pretty easy (if the heading is unique at least).
-Daniel
> +
> +.. glossary::
> +
> + CPLIB
> + Content Protection Library
> +
> + DFS
> + Digital Frequency Synthesizer
> +
> + ECP
> + Enhanced Content Protection
> +
> + EOP
> + End Of Pipe/Pipeline
> +
> + HQD
> + Hardware Queue Descriptor
> +
> + KCQ
> + Kernel Compute Queue
> +
> + KGQ
> + Kernel Graphics Queue
> +
> + KIQ
> + Kernel Interface Queue
> +
> + MQD
> + Memory Queue Descriptor
> +
> + PPLib
> + PowerPlay Library - PowerPlay is the power management component.
> +
> + SMU
> + System Management Unit
> +
> + VCE
> + Video Compression Engine
> +
> + VCN
> + Video Codec Next
> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> new file mode 100644
> index 000000000000..547c0bfbb3e2
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> @@ -0,0 +1,243 @@
> +===========
> +DC Glossary
> +===========
> +
> +On this page, we try to keep track of acronyms related to the display
> +component. If you do not find what you are looking for, look at the amdgpu
> +glossary; if you cannot find it anywhere, consider asking in the amdgfx and
> +update this page.
> +
> +.. glossary::
> +
> + ABM
> + Adaptive Backlight Modulation
> +
> + APU
> + Accelerated Processing Unit
> +
> + ASIC
> + Application-Specific Integrated Circuit
> +
> + ASSR
> + Alternate Scrambler Seed Reset
> +
> + AZ
> + Azalia (HD audio DMA engine)
> +
> + BPC
> + Bits Per Colour/Component
> +
> + BPP
> + Bits Per Pixel
> +
> + Clocks
> + * PCLK: Pixel Clock
> + * SYMCLK: Symbol Clock
> + * SOCCLK: GPU Engine Clock
> + * DISPCLK: Display Clock
> + * DPPCLK: DPP Clock
> + * DCFCLK: Display Controller Fabric Clock
> + * REFCLK: Real Time Reference Clock
> + * PPLL: Pixel PLL
> + * FCLK: Fabric Clock
> + * MCLK: Memory Clock
> +
> + CRC
> + Cyclic Redundancy Check
> +
> + CRTC
> + Cathode Ray Tube Controller - commonly called "Controller" - Generates
> + raw stream of pixels, clocked at pixel clock
> +
> + CVT
> + Coordinated Video Timings
> +
> + DAL
> + Display Abstraction layer
> +
> + DC (Software)
> + Display Core
> +
> + DC (Hardware)
> + Display Controller
> +
> + DCC
> + Delta Colour Compression
> +
> + DCE
> + Display Controller Engine
> +
> + DCHUB
> + Display Controller HUB
> +
> + ARB
> + Arbiter
> +
> + VTG
> + Vertical Timing Generator
> +
> + DCN
> + Display Core Next
> +
> + DCCG
> + Display Clock Generator block
> +
> + DDC
> + Display Data Channel
> +
> + DIO
> + Display IO
> +
> + DPP
> + Display Pipes and Planes
> +
> + DSC
> + Display Stream Compression (Reduce the amount of bits to represent pixel
> + count while at the same pixel clock)
> +
> + dGPU
> + discrete GPU
> +
> + DMIF
> + Display Memory Interface
> +
> + DML
> + Display Mode Library
> +
> + DMCU
> + Display Micro-Controller Unit
> +
> + DMCUB
> + Display Micro-Controller Unit, version B
> +
> + DPCD
> + DisplayPort Configuration Data
> +
> + DPM(S)
> + Display Power Management (Signaling)
> +
> + DRR
> + Dynamic Refresh Rate
> +
> + DWB
> + Display Writeback
> +
> + FB
> + Frame Buffer
> +
> + FBC
> + Frame Buffer Compression
> +
> + FEC
> + Forward Error Correction
> +
> + FRL
> + Fixed Rate Link
> +
> + GCO
> + Graphical Controller Object
> +
> + GMC
> + Graphic Memory Controller
> +
> + GSL
> + Global Swap Lock
> +
> + iGPU
> + integrated GPU
> +
> + IH
> + Interrupt Handler
> +
> + ISR
> + Interrupt Service Request
> +
> + ISV
> + Independent Software Vendor
> +
> + KMD
> + Kernel Mode Driver
> +
> + LB
> + Line Buffer
> +
> + LFC
> + Low Framerate Compensation
> +
> + LTTPR
> + Link Training Tunable Phy Repeater
> +
> + LUT
> + Lookup Table
> +
> + MALL
> + Memory Access at Last Level
> +
> + MC
> + Memory Controller
> +
> + MPC
> + Multiple pipes and plane combine
> +
> + MPO
> + Multi Plane Overlay
> +
> + MST
> + Multi Stream Transport
> +
> + NBP State
> + Northbridge Power State
> +
> + NBIO
> + North Bridge Input/Output
> +
> + ODM
> + Output Data Mapping
> +
> + OPM
> + Output Protection Manager
> +
> + OPP
> + Output Plane Processor
> +
> + OPTC
> + Output Pipe Timing Combiner
> +
> + OTG
> + Output Timing Generator
> +
> + PCON
> + Power Controller
> +
> + PGFSM
> + Power Gate Finite State Machine
> +
> + PSR
> + Panel Self Refresh
> +
> + SCL
> + Scaler
> +
> + SDP
> + Scalable Data Port
> +
> + SLS
> + Single Large Surface
> +
> + SST
> + Single Stream Transport
> +
> + TMDS
> + Transition-Minimized Differential Signaling
> +
> + TMZ
> + Trusted Memory Zone
> +
> + TTU
> + Time to Underflow
> +
> + VRR
> + Variable Refresh Rate
> +
> + UVD
> + Unified Video Decoder
> diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
> index fe2ecad8df81..e23c752ee5f5 100644
> --- a/Documentation/gpu/amdgpu/display/index.rst
> +++ b/Documentation/gpu/amdgpu/display/index.rst
> @@ -26,3 +26,4 @@ table of content:
> display-manager.rst
> dc-debug.rst
> dcn-overview.rst
> + dc-glossary.rst
> diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
> index 5c8cbf514097..ff38c360b04e 100644
> --- a/Documentation/gpu/amdgpu/index.rst
> +++ b/Documentation/gpu/amdgpu/index.rst
> @@ -334,3 +334,10 @@ smartshift_bias
>
> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> :doc: smartshift_bias
> +
> +AMDGPU Glossary
> +===============
> +
> +.. toctree::
> +
> + amdgpu-glossary.rst
> --
> 2.25.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
@ 2021-12-07 18:19 ` Daniel Vetter
0 siblings, 0 replies; 31+ messages in thread
From: Daniel Vetter @ 2021-12-07 18:19 UTC (permalink / raw)
To: Rodrigo Siqueira
Cc: linux-doc, dri-devel, amd-gfx, aurabindo.pillai, Roman Gilg,
Marek Olsak, Yann Dirson, Michel Daenzer, Sean Paul,
bhawanpreet.lakha, Mark Yacoub, qingqing.zhuo, roman.li,
Christian Koenig, nicholas.choi, Alex Deucher,
Nicholas Kazlauskas
On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
> In the DC driver, we have multiple acronyms that are not obvious most of
> the time; the same idea is valid for amdgpu. This commit introduces a DC
> and amdgpu glossary in order to make it easier to navigate through our
> driver.
>
> Changes since V1:
> - Yann: Divide glossary based on driver context.
> - Alex: Make terms more consistent and update CPLIB
> - Add new acronyms to the glossary
>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
> .../gpu/amdgpu/display/dc-glossary.rst | 243 ++++++++++++++++++
> Documentation/gpu/amdgpu/display/index.rst | 1 +
> Documentation/gpu/amdgpu/index.rst | 7 +
> 4 files changed, 298 insertions(+)
> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
> create mode 100644 Documentation/gpu/amdgpu/display/dc-glossary.rst
>
> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> new file mode 100644
> index 000000000000..e635851025e7
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -0,0 +1,47 @@
> +===============
> +AMDGPU Glossary
> +===============
> +
> +Here you can find some generic acronyms used in the amdgpu driver. Notice that
> +we have a dedicated glossary for Display Core.
Maybe add a link to that here so it's easier to find? sphinx autogenerates
header targets so pretty easy (if the heading is unique at least).
-Daniel
> +
> +.. glossary::
> +
> + CPLIB
> + Content Protection Library
> +
> + DFS
> + Digital Frequency Synthesizer
> +
> + ECP
> + Enhanced Content Protection
> +
> + EOP
> + End Of Pipe/Pipeline
> +
> + HQD
> + Hardware Queue Descriptor
> +
> + KCQ
> + Kernel Compute Queue
> +
> + KGQ
> + Kernel Graphics Queue
> +
> + KIQ
> + Kernel Interface Queue
> +
> + MQD
> + Memory Queue Descriptor
> +
> + PPLib
> + PowerPlay Library - PowerPlay is the power management component.
> +
> + SMU
> + System Management Unit
> +
> + VCE
> + Video Compression Engine
> +
> + VCN
> + Video Codec Next
> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> new file mode 100644
> index 000000000000..547c0bfbb3e2
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> @@ -0,0 +1,243 @@
> +===========
> +DC Glossary
> +===========
> +
> +On this page, we try to keep track of acronyms related to the display
> +component. If you do not find what you are looking for, look at the amdgpu
> +glossary; if you cannot find it anywhere, consider asking in the amdgfx and
> +update this page.
> +
> +.. glossary::
> +
> + ABM
> + Adaptive Backlight Modulation
> +
> + APU
> + Accelerated Processing Unit
> +
> + ASIC
> + Application-Specific Integrated Circuit
> +
> + ASSR
> + Alternate Scrambler Seed Reset
> +
> + AZ
> + Azalia (HD audio DMA engine)
> +
> + BPC
> + Bits Per Colour/Component
> +
> + BPP
> + Bits Per Pixel
> +
> + Clocks
> + * PCLK: Pixel Clock
> + * SYMCLK: Symbol Clock
> + * SOCCLK: GPU Engine Clock
> + * DISPCLK: Display Clock
> + * DPPCLK: DPP Clock
> + * DCFCLK: Display Controller Fabric Clock
> + * REFCLK: Real Time Reference Clock
> + * PPLL: Pixel PLL
> + * FCLK: Fabric Clock
> + * MCLK: Memory Clock
> +
> + CRC
> + Cyclic Redundancy Check
> +
> + CRTC
> + Cathode Ray Tube Controller - commonly called "Controller" - Generates
> + raw stream of pixels, clocked at pixel clock
> +
> + CVT
> + Coordinated Video Timings
> +
> + DAL
> + Display Abstraction layer
> +
> + DC (Software)
> + Display Core
> +
> + DC (Hardware)
> + Display Controller
> +
> + DCC
> + Delta Colour Compression
> +
> + DCE
> + Display Controller Engine
> +
> + DCHUB
> + Display Controller HUB
> +
> + ARB
> + Arbiter
> +
> + VTG
> + Vertical Timing Generator
> +
> + DCN
> + Display Core Next
> +
> + DCCG
> + Display Clock Generator block
> +
> + DDC
> + Display Data Channel
> +
> + DIO
> + Display IO
> +
> + DPP
> + Display Pipes and Planes
> +
> + DSC
> + Display Stream Compression (Reduce the amount of bits to represent pixel
> + count while at the same pixel clock)
> +
> + dGPU
> + discrete GPU
> +
> + DMIF
> + Display Memory Interface
> +
> + DML
> + Display Mode Library
> +
> + DMCU
> + Display Micro-Controller Unit
> +
> + DMCUB
> + Display Micro-Controller Unit, version B
> +
> + DPCD
> + DisplayPort Configuration Data
> +
> + DPM(S)
> + Display Power Management (Signaling)
> +
> + DRR
> + Dynamic Refresh Rate
> +
> + DWB
> + Display Writeback
> +
> + FB
> + Frame Buffer
> +
> + FBC
> + Frame Buffer Compression
> +
> + FEC
> + Forward Error Correction
> +
> + FRL
> + Fixed Rate Link
> +
> + GCO
> + Graphical Controller Object
> +
> + GMC
> + Graphic Memory Controller
> +
> + GSL
> + Global Swap Lock
> +
> + iGPU
> + integrated GPU
> +
> + IH
> + Interrupt Handler
> +
> + ISR
> + Interrupt Service Request
> +
> + ISV
> + Independent Software Vendor
> +
> + KMD
> + Kernel Mode Driver
> +
> + LB
> + Line Buffer
> +
> + LFC
> + Low Framerate Compensation
> +
> + LTTPR
> + Link Training Tunable Phy Repeater
> +
> + LUT
> + Lookup Table
> +
> + MALL
> + Memory Access at Last Level
> +
> + MC
> + Memory Controller
> +
> + MPC
> + Multiple pipes and plane combine
> +
> + MPO
> + Multi Plane Overlay
> +
> + MST
> + Multi Stream Transport
> +
> + NBP State
> + Northbridge Power State
> +
> + NBIO
> + North Bridge Input/Output
> +
> + ODM
> + Output Data Mapping
> +
> + OPM
> + Output Protection Manager
> +
> + OPP
> + Output Plane Processor
> +
> + OPTC
> + Output Pipe Timing Combiner
> +
> + OTG
> + Output Timing Generator
> +
> + PCON
> + Power Controller
> +
> + PGFSM
> + Power Gate Finite State Machine
> +
> + PSR
> + Panel Self Refresh
> +
> + SCL
> + Scaler
> +
> + SDP
> + Scalable Data Port
> +
> + SLS
> + Single Large Surface
> +
> + SST
> + Single Stream Transport
> +
> + TMDS
> + Transition-Minimized Differential Signaling
> +
> + TMZ
> + Trusted Memory Zone
> +
> + TTU
> + Time to Underflow
> +
> + VRR
> + Variable Refresh Rate
> +
> + UVD
> + Unified Video Decoder
> diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
> index fe2ecad8df81..e23c752ee5f5 100644
> --- a/Documentation/gpu/amdgpu/display/index.rst
> +++ b/Documentation/gpu/amdgpu/display/index.rst
> @@ -26,3 +26,4 @@ table of content:
> display-manager.rst
> dc-debug.rst
> dcn-overview.rst
> + dc-glossary.rst
> diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
> index 5c8cbf514097..ff38c360b04e 100644
> --- a/Documentation/gpu/amdgpu/index.rst
> +++ b/Documentation/gpu/amdgpu/index.rst
> @@ -334,3 +334,10 @@ smartshift_bias
>
> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> :doc: smartshift_bias
> +
> +AMDGPU Glossary
> +===============
> +
> +.. toctree::
> +
> + amdgpu-glossary.rst
> --
> 2.25.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
@ 2021-12-07 18:19 ` Daniel Vetter
0 siblings, 0 replies; 31+ messages in thread
From: Daniel Vetter @ 2021-12-07 18:19 UTC (permalink / raw)
To: Rodrigo Siqueira
Cc: linux-doc, dri-devel, amd-gfx, aurabindo.pillai, Roman Gilg,
Harry Wentland, Marek Olsak, Yann Dirson, Michel Daenzer,
Bas Nieuwenhuizen, Pekka Paalanen, Sean Paul, bhawanpreet.lakha,
Mark Yacoub, qingqing.zhuo, roman.li, Christian Koenig,
nicholas.choi, Daniel Vetter, Simon Ser, Alex Deucher,
Nicholas Kazlauskas
On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
> In the DC driver, we have multiple acronyms that are not obvious most of
> the time; the same idea is valid for amdgpu. This commit introduces a DC
> and amdgpu glossary in order to make it easier to navigate through our
> driver.
>
> Changes since V1:
> - Yann: Divide glossary based on driver context.
> - Alex: Make terms more consistent and update CPLIB
> - Add new acronyms to the glossary
>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
> .../gpu/amdgpu/display/dc-glossary.rst | 243 ++++++++++++++++++
> Documentation/gpu/amdgpu/display/index.rst | 1 +
> Documentation/gpu/amdgpu/index.rst | 7 +
> 4 files changed, 298 insertions(+)
> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
> create mode 100644 Documentation/gpu/amdgpu/display/dc-glossary.rst
>
> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> new file mode 100644
> index 000000000000..e635851025e7
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -0,0 +1,47 @@
> +===============
> +AMDGPU Glossary
> +===============
> +
> +Here you can find some generic acronyms used in the amdgpu driver. Notice that
> +we have a dedicated glossary for Display Core.
Maybe add a link to that here so it's easier to find? sphinx autogenerates
header targets so pretty easy (if the heading is unique at least).
-Daniel
> +
> +.. glossary::
> +
> + CPLIB
> + Content Protection Library
> +
> + DFS
> + Digital Frequency Synthesizer
> +
> + ECP
> + Enhanced Content Protection
> +
> + EOP
> + End Of Pipe/Pipeline
> +
> + HQD
> + Hardware Queue Descriptor
> +
> + KCQ
> + Kernel Compute Queue
> +
> + KGQ
> + Kernel Graphics Queue
> +
> + KIQ
> + Kernel Interface Queue
> +
> + MQD
> + Memory Queue Descriptor
> +
> + PPLib
> + PowerPlay Library - PowerPlay is the power management component.
> +
> + SMU
> + System Management Unit
> +
> + VCE
> + Video Compression Engine
> +
> + VCN
> + Video Codec Next
> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> new file mode 100644
> index 000000000000..547c0bfbb3e2
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> @@ -0,0 +1,243 @@
> +===========
> +DC Glossary
> +===========
> +
> +On this page, we try to keep track of acronyms related to the display
> +component. If you do not find what you are looking for, look at the amdgpu
> +glossary; if you cannot find it anywhere, consider asking in the amdgfx and
> +update this page.
> +
> +.. glossary::
> +
> + ABM
> + Adaptive Backlight Modulation
> +
> + APU
> + Accelerated Processing Unit
> +
> + ASIC
> + Application-Specific Integrated Circuit
> +
> + ASSR
> + Alternate Scrambler Seed Reset
> +
> + AZ
> + Azalia (HD audio DMA engine)
> +
> + BPC
> + Bits Per Colour/Component
> +
> + BPP
> + Bits Per Pixel
> +
> + Clocks
> + * PCLK: Pixel Clock
> + * SYMCLK: Symbol Clock
> + * SOCCLK: GPU Engine Clock
> + * DISPCLK: Display Clock
> + * DPPCLK: DPP Clock
> + * DCFCLK: Display Controller Fabric Clock
> + * REFCLK: Real Time Reference Clock
> + * PPLL: Pixel PLL
> + * FCLK: Fabric Clock
> + * MCLK: Memory Clock
> +
> + CRC
> + Cyclic Redundancy Check
> +
> + CRTC
> + Cathode Ray Tube Controller - commonly called "Controller" - Generates
> + raw stream of pixels, clocked at pixel clock
> +
> + CVT
> + Coordinated Video Timings
> +
> + DAL
> + Display Abstraction layer
> +
> + DC (Software)
> + Display Core
> +
> + DC (Hardware)
> + Display Controller
> +
> + DCC
> + Delta Colour Compression
> +
> + DCE
> + Display Controller Engine
> +
> + DCHUB
> + Display Controller HUB
> +
> + ARB
> + Arbiter
> +
> + VTG
> + Vertical Timing Generator
> +
> + DCN
> + Display Core Next
> +
> + DCCG
> + Display Clock Generator block
> +
> + DDC
> + Display Data Channel
> +
> + DIO
> + Display IO
> +
> + DPP
> + Display Pipes and Planes
> +
> + DSC
> + Display Stream Compression (Reduce the amount of bits to represent pixel
> + count while at the same pixel clock)
> +
> + dGPU
> + discrete GPU
> +
> + DMIF
> + Display Memory Interface
> +
> + DML
> + Display Mode Library
> +
> + DMCU
> + Display Micro-Controller Unit
> +
> + DMCUB
> + Display Micro-Controller Unit, version B
> +
> + DPCD
> + DisplayPort Configuration Data
> +
> + DPM(S)
> + Display Power Management (Signaling)
> +
> + DRR
> + Dynamic Refresh Rate
> +
> + DWB
> + Display Writeback
> +
> + FB
> + Frame Buffer
> +
> + FBC
> + Frame Buffer Compression
> +
> + FEC
> + Forward Error Correction
> +
> + FRL
> + Fixed Rate Link
> +
> + GCO
> + Graphical Controller Object
> +
> + GMC
> + Graphic Memory Controller
> +
> + GSL
> + Global Swap Lock
> +
> + iGPU
> + integrated GPU
> +
> + IH
> + Interrupt Handler
> +
> + ISR
> + Interrupt Service Request
> +
> + ISV
> + Independent Software Vendor
> +
> + KMD
> + Kernel Mode Driver
> +
> + LB
> + Line Buffer
> +
> + LFC
> + Low Framerate Compensation
> +
> + LTTPR
> + Link Training Tunable Phy Repeater
> +
> + LUT
> + Lookup Table
> +
> + MALL
> + Memory Access at Last Level
> +
> + MC
> + Memory Controller
> +
> + MPC
> + Multiple pipes and plane combine
> +
> + MPO
> + Multi Plane Overlay
> +
> + MST
> + Multi Stream Transport
> +
> + NBP State
> + Northbridge Power State
> +
> + NBIO
> + North Bridge Input/Output
> +
> + ODM
> + Output Data Mapping
> +
> + OPM
> + Output Protection Manager
> +
> + OPP
> + Output Plane Processor
> +
> + OPTC
> + Output Pipe Timing Combiner
> +
> + OTG
> + Output Timing Generator
> +
> + PCON
> + Power Controller
> +
> + PGFSM
> + Power Gate Finite State Machine
> +
> + PSR
> + Panel Self Refresh
> +
> + SCL
> + Scaler
> +
> + SDP
> + Scalable Data Port
> +
> + SLS
> + Single Large Surface
> +
> + SST
> + Single Stream Transport
> +
> + TMDS
> + Transition-Minimized Differential Signaling
> +
> + TMZ
> + Trusted Memory Zone
> +
> + TTU
> + Time to Underflow
> +
> + VRR
> + Variable Refresh Rate
> +
> + UVD
> + Unified Video Decoder
> diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
> index fe2ecad8df81..e23c752ee5f5 100644
> --- a/Documentation/gpu/amdgpu/display/index.rst
> +++ b/Documentation/gpu/amdgpu/display/index.rst
> @@ -26,3 +26,4 @@ table of content:
> display-manager.rst
> dc-debug.rst
> dcn-overview.rst
> + dc-glossary.rst
> diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
> index 5c8cbf514097..ff38c360b04e 100644
> --- a/Documentation/gpu/amdgpu/index.rst
> +++ b/Documentation/gpu/amdgpu/index.rst
> @@ -334,3 +334,10 @@ smartshift_bias
>
> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> :doc: smartshift_bias
> +
> +AMDGPU Glossary
> +===============
> +
> +.. toctree::
> +
> + amdgpu-glossary.rst
> --
> 2.25.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
2021-12-07 18:19 ` Daniel Vetter
(?)
@ 2021-12-07 19:49 ` Yann Dirson
-1 siblings, 0 replies; 31+ messages in thread
From: Yann Dirson @ 2021-12-07 19:49 UTC (permalink / raw)
To: Rodrigo Siqueira
Cc: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Daniel Vetter, Nicholas Kazlauskas, Harry Wentland,
Mark Yacoub, Sean Paul, Pekka Paalanen, linux-doc, qingqing zhuo,
roman li, amd-gfx, aurabindo pillai, nicholas choi, dri-devel,
Alex Deucher, bhawanpreet lakha, Christian Koenig
> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
> > In the DC driver, we have multiple acronyms that are not obvious
> > most of
> > the time; the same idea is valid for amdgpu. This commit introduces
> > a DC
> > and amdgpu glossary in order to make it easier to navigate through
> > our
> > driver.
> >
> > Changes since V1:
> > - Yann: Divide glossary based on driver context.
> > - Alex: Make terms more consistent and update CPLIB
> > - Add new acronyms to the glossary
If you're rerolling, it could be a good time to include the additional
(and detailed) entries from Alex's answer to "Looking for clarifications
around gfx/kcq/kiq". Finding a way to fit the other details not
fitting directly in the glossary will likely take more rounds, though,
so we can wait for the first round to be merged before dealing with them.
> >
> > Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> > ---
> > Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
> > .../gpu/amdgpu/display/dc-glossary.rst | 243
> > ++++++++++++++++++
> > Documentation/gpu/amdgpu/display/index.rst | 1 +
> > Documentation/gpu/amdgpu/index.rst | 7 +
> > 4 files changed, 298 insertions(+)
> > create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > create mode 100644
> > Documentation/gpu/amdgpu/display/dc-glossary.rst
> >
> > diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > new file mode 100644
> > index 000000000000..e635851025e7
> > --- /dev/null
> > +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > @@ -0,0 +1,47 @@
> > +===============
> > +AMDGPU Glossary
> > +===============
> > +
> > +Here you can find some generic acronyms used in the amdgpu driver.
> > Notice that
> > +we have a dedicated glossary for Display Core.
>
> Maybe add a link to that here so it's easier to find? sphinx
> autogenerates
> header targets so pretty easy (if the heading is unique at least).
> -Daniel
>
> > +
> > +.. glossary::
> > +
> > + CPLIB
> > + Content Protection Library
> > +
> > + DFS
> > + Digital Frequency Synthesizer
> > +
> > + ECP
> > + Enhanced Content Protection
> > +
> > + EOP
> > + End Of Pipe/Pipeline
> > +
> > + HQD
> > + Hardware Queue Descriptor
> > +
> > + KCQ
> > + Kernel Compute Queue
> > +
> > + KGQ
> > + Kernel Graphics Queue
> > +
> > + KIQ
> > + Kernel Interface Queue
> > +
> > + MQD
> > + Memory Queue Descriptor
> > +
> > + PPLib
> > + PowerPlay Library - PowerPlay is the power management
> > component.
> > +
> > + SMU
> > + System Management Unit
> > +
> > + VCE
> > + Video Compression Engine
> > +
> > + VCN
> > + Video Codec Next
> > diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
> > b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> > new file mode 100644
> > index 000000000000..547c0bfbb3e2
> > --- /dev/null
> > +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> > @@ -0,0 +1,243 @@
> > +===========
> > +DC Glossary
> > +===========
> > +
> > +On this page, we try to keep track of acronyms related to the
> > display
> > +component. If you do not find what you are looking for, look at
> > the amdgpu
> > +glossary; if you cannot find it anywhere, consider asking in the
> > amdgfx and
> > +update this page.
> > +
> > +.. glossary::
> > +
> > + ABM
> > + Adaptive Backlight Modulation
> > +
> > + APU
> > + Accelerated Processing Unit
> > +
> > + ASIC
> > + Application-Specific Integrated Circuit
> > +
> > + ASSR
> > + Alternate Scrambler Seed Reset
> > +
> > + AZ
> > + Azalia (HD audio DMA engine)
> > +
> > + BPC
> > + Bits Per Colour/Component
> > +
> > + BPP
> > + Bits Per Pixel
> > +
> > + Clocks
> > + * PCLK: Pixel Clock
> > + * SYMCLK: Symbol Clock
> > + * SOCCLK: GPU Engine Clock
> > + * DISPCLK: Display Clock
> > + * DPPCLK: DPP Clock
> > + * DCFCLK: Display Controller Fabric Clock
> > + * REFCLK: Real Time Reference Clock
> > + * PPLL: Pixel PLL
> > + * FCLK: Fabric Clock
> > + * MCLK: Memory Clock
> > +
> > + CRC
> > + Cyclic Redundancy Check
> > +
> > + CRTC
> > + Cathode Ray Tube Controller - commonly called "Controller" -
> > Generates
> > + raw stream of pixels, clocked at pixel clock
> > +
> > + CVT
> > + Coordinated Video Timings
> > +
> > + DAL
> > + Display Abstraction layer
> > +
> > + DC (Software)
> > + Display Core
> > +
> > + DC (Hardware)
> > + Display Controller
> > +
> > + DCC
> > + Delta Colour Compression
> > +
> > + DCE
> > + Display Controller Engine
> > +
> > + DCHUB
> > + Display Controller HUB
> > +
> > + ARB
> > + Arbiter
> > +
> > + VTG
> > + Vertical Timing Generator
> > +
> > + DCN
> > + Display Core Next
> > +
> > + DCCG
> > + Display Clock Generator block
> > +
> > + DDC
> > + Display Data Channel
> > +
> > + DIO
> > + Display IO
> > +
> > + DPP
> > + Display Pipes and Planes
> > +
> > + DSC
> > + Display Stream Compression (Reduce the amount of bits to
> > represent pixel
> > + count while at the same pixel clock)
> > +
> > + dGPU
> > + discrete GPU
> > +
> > + DMIF
> > + Display Memory Interface
> > +
> > + DML
> > + Display Mode Library
> > +
> > + DMCU
> > + Display Micro-Controller Unit
> > +
> > + DMCUB
> > + Display Micro-Controller Unit, version B
> > +
> > + DPCD
> > + DisplayPort Configuration Data
> > +
> > + DPM(S)
> > + Display Power Management (Signaling)
> > +
> > + DRR
> > + Dynamic Refresh Rate
> > +
> > + DWB
> > + Display Writeback
> > +
> > + FB
> > + Frame Buffer
> > +
> > + FBC
> > + Frame Buffer Compression
> > +
> > + FEC
> > + Forward Error Correction
> > +
> > + FRL
> > + Fixed Rate Link
> > +
> > + GCO
> > + Graphical Controller Object
> > +
> > + GMC
> > + Graphic Memory Controller
> > +
> > + GSL
> > + Global Swap Lock
> > +
> > + iGPU
> > + integrated GPU
> > +
> > + IH
> > + Interrupt Handler
> > +
> > + ISR
> > + Interrupt Service Request
> > +
> > + ISV
> > + Independent Software Vendor
> > +
> > + KMD
> > + Kernel Mode Driver
> > +
> > + LB
> > + Line Buffer
> > +
> > + LFC
> > + Low Framerate Compensation
> > +
> > + LTTPR
> > + Link Training Tunable Phy Repeater
> > +
> > + LUT
> > + Lookup Table
> > +
> > + MALL
> > + Memory Access at Last Level
> > +
> > + MC
> > + Memory Controller
> > +
> > + MPC
> > + Multiple pipes and plane combine
> > +
> > + MPO
> > + Multi Plane Overlay
> > +
> > + MST
> > + Multi Stream Transport
> > +
> > + NBP State
> > + Northbridge Power State
> > +
> > + NBIO
> > + North Bridge Input/Output
> > +
> > + ODM
> > + Output Data Mapping
> > +
> > + OPM
> > + Output Protection Manager
> > +
> > + OPP
> > + Output Plane Processor
> > +
> > + OPTC
> > + Output Pipe Timing Combiner
> > +
> > + OTG
> > + Output Timing Generator
> > +
> > + PCON
> > + Power Controller
> > +
> > + PGFSM
> > + Power Gate Finite State Machine
> > +
> > + PSR
> > + Panel Self Refresh
> > +
> > + SCL
> > + Scaler
> > +
> > + SDP
> > + Scalable Data Port
> > +
> > + SLS
> > + Single Large Surface
> > +
> > + SST
> > + Single Stream Transport
> > +
> > + TMDS
> > + Transition-Minimized Differential Signaling
> > +
> > + TMZ
> > + Trusted Memory Zone
> > +
> > + TTU
> > + Time to Underflow
> > +
> > + VRR
> > + Variable Refresh Rate
> > +
> > + UVD
> > + Unified Video Decoder
> > diff --git a/Documentation/gpu/amdgpu/display/index.rst
> > b/Documentation/gpu/amdgpu/display/index.rst
> > index fe2ecad8df81..e23c752ee5f5 100644
> > --- a/Documentation/gpu/amdgpu/display/index.rst
> > +++ b/Documentation/gpu/amdgpu/display/index.rst
> > @@ -26,3 +26,4 @@ table of content:
> > display-manager.rst
> > dc-debug.rst
> > dcn-overview.rst
> > + dc-glossary.rst
> > diff --git a/Documentation/gpu/amdgpu/index.rst
> > b/Documentation/gpu/amdgpu/index.rst
> > index 5c8cbf514097..ff38c360b04e 100644
> > --- a/Documentation/gpu/amdgpu/index.rst
> > +++ b/Documentation/gpu/amdgpu/index.rst
> > @@ -334,3 +334,10 @@ smartshift_bias
> >
> > .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > :doc: smartshift_bias
> > +
> > +AMDGPU Glossary
> > +===============
> > +
> > +.. toctree::
> > +
> > + amdgpu-glossary.rst
> > --
> > 2.25.1
> >
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
@ 2021-12-07 19:49 ` Yann Dirson
0 siblings, 0 replies; 31+ messages in thread
From: Yann Dirson @ 2021-12-07 19:49 UTC (permalink / raw)
To: Rodrigo Siqueira
Cc: Mark Yacoub, bhawanpreet lakha, nicholas choi, linux-doc,
Michel Daenzer, roman li, amd-gfx, Nicholas Kazlauskas,
Marek Olsak, aurabindo pillai, Sean Paul, dri-devel,
Alex Deucher, qingqing zhuo, Christian Koenig, Roman Gilg
> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
> > In the DC driver, we have multiple acronyms that are not obvious
> > most of
> > the time; the same idea is valid for amdgpu. This commit introduces
> > a DC
> > and amdgpu glossary in order to make it easier to navigate through
> > our
> > driver.
> >
> > Changes since V1:
> > - Yann: Divide glossary based on driver context.
> > - Alex: Make terms more consistent and update CPLIB
> > - Add new acronyms to the glossary
If you're rerolling, it could be a good time to include the additional
(and detailed) entries from Alex's answer to "Looking for clarifications
around gfx/kcq/kiq". Finding a way to fit the other details not
fitting directly in the glossary will likely take more rounds, though,
so we can wait for the first round to be merged before dealing with them.
> >
> > Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> > ---
> > Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
> > .../gpu/amdgpu/display/dc-glossary.rst | 243
> > ++++++++++++++++++
> > Documentation/gpu/amdgpu/display/index.rst | 1 +
> > Documentation/gpu/amdgpu/index.rst | 7 +
> > 4 files changed, 298 insertions(+)
> > create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > create mode 100644
> > Documentation/gpu/amdgpu/display/dc-glossary.rst
> >
> > diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > new file mode 100644
> > index 000000000000..e635851025e7
> > --- /dev/null
> > +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > @@ -0,0 +1,47 @@
> > +===============
> > +AMDGPU Glossary
> > +===============
> > +
> > +Here you can find some generic acronyms used in the amdgpu driver.
> > Notice that
> > +we have a dedicated glossary for Display Core.
>
> Maybe add a link to that here so it's easier to find? sphinx
> autogenerates
> header targets so pretty easy (if the heading is unique at least).
> -Daniel
>
> > +
> > +.. glossary::
> > +
> > + CPLIB
> > + Content Protection Library
> > +
> > + DFS
> > + Digital Frequency Synthesizer
> > +
> > + ECP
> > + Enhanced Content Protection
> > +
> > + EOP
> > + End Of Pipe/Pipeline
> > +
> > + HQD
> > + Hardware Queue Descriptor
> > +
> > + KCQ
> > + Kernel Compute Queue
> > +
> > + KGQ
> > + Kernel Graphics Queue
> > +
> > + KIQ
> > + Kernel Interface Queue
> > +
> > + MQD
> > + Memory Queue Descriptor
> > +
> > + PPLib
> > + PowerPlay Library - PowerPlay is the power management
> > component.
> > +
> > + SMU
> > + System Management Unit
> > +
> > + VCE
> > + Video Compression Engine
> > +
> > + VCN
> > + Video Codec Next
> > diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
> > b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> > new file mode 100644
> > index 000000000000..547c0bfbb3e2
> > --- /dev/null
> > +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> > @@ -0,0 +1,243 @@
> > +===========
> > +DC Glossary
> > +===========
> > +
> > +On this page, we try to keep track of acronyms related to the
> > display
> > +component. If you do not find what you are looking for, look at
> > the amdgpu
> > +glossary; if you cannot find it anywhere, consider asking in the
> > amdgfx and
> > +update this page.
> > +
> > +.. glossary::
> > +
> > + ABM
> > + Adaptive Backlight Modulation
> > +
> > + APU
> > + Accelerated Processing Unit
> > +
> > + ASIC
> > + Application-Specific Integrated Circuit
> > +
> > + ASSR
> > + Alternate Scrambler Seed Reset
> > +
> > + AZ
> > + Azalia (HD audio DMA engine)
> > +
> > + BPC
> > + Bits Per Colour/Component
> > +
> > + BPP
> > + Bits Per Pixel
> > +
> > + Clocks
> > + * PCLK: Pixel Clock
> > + * SYMCLK: Symbol Clock
> > + * SOCCLK: GPU Engine Clock
> > + * DISPCLK: Display Clock
> > + * DPPCLK: DPP Clock
> > + * DCFCLK: Display Controller Fabric Clock
> > + * REFCLK: Real Time Reference Clock
> > + * PPLL: Pixel PLL
> > + * FCLK: Fabric Clock
> > + * MCLK: Memory Clock
> > +
> > + CRC
> > + Cyclic Redundancy Check
> > +
> > + CRTC
> > + Cathode Ray Tube Controller - commonly called "Controller" -
> > Generates
> > + raw stream of pixels, clocked at pixel clock
> > +
> > + CVT
> > + Coordinated Video Timings
> > +
> > + DAL
> > + Display Abstraction layer
> > +
> > + DC (Software)
> > + Display Core
> > +
> > + DC (Hardware)
> > + Display Controller
> > +
> > + DCC
> > + Delta Colour Compression
> > +
> > + DCE
> > + Display Controller Engine
> > +
> > + DCHUB
> > + Display Controller HUB
> > +
> > + ARB
> > + Arbiter
> > +
> > + VTG
> > + Vertical Timing Generator
> > +
> > + DCN
> > + Display Core Next
> > +
> > + DCCG
> > + Display Clock Generator block
> > +
> > + DDC
> > + Display Data Channel
> > +
> > + DIO
> > + Display IO
> > +
> > + DPP
> > + Display Pipes and Planes
> > +
> > + DSC
> > + Display Stream Compression (Reduce the amount of bits to
> > represent pixel
> > + count while at the same pixel clock)
> > +
> > + dGPU
> > + discrete GPU
> > +
> > + DMIF
> > + Display Memory Interface
> > +
> > + DML
> > + Display Mode Library
> > +
> > + DMCU
> > + Display Micro-Controller Unit
> > +
> > + DMCUB
> > + Display Micro-Controller Unit, version B
> > +
> > + DPCD
> > + DisplayPort Configuration Data
> > +
> > + DPM(S)
> > + Display Power Management (Signaling)
> > +
> > + DRR
> > + Dynamic Refresh Rate
> > +
> > + DWB
> > + Display Writeback
> > +
> > + FB
> > + Frame Buffer
> > +
> > + FBC
> > + Frame Buffer Compression
> > +
> > + FEC
> > + Forward Error Correction
> > +
> > + FRL
> > + Fixed Rate Link
> > +
> > + GCO
> > + Graphical Controller Object
> > +
> > + GMC
> > + Graphic Memory Controller
> > +
> > + GSL
> > + Global Swap Lock
> > +
> > + iGPU
> > + integrated GPU
> > +
> > + IH
> > + Interrupt Handler
> > +
> > + ISR
> > + Interrupt Service Request
> > +
> > + ISV
> > + Independent Software Vendor
> > +
> > + KMD
> > + Kernel Mode Driver
> > +
> > + LB
> > + Line Buffer
> > +
> > + LFC
> > + Low Framerate Compensation
> > +
> > + LTTPR
> > + Link Training Tunable Phy Repeater
> > +
> > + LUT
> > + Lookup Table
> > +
> > + MALL
> > + Memory Access at Last Level
> > +
> > + MC
> > + Memory Controller
> > +
> > + MPC
> > + Multiple pipes and plane combine
> > +
> > + MPO
> > + Multi Plane Overlay
> > +
> > + MST
> > + Multi Stream Transport
> > +
> > + NBP State
> > + Northbridge Power State
> > +
> > + NBIO
> > + North Bridge Input/Output
> > +
> > + ODM
> > + Output Data Mapping
> > +
> > + OPM
> > + Output Protection Manager
> > +
> > + OPP
> > + Output Plane Processor
> > +
> > + OPTC
> > + Output Pipe Timing Combiner
> > +
> > + OTG
> > + Output Timing Generator
> > +
> > + PCON
> > + Power Controller
> > +
> > + PGFSM
> > + Power Gate Finite State Machine
> > +
> > + PSR
> > + Panel Self Refresh
> > +
> > + SCL
> > + Scaler
> > +
> > + SDP
> > + Scalable Data Port
> > +
> > + SLS
> > + Single Large Surface
> > +
> > + SST
> > + Single Stream Transport
> > +
> > + TMDS
> > + Transition-Minimized Differential Signaling
> > +
> > + TMZ
> > + Trusted Memory Zone
> > +
> > + TTU
> > + Time to Underflow
> > +
> > + VRR
> > + Variable Refresh Rate
> > +
> > + UVD
> > + Unified Video Decoder
> > diff --git a/Documentation/gpu/amdgpu/display/index.rst
> > b/Documentation/gpu/amdgpu/display/index.rst
> > index fe2ecad8df81..e23c752ee5f5 100644
> > --- a/Documentation/gpu/amdgpu/display/index.rst
> > +++ b/Documentation/gpu/amdgpu/display/index.rst
> > @@ -26,3 +26,4 @@ table of content:
> > display-manager.rst
> > dc-debug.rst
> > dcn-overview.rst
> > + dc-glossary.rst
> > diff --git a/Documentation/gpu/amdgpu/index.rst
> > b/Documentation/gpu/amdgpu/index.rst
> > index 5c8cbf514097..ff38c360b04e 100644
> > --- a/Documentation/gpu/amdgpu/index.rst
> > +++ b/Documentation/gpu/amdgpu/index.rst
> > @@ -334,3 +334,10 @@ smartshift_bias
> >
> > .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > :doc: smartshift_bias
> > +
> > +AMDGPU Glossary
> > +===============
> > +
> > +.. toctree::
> > +
> > + amdgpu-glossary.rst
> > --
> > 2.25.1
> >
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
@ 2021-12-07 19:49 ` Yann Dirson
0 siblings, 0 replies; 31+ messages in thread
From: Yann Dirson @ 2021-12-07 19:49 UTC (permalink / raw)
To: Rodrigo Siqueira
Cc: Mark Yacoub, bhawanpreet lakha, nicholas choi, linux-doc,
Simon Ser, Michel Daenzer, roman li, amd-gfx,
Nicholas Kazlauskas, Marek Olsak, Pekka Paalanen,
aurabindo pillai, Sean Paul, dri-devel, Daniel Vetter,
Bas Nieuwenhuizen, Alex Deucher, qingqing zhuo, Christian Koenig,
Harry Wentland, Roman Gilg
> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
> > In the DC driver, we have multiple acronyms that are not obvious
> > most of
> > the time; the same idea is valid for amdgpu. This commit introduces
> > a DC
> > and amdgpu glossary in order to make it easier to navigate through
> > our
> > driver.
> >
> > Changes since V1:
> > - Yann: Divide glossary based on driver context.
> > - Alex: Make terms more consistent and update CPLIB
> > - Add new acronyms to the glossary
If you're rerolling, it could be a good time to include the additional
(and detailed) entries from Alex's answer to "Looking for clarifications
around gfx/kcq/kiq". Finding a way to fit the other details not
fitting directly in the glossary will likely take more rounds, though,
so we can wait for the first round to be merged before dealing with them.
> >
> > Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> > ---
> > Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
> > .../gpu/amdgpu/display/dc-glossary.rst | 243
> > ++++++++++++++++++
> > Documentation/gpu/amdgpu/display/index.rst | 1 +
> > Documentation/gpu/amdgpu/index.rst | 7 +
> > 4 files changed, 298 insertions(+)
> > create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > create mode 100644
> > Documentation/gpu/amdgpu/display/dc-glossary.rst
> >
> > diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > new file mode 100644
> > index 000000000000..e635851025e7
> > --- /dev/null
> > +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> > @@ -0,0 +1,47 @@
> > +===============
> > +AMDGPU Glossary
> > +===============
> > +
> > +Here you can find some generic acronyms used in the amdgpu driver.
> > Notice that
> > +we have a dedicated glossary for Display Core.
>
> Maybe add a link to that here so it's easier to find? sphinx
> autogenerates
> header targets so pretty easy (if the heading is unique at least).
> -Daniel
>
> > +
> > +.. glossary::
> > +
> > + CPLIB
> > + Content Protection Library
> > +
> > + DFS
> > + Digital Frequency Synthesizer
> > +
> > + ECP
> > + Enhanced Content Protection
> > +
> > + EOP
> > + End Of Pipe/Pipeline
> > +
> > + HQD
> > + Hardware Queue Descriptor
> > +
> > + KCQ
> > + Kernel Compute Queue
> > +
> > + KGQ
> > + Kernel Graphics Queue
> > +
> > + KIQ
> > + Kernel Interface Queue
> > +
> > + MQD
> > + Memory Queue Descriptor
> > +
> > + PPLib
> > + PowerPlay Library - PowerPlay is the power management
> > component.
> > +
> > + SMU
> > + System Management Unit
> > +
> > + VCE
> > + Video Compression Engine
> > +
> > + VCN
> > + Video Codec Next
> > diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
> > b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> > new file mode 100644
> > index 000000000000..547c0bfbb3e2
> > --- /dev/null
> > +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> > @@ -0,0 +1,243 @@
> > +===========
> > +DC Glossary
> > +===========
> > +
> > +On this page, we try to keep track of acronyms related to the
> > display
> > +component. If you do not find what you are looking for, look at
> > the amdgpu
> > +glossary; if you cannot find it anywhere, consider asking in the
> > amdgfx and
> > +update this page.
> > +
> > +.. glossary::
> > +
> > + ABM
> > + Adaptive Backlight Modulation
> > +
> > + APU
> > + Accelerated Processing Unit
> > +
> > + ASIC
> > + Application-Specific Integrated Circuit
> > +
> > + ASSR
> > + Alternate Scrambler Seed Reset
> > +
> > + AZ
> > + Azalia (HD audio DMA engine)
> > +
> > + BPC
> > + Bits Per Colour/Component
> > +
> > + BPP
> > + Bits Per Pixel
> > +
> > + Clocks
> > + * PCLK: Pixel Clock
> > + * SYMCLK: Symbol Clock
> > + * SOCCLK: GPU Engine Clock
> > + * DISPCLK: Display Clock
> > + * DPPCLK: DPP Clock
> > + * DCFCLK: Display Controller Fabric Clock
> > + * REFCLK: Real Time Reference Clock
> > + * PPLL: Pixel PLL
> > + * FCLK: Fabric Clock
> > + * MCLK: Memory Clock
> > +
> > + CRC
> > + Cyclic Redundancy Check
> > +
> > + CRTC
> > + Cathode Ray Tube Controller - commonly called "Controller" -
> > Generates
> > + raw stream of pixels, clocked at pixel clock
> > +
> > + CVT
> > + Coordinated Video Timings
> > +
> > + DAL
> > + Display Abstraction layer
> > +
> > + DC (Software)
> > + Display Core
> > +
> > + DC (Hardware)
> > + Display Controller
> > +
> > + DCC
> > + Delta Colour Compression
> > +
> > + DCE
> > + Display Controller Engine
> > +
> > + DCHUB
> > + Display Controller HUB
> > +
> > + ARB
> > + Arbiter
> > +
> > + VTG
> > + Vertical Timing Generator
> > +
> > + DCN
> > + Display Core Next
> > +
> > + DCCG
> > + Display Clock Generator block
> > +
> > + DDC
> > + Display Data Channel
> > +
> > + DIO
> > + Display IO
> > +
> > + DPP
> > + Display Pipes and Planes
> > +
> > + DSC
> > + Display Stream Compression (Reduce the amount of bits to
> > represent pixel
> > + count while at the same pixel clock)
> > +
> > + dGPU
> > + discrete GPU
> > +
> > + DMIF
> > + Display Memory Interface
> > +
> > + DML
> > + Display Mode Library
> > +
> > + DMCU
> > + Display Micro-Controller Unit
> > +
> > + DMCUB
> > + Display Micro-Controller Unit, version B
> > +
> > + DPCD
> > + DisplayPort Configuration Data
> > +
> > + DPM(S)
> > + Display Power Management (Signaling)
> > +
> > + DRR
> > + Dynamic Refresh Rate
> > +
> > + DWB
> > + Display Writeback
> > +
> > + FB
> > + Frame Buffer
> > +
> > + FBC
> > + Frame Buffer Compression
> > +
> > + FEC
> > + Forward Error Correction
> > +
> > + FRL
> > + Fixed Rate Link
> > +
> > + GCO
> > + Graphical Controller Object
> > +
> > + GMC
> > + Graphic Memory Controller
> > +
> > + GSL
> > + Global Swap Lock
> > +
> > + iGPU
> > + integrated GPU
> > +
> > + IH
> > + Interrupt Handler
> > +
> > + ISR
> > + Interrupt Service Request
> > +
> > + ISV
> > + Independent Software Vendor
> > +
> > + KMD
> > + Kernel Mode Driver
> > +
> > + LB
> > + Line Buffer
> > +
> > + LFC
> > + Low Framerate Compensation
> > +
> > + LTTPR
> > + Link Training Tunable Phy Repeater
> > +
> > + LUT
> > + Lookup Table
> > +
> > + MALL
> > + Memory Access at Last Level
> > +
> > + MC
> > + Memory Controller
> > +
> > + MPC
> > + Multiple pipes and plane combine
> > +
> > + MPO
> > + Multi Plane Overlay
> > +
> > + MST
> > + Multi Stream Transport
> > +
> > + NBP State
> > + Northbridge Power State
> > +
> > + NBIO
> > + North Bridge Input/Output
> > +
> > + ODM
> > + Output Data Mapping
> > +
> > + OPM
> > + Output Protection Manager
> > +
> > + OPP
> > + Output Plane Processor
> > +
> > + OPTC
> > + Output Pipe Timing Combiner
> > +
> > + OTG
> > + Output Timing Generator
> > +
> > + PCON
> > + Power Controller
> > +
> > + PGFSM
> > + Power Gate Finite State Machine
> > +
> > + PSR
> > + Panel Self Refresh
> > +
> > + SCL
> > + Scaler
> > +
> > + SDP
> > + Scalable Data Port
> > +
> > + SLS
> > + Single Large Surface
> > +
> > + SST
> > + Single Stream Transport
> > +
> > + TMDS
> > + Transition-Minimized Differential Signaling
> > +
> > + TMZ
> > + Trusted Memory Zone
> > +
> > + TTU
> > + Time to Underflow
> > +
> > + VRR
> > + Variable Refresh Rate
> > +
> > + UVD
> > + Unified Video Decoder
> > diff --git a/Documentation/gpu/amdgpu/display/index.rst
> > b/Documentation/gpu/amdgpu/display/index.rst
> > index fe2ecad8df81..e23c752ee5f5 100644
> > --- a/Documentation/gpu/amdgpu/display/index.rst
> > +++ b/Documentation/gpu/amdgpu/display/index.rst
> > @@ -26,3 +26,4 @@ table of content:
> > display-manager.rst
> > dc-debug.rst
> > dcn-overview.rst
> > + dc-glossary.rst
> > diff --git a/Documentation/gpu/amdgpu/index.rst
> > b/Documentation/gpu/amdgpu/index.rst
> > index 5c8cbf514097..ff38c360b04e 100644
> > --- a/Documentation/gpu/amdgpu/index.rst
> > +++ b/Documentation/gpu/amdgpu/index.rst
> > @@ -334,3 +334,10 @@ smartshift_bias
> >
> > .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > :doc: smartshift_bias
> > +
> > +AMDGPU Glossary
> > +===============
> > +
> > +.. toctree::
> > +
> > + amdgpu-glossary.rst
> > --
> > 2.25.1
> >
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
2021-12-07 19:49 ` Yann Dirson
(?)
@ 2021-12-08 15:46 ` Rodrigo Siqueira Jordao
-1 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira Jordao @ 2021-12-08 15:46 UTC (permalink / raw)
To: Yann Dirson, Rodrigo Siqueira
Cc: Simon Ser, Michel Daenzer, Bas Nieuwenhuizen, Marek Olsak,
Roman Gilg, Daniel Vetter, Nicholas Kazlauskas, Harry Wentland,
Mark Yacoub, Sean Paul, Pekka Paalanen, linux-doc, qingqing zhuo,
roman li, amd-gfx, aurabindo pillai, nicholas choi, dri-devel,
Alex Deucher, bhawanpreet lakha, Christian Koenig
On 2021-12-07 2:49 p.m., Yann Dirson wrote:
>
>> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
>>> In the DC driver, we have multiple acronyms that are not obvious
>>> most of
>>> the time; the same idea is valid for amdgpu. This commit introduces
>>> a DC
>>> and amdgpu glossary in order to make it easier to navigate through
>>> our
>>> driver.
>>>
>>> Changes since V1:
>>> - Yann: Divide glossary based on driver context.
>>> - Alex: Make terms more consistent and update CPLIB
>>> - Add new acronyms to the glossary
>
> If you're rerolling, it could be a good time to include the additional
> (and detailed) entries from Alex's answer to "Looking for clarifications
> around gfx/kcq/kiq". Finding a way to fit the other details not
> fitting directly in the glossary will likely take more rounds, though,
> so we can wait for the first round to be merged before dealing with them.
Hi Yann,
I will send another version to address Daniel's comment, and I'll also
expand the amdgpu acronyms glossary based on your mail thread with Alex.
However, I don't want to add more details about that discussion in this
series because I don't want to lose focus in this patchset since my main
goal is to start to expand display documentation.
By the way, I think you could consider writing a kernel-doc based on
your discussion with Alex. This way, you can try to consolidate what you
discover and get reviews in the content.
Thanks
Siqueira
>
>
>>>
>>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>>> ---
>>> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
>>> .../gpu/amdgpu/display/dc-glossary.rst | 243
>>> ++++++++++++++++++
>>> Documentation/gpu/amdgpu/display/index.rst | 1 +
>>> Documentation/gpu/amdgpu/index.rst | 7 +
>>> 4 files changed, 298 insertions(+)
>>> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> create mode 100644
>>> Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>
>>> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> new file mode 100644
>>> index 000000000000..e635851025e7
>>> --- /dev/null
>>> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> @@ -0,0 +1,47 @@
>>> +===============
>>> +AMDGPU Glossary
>>> +===============
>>> +
>>> +Here you can find some generic acronyms used in the amdgpu driver.
>>> Notice that
>>> +we have a dedicated glossary for Display Core.
>>
>> Maybe add a link to that here so it's easier to find? sphinx
>> autogenerates
>> header targets so pretty easy (if the heading is unique at least).
>> -Daniel
>>
>>> +
>>> +.. glossary::
>>> +
>>> + CPLIB
>>> + Content Protection Library
>>> +
>>> + DFS
>>> + Digital Frequency Synthesizer
>>> +
>>> + ECP
>>> + Enhanced Content Protection
>>> +
>>> + EOP
>>> + End Of Pipe/Pipeline
>>> +
>>> + HQD
>>> + Hardware Queue Descriptor
>>> +
>>> + KCQ
>>> + Kernel Compute Queue
>>> +
>>> + KGQ
>>> + Kernel Graphics Queue
>>> +
>>> + KIQ
>>> + Kernel Interface Queue
>>> +
>>> + MQD
>>> + Memory Queue Descriptor
>>> +
>>> + PPLib
>>> + PowerPlay Library - PowerPlay is the power management
>>> component.
>>> +
>>> + SMU
>>> + System Management Unit
>>> +
>>> + VCE
>>> + Video Compression Engine
>>> +
>>> + VCN
>>> + Video Codec Next
>>> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>> b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>> new file mode 100644
>>> index 000000000000..547c0bfbb3e2
>>> --- /dev/null
>>> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>> @@ -0,0 +1,243 @@
>>> +===========
>>> +DC Glossary
>>> +===========
>>> +
>>> +On this page, we try to keep track of acronyms related to the
>>> display
>>> +component. If you do not find what you are looking for, look at
>>> the amdgpu
>>> +glossary; if you cannot find it anywhere, consider asking in the
>>> amdgfx and
>>> +update this page.
>>> +
>>> +.. glossary::
>>> +
>>> + ABM
>>> + Adaptive Backlight Modulation
>>> +
>>> + APU
>>> + Accelerated Processing Unit
>>> +
>>> + ASIC
>>> + Application-Specific Integrated Circuit
>>> +
>>> + ASSR
>>> + Alternate Scrambler Seed Reset
>>> +
>>> + AZ
>>> + Azalia (HD audio DMA engine)
>>> +
>>> + BPC
>>> + Bits Per Colour/Component
>>> +
>>> + BPP
>>> + Bits Per Pixel
>>> +
>>> + Clocks
>>> + * PCLK: Pixel Clock
>>> + * SYMCLK: Symbol Clock
>>> + * SOCCLK: GPU Engine Clock
>>> + * DISPCLK: Display Clock
>>> + * DPPCLK: DPP Clock
>>> + * DCFCLK: Display Controller Fabric Clock
>>> + * REFCLK: Real Time Reference Clock
>>> + * PPLL: Pixel PLL
>>> + * FCLK: Fabric Clock
>>> + * MCLK: Memory Clock
>>> +
>>> + CRC
>>> + Cyclic Redundancy Check
>>> +
>>> + CRTC
>>> + Cathode Ray Tube Controller - commonly called "Controller" -
>>> Generates
>>> + raw stream of pixels, clocked at pixel clock
>>> +
>>> + CVT
>>> + Coordinated Video Timings
>>> +
>>> + DAL
>>> + Display Abstraction layer
>>> +
>>> + DC (Software)
>>> + Display Core
>>> +
>>> + DC (Hardware)
>>> + Display Controller
>>> +
>>> + DCC
>>> + Delta Colour Compression
>>> +
>>> + DCE
>>> + Display Controller Engine
>>> +
>>> + DCHUB
>>> + Display Controller HUB
>>> +
>>> + ARB
>>> + Arbiter
>>> +
>>> + VTG
>>> + Vertical Timing Generator
>>> +
>>> + DCN
>>> + Display Core Next
>>> +
>>> + DCCG
>>> + Display Clock Generator block
>>> +
>>> + DDC
>>> + Display Data Channel
>>> +
>>> + DIO
>>> + Display IO
>>> +
>>> + DPP
>>> + Display Pipes and Planes
>>> +
>>> + DSC
>>> + Display Stream Compression (Reduce the amount of bits to
>>> represent pixel
>>> + count while at the same pixel clock)
>>> +
>>> + dGPU
>>> + discrete GPU
>>> +
>>> + DMIF
>>> + Display Memory Interface
>>> +
>>> + DML
>>> + Display Mode Library
>>> +
>>> + DMCU
>>> + Display Micro-Controller Unit
>>> +
>>> + DMCUB
>>> + Display Micro-Controller Unit, version B
>>> +
>>> + DPCD
>>> + DisplayPort Configuration Data
>>> +
>>> + DPM(S)
>>> + Display Power Management (Signaling)
>>> +
>>> + DRR
>>> + Dynamic Refresh Rate
>>> +
>>> + DWB
>>> + Display Writeback
>>> +
>>> + FB
>>> + Frame Buffer
>>> +
>>> + FBC
>>> + Frame Buffer Compression
>>> +
>>> + FEC
>>> + Forward Error Correction
>>> +
>>> + FRL
>>> + Fixed Rate Link
>>> +
>>> + GCO
>>> + Graphical Controller Object
>>> +
>>> + GMC
>>> + Graphic Memory Controller
>>> +
>>> + GSL
>>> + Global Swap Lock
>>> +
>>> + iGPU
>>> + integrated GPU
>>> +
>>> + IH
>>> + Interrupt Handler
>>> +
>>> + ISR
>>> + Interrupt Service Request
>>> +
>>> + ISV
>>> + Independent Software Vendor
>>> +
>>> + KMD
>>> + Kernel Mode Driver
>>> +
>>> + LB
>>> + Line Buffer
>>> +
>>> + LFC
>>> + Low Framerate Compensation
>>> +
>>> + LTTPR
>>> + Link Training Tunable Phy Repeater
>>> +
>>> + LUT
>>> + Lookup Table
>>> +
>>> + MALL
>>> + Memory Access at Last Level
>>> +
>>> + MC
>>> + Memory Controller
>>> +
>>> + MPC
>>> + Multiple pipes and plane combine
>>> +
>>> + MPO
>>> + Multi Plane Overlay
>>> +
>>> + MST
>>> + Multi Stream Transport
>>> +
>>> + NBP State
>>> + Northbridge Power State
>>> +
>>> + NBIO
>>> + North Bridge Input/Output
>>> +
>>> + ODM
>>> + Output Data Mapping
>>> +
>>> + OPM
>>> + Output Protection Manager
>>> +
>>> + OPP
>>> + Output Plane Processor
>>> +
>>> + OPTC
>>> + Output Pipe Timing Combiner
>>> +
>>> + OTG
>>> + Output Timing Generator
>>> +
>>> + PCON
>>> + Power Controller
>>> +
>>> + PGFSM
>>> + Power Gate Finite State Machine
>>> +
>>> + PSR
>>> + Panel Self Refresh
>>> +
>>> + SCL
>>> + Scaler
>>> +
>>> + SDP
>>> + Scalable Data Port
>>> +
>>> + SLS
>>> + Single Large Surface
>>> +
>>> + SST
>>> + Single Stream Transport
>>> +
>>> + TMDS
>>> + Transition-Minimized Differential Signaling
>>> +
>>> + TMZ
>>> + Trusted Memory Zone
>>> +
>>> + TTU
>>> + Time to Underflow
>>> +
>>> + VRR
>>> + Variable Refresh Rate
>>> +
>>> + UVD
>>> + Unified Video Decoder
>>> diff --git a/Documentation/gpu/amdgpu/display/index.rst
>>> b/Documentation/gpu/amdgpu/display/index.rst
>>> index fe2ecad8df81..e23c752ee5f5 100644
>>> --- a/Documentation/gpu/amdgpu/display/index.rst
>>> +++ b/Documentation/gpu/amdgpu/display/index.rst
>>> @@ -26,3 +26,4 @@ table of content:
>>> display-manager.rst
>>> dc-debug.rst
>>> dcn-overview.rst
>>> + dc-glossary.rst
>>> diff --git a/Documentation/gpu/amdgpu/index.rst
>>> b/Documentation/gpu/amdgpu/index.rst
>>> index 5c8cbf514097..ff38c360b04e 100644
>>> --- a/Documentation/gpu/amdgpu/index.rst
>>> +++ b/Documentation/gpu/amdgpu/index.rst
>>> @@ -334,3 +334,10 @@ smartshift_bias
>>>
>>> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
>>> :doc: smartshift_bias
>>> +
>>> +AMDGPU Glossary
>>> +===============
>>> +
>>> +.. toctree::
>>> +
>>> + amdgpu-glossary.rst
>>> --
>>> 2.25.1
>>>
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> http://blog.ffwll.ch/>>>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
@ 2021-12-08 15:46 ` Rodrigo Siqueira Jordao
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira Jordao @ 2021-12-08 15:46 UTC (permalink / raw)
To: Yann Dirson, Rodrigo Siqueira
Cc: Mark Yacoub, bhawanpreet lakha, nicholas choi, linux-doc,
Michel Daenzer, roman li, amd-gfx, Nicholas Kazlauskas,
Marek Olsak, aurabindo pillai, Sean Paul, dri-devel,
Alex Deucher, qingqing zhuo, Christian Koenig, Roman Gilg
On 2021-12-07 2:49 p.m., Yann Dirson wrote:
>
>> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
>>> In the DC driver, we have multiple acronyms that are not obvious
>>> most of
>>> the time; the same idea is valid for amdgpu. This commit introduces
>>> a DC
>>> and amdgpu glossary in order to make it easier to navigate through
>>> our
>>> driver.
>>>
>>> Changes since V1:
>>> - Yann: Divide glossary based on driver context.
>>> - Alex: Make terms more consistent and update CPLIB
>>> - Add new acronyms to the glossary
>
> If you're rerolling, it could be a good time to include the additional
> (and detailed) entries from Alex's answer to "Looking for clarifications
> around gfx/kcq/kiq". Finding a way to fit the other details not
> fitting directly in the glossary will likely take more rounds, though,
> so we can wait for the first round to be merged before dealing with them.
Hi Yann,
I will send another version to address Daniel's comment, and I'll also
expand the amdgpu acronyms glossary based on your mail thread with Alex.
However, I don't want to add more details about that discussion in this
series because I don't want to lose focus in this patchset since my main
goal is to start to expand display documentation.
By the way, I think you could consider writing a kernel-doc based on
your discussion with Alex. This way, you can try to consolidate what you
discover and get reviews in the content.
Thanks
Siqueira
>
>
>>>
>>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>>> ---
>>> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
>>> .../gpu/amdgpu/display/dc-glossary.rst | 243
>>> ++++++++++++++++++
>>> Documentation/gpu/amdgpu/display/index.rst | 1 +
>>> Documentation/gpu/amdgpu/index.rst | 7 +
>>> 4 files changed, 298 insertions(+)
>>> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> create mode 100644
>>> Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>
>>> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> new file mode 100644
>>> index 000000000000..e635851025e7
>>> --- /dev/null
>>> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> @@ -0,0 +1,47 @@
>>> +===============
>>> +AMDGPU Glossary
>>> +===============
>>> +
>>> +Here you can find some generic acronyms used in the amdgpu driver.
>>> Notice that
>>> +we have a dedicated glossary for Display Core.
>>
>> Maybe add a link to that here so it's easier to find? sphinx
>> autogenerates
>> header targets so pretty easy (if the heading is unique at least).
>> -Daniel
>>
>>> +
>>> +.. glossary::
>>> +
>>> + CPLIB
>>> + Content Protection Library
>>> +
>>> + DFS
>>> + Digital Frequency Synthesizer
>>> +
>>> + ECP
>>> + Enhanced Content Protection
>>> +
>>> + EOP
>>> + End Of Pipe/Pipeline
>>> +
>>> + HQD
>>> + Hardware Queue Descriptor
>>> +
>>> + KCQ
>>> + Kernel Compute Queue
>>> +
>>> + KGQ
>>> + Kernel Graphics Queue
>>> +
>>> + KIQ
>>> + Kernel Interface Queue
>>> +
>>> + MQD
>>> + Memory Queue Descriptor
>>> +
>>> + PPLib
>>> + PowerPlay Library - PowerPlay is the power management
>>> component.
>>> +
>>> + SMU
>>> + System Management Unit
>>> +
>>> + VCE
>>> + Video Compression Engine
>>> +
>>> + VCN
>>> + Video Codec Next
>>> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>> b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>> new file mode 100644
>>> index 000000000000..547c0bfbb3e2
>>> --- /dev/null
>>> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>> @@ -0,0 +1,243 @@
>>> +===========
>>> +DC Glossary
>>> +===========
>>> +
>>> +On this page, we try to keep track of acronyms related to the
>>> display
>>> +component. If you do not find what you are looking for, look at
>>> the amdgpu
>>> +glossary; if you cannot find it anywhere, consider asking in the
>>> amdgfx and
>>> +update this page.
>>> +
>>> +.. glossary::
>>> +
>>> + ABM
>>> + Adaptive Backlight Modulation
>>> +
>>> + APU
>>> + Accelerated Processing Unit
>>> +
>>> + ASIC
>>> + Application-Specific Integrated Circuit
>>> +
>>> + ASSR
>>> + Alternate Scrambler Seed Reset
>>> +
>>> + AZ
>>> + Azalia (HD audio DMA engine)
>>> +
>>> + BPC
>>> + Bits Per Colour/Component
>>> +
>>> + BPP
>>> + Bits Per Pixel
>>> +
>>> + Clocks
>>> + * PCLK: Pixel Clock
>>> + * SYMCLK: Symbol Clock
>>> + * SOCCLK: GPU Engine Clock
>>> + * DISPCLK: Display Clock
>>> + * DPPCLK: DPP Clock
>>> + * DCFCLK: Display Controller Fabric Clock
>>> + * REFCLK: Real Time Reference Clock
>>> + * PPLL: Pixel PLL
>>> + * FCLK: Fabric Clock
>>> + * MCLK: Memory Clock
>>> +
>>> + CRC
>>> + Cyclic Redundancy Check
>>> +
>>> + CRTC
>>> + Cathode Ray Tube Controller - commonly called "Controller" -
>>> Generates
>>> + raw stream of pixels, clocked at pixel clock
>>> +
>>> + CVT
>>> + Coordinated Video Timings
>>> +
>>> + DAL
>>> + Display Abstraction layer
>>> +
>>> + DC (Software)
>>> + Display Core
>>> +
>>> + DC (Hardware)
>>> + Display Controller
>>> +
>>> + DCC
>>> + Delta Colour Compression
>>> +
>>> + DCE
>>> + Display Controller Engine
>>> +
>>> + DCHUB
>>> + Display Controller HUB
>>> +
>>> + ARB
>>> + Arbiter
>>> +
>>> + VTG
>>> + Vertical Timing Generator
>>> +
>>> + DCN
>>> + Display Core Next
>>> +
>>> + DCCG
>>> + Display Clock Generator block
>>> +
>>> + DDC
>>> + Display Data Channel
>>> +
>>> + DIO
>>> + Display IO
>>> +
>>> + DPP
>>> + Display Pipes and Planes
>>> +
>>> + DSC
>>> + Display Stream Compression (Reduce the amount of bits to
>>> represent pixel
>>> + count while at the same pixel clock)
>>> +
>>> + dGPU
>>> + discrete GPU
>>> +
>>> + DMIF
>>> + Display Memory Interface
>>> +
>>> + DML
>>> + Display Mode Library
>>> +
>>> + DMCU
>>> + Display Micro-Controller Unit
>>> +
>>> + DMCUB
>>> + Display Micro-Controller Unit, version B
>>> +
>>> + DPCD
>>> + DisplayPort Configuration Data
>>> +
>>> + DPM(S)
>>> + Display Power Management (Signaling)
>>> +
>>> + DRR
>>> + Dynamic Refresh Rate
>>> +
>>> + DWB
>>> + Display Writeback
>>> +
>>> + FB
>>> + Frame Buffer
>>> +
>>> + FBC
>>> + Frame Buffer Compression
>>> +
>>> + FEC
>>> + Forward Error Correction
>>> +
>>> + FRL
>>> + Fixed Rate Link
>>> +
>>> + GCO
>>> + Graphical Controller Object
>>> +
>>> + GMC
>>> + Graphic Memory Controller
>>> +
>>> + GSL
>>> + Global Swap Lock
>>> +
>>> + iGPU
>>> + integrated GPU
>>> +
>>> + IH
>>> + Interrupt Handler
>>> +
>>> + ISR
>>> + Interrupt Service Request
>>> +
>>> + ISV
>>> + Independent Software Vendor
>>> +
>>> + KMD
>>> + Kernel Mode Driver
>>> +
>>> + LB
>>> + Line Buffer
>>> +
>>> + LFC
>>> + Low Framerate Compensation
>>> +
>>> + LTTPR
>>> + Link Training Tunable Phy Repeater
>>> +
>>> + LUT
>>> + Lookup Table
>>> +
>>> + MALL
>>> + Memory Access at Last Level
>>> +
>>> + MC
>>> + Memory Controller
>>> +
>>> + MPC
>>> + Multiple pipes and plane combine
>>> +
>>> + MPO
>>> + Multi Plane Overlay
>>> +
>>> + MST
>>> + Multi Stream Transport
>>> +
>>> + NBP State
>>> + Northbridge Power State
>>> +
>>> + NBIO
>>> + North Bridge Input/Output
>>> +
>>> + ODM
>>> + Output Data Mapping
>>> +
>>> + OPM
>>> + Output Protection Manager
>>> +
>>> + OPP
>>> + Output Plane Processor
>>> +
>>> + OPTC
>>> + Output Pipe Timing Combiner
>>> +
>>> + OTG
>>> + Output Timing Generator
>>> +
>>> + PCON
>>> + Power Controller
>>> +
>>> + PGFSM
>>> + Power Gate Finite State Machine
>>> +
>>> + PSR
>>> + Panel Self Refresh
>>> +
>>> + SCL
>>> + Scaler
>>> +
>>> + SDP
>>> + Scalable Data Port
>>> +
>>> + SLS
>>> + Single Large Surface
>>> +
>>> + SST
>>> + Single Stream Transport
>>> +
>>> + TMDS
>>> + Transition-Minimized Differential Signaling
>>> +
>>> + TMZ
>>> + Trusted Memory Zone
>>> +
>>> + TTU
>>> + Time to Underflow
>>> +
>>> + VRR
>>> + Variable Refresh Rate
>>> +
>>> + UVD
>>> + Unified Video Decoder
>>> diff --git a/Documentation/gpu/amdgpu/display/index.rst
>>> b/Documentation/gpu/amdgpu/display/index.rst
>>> index fe2ecad8df81..e23c752ee5f5 100644
>>> --- a/Documentation/gpu/amdgpu/display/index.rst
>>> +++ b/Documentation/gpu/amdgpu/display/index.rst
>>> @@ -26,3 +26,4 @@ table of content:
>>> display-manager.rst
>>> dc-debug.rst
>>> dcn-overview.rst
>>> + dc-glossary.rst
>>> diff --git a/Documentation/gpu/amdgpu/index.rst
>>> b/Documentation/gpu/amdgpu/index.rst
>>> index 5c8cbf514097..ff38c360b04e 100644
>>> --- a/Documentation/gpu/amdgpu/index.rst
>>> +++ b/Documentation/gpu/amdgpu/index.rst
>>> @@ -334,3 +334,10 @@ smartshift_bias
>>>
>>> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
>>> :doc: smartshift_bias
>>> +
>>> +AMDGPU Glossary
>>> +===============
>>> +
>>> +.. toctree::
>>> +
>>> + amdgpu-glossary.rst
>>> --
>>> 2.25.1
>>>
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> http://blog.ffwll.ch/>>>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
@ 2021-12-08 15:46 ` Rodrigo Siqueira Jordao
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira Jordao @ 2021-12-08 15:46 UTC (permalink / raw)
To: Yann Dirson, Rodrigo Siqueira
Cc: Mark Yacoub, bhawanpreet lakha, nicholas choi, linux-doc,
Simon Ser, Michel Daenzer, roman li, amd-gfx,
Nicholas Kazlauskas, Marek Olsak, Pekka Paalanen,
aurabindo pillai, Sean Paul, dri-devel, Daniel Vetter,
Bas Nieuwenhuizen, Alex Deucher, qingqing zhuo, Christian Koenig,
Harry Wentland, Roman Gilg
On 2021-12-07 2:49 p.m., Yann Dirson wrote:
>
>> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
>>> In the DC driver, we have multiple acronyms that are not obvious
>>> most of
>>> the time; the same idea is valid for amdgpu. This commit introduces
>>> a DC
>>> and amdgpu glossary in order to make it easier to navigate through
>>> our
>>> driver.
>>>
>>> Changes since V1:
>>> - Yann: Divide glossary based on driver context.
>>> - Alex: Make terms more consistent and update CPLIB
>>> - Add new acronyms to the glossary
>
> If you're rerolling, it could be a good time to include the additional
> (and detailed) entries from Alex's answer to "Looking for clarifications
> around gfx/kcq/kiq". Finding a way to fit the other details not
> fitting directly in the glossary will likely take more rounds, though,
> so we can wait for the first round to be merged before dealing with them.
Hi Yann,
I will send another version to address Daniel's comment, and I'll also
expand the amdgpu acronyms glossary based on your mail thread with Alex.
However, I don't want to add more details about that discussion in this
series because I don't want to lose focus in this patchset since my main
goal is to start to expand display documentation.
By the way, I think you could consider writing a kernel-doc based on
your discussion with Alex. This way, you can try to consolidate what you
discover and get reviews in the content.
Thanks
Siqueira
>
>
>>>
>>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>>> ---
>>> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
>>> .../gpu/amdgpu/display/dc-glossary.rst | 243
>>> ++++++++++++++++++
>>> Documentation/gpu/amdgpu/display/index.rst | 1 +
>>> Documentation/gpu/amdgpu/index.rst | 7 +
>>> 4 files changed, 298 insertions(+)
>>> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> create mode 100644
>>> Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>
>>> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> new file mode 100644
>>> index 000000000000..e635851025e7
>>> --- /dev/null
>>> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> @@ -0,0 +1,47 @@
>>> +===============
>>> +AMDGPU Glossary
>>> +===============
>>> +
>>> +Here you can find some generic acronyms used in the amdgpu driver.
>>> Notice that
>>> +we have a dedicated glossary for Display Core.
>>
>> Maybe add a link to that here so it's easier to find? sphinx
>> autogenerates
>> header targets so pretty easy (if the heading is unique at least).
>> -Daniel
>>
>>> +
>>> +.. glossary::
>>> +
>>> + CPLIB
>>> + Content Protection Library
>>> +
>>> + DFS
>>> + Digital Frequency Synthesizer
>>> +
>>> + ECP
>>> + Enhanced Content Protection
>>> +
>>> + EOP
>>> + End Of Pipe/Pipeline
>>> +
>>> + HQD
>>> + Hardware Queue Descriptor
>>> +
>>> + KCQ
>>> + Kernel Compute Queue
>>> +
>>> + KGQ
>>> + Kernel Graphics Queue
>>> +
>>> + KIQ
>>> + Kernel Interface Queue
>>> +
>>> + MQD
>>> + Memory Queue Descriptor
>>> +
>>> + PPLib
>>> + PowerPlay Library - PowerPlay is the power management
>>> component.
>>> +
>>> + SMU
>>> + System Management Unit
>>> +
>>> + VCE
>>> + Video Compression Engine
>>> +
>>> + VCN
>>> + Video Codec Next
>>> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>> b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>> new file mode 100644
>>> index 000000000000..547c0bfbb3e2
>>> --- /dev/null
>>> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>> @@ -0,0 +1,243 @@
>>> +===========
>>> +DC Glossary
>>> +===========
>>> +
>>> +On this page, we try to keep track of acronyms related to the
>>> display
>>> +component. If you do not find what you are looking for, look at
>>> the amdgpu
>>> +glossary; if you cannot find it anywhere, consider asking in the
>>> amdgfx and
>>> +update this page.
>>> +
>>> +.. glossary::
>>> +
>>> + ABM
>>> + Adaptive Backlight Modulation
>>> +
>>> + APU
>>> + Accelerated Processing Unit
>>> +
>>> + ASIC
>>> + Application-Specific Integrated Circuit
>>> +
>>> + ASSR
>>> + Alternate Scrambler Seed Reset
>>> +
>>> + AZ
>>> + Azalia (HD audio DMA engine)
>>> +
>>> + BPC
>>> + Bits Per Colour/Component
>>> +
>>> + BPP
>>> + Bits Per Pixel
>>> +
>>> + Clocks
>>> + * PCLK: Pixel Clock
>>> + * SYMCLK: Symbol Clock
>>> + * SOCCLK: GPU Engine Clock
>>> + * DISPCLK: Display Clock
>>> + * DPPCLK: DPP Clock
>>> + * DCFCLK: Display Controller Fabric Clock
>>> + * REFCLK: Real Time Reference Clock
>>> + * PPLL: Pixel PLL
>>> + * FCLK: Fabric Clock
>>> + * MCLK: Memory Clock
>>> +
>>> + CRC
>>> + Cyclic Redundancy Check
>>> +
>>> + CRTC
>>> + Cathode Ray Tube Controller - commonly called "Controller" -
>>> Generates
>>> + raw stream of pixels, clocked at pixel clock
>>> +
>>> + CVT
>>> + Coordinated Video Timings
>>> +
>>> + DAL
>>> + Display Abstraction layer
>>> +
>>> + DC (Software)
>>> + Display Core
>>> +
>>> + DC (Hardware)
>>> + Display Controller
>>> +
>>> + DCC
>>> + Delta Colour Compression
>>> +
>>> + DCE
>>> + Display Controller Engine
>>> +
>>> + DCHUB
>>> + Display Controller HUB
>>> +
>>> + ARB
>>> + Arbiter
>>> +
>>> + VTG
>>> + Vertical Timing Generator
>>> +
>>> + DCN
>>> + Display Core Next
>>> +
>>> + DCCG
>>> + Display Clock Generator block
>>> +
>>> + DDC
>>> + Display Data Channel
>>> +
>>> + DIO
>>> + Display IO
>>> +
>>> + DPP
>>> + Display Pipes and Planes
>>> +
>>> + DSC
>>> + Display Stream Compression (Reduce the amount of bits to
>>> represent pixel
>>> + count while at the same pixel clock)
>>> +
>>> + dGPU
>>> + discrete GPU
>>> +
>>> + DMIF
>>> + Display Memory Interface
>>> +
>>> + DML
>>> + Display Mode Library
>>> +
>>> + DMCU
>>> + Display Micro-Controller Unit
>>> +
>>> + DMCUB
>>> + Display Micro-Controller Unit, version B
>>> +
>>> + DPCD
>>> + DisplayPort Configuration Data
>>> +
>>> + DPM(S)
>>> + Display Power Management (Signaling)
>>> +
>>> + DRR
>>> + Dynamic Refresh Rate
>>> +
>>> + DWB
>>> + Display Writeback
>>> +
>>> + FB
>>> + Frame Buffer
>>> +
>>> + FBC
>>> + Frame Buffer Compression
>>> +
>>> + FEC
>>> + Forward Error Correction
>>> +
>>> + FRL
>>> + Fixed Rate Link
>>> +
>>> + GCO
>>> + Graphical Controller Object
>>> +
>>> + GMC
>>> + Graphic Memory Controller
>>> +
>>> + GSL
>>> + Global Swap Lock
>>> +
>>> + iGPU
>>> + integrated GPU
>>> +
>>> + IH
>>> + Interrupt Handler
>>> +
>>> + ISR
>>> + Interrupt Service Request
>>> +
>>> + ISV
>>> + Independent Software Vendor
>>> +
>>> + KMD
>>> + Kernel Mode Driver
>>> +
>>> + LB
>>> + Line Buffer
>>> +
>>> + LFC
>>> + Low Framerate Compensation
>>> +
>>> + LTTPR
>>> + Link Training Tunable Phy Repeater
>>> +
>>> + LUT
>>> + Lookup Table
>>> +
>>> + MALL
>>> + Memory Access at Last Level
>>> +
>>> + MC
>>> + Memory Controller
>>> +
>>> + MPC
>>> + Multiple pipes and plane combine
>>> +
>>> + MPO
>>> + Multi Plane Overlay
>>> +
>>> + MST
>>> + Multi Stream Transport
>>> +
>>> + NBP State
>>> + Northbridge Power State
>>> +
>>> + NBIO
>>> + North Bridge Input/Output
>>> +
>>> + ODM
>>> + Output Data Mapping
>>> +
>>> + OPM
>>> + Output Protection Manager
>>> +
>>> + OPP
>>> + Output Plane Processor
>>> +
>>> + OPTC
>>> + Output Pipe Timing Combiner
>>> +
>>> + OTG
>>> + Output Timing Generator
>>> +
>>> + PCON
>>> + Power Controller
>>> +
>>> + PGFSM
>>> + Power Gate Finite State Machine
>>> +
>>> + PSR
>>> + Panel Self Refresh
>>> +
>>> + SCL
>>> + Scaler
>>> +
>>> + SDP
>>> + Scalable Data Port
>>> +
>>> + SLS
>>> + Single Large Surface
>>> +
>>> + SST
>>> + Single Stream Transport
>>> +
>>> + TMDS
>>> + Transition-Minimized Differential Signaling
>>> +
>>> + TMZ
>>> + Trusted Memory Zone
>>> +
>>> + TTU
>>> + Time to Underflow
>>> +
>>> + VRR
>>> + Variable Refresh Rate
>>> +
>>> + UVD
>>> + Unified Video Decoder
>>> diff --git a/Documentation/gpu/amdgpu/display/index.rst
>>> b/Documentation/gpu/amdgpu/display/index.rst
>>> index fe2ecad8df81..e23c752ee5f5 100644
>>> --- a/Documentation/gpu/amdgpu/display/index.rst
>>> +++ b/Documentation/gpu/amdgpu/display/index.rst
>>> @@ -26,3 +26,4 @@ table of content:
>>> display-manager.rst
>>> dc-debug.rst
>>> dcn-overview.rst
>>> + dc-glossary.rst
>>> diff --git a/Documentation/gpu/amdgpu/index.rst
>>> b/Documentation/gpu/amdgpu/index.rst
>>> index 5c8cbf514097..ff38c360b04e 100644
>>> --- a/Documentation/gpu/amdgpu/index.rst
>>> +++ b/Documentation/gpu/amdgpu/index.rst
>>> @@ -334,3 +334,10 @@ smartshift_bias
>>>
>>> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
>>> :doc: smartshift_bias
>>> +
>>> +AMDGPU Glossary
>>> +===============
>>> +
>>> +.. toctree::
>>> +
>>> + amdgpu-glossary.rst
>>> --
>>> 2.25.1
>>>
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> http://blog.ffwll.ch/>>>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
2021-12-08 15:46 ` Rodrigo Siqueira Jordao
(?)
@ 2021-12-08 16:16 ` Yann Dirson
-1 siblings, 0 replies; 31+ messages in thread
From: Yann Dirson @ 2021-12-08 16:16 UTC (permalink / raw)
To: Rodrigo Siqueira Jordao
Cc: Mark Yacoub, bhawanpreet lakha, nicholas choi, linux-doc,
Simon Ser, Michel Daenzer, roman li, amd-gfx,
Nicholas Kazlauskas, Marek Olsak, Pekka Paalanen,
aurabindo pillai, Sean Paul, dri-devel, Daniel Vetter,
Bas Nieuwenhuizen, Alex Deucher, qingqing zhuo, Christian Koenig,
Harry Wentland, Roman Gilg, Rodrigo Siqueira
Hi Rodrigo,
> On 2021-12-07 2:49 p.m., Yann Dirson wrote:
> >
> >> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
> >>> In the DC driver, we have multiple acronyms that are not obvious
> >>> most of
> >>> the time; the same idea is valid for amdgpu. This commit
> >>> introduces
> >>> a DC
> >>> and amdgpu glossary in order to make it easier to navigate
> >>> through
> >>> our
> >>> driver.
> >>>
> >>> Changes since V1:
> >>> - Yann: Divide glossary based on driver context.
> >>> - Alex: Make terms more consistent and update CPLIB
> >>> - Add new acronyms to the glossary
> >
> > If you're rerolling, it could be a good time to include the
> > additional
> > (and detailed) entries from Alex's answer to "Looking for
> > clarifications
> > around gfx/kcq/kiq". Finding a way to fit the other details not
> > fitting directly in the glossary will likely take more rounds,
> > though,
> > so we can wait for the first round to be merged before dealing with
> > them.
>
> Hi Yann,
>
> I will send another version to address Daniel's comment, and I'll
> also
> expand the amdgpu acronyms glossary based on your mail thread with
> Alex.
> However, I don't want to add more details about that discussion in
> this
> series because I don't want to lose focus in this patchset since my
> main
> goal is to start to expand display documentation.
fair enough
> By the way, I think you could consider writing a kernel-doc based on
> your discussion with Alex. This way, you can try to consolidate what
> you
> discover and get reviews in the content.
that's the idea, though I'm not sure I have enough material to start with
yet :)
>
> Thanks
> Siqueira
>
> >
> >
> >>>
> >>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> >>> ---
> >>> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
> >>> .../gpu/amdgpu/display/dc-glossary.rst | 243
> >>> ++++++++++++++++++
> >>> Documentation/gpu/amdgpu/display/index.rst | 1 +
> >>> Documentation/gpu/amdgpu/index.rst | 7 +
> >>> 4 files changed, 298 insertions(+)
> >>> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> create mode 100644
> >>> Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>>
> >>> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> new file mode 100644
> >>> index 000000000000..e635851025e7
> >>> --- /dev/null
> >>> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> @@ -0,0 +1,47 @@
> >>> +===============
> >>> +AMDGPU Glossary
> >>> +===============
> >>> +
> >>> +Here you can find some generic acronyms used in the amdgpu
> >>> driver.
> >>> Notice that
> >>> +we have a dedicated glossary for Display Core.
> >>
> >> Maybe add a link to that here so it's easier to find? sphinx
> >> autogenerates
> >> header targets so pretty easy (if the heading is unique at least).
> >> -Daniel
> >>
> >>> +
> >>> +.. glossary::
> >>> +
> >>> + CPLIB
> >>> + Content Protection Library
> >>> +
> >>> + DFS
> >>> + Digital Frequency Synthesizer
> >>> +
> >>> + ECP
> >>> + Enhanced Content Protection
> >>> +
> >>> + EOP
> >>> + End Of Pipe/Pipeline
> >>> +
> >>> + HQD
> >>> + Hardware Queue Descriptor
> >>> +
> >>> + KCQ
> >>> + Kernel Compute Queue
> >>> +
> >>> + KGQ
> >>> + Kernel Graphics Queue
> >>> +
> >>> + KIQ
> >>> + Kernel Interface Queue
> >>> +
> >>> + MQD
> >>> + Memory Queue Descriptor
> >>> +
> >>> + PPLib
> >>> + PowerPlay Library - PowerPlay is the power management
> >>> component.
> >>> +
> >>> + SMU
> >>> + System Management Unit
> >>> +
> >>> + VCE
> >>> + Video Compression Engine
> >>> +
> >>> + VCN
> >>> + Video Codec Next
> >>> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>> b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>> new file mode 100644
> >>> index 000000000000..547c0bfbb3e2
> >>> --- /dev/null
> >>> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>> @@ -0,0 +1,243 @@
> >>> +===========
> >>> +DC Glossary
> >>> +===========
> >>> +
> >>> +On this page, we try to keep track of acronyms related to the
> >>> display
> >>> +component. If you do not find what you are looking for, look at
> >>> the amdgpu
> >>> +glossary; if you cannot find it anywhere, consider asking in the
> >>> amdgfx and
> >>> +update this page.
> >>> +
> >>> +.. glossary::
> >>> +
> >>> + ABM
> >>> + Adaptive Backlight Modulation
> >>> +
> >>> + APU
> >>> + Accelerated Processing Unit
> >>> +
> >>> + ASIC
> >>> + Application-Specific Integrated Circuit
> >>> +
> >>> + ASSR
> >>> + Alternate Scrambler Seed Reset
> >>> +
> >>> + AZ
> >>> + Azalia (HD audio DMA engine)
> >>> +
> >>> + BPC
> >>> + Bits Per Colour/Component
> >>> +
> >>> + BPP
> >>> + Bits Per Pixel
> >>> +
> >>> + Clocks
> >>> + * PCLK: Pixel Clock
> >>> + * SYMCLK: Symbol Clock
> >>> + * SOCCLK: GPU Engine Clock
> >>> + * DISPCLK: Display Clock
> >>> + * DPPCLK: DPP Clock
> >>> + * DCFCLK: Display Controller Fabric Clock
> >>> + * REFCLK: Real Time Reference Clock
> >>> + * PPLL: Pixel PLL
> >>> + * FCLK: Fabric Clock
> >>> + * MCLK: Memory Clock
> >>> +
> >>> + CRC
> >>> + Cyclic Redundancy Check
> >>> +
> >>> + CRTC
> >>> + Cathode Ray Tube Controller - commonly called "Controller"
> >>> -
> >>> Generates
> >>> + raw stream of pixels, clocked at pixel clock
> >>> +
> >>> + CVT
> >>> + Coordinated Video Timings
> >>> +
> >>> + DAL
> >>> + Display Abstraction layer
> >>> +
> >>> + DC (Software)
> >>> + Display Core
> >>> +
> >>> + DC (Hardware)
> >>> + Display Controller
> >>> +
> >>> + DCC
> >>> + Delta Colour Compression
> >>> +
> >>> + DCE
> >>> + Display Controller Engine
> >>> +
> >>> + DCHUB
> >>> + Display Controller HUB
> >>> +
> >>> + ARB
> >>> + Arbiter
> >>> +
> >>> + VTG
> >>> + Vertical Timing Generator
> >>> +
> >>> + DCN
> >>> + Display Core Next
> >>> +
> >>> + DCCG
> >>> + Display Clock Generator block
> >>> +
> >>> + DDC
> >>> + Display Data Channel
> >>> +
> >>> + DIO
> >>> + Display IO
> >>> +
> >>> + DPP
> >>> + Display Pipes and Planes
> >>> +
> >>> + DSC
> >>> + Display Stream Compression (Reduce the amount of bits to
> >>> represent pixel
> >>> + count while at the same pixel clock)
> >>> +
> >>> + dGPU
> >>> + discrete GPU
> >>> +
> >>> + DMIF
> >>> + Display Memory Interface
> >>> +
> >>> + DML
> >>> + Display Mode Library
> >>> +
> >>> + DMCU
> >>> + Display Micro-Controller Unit
> >>> +
> >>> + DMCUB
> >>> + Display Micro-Controller Unit, version B
> >>> +
> >>> + DPCD
> >>> + DisplayPort Configuration Data
> >>> +
> >>> + DPM(S)
> >>> + Display Power Management (Signaling)
> >>> +
> >>> + DRR
> >>> + Dynamic Refresh Rate
> >>> +
> >>> + DWB
> >>> + Display Writeback
> >>> +
> >>> + FB
> >>> + Frame Buffer
> >>> +
> >>> + FBC
> >>> + Frame Buffer Compression
> >>> +
> >>> + FEC
> >>> + Forward Error Correction
> >>> +
> >>> + FRL
> >>> + Fixed Rate Link
> >>> +
> >>> + GCO
> >>> + Graphical Controller Object
> >>> +
> >>> + GMC
> >>> + Graphic Memory Controller
> >>> +
> >>> + GSL
> >>> + Global Swap Lock
> >>> +
> >>> + iGPU
> >>> + integrated GPU
> >>> +
> >>> + IH
> >>> + Interrupt Handler
> >>> +
> >>> + ISR
> >>> + Interrupt Service Request
> >>> +
> >>> + ISV
> >>> + Independent Software Vendor
> >>> +
> >>> + KMD
> >>> + Kernel Mode Driver
> >>> +
> >>> + LB
> >>> + Line Buffer
> >>> +
> >>> + LFC
> >>> + Low Framerate Compensation
> >>> +
> >>> + LTTPR
> >>> + Link Training Tunable Phy Repeater
> >>> +
> >>> + LUT
> >>> + Lookup Table
> >>> +
> >>> + MALL
> >>> + Memory Access at Last Level
> >>> +
> >>> + MC
> >>> + Memory Controller
> >>> +
> >>> + MPC
> >>> + Multiple pipes and plane combine
> >>> +
> >>> + MPO
> >>> + Multi Plane Overlay
> >>> +
> >>> + MST
> >>> + Multi Stream Transport
> >>> +
> >>> + NBP State
> >>> + Northbridge Power State
> >>> +
> >>> + NBIO
> >>> + North Bridge Input/Output
> >>> +
> >>> + ODM
> >>> + Output Data Mapping
> >>> +
> >>> + OPM
> >>> + Output Protection Manager
> >>> +
> >>> + OPP
> >>> + Output Plane Processor
> >>> +
> >>> + OPTC
> >>> + Output Pipe Timing Combiner
> >>> +
> >>> + OTG
> >>> + Output Timing Generator
> >>> +
> >>> + PCON
> >>> + Power Controller
> >>> +
> >>> + PGFSM
> >>> + Power Gate Finite State Machine
> >>> +
> >>> + PSR
> >>> + Panel Self Refresh
> >>> +
> >>> + SCL
> >>> + Scaler
> >>> +
> >>> + SDP
> >>> + Scalable Data Port
> >>> +
> >>> + SLS
> >>> + Single Large Surface
> >>> +
> >>> + SST
> >>> + Single Stream Transport
> >>> +
> >>> + TMDS
> >>> + Transition-Minimized Differential Signaling
> >>> +
> >>> + TMZ
> >>> + Trusted Memory Zone
> >>> +
> >>> + TTU
> >>> + Time to Underflow
> >>> +
> >>> + VRR
> >>> + Variable Refresh Rate
> >>> +
> >>> + UVD
> >>> + Unified Video Decoder
> >>> diff --git a/Documentation/gpu/amdgpu/display/index.rst
> >>> b/Documentation/gpu/amdgpu/display/index.rst
> >>> index fe2ecad8df81..e23c752ee5f5 100644
> >>> --- a/Documentation/gpu/amdgpu/display/index.rst
> >>> +++ b/Documentation/gpu/amdgpu/display/index.rst
> >>> @@ -26,3 +26,4 @@ table of content:
> >>> display-manager.rst
> >>> dc-debug.rst
> >>> dcn-overview.rst
> >>> + dc-glossary.rst
> >>> diff --git a/Documentation/gpu/amdgpu/index.rst
> >>> b/Documentation/gpu/amdgpu/index.rst
> >>> index 5c8cbf514097..ff38c360b04e 100644
> >>> --- a/Documentation/gpu/amdgpu/index.rst
> >>> +++ b/Documentation/gpu/amdgpu/index.rst
> >>> @@ -334,3 +334,10 @@ smartshift_bias
> >>>
> >>> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> >>> :doc: smartshift_bias
> >>> +
> >>> +AMDGPU Glossary
> >>> +===============
> >>> +
> >>> +.. toctree::
> >>> +
> >>> + amdgpu-glossary.rst
> >>> --
> >>> 2.25.1
> >>>
> >>
> >> --
> >> Daniel Vetter
> >> Software Engineer, Intel Corporation
> >> http://blog.ffwll.ch/>>>
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
@ 2021-12-08 16:16 ` Yann Dirson
0 siblings, 0 replies; 31+ messages in thread
From: Yann Dirson @ 2021-12-08 16:16 UTC (permalink / raw)
To: Rodrigo Siqueira Jordao
Cc: linux-doc, dri-devel, Rodrigo Siqueira, amd-gfx,
aurabindo pillai, Marek Olsak, Michel Daenzer, Sean Paul,
bhawanpreet lakha, Mark Yacoub, qingqing zhuo, roman li,
Roman Gilg, nicholas choi, Alex Deucher, Nicholas Kazlauskas,
Christian Koenig
Hi Rodrigo,
> On 2021-12-07 2:49 p.m., Yann Dirson wrote:
> >
> >> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
> >>> In the DC driver, we have multiple acronyms that are not obvious
> >>> most of
> >>> the time; the same idea is valid for amdgpu. This commit
> >>> introduces
> >>> a DC
> >>> and amdgpu glossary in order to make it easier to navigate
> >>> through
> >>> our
> >>> driver.
> >>>
> >>> Changes since V1:
> >>> - Yann: Divide glossary based on driver context.
> >>> - Alex: Make terms more consistent and update CPLIB
> >>> - Add new acronyms to the glossary
> >
> > If you're rerolling, it could be a good time to include the
> > additional
> > (and detailed) entries from Alex's answer to "Looking for
> > clarifications
> > around gfx/kcq/kiq". Finding a way to fit the other details not
> > fitting directly in the glossary will likely take more rounds,
> > though,
> > so we can wait for the first round to be merged before dealing with
> > them.
>
> Hi Yann,
>
> I will send another version to address Daniel's comment, and I'll
> also
> expand the amdgpu acronyms glossary based on your mail thread with
> Alex.
> However, I don't want to add more details about that discussion in
> this
> series because I don't want to lose focus in this patchset since my
> main
> goal is to start to expand display documentation.
fair enough
> By the way, I think you could consider writing a kernel-doc based on
> your discussion with Alex. This way, you can try to consolidate what
> you
> discover and get reviews in the content.
that's the idea, though I'm not sure I have enough material to start with
yet :)
>
> Thanks
> Siqueira
>
> >
> >
> >>>
> >>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> >>> ---
> >>> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
> >>> .../gpu/amdgpu/display/dc-glossary.rst | 243
> >>> ++++++++++++++++++
> >>> Documentation/gpu/amdgpu/display/index.rst | 1 +
> >>> Documentation/gpu/amdgpu/index.rst | 7 +
> >>> 4 files changed, 298 insertions(+)
> >>> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> create mode 100644
> >>> Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>>
> >>> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> new file mode 100644
> >>> index 000000000000..e635851025e7
> >>> --- /dev/null
> >>> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> @@ -0,0 +1,47 @@
> >>> +===============
> >>> +AMDGPU Glossary
> >>> +===============
> >>> +
> >>> +Here you can find some generic acronyms used in the amdgpu
> >>> driver.
> >>> Notice that
> >>> +we have a dedicated glossary for Display Core.
> >>
> >> Maybe add a link to that here so it's easier to find? sphinx
> >> autogenerates
> >> header targets so pretty easy (if the heading is unique at least).
> >> -Daniel
> >>
> >>> +
> >>> +.. glossary::
> >>> +
> >>> + CPLIB
> >>> + Content Protection Library
> >>> +
> >>> + DFS
> >>> + Digital Frequency Synthesizer
> >>> +
> >>> + ECP
> >>> + Enhanced Content Protection
> >>> +
> >>> + EOP
> >>> + End Of Pipe/Pipeline
> >>> +
> >>> + HQD
> >>> + Hardware Queue Descriptor
> >>> +
> >>> + KCQ
> >>> + Kernel Compute Queue
> >>> +
> >>> + KGQ
> >>> + Kernel Graphics Queue
> >>> +
> >>> + KIQ
> >>> + Kernel Interface Queue
> >>> +
> >>> + MQD
> >>> + Memory Queue Descriptor
> >>> +
> >>> + PPLib
> >>> + PowerPlay Library - PowerPlay is the power management
> >>> component.
> >>> +
> >>> + SMU
> >>> + System Management Unit
> >>> +
> >>> + VCE
> >>> + Video Compression Engine
> >>> +
> >>> + VCN
> >>> + Video Codec Next
> >>> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>> b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>> new file mode 100644
> >>> index 000000000000..547c0bfbb3e2
> >>> --- /dev/null
> >>> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>> @@ -0,0 +1,243 @@
> >>> +===========
> >>> +DC Glossary
> >>> +===========
> >>> +
> >>> +On this page, we try to keep track of acronyms related to the
> >>> display
> >>> +component. If you do not find what you are looking for, look at
> >>> the amdgpu
> >>> +glossary; if you cannot find it anywhere, consider asking in the
> >>> amdgfx and
> >>> +update this page.
> >>> +
> >>> +.. glossary::
> >>> +
> >>> + ABM
> >>> + Adaptive Backlight Modulation
> >>> +
> >>> + APU
> >>> + Accelerated Processing Unit
> >>> +
> >>> + ASIC
> >>> + Application-Specific Integrated Circuit
> >>> +
> >>> + ASSR
> >>> + Alternate Scrambler Seed Reset
> >>> +
> >>> + AZ
> >>> + Azalia (HD audio DMA engine)
> >>> +
> >>> + BPC
> >>> + Bits Per Colour/Component
> >>> +
> >>> + BPP
> >>> + Bits Per Pixel
> >>> +
> >>> + Clocks
> >>> + * PCLK: Pixel Clock
> >>> + * SYMCLK: Symbol Clock
> >>> + * SOCCLK: GPU Engine Clock
> >>> + * DISPCLK: Display Clock
> >>> + * DPPCLK: DPP Clock
> >>> + * DCFCLK: Display Controller Fabric Clock
> >>> + * REFCLK: Real Time Reference Clock
> >>> + * PPLL: Pixel PLL
> >>> + * FCLK: Fabric Clock
> >>> + * MCLK: Memory Clock
> >>> +
> >>> + CRC
> >>> + Cyclic Redundancy Check
> >>> +
> >>> + CRTC
> >>> + Cathode Ray Tube Controller - commonly called "Controller"
> >>> -
> >>> Generates
> >>> + raw stream of pixels, clocked at pixel clock
> >>> +
> >>> + CVT
> >>> + Coordinated Video Timings
> >>> +
> >>> + DAL
> >>> + Display Abstraction layer
> >>> +
> >>> + DC (Software)
> >>> + Display Core
> >>> +
> >>> + DC (Hardware)
> >>> + Display Controller
> >>> +
> >>> + DCC
> >>> + Delta Colour Compression
> >>> +
> >>> + DCE
> >>> + Display Controller Engine
> >>> +
> >>> + DCHUB
> >>> + Display Controller HUB
> >>> +
> >>> + ARB
> >>> + Arbiter
> >>> +
> >>> + VTG
> >>> + Vertical Timing Generator
> >>> +
> >>> + DCN
> >>> + Display Core Next
> >>> +
> >>> + DCCG
> >>> + Display Clock Generator block
> >>> +
> >>> + DDC
> >>> + Display Data Channel
> >>> +
> >>> + DIO
> >>> + Display IO
> >>> +
> >>> + DPP
> >>> + Display Pipes and Planes
> >>> +
> >>> + DSC
> >>> + Display Stream Compression (Reduce the amount of bits to
> >>> represent pixel
> >>> + count while at the same pixel clock)
> >>> +
> >>> + dGPU
> >>> + discrete GPU
> >>> +
> >>> + DMIF
> >>> + Display Memory Interface
> >>> +
> >>> + DML
> >>> + Display Mode Library
> >>> +
> >>> + DMCU
> >>> + Display Micro-Controller Unit
> >>> +
> >>> + DMCUB
> >>> + Display Micro-Controller Unit, version B
> >>> +
> >>> + DPCD
> >>> + DisplayPort Configuration Data
> >>> +
> >>> + DPM(S)
> >>> + Display Power Management (Signaling)
> >>> +
> >>> + DRR
> >>> + Dynamic Refresh Rate
> >>> +
> >>> + DWB
> >>> + Display Writeback
> >>> +
> >>> + FB
> >>> + Frame Buffer
> >>> +
> >>> + FBC
> >>> + Frame Buffer Compression
> >>> +
> >>> + FEC
> >>> + Forward Error Correction
> >>> +
> >>> + FRL
> >>> + Fixed Rate Link
> >>> +
> >>> + GCO
> >>> + Graphical Controller Object
> >>> +
> >>> + GMC
> >>> + Graphic Memory Controller
> >>> +
> >>> + GSL
> >>> + Global Swap Lock
> >>> +
> >>> + iGPU
> >>> + integrated GPU
> >>> +
> >>> + IH
> >>> + Interrupt Handler
> >>> +
> >>> + ISR
> >>> + Interrupt Service Request
> >>> +
> >>> + ISV
> >>> + Independent Software Vendor
> >>> +
> >>> + KMD
> >>> + Kernel Mode Driver
> >>> +
> >>> + LB
> >>> + Line Buffer
> >>> +
> >>> + LFC
> >>> + Low Framerate Compensation
> >>> +
> >>> + LTTPR
> >>> + Link Training Tunable Phy Repeater
> >>> +
> >>> + LUT
> >>> + Lookup Table
> >>> +
> >>> + MALL
> >>> + Memory Access at Last Level
> >>> +
> >>> + MC
> >>> + Memory Controller
> >>> +
> >>> + MPC
> >>> + Multiple pipes and plane combine
> >>> +
> >>> + MPO
> >>> + Multi Plane Overlay
> >>> +
> >>> + MST
> >>> + Multi Stream Transport
> >>> +
> >>> + NBP State
> >>> + Northbridge Power State
> >>> +
> >>> + NBIO
> >>> + North Bridge Input/Output
> >>> +
> >>> + ODM
> >>> + Output Data Mapping
> >>> +
> >>> + OPM
> >>> + Output Protection Manager
> >>> +
> >>> + OPP
> >>> + Output Plane Processor
> >>> +
> >>> + OPTC
> >>> + Output Pipe Timing Combiner
> >>> +
> >>> + OTG
> >>> + Output Timing Generator
> >>> +
> >>> + PCON
> >>> + Power Controller
> >>> +
> >>> + PGFSM
> >>> + Power Gate Finite State Machine
> >>> +
> >>> + PSR
> >>> + Panel Self Refresh
> >>> +
> >>> + SCL
> >>> + Scaler
> >>> +
> >>> + SDP
> >>> + Scalable Data Port
> >>> +
> >>> + SLS
> >>> + Single Large Surface
> >>> +
> >>> + SST
> >>> + Single Stream Transport
> >>> +
> >>> + TMDS
> >>> + Transition-Minimized Differential Signaling
> >>> +
> >>> + TMZ
> >>> + Trusted Memory Zone
> >>> +
> >>> + TTU
> >>> + Time to Underflow
> >>> +
> >>> + VRR
> >>> + Variable Refresh Rate
> >>> +
> >>> + UVD
> >>> + Unified Video Decoder
> >>> diff --git a/Documentation/gpu/amdgpu/display/index.rst
> >>> b/Documentation/gpu/amdgpu/display/index.rst
> >>> index fe2ecad8df81..e23c752ee5f5 100644
> >>> --- a/Documentation/gpu/amdgpu/display/index.rst
> >>> +++ b/Documentation/gpu/amdgpu/display/index.rst
> >>> @@ -26,3 +26,4 @@ table of content:
> >>> display-manager.rst
> >>> dc-debug.rst
> >>> dcn-overview.rst
> >>> + dc-glossary.rst
> >>> diff --git a/Documentation/gpu/amdgpu/index.rst
> >>> b/Documentation/gpu/amdgpu/index.rst
> >>> index 5c8cbf514097..ff38c360b04e 100644
> >>> --- a/Documentation/gpu/amdgpu/index.rst
> >>> +++ b/Documentation/gpu/amdgpu/index.rst
> >>> @@ -334,3 +334,10 @@ smartshift_bias
> >>>
> >>> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> >>> :doc: smartshift_bias
> >>> +
> >>> +AMDGPU Glossary
> >>> +===============
> >>> +
> >>> +.. toctree::
> >>> +
> >>> + amdgpu-glossary.rst
> >>> --
> >>> 2.25.1
> >>>
> >>
> >> --
> >> Daniel Vetter
> >> Software Engineer, Intel Corporation
> >> http://blog.ffwll.ch/>>>
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
@ 2021-12-08 16:16 ` Yann Dirson
0 siblings, 0 replies; 31+ messages in thread
From: Yann Dirson @ 2021-12-08 16:16 UTC (permalink / raw)
To: Rodrigo Siqueira Jordao
Cc: Simon Ser, linux-doc, dri-devel, Rodrigo Siqueira, amd-gfx,
aurabindo pillai, Harry Wentland, Marek Olsak, Michel Daenzer,
Pekka Paalanen, Sean Paul, bhawanpreet lakha, Mark Yacoub,
qingqing zhuo, roman li, Roman Gilg, nicholas choi,
Daniel Vetter, Bas Nieuwenhuizen, Alex Deucher,
Nicholas Kazlauskas, Christian Koenig
Hi Rodrigo,
> On 2021-12-07 2:49 p.m., Yann Dirson wrote:
> >
> >> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
> >>> In the DC driver, we have multiple acronyms that are not obvious
> >>> most of
> >>> the time; the same idea is valid for amdgpu. This commit
> >>> introduces
> >>> a DC
> >>> and amdgpu glossary in order to make it easier to navigate
> >>> through
> >>> our
> >>> driver.
> >>>
> >>> Changes since V1:
> >>> - Yann: Divide glossary based on driver context.
> >>> - Alex: Make terms more consistent and update CPLIB
> >>> - Add new acronyms to the glossary
> >
> > If you're rerolling, it could be a good time to include the
> > additional
> > (and detailed) entries from Alex's answer to "Looking for
> > clarifications
> > around gfx/kcq/kiq". Finding a way to fit the other details not
> > fitting directly in the glossary will likely take more rounds,
> > though,
> > so we can wait for the first round to be merged before dealing with
> > them.
>
> Hi Yann,
>
> I will send another version to address Daniel's comment, and I'll
> also
> expand the amdgpu acronyms glossary based on your mail thread with
> Alex.
> However, I don't want to add more details about that discussion in
> this
> series because I don't want to lose focus in this patchset since my
> main
> goal is to start to expand display documentation.
fair enough
> By the way, I think you could consider writing a kernel-doc based on
> your discussion with Alex. This way, you can try to consolidate what
> you
> discover and get reviews in the content.
that's the idea, though I'm not sure I have enough material to start with
yet :)
>
> Thanks
> Siqueira
>
> >
> >
> >>>
> >>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> >>> ---
> >>> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
> >>> .../gpu/amdgpu/display/dc-glossary.rst | 243
> >>> ++++++++++++++++++
> >>> Documentation/gpu/amdgpu/display/index.rst | 1 +
> >>> Documentation/gpu/amdgpu/index.rst | 7 +
> >>> 4 files changed, 298 insertions(+)
> >>> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> create mode 100644
> >>> Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>>
> >>> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> new file mode 100644
> >>> index 000000000000..e635851025e7
> >>> --- /dev/null
> >>> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> >>> @@ -0,0 +1,47 @@
> >>> +===============
> >>> +AMDGPU Glossary
> >>> +===============
> >>> +
> >>> +Here you can find some generic acronyms used in the amdgpu
> >>> driver.
> >>> Notice that
> >>> +we have a dedicated glossary for Display Core.
> >>
> >> Maybe add a link to that here so it's easier to find? sphinx
> >> autogenerates
> >> header targets so pretty easy (if the heading is unique at least).
> >> -Daniel
> >>
> >>> +
> >>> +.. glossary::
> >>> +
> >>> + CPLIB
> >>> + Content Protection Library
> >>> +
> >>> + DFS
> >>> + Digital Frequency Synthesizer
> >>> +
> >>> + ECP
> >>> + Enhanced Content Protection
> >>> +
> >>> + EOP
> >>> + End Of Pipe/Pipeline
> >>> +
> >>> + HQD
> >>> + Hardware Queue Descriptor
> >>> +
> >>> + KCQ
> >>> + Kernel Compute Queue
> >>> +
> >>> + KGQ
> >>> + Kernel Graphics Queue
> >>> +
> >>> + KIQ
> >>> + Kernel Interface Queue
> >>> +
> >>> + MQD
> >>> + Memory Queue Descriptor
> >>> +
> >>> + PPLib
> >>> + PowerPlay Library - PowerPlay is the power management
> >>> component.
> >>> +
> >>> + SMU
> >>> + System Management Unit
> >>> +
> >>> + VCE
> >>> + Video Compression Engine
> >>> +
> >>> + VCN
> >>> + Video Codec Next
> >>> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>> b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>> new file mode 100644
> >>> index 000000000000..547c0bfbb3e2
> >>> --- /dev/null
> >>> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
> >>> @@ -0,0 +1,243 @@
> >>> +===========
> >>> +DC Glossary
> >>> +===========
> >>> +
> >>> +On this page, we try to keep track of acronyms related to the
> >>> display
> >>> +component. If you do not find what you are looking for, look at
> >>> the amdgpu
> >>> +glossary; if you cannot find it anywhere, consider asking in the
> >>> amdgfx and
> >>> +update this page.
> >>> +
> >>> +.. glossary::
> >>> +
> >>> + ABM
> >>> + Adaptive Backlight Modulation
> >>> +
> >>> + APU
> >>> + Accelerated Processing Unit
> >>> +
> >>> + ASIC
> >>> + Application-Specific Integrated Circuit
> >>> +
> >>> + ASSR
> >>> + Alternate Scrambler Seed Reset
> >>> +
> >>> + AZ
> >>> + Azalia (HD audio DMA engine)
> >>> +
> >>> + BPC
> >>> + Bits Per Colour/Component
> >>> +
> >>> + BPP
> >>> + Bits Per Pixel
> >>> +
> >>> + Clocks
> >>> + * PCLK: Pixel Clock
> >>> + * SYMCLK: Symbol Clock
> >>> + * SOCCLK: GPU Engine Clock
> >>> + * DISPCLK: Display Clock
> >>> + * DPPCLK: DPP Clock
> >>> + * DCFCLK: Display Controller Fabric Clock
> >>> + * REFCLK: Real Time Reference Clock
> >>> + * PPLL: Pixel PLL
> >>> + * FCLK: Fabric Clock
> >>> + * MCLK: Memory Clock
> >>> +
> >>> + CRC
> >>> + Cyclic Redundancy Check
> >>> +
> >>> + CRTC
> >>> + Cathode Ray Tube Controller - commonly called "Controller"
> >>> -
> >>> Generates
> >>> + raw stream of pixels, clocked at pixel clock
> >>> +
> >>> + CVT
> >>> + Coordinated Video Timings
> >>> +
> >>> + DAL
> >>> + Display Abstraction layer
> >>> +
> >>> + DC (Software)
> >>> + Display Core
> >>> +
> >>> + DC (Hardware)
> >>> + Display Controller
> >>> +
> >>> + DCC
> >>> + Delta Colour Compression
> >>> +
> >>> + DCE
> >>> + Display Controller Engine
> >>> +
> >>> + DCHUB
> >>> + Display Controller HUB
> >>> +
> >>> + ARB
> >>> + Arbiter
> >>> +
> >>> + VTG
> >>> + Vertical Timing Generator
> >>> +
> >>> + DCN
> >>> + Display Core Next
> >>> +
> >>> + DCCG
> >>> + Display Clock Generator block
> >>> +
> >>> + DDC
> >>> + Display Data Channel
> >>> +
> >>> + DIO
> >>> + Display IO
> >>> +
> >>> + DPP
> >>> + Display Pipes and Planes
> >>> +
> >>> + DSC
> >>> + Display Stream Compression (Reduce the amount of bits to
> >>> represent pixel
> >>> + count while at the same pixel clock)
> >>> +
> >>> + dGPU
> >>> + discrete GPU
> >>> +
> >>> + DMIF
> >>> + Display Memory Interface
> >>> +
> >>> + DML
> >>> + Display Mode Library
> >>> +
> >>> + DMCU
> >>> + Display Micro-Controller Unit
> >>> +
> >>> + DMCUB
> >>> + Display Micro-Controller Unit, version B
> >>> +
> >>> + DPCD
> >>> + DisplayPort Configuration Data
> >>> +
> >>> + DPM(S)
> >>> + Display Power Management (Signaling)
> >>> +
> >>> + DRR
> >>> + Dynamic Refresh Rate
> >>> +
> >>> + DWB
> >>> + Display Writeback
> >>> +
> >>> + FB
> >>> + Frame Buffer
> >>> +
> >>> + FBC
> >>> + Frame Buffer Compression
> >>> +
> >>> + FEC
> >>> + Forward Error Correction
> >>> +
> >>> + FRL
> >>> + Fixed Rate Link
> >>> +
> >>> + GCO
> >>> + Graphical Controller Object
> >>> +
> >>> + GMC
> >>> + Graphic Memory Controller
> >>> +
> >>> + GSL
> >>> + Global Swap Lock
> >>> +
> >>> + iGPU
> >>> + integrated GPU
> >>> +
> >>> + IH
> >>> + Interrupt Handler
> >>> +
> >>> + ISR
> >>> + Interrupt Service Request
> >>> +
> >>> + ISV
> >>> + Independent Software Vendor
> >>> +
> >>> + KMD
> >>> + Kernel Mode Driver
> >>> +
> >>> + LB
> >>> + Line Buffer
> >>> +
> >>> + LFC
> >>> + Low Framerate Compensation
> >>> +
> >>> + LTTPR
> >>> + Link Training Tunable Phy Repeater
> >>> +
> >>> + LUT
> >>> + Lookup Table
> >>> +
> >>> + MALL
> >>> + Memory Access at Last Level
> >>> +
> >>> + MC
> >>> + Memory Controller
> >>> +
> >>> + MPC
> >>> + Multiple pipes and plane combine
> >>> +
> >>> + MPO
> >>> + Multi Plane Overlay
> >>> +
> >>> + MST
> >>> + Multi Stream Transport
> >>> +
> >>> + NBP State
> >>> + Northbridge Power State
> >>> +
> >>> + NBIO
> >>> + North Bridge Input/Output
> >>> +
> >>> + ODM
> >>> + Output Data Mapping
> >>> +
> >>> + OPM
> >>> + Output Protection Manager
> >>> +
> >>> + OPP
> >>> + Output Plane Processor
> >>> +
> >>> + OPTC
> >>> + Output Pipe Timing Combiner
> >>> +
> >>> + OTG
> >>> + Output Timing Generator
> >>> +
> >>> + PCON
> >>> + Power Controller
> >>> +
> >>> + PGFSM
> >>> + Power Gate Finite State Machine
> >>> +
> >>> + PSR
> >>> + Panel Self Refresh
> >>> +
> >>> + SCL
> >>> + Scaler
> >>> +
> >>> + SDP
> >>> + Scalable Data Port
> >>> +
> >>> + SLS
> >>> + Single Large Surface
> >>> +
> >>> + SST
> >>> + Single Stream Transport
> >>> +
> >>> + TMDS
> >>> + Transition-Minimized Differential Signaling
> >>> +
> >>> + TMZ
> >>> + Trusted Memory Zone
> >>> +
> >>> + TTU
> >>> + Time to Underflow
> >>> +
> >>> + VRR
> >>> + Variable Refresh Rate
> >>> +
> >>> + UVD
> >>> + Unified Video Decoder
> >>> diff --git a/Documentation/gpu/amdgpu/display/index.rst
> >>> b/Documentation/gpu/amdgpu/display/index.rst
> >>> index fe2ecad8df81..e23c752ee5f5 100644
> >>> --- a/Documentation/gpu/amdgpu/display/index.rst
> >>> +++ b/Documentation/gpu/amdgpu/display/index.rst
> >>> @@ -26,3 +26,4 @@ table of content:
> >>> display-manager.rst
> >>> dc-debug.rst
> >>> dcn-overview.rst
> >>> + dc-glossary.rst
> >>> diff --git a/Documentation/gpu/amdgpu/index.rst
> >>> b/Documentation/gpu/amdgpu/index.rst
> >>> index 5c8cbf514097..ff38c360b04e 100644
> >>> --- a/Documentation/gpu/amdgpu/index.rst
> >>> +++ b/Documentation/gpu/amdgpu/index.rst
> >>> @@ -334,3 +334,10 @@ smartshift_bias
> >>>
> >>> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> >>> :doc: smartshift_bias
> >>> +
> >>> +AMDGPU Glossary
> >>> +===============
> >>> +
> >>> +.. toctree::
> >>> +
> >>> + amdgpu-glossary.rst
> >>> --
> >>> 2.25.1
> >>>
> >>
> >> --
> >> Daniel Vetter
> >> Software Engineer, Intel Corporation
> >> http://blog.ffwll.ch/>>>
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
2021-12-08 16:16 ` Yann Dirson
(?)
@ 2021-12-08 16:29 ` Rodrigo Siqueira Jordao
-1 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira Jordao @ 2021-12-08 16:29 UTC (permalink / raw)
To: Yann Dirson
Cc: Mark Yacoub, bhawanpreet lakha, nicholas choi, linux-doc,
Simon Ser, Michel Daenzer, roman li, amd-gfx,
Nicholas Kazlauskas, Marek Olsak, Pekka Paalanen,
aurabindo pillai, Sean Paul, dri-devel, Daniel Vetter,
Bas Nieuwenhuizen, Alex Deucher, qingqing zhuo, Christian Koenig,
Harry Wentland, Roman Gilg, Rodrigo Siqueira
On 2021-12-08 11:16 a.m., Yann Dirson wrote:
> Hi Rodrigo,
>
>> On 2021-12-07 2:49 p.m., Yann Dirson wrote:
>>>
>>>> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
>>>>> In the DC driver, we have multiple acronyms that are not obvious
>>>>> most of
>>>>> the time; the same idea is valid for amdgpu. This commit
>>>>> introduces
>>>>> a DC
>>>>> and amdgpu glossary in order to make it easier to navigate
>>>>> through
>>>>> our
>>>>> driver.
>>>>>
>>>>> Changes since V1:
>>>>> - Yann: Divide glossary based on driver context.
>>>>> - Alex: Make terms more consistent and update CPLIB
>>>>> - Add new acronyms to the glossary
>>>
>>> If you're rerolling, it could be a good time to include the
>>> additional
>>> (and detailed) entries from Alex's answer to "Looking for
>>> clarifications
>>> around gfx/kcq/kiq". Finding a way to fit the other details not
>>> fitting directly in the glossary will likely take more rounds,
>>> though,
>>> so we can wait for the first round to be merged before dealing with
>>> them.
>>
>> Hi Yann,
>>
>> I will send another version to address Daniel's comment, and I'll
>> also
>> expand the amdgpu acronyms glossary based on your mail thread with
>> Alex.
>> However, I don't want to add more details about that discussion in
>> this
>> series because I don't want to lose focus in this patchset since my
>> main
>> goal is to start to expand display documentation.
>
> fair enough
>
>
>> By the way, I think you could consider writing a kernel-doc based on
>> your discussion with Alex. This way, you can try to consolidate what
>> you
>> discover and get reviews in the content.
>
> that's the idea, though I'm not sure I have enough material to start with
> yet :)
As you know, right now, we have zero documentation about that, which
means that if you add something, it is an excellent improvement in the
current status :)
>>
>> Thanks
>> Siqueira
>>
>>>
>>>
>>>>>
>>>>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>>>>> ---
>>>>> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
>>>>> .../gpu/amdgpu/display/dc-glossary.rst | 243
>>>>> ++++++++++++++++++
>>>>> Documentation/gpu/amdgpu/display/index.rst | 1 +
>>>>> Documentation/gpu/amdgpu/index.rst | 7 +
>>>>> 4 files changed, 298 insertions(+)
>>>>> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> create mode 100644
>>>>> Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>>
>>>>> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> new file mode 100644
>>>>> index 000000000000..e635851025e7
>>>>> --- /dev/null
>>>>> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> @@ -0,0 +1,47 @@
>>>>> +===============
>>>>> +AMDGPU Glossary
>>>>> +===============
>>>>> +
>>>>> +Here you can find some generic acronyms used in the amdgpu
>>>>> driver.
>>>>> Notice that
>>>>> +we have a dedicated glossary for Display Core.
>>>>
>>>> Maybe add a link to that here so it's easier to find? sphinx
>>>> autogenerates
>>>> header targets so pretty easy (if the heading is unique at least).
>>>> -Daniel
>>>>
>>>>> +
>>>>> +.. glossary::
>>>>> +
>>>>> + CPLIB
>>>>> + Content Protection Library
>>>>> +
>>>>> + DFS
>>>>> + Digital Frequency Synthesizer
>>>>> +
>>>>> + ECP
>>>>> + Enhanced Content Protection
>>>>> +
>>>>> + EOP
>>>>> + End Of Pipe/Pipeline
>>>>> +
>>>>> + HQD
>>>>> + Hardware Queue Descriptor
>>>>> +
>>>>> + KCQ
>>>>> + Kernel Compute Queue
>>>>> +
>>>>> + KGQ
>>>>> + Kernel Graphics Queue
>>>>> +
>>>>> + KIQ
>>>>> + Kernel Interface Queue
>>>>> +
>>>>> + MQD
>>>>> + Memory Queue Descriptor
>>>>> +
>>>>> + PPLib
>>>>> + PowerPlay Library - PowerPlay is the power management
>>>>> component.
>>>>> +
>>>>> + SMU
>>>>> + System Management Unit
>>>>> +
>>>>> + VCE
>>>>> + Video Compression Engine
>>>>> +
>>>>> + VCN
>>>>> + Video Codec Next
>>>>> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>> b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>> new file mode 100644
>>>>> index 000000000000..547c0bfbb3e2
>>>>> --- /dev/null
>>>>> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>> @@ -0,0 +1,243 @@
>>>>> +===========
>>>>> +DC Glossary
>>>>> +===========
>>>>> +
>>>>> +On this page, we try to keep track of acronyms related to the
>>>>> display
>>>>> +component. If you do not find what you are looking for, look at
>>>>> the amdgpu
>>>>> +glossary; if you cannot find it anywhere, consider asking in the
>>>>> amdgfx and
>>>>> +update this page.
>>>>> +
>>>>> +.. glossary::
>>>>> +
>>>>> + ABM
>>>>> + Adaptive Backlight Modulation
>>>>> +
>>>>> + APU
>>>>> + Accelerated Processing Unit
>>>>> +
>>>>> + ASIC
>>>>> + Application-Specific Integrated Circuit
>>>>> +
>>>>> + ASSR
>>>>> + Alternate Scrambler Seed Reset
>>>>> +
>>>>> + AZ
>>>>> + Azalia (HD audio DMA engine)
>>>>> +
>>>>> + BPC
>>>>> + Bits Per Colour/Component
>>>>> +
>>>>> + BPP
>>>>> + Bits Per Pixel
>>>>> +
>>>>> + Clocks
>>>>> + * PCLK: Pixel Clock
>>>>> + * SYMCLK: Symbol Clock
>>>>> + * SOCCLK: GPU Engine Clock
>>>>> + * DISPCLK: Display Clock
>>>>> + * DPPCLK: DPP Clock
>>>>> + * DCFCLK: Display Controller Fabric Clock
>>>>> + * REFCLK: Real Time Reference Clock
>>>>> + * PPLL: Pixel PLL
>>>>> + * FCLK: Fabric Clock
>>>>> + * MCLK: Memory Clock
>>>>> +
>>>>> + CRC
>>>>> + Cyclic Redundancy Check
>>>>> +
>>>>> + CRTC
>>>>> + Cathode Ray Tube Controller - commonly called "Controller"
>>>>> -
>>>>> Generates
>>>>> + raw stream of pixels, clocked at pixel clock
>>>>> +
>>>>> + CVT
>>>>> + Coordinated Video Timings
>>>>> +
>>>>> + DAL
>>>>> + Display Abstraction layer
>>>>> +
>>>>> + DC (Software)
>>>>> + Display Core
>>>>> +
>>>>> + DC (Hardware)
>>>>> + Display Controller
>>>>> +
>>>>> + DCC
>>>>> + Delta Colour Compression
>>>>> +
>>>>> + DCE
>>>>> + Display Controller Engine
>>>>> +
>>>>> + DCHUB
>>>>> + Display Controller HUB
>>>>> +
>>>>> + ARB
>>>>> + Arbiter
>>>>> +
>>>>> + VTG
>>>>> + Vertical Timing Generator
>>>>> +
>>>>> + DCN
>>>>> + Display Core Next
>>>>> +
>>>>> + DCCG
>>>>> + Display Clock Generator block
>>>>> +
>>>>> + DDC
>>>>> + Display Data Channel
>>>>> +
>>>>> + DIO
>>>>> + Display IO
>>>>> +
>>>>> + DPP
>>>>> + Display Pipes and Planes
>>>>> +
>>>>> + DSC
>>>>> + Display Stream Compression (Reduce the amount of bits to
>>>>> represent pixel
>>>>> + count while at the same pixel clock)
>>>>> +
>>>>> + dGPU
>>>>> + discrete GPU
>>>>> +
>>>>> + DMIF
>>>>> + Display Memory Interface
>>>>> +
>>>>> + DML
>>>>> + Display Mode Library
>>>>> +
>>>>> + DMCU
>>>>> + Display Micro-Controller Unit
>>>>> +
>>>>> + DMCUB
>>>>> + Display Micro-Controller Unit, version B
>>>>> +
>>>>> + DPCD
>>>>> + DisplayPort Configuration Data
>>>>> +
>>>>> + DPM(S)
>>>>> + Display Power Management (Signaling)
>>>>> +
>>>>> + DRR
>>>>> + Dynamic Refresh Rate
>>>>> +
>>>>> + DWB
>>>>> + Display Writeback
>>>>> +
>>>>> + FB
>>>>> + Frame Buffer
>>>>> +
>>>>> + FBC
>>>>> + Frame Buffer Compression
>>>>> +
>>>>> + FEC
>>>>> + Forward Error Correction
>>>>> +
>>>>> + FRL
>>>>> + Fixed Rate Link
>>>>> +
>>>>> + GCO
>>>>> + Graphical Controller Object
>>>>> +
>>>>> + GMC
>>>>> + Graphic Memory Controller
>>>>> +
>>>>> + GSL
>>>>> + Global Swap Lock
>>>>> +
>>>>> + iGPU
>>>>> + integrated GPU
>>>>> +
>>>>> + IH
>>>>> + Interrupt Handler
>>>>> +
>>>>> + ISR
>>>>> + Interrupt Service Request
>>>>> +
>>>>> + ISV
>>>>> + Independent Software Vendor
>>>>> +
>>>>> + KMD
>>>>> + Kernel Mode Driver
>>>>> +
>>>>> + LB
>>>>> + Line Buffer
>>>>> +
>>>>> + LFC
>>>>> + Low Framerate Compensation
>>>>> +
>>>>> + LTTPR
>>>>> + Link Training Tunable Phy Repeater
>>>>> +
>>>>> + LUT
>>>>> + Lookup Table
>>>>> +
>>>>> + MALL
>>>>> + Memory Access at Last Level
>>>>> +
>>>>> + MC
>>>>> + Memory Controller
>>>>> +
>>>>> + MPC
>>>>> + Multiple pipes and plane combine
>>>>> +
>>>>> + MPO
>>>>> + Multi Plane Overlay
>>>>> +
>>>>> + MST
>>>>> + Multi Stream Transport
>>>>> +
>>>>> + NBP State
>>>>> + Northbridge Power State
>>>>> +
>>>>> + NBIO
>>>>> + North Bridge Input/Output
>>>>> +
>>>>> + ODM
>>>>> + Output Data Mapping
>>>>> +
>>>>> + OPM
>>>>> + Output Protection Manager
>>>>> +
>>>>> + OPP
>>>>> + Output Plane Processor
>>>>> +
>>>>> + OPTC
>>>>> + Output Pipe Timing Combiner
>>>>> +
>>>>> + OTG
>>>>> + Output Timing Generator
>>>>> +
>>>>> + PCON
>>>>> + Power Controller
>>>>> +
>>>>> + PGFSM
>>>>> + Power Gate Finite State Machine
>>>>> +
>>>>> + PSR
>>>>> + Panel Self Refresh
>>>>> +
>>>>> + SCL
>>>>> + Scaler
>>>>> +
>>>>> + SDP
>>>>> + Scalable Data Port
>>>>> +
>>>>> + SLS
>>>>> + Single Large Surface
>>>>> +
>>>>> + SST
>>>>> + Single Stream Transport
>>>>> +
>>>>> + TMDS
>>>>> + Transition-Minimized Differential Signaling
>>>>> +
>>>>> + TMZ
>>>>> + Trusted Memory Zone
>>>>> +
>>>>> + TTU
>>>>> + Time to Underflow
>>>>> +
>>>>> + VRR
>>>>> + Variable Refresh Rate
>>>>> +
>>>>> + UVD
>>>>> + Unified Video Decoder
>>>>> diff --git a/Documentation/gpu/amdgpu/display/index.rst
>>>>> b/Documentation/gpu/amdgpu/display/index.rst
>>>>> index fe2ecad8df81..e23c752ee5f5 100644
>>>>> --- a/Documentation/gpu/amdgpu/display/index.rst
>>>>> +++ b/Documentation/gpu/amdgpu/display/index.rst
>>>>> @@ -26,3 +26,4 @@ table of content:
>>>>> display-manager.rst
>>>>> dc-debug.rst
>>>>> dcn-overview.rst
>>>>> + dc-glossary.rst
>>>>> diff --git a/Documentation/gpu/amdgpu/index.rst
>>>>> b/Documentation/gpu/amdgpu/index.rst
>>>>> index 5c8cbf514097..ff38c360b04e 100644
>>>>> --- a/Documentation/gpu/amdgpu/index.rst
>>>>> +++ b/Documentation/gpu/amdgpu/index.rst
>>>>> @@ -334,3 +334,10 @@ smartshift_bias
>>>>>
>>>>> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
>>>>> :doc: smartshift_bias
>>>>> +
>>>>> +AMDGPU Glossary
>>>>> +===============
>>>>> +
>>>>> +.. toctree::
>>>>> +
>>>>> + amdgpu-glossary.rst
>>>>> --
>>>>> 2.25.1
>>>>>
>>>>
>>>> --
>>>> Daniel Vetter
>>>> Software Engineer, Intel Corporation
>>>> http://blog.ffwll.ch/>>>
>>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
@ 2021-12-08 16:29 ` Rodrigo Siqueira Jordao
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira Jordao @ 2021-12-08 16:29 UTC (permalink / raw)
To: Yann Dirson
Cc: linux-doc, dri-devel, Rodrigo Siqueira, amd-gfx,
aurabindo pillai, Marek Olsak, Michel Daenzer, Sean Paul,
bhawanpreet lakha, Mark Yacoub, qingqing zhuo, roman li,
Roman Gilg, nicholas choi, Alex Deucher, Nicholas Kazlauskas,
Christian Koenig
On 2021-12-08 11:16 a.m., Yann Dirson wrote:
> Hi Rodrigo,
>
>> On 2021-12-07 2:49 p.m., Yann Dirson wrote:
>>>
>>>> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
>>>>> In the DC driver, we have multiple acronyms that are not obvious
>>>>> most of
>>>>> the time; the same idea is valid for amdgpu. This commit
>>>>> introduces
>>>>> a DC
>>>>> and amdgpu glossary in order to make it easier to navigate
>>>>> through
>>>>> our
>>>>> driver.
>>>>>
>>>>> Changes since V1:
>>>>> - Yann: Divide glossary based on driver context.
>>>>> - Alex: Make terms more consistent and update CPLIB
>>>>> - Add new acronyms to the glossary
>>>
>>> If you're rerolling, it could be a good time to include the
>>> additional
>>> (and detailed) entries from Alex's answer to "Looking for
>>> clarifications
>>> around gfx/kcq/kiq". Finding a way to fit the other details not
>>> fitting directly in the glossary will likely take more rounds,
>>> though,
>>> so we can wait for the first round to be merged before dealing with
>>> them.
>>
>> Hi Yann,
>>
>> I will send another version to address Daniel's comment, and I'll
>> also
>> expand the amdgpu acronyms glossary based on your mail thread with
>> Alex.
>> However, I don't want to add more details about that discussion in
>> this
>> series because I don't want to lose focus in this patchset since my
>> main
>> goal is to start to expand display documentation.
>
> fair enough
>
>
>> By the way, I think you could consider writing a kernel-doc based on
>> your discussion with Alex. This way, you can try to consolidate what
>> you
>> discover and get reviews in the content.
>
> that's the idea, though I'm not sure I have enough material to start with
> yet :)
As you know, right now, we have zero documentation about that, which
means that if you add something, it is an excellent improvement in the
current status :)
>>
>> Thanks
>> Siqueira
>>
>>>
>>>
>>>>>
>>>>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>>>>> ---
>>>>> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
>>>>> .../gpu/amdgpu/display/dc-glossary.rst | 243
>>>>> ++++++++++++++++++
>>>>> Documentation/gpu/amdgpu/display/index.rst | 1 +
>>>>> Documentation/gpu/amdgpu/index.rst | 7 +
>>>>> 4 files changed, 298 insertions(+)
>>>>> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> create mode 100644
>>>>> Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>>
>>>>> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> new file mode 100644
>>>>> index 000000000000..e635851025e7
>>>>> --- /dev/null
>>>>> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> @@ -0,0 +1,47 @@
>>>>> +===============
>>>>> +AMDGPU Glossary
>>>>> +===============
>>>>> +
>>>>> +Here you can find some generic acronyms used in the amdgpu
>>>>> driver.
>>>>> Notice that
>>>>> +we have a dedicated glossary for Display Core.
>>>>
>>>> Maybe add a link to that here so it's easier to find? sphinx
>>>> autogenerates
>>>> header targets so pretty easy (if the heading is unique at least).
>>>> -Daniel
>>>>
>>>>> +
>>>>> +.. glossary::
>>>>> +
>>>>> + CPLIB
>>>>> + Content Protection Library
>>>>> +
>>>>> + DFS
>>>>> + Digital Frequency Synthesizer
>>>>> +
>>>>> + ECP
>>>>> + Enhanced Content Protection
>>>>> +
>>>>> + EOP
>>>>> + End Of Pipe/Pipeline
>>>>> +
>>>>> + HQD
>>>>> + Hardware Queue Descriptor
>>>>> +
>>>>> + KCQ
>>>>> + Kernel Compute Queue
>>>>> +
>>>>> + KGQ
>>>>> + Kernel Graphics Queue
>>>>> +
>>>>> + KIQ
>>>>> + Kernel Interface Queue
>>>>> +
>>>>> + MQD
>>>>> + Memory Queue Descriptor
>>>>> +
>>>>> + PPLib
>>>>> + PowerPlay Library - PowerPlay is the power management
>>>>> component.
>>>>> +
>>>>> + SMU
>>>>> + System Management Unit
>>>>> +
>>>>> + VCE
>>>>> + Video Compression Engine
>>>>> +
>>>>> + VCN
>>>>> + Video Codec Next
>>>>> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>> b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>> new file mode 100644
>>>>> index 000000000000..547c0bfbb3e2
>>>>> --- /dev/null
>>>>> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>> @@ -0,0 +1,243 @@
>>>>> +===========
>>>>> +DC Glossary
>>>>> +===========
>>>>> +
>>>>> +On this page, we try to keep track of acronyms related to the
>>>>> display
>>>>> +component. If you do not find what you are looking for, look at
>>>>> the amdgpu
>>>>> +glossary; if you cannot find it anywhere, consider asking in the
>>>>> amdgfx and
>>>>> +update this page.
>>>>> +
>>>>> +.. glossary::
>>>>> +
>>>>> + ABM
>>>>> + Adaptive Backlight Modulation
>>>>> +
>>>>> + APU
>>>>> + Accelerated Processing Unit
>>>>> +
>>>>> + ASIC
>>>>> + Application-Specific Integrated Circuit
>>>>> +
>>>>> + ASSR
>>>>> + Alternate Scrambler Seed Reset
>>>>> +
>>>>> + AZ
>>>>> + Azalia (HD audio DMA engine)
>>>>> +
>>>>> + BPC
>>>>> + Bits Per Colour/Component
>>>>> +
>>>>> + BPP
>>>>> + Bits Per Pixel
>>>>> +
>>>>> + Clocks
>>>>> + * PCLK: Pixel Clock
>>>>> + * SYMCLK: Symbol Clock
>>>>> + * SOCCLK: GPU Engine Clock
>>>>> + * DISPCLK: Display Clock
>>>>> + * DPPCLK: DPP Clock
>>>>> + * DCFCLK: Display Controller Fabric Clock
>>>>> + * REFCLK: Real Time Reference Clock
>>>>> + * PPLL: Pixel PLL
>>>>> + * FCLK: Fabric Clock
>>>>> + * MCLK: Memory Clock
>>>>> +
>>>>> + CRC
>>>>> + Cyclic Redundancy Check
>>>>> +
>>>>> + CRTC
>>>>> + Cathode Ray Tube Controller - commonly called "Controller"
>>>>> -
>>>>> Generates
>>>>> + raw stream of pixels, clocked at pixel clock
>>>>> +
>>>>> + CVT
>>>>> + Coordinated Video Timings
>>>>> +
>>>>> + DAL
>>>>> + Display Abstraction layer
>>>>> +
>>>>> + DC (Software)
>>>>> + Display Core
>>>>> +
>>>>> + DC (Hardware)
>>>>> + Display Controller
>>>>> +
>>>>> + DCC
>>>>> + Delta Colour Compression
>>>>> +
>>>>> + DCE
>>>>> + Display Controller Engine
>>>>> +
>>>>> + DCHUB
>>>>> + Display Controller HUB
>>>>> +
>>>>> + ARB
>>>>> + Arbiter
>>>>> +
>>>>> + VTG
>>>>> + Vertical Timing Generator
>>>>> +
>>>>> + DCN
>>>>> + Display Core Next
>>>>> +
>>>>> + DCCG
>>>>> + Display Clock Generator block
>>>>> +
>>>>> + DDC
>>>>> + Display Data Channel
>>>>> +
>>>>> + DIO
>>>>> + Display IO
>>>>> +
>>>>> + DPP
>>>>> + Display Pipes and Planes
>>>>> +
>>>>> + DSC
>>>>> + Display Stream Compression (Reduce the amount of bits to
>>>>> represent pixel
>>>>> + count while at the same pixel clock)
>>>>> +
>>>>> + dGPU
>>>>> + discrete GPU
>>>>> +
>>>>> + DMIF
>>>>> + Display Memory Interface
>>>>> +
>>>>> + DML
>>>>> + Display Mode Library
>>>>> +
>>>>> + DMCU
>>>>> + Display Micro-Controller Unit
>>>>> +
>>>>> + DMCUB
>>>>> + Display Micro-Controller Unit, version B
>>>>> +
>>>>> + DPCD
>>>>> + DisplayPort Configuration Data
>>>>> +
>>>>> + DPM(S)
>>>>> + Display Power Management (Signaling)
>>>>> +
>>>>> + DRR
>>>>> + Dynamic Refresh Rate
>>>>> +
>>>>> + DWB
>>>>> + Display Writeback
>>>>> +
>>>>> + FB
>>>>> + Frame Buffer
>>>>> +
>>>>> + FBC
>>>>> + Frame Buffer Compression
>>>>> +
>>>>> + FEC
>>>>> + Forward Error Correction
>>>>> +
>>>>> + FRL
>>>>> + Fixed Rate Link
>>>>> +
>>>>> + GCO
>>>>> + Graphical Controller Object
>>>>> +
>>>>> + GMC
>>>>> + Graphic Memory Controller
>>>>> +
>>>>> + GSL
>>>>> + Global Swap Lock
>>>>> +
>>>>> + iGPU
>>>>> + integrated GPU
>>>>> +
>>>>> + IH
>>>>> + Interrupt Handler
>>>>> +
>>>>> + ISR
>>>>> + Interrupt Service Request
>>>>> +
>>>>> + ISV
>>>>> + Independent Software Vendor
>>>>> +
>>>>> + KMD
>>>>> + Kernel Mode Driver
>>>>> +
>>>>> + LB
>>>>> + Line Buffer
>>>>> +
>>>>> + LFC
>>>>> + Low Framerate Compensation
>>>>> +
>>>>> + LTTPR
>>>>> + Link Training Tunable Phy Repeater
>>>>> +
>>>>> + LUT
>>>>> + Lookup Table
>>>>> +
>>>>> + MALL
>>>>> + Memory Access at Last Level
>>>>> +
>>>>> + MC
>>>>> + Memory Controller
>>>>> +
>>>>> + MPC
>>>>> + Multiple pipes and plane combine
>>>>> +
>>>>> + MPO
>>>>> + Multi Plane Overlay
>>>>> +
>>>>> + MST
>>>>> + Multi Stream Transport
>>>>> +
>>>>> + NBP State
>>>>> + Northbridge Power State
>>>>> +
>>>>> + NBIO
>>>>> + North Bridge Input/Output
>>>>> +
>>>>> + ODM
>>>>> + Output Data Mapping
>>>>> +
>>>>> + OPM
>>>>> + Output Protection Manager
>>>>> +
>>>>> + OPP
>>>>> + Output Plane Processor
>>>>> +
>>>>> + OPTC
>>>>> + Output Pipe Timing Combiner
>>>>> +
>>>>> + OTG
>>>>> + Output Timing Generator
>>>>> +
>>>>> + PCON
>>>>> + Power Controller
>>>>> +
>>>>> + PGFSM
>>>>> + Power Gate Finite State Machine
>>>>> +
>>>>> + PSR
>>>>> + Panel Self Refresh
>>>>> +
>>>>> + SCL
>>>>> + Scaler
>>>>> +
>>>>> + SDP
>>>>> + Scalable Data Port
>>>>> +
>>>>> + SLS
>>>>> + Single Large Surface
>>>>> +
>>>>> + SST
>>>>> + Single Stream Transport
>>>>> +
>>>>> + TMDS
>>>>> + Transition-Minimized Differential Signaling
>>>>> +
>>>>> + TMZ
>>>>> + Trusted Memory Zone
>>>>> +
>>>>> + TTU
>>>>> + Time to Underflow
>>>>> +
>>>>> + VRR
>>>>> + Variable Refresh Rate
>>>>> +
>>>>> + UVD
>>>>> + Unified Video Decoder
>>>>> diff --git a/Documentation/gpu/amdgpu/display/index.rst
>>>>> b/Documentation/gpu/amdgpu/display/index.rst
>>>>> index fe2ecad8df81..e23c752ee5f5 100644
>>>>> --- a/Documentation/gpu/amdgpu/display/index.rst
>>>>> +++ b/Documentation/gpu/amdgpu/display/index.rst
>>>>> @@ -26,3 +26,4 @@ table of content:
>>>>> display-manager.rst
>>>>> dc-debug.rst
>>>>> dcn-overview.rst
>>>>> + dc-glossary.rst
>>>>> diff --git a/Documentation/gpu/amdgpu/index.rst
>>>>> b/Documentation/gpu/amdgpu/index.rst
>>>>> index 5c8cbf514097..ff38c360b04e 100644
>>>>> --- a/Documentation/gpu/amdgpu/index.rst
>>>>> +++ b/Documentation/gpu/amdgpu/index.rst
>>>>> @@ -334,3 +334,10 @@ smartshift_bias
>>>>>
>>>>> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
>>>>> :doc: smartshift_bias
>>>>> +
>>>>> +AMDGPU Glossary
>>>>> +===============
>>>>> +
>>>>> +.. toctree::
>>>>> +
>>>>> + amdgpu-glossary.rst
>>>>> --
>>>>> 2.25.1
>>>>>
>>>>
>>>> --
>>>> Daniel Vetter
>>>> Software Engineer, Intel Corporation
>>>> http://blog.ffwll.ch/>>>
>>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary
@ 2021-12-08 16:29 ` Rodrigo Siqueira Jordao
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Siqueira Jordao @ 2021-12-08 16:29 UTC (permalink / raw)
To: Yann Dirson
Cc: Simon Ser, linux-doc, dri-devel, Rodrigo Siqueira, amd-gfx,
aurabindo pillai, Harry Wentland, Marek Olsak, Michel Daenzer,
Pekka Paalanen, Sean Paul, bhawanpreet lakha, Mark Yacoub,
qingqing zhuo, roman li, Roman Gilg, nicholas choi,
Daniel Vetter, Bas Nieuwenhuizen, Alex Deucher,
Nicholas Kazlauskas, Christian Koenig
On 2021-12-08 11:16 a.m., Yann Dirson wrote:
> Hi Rodrigo,
>
>> On 2021-12-07 2:49 p.m., Yann Dirson wrote:
>>>
>>>> On Thu, Dec 02, 2021 at 11:01:32AM -0500, Rodrigo Siqueira wrote:
>>>>> In the DC driver, we have multiple acronyms that are not obvious
>>>>> most of
>>>>> the time; the same idea is valid for amdgpu. This commit
>>>>> introduces
>>>>> a DC
>>>>> and amdgpu glossary in order to make it easier to navigate
>>>>> through
>>>>> our
>>>>> driver.
>>>>>
>>>>> Changes since V1:
>>>>> - Yann: Divide glossary based on driver context.
>>>>> - Alex: Make terms more consistent and update CPLIB
>>>>> - Add new acronyms to the glossary
>>>
>>> If you're rerolling, it could be a good time to include the
>>> additional
>>> (and detailed) entries from Alex's answer to "Looking for
>>> clarifications
>>> around gfx/kcq/kiq". Finding a way to fit the other details not
>>> fitting directly in the glossary will likely take more rounds,
>>> though,
>>> so we can wait for the first round to be merged before dealing with
>>> them.
>>
>> Hi Yann,
>>
>> I will send another version to address Daniel's comment, and I'll
>> also
>> expand the amdgpu acronyms glossary based on your mail thread with
>> Alex.
>> However, I don't want to add more details about that discussion in
>> this
>> series because I don't want to lose focus in this patchset since my
>> main
>> goal is to start to expand display documentation.
>
> fair enough
>
>
>> By the way, I think you could consider writing a kernel-doc based on
>> your discussion with Alex. This way, you can try to consolidate what
>> you
>> discover and get reviews in the content.
>
> that's the idea, though I'm not sure I have enough material to start with
> yet :)
As you know, right now, we have zero documentation about that, which
means that if you add something, it is an excellent improvement in the
current status :)
>>
>> Thanks
>> Siqueira
>>
>>>
>>>
>>>>>
>>>>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>>>>> ---
>>>>> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 47 ++++
>>>>> .../gpu/amdgpu/display/dc-glossary.rst | 243
>>>>> ++++++++++++++++++
>>>>> Documentation/gpu/amdgpu/display/index.rst | 1 +
>>>>> Documentation/gpu/amdgpu/index.rst | 7 +
>>>>> 4 files changed, 298 insertions(+)
>>>>> create mode 100644 Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> create mode 100644
>>>>> Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>>
>>>>> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> new file mode 100644
>>>>> index 000000000000..e635851025e7
>>>>> --- /dev/null
>>>>> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>>>> @@ -0,0 +1,47 @@
>>>>> +===============
>>>>> +AMDGPU Glossary
>>>>> +===============
>>>>> +
>>>>> +Here you can find some generic acronyms used in the amdgpu
>>>>> driver.
>>>>> Notice that
>>>>> +we have a dedicated glossary for Display Core.
>>>>
>>>> Maybe add a link to that here so it's easier to find? sphinx
>>>> autogenerates
>>>> header targets so pretty easy (if the heading is unique at least).
>>>> -Daniel
>>>>
>>>>> +
>>>>> +.. glossary::
>>>>> +
>>>>> + CPLIB
>>>>> + Content Protection Library
>>>>> +
>>>>> + DFS
>>>>> + Digital Frequency Synthesizer
>>>>> +
>>>>> + ECP
>>>>> + Enhanced Content Protection
>>>>> +
>>>>> + EOP
>>>>> + End Of Pipe/Pipeline
>>>>> +
>>>>> + HQD
>>>>> + Hardware Queue Descriptor
>>>>> +
>>>>> + KCQ
>>>>> + Kernel Compute Queue
>>>>> +
>>>>> + KGQ
>>>>> + Kernel Graphics Queue
>>>>> +
>>>>> + KIQ
>>>>> + Kernel Interface Queue
>>>>> +
>>>>> + MQD
>>>>> + Memory Queue Descriptor
>>>>> +
>>>>> + PPLib
>>>>> + PowerPlay Library - PowerPlay is the power management
>>>>> component.
>>>>> +
>>>>> + SMU
>>>>> + System Management Unit
>>>>> +
>>>>> + VCE
>>>>> + Video Compression Engine
>>>>> +
>>>>> + VCN
>>>>> + Video Codec Next
>>>>> diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>> b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>> new file mode 100644
>>>>> index 000000000000..547c0bfbb3e2
>>>>> --- /dev/null
>>>>> +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst
>>>>> @@ -0,0 +1,243 @@
>>>>> +===========
>>>>> +DC Glossary
>>>>> +===========
>>>>> +
>>>>> +On this page, we try to keep track of acronyms related to the
>>>>> display
>>>>> +component. If you do not find what you are looking for, look at
>>>>> the amdgpu
>>>>> +glossary; if you cannot find it anywhere, consider asking in the
>>>>> amdgfx and
>>>>> +update this page.
>>>>> +
>>>>> +.. glossary::
>>>>> +
>>>>> + ABM
>>>>> + Adaptive Backlight Modulation
>>>>> +
>>>>> + APU
>>>>> + Accelerated Processing Unit
>>>>> +
>>>>> + ASIC
>>>>> + Application-Specific Integrated Circuit
>>>>> +
>>>>> + ASSR
>>>>> + Alternate Scrambler Seed Reset
>>>>> +
>>>>> + AZ
>>>>> + Azalia (HD audio DMA engine)
>>>>> +
>>>>> + BPC
>>>>> + Bits Per Colour/Component
>>>>> +
>>>>> + BPP
>>>>> + Bits Per Pixel
>>>>> +
>>>>> + Clocks
>>>>> + * PCLK: Pixel Clock
>>>>> + * SYMCLK: Symbol Clock
>>>>> + * SOCCLK: GPU Engine Clock
>>>>> + * DISPCLK: Display Clock
>>>>> + * DPPCLK: DPP Clock
>>>>> + * DCFCLK: Display Controller Fabric Clock
>>>>> + * REFCLK: Real Time Reference Clock
>>>>> + * PPLL: Pixel PLL
>>>>> + * FCLK: Fabric Clock
>>>>> + * MCLK: Memory Clock
>>>>> +
>>>>> + CRC
>>>>> + Cyclic Redundancy Check
>>>>> +
>>>>> + CRTC
>>>>> + Cathode Ray Tube Controller - commonly called "Controller"
>>>>> -
>>>>> Generates
>>>>> + raw stream of pixels, clocked at pixel clock
>>>>> +
>>>>> + CVT
>>>>> + Coordinated Video Timings
>>>>> +
>>>>> + DAL
>>>>> + Display Abstraction layer
>>>>> +
>>>>> + DC (Software)
>>>>> + Display Core
>>>>> +
>>>>> + DC (Hardware)
>>>>> + Display Controller
>>>>> +
>>>>> + DCC
>>>>> + Delta Colour Compression
>>>>> +
>>>>> + DCE
>>>>> + Display Controller Engine
>>>>> +
>>>>> + DCHUB
>>>>> + Display Controller HUB
>>>>> +
>>>>> + ARB
>>>>> + Arbiter
>>>>> +
>>>>> + VTG
>>>>> + Vertical Timing Generator
>>>>> +
>>>>> + DCN
>>>>> + Display Core Next
>>>>> +
>>>>> + DCCG
>>>>> + Display Clock Generator block
>>>>> +
>>>>> + DDC
>>>>> + Display Data Channel
>>>>> +
>>>>> + DIO
>>>>> + Display IO
>>>>> +
>>>>> + DPP
>>>>> + Display Pipes and Planes
>>>>> +
>>>>> + DSC
>>>>> + Display Stream Compression (Reduce the amount of bits to
>>>>> represent pixel
>>>>> + count while at the same pixel clock)
>>>>> +
>>>>> + dGPU
>>>>> + discrete GPU
>>>>> +
>>>>> + DMIF
>>>>> + Display Memory Interface
>>>>> +
>>>>> + DML
>>>>> + Display Mode Library
>>>>> +
>>>>> + DMCU
>>>>> + Display Micro-Controller Unit
>>>>> +
>>>>> + DMCUB
>>>>> + Display Micro-Controller Unit, version B
>>>>> +
>>>>> + DPCD
>>>>> + DisplayPort Configuration Data
>>>>> +
>>>>> + DPM(S)
>>>>> + Display Power Management (Signaling)
>>>>> +
>>>>> + DRR
>>>>> + Dynamic Refresh Rate
>>>>> +
>>>>> + DWB
>>>>> + Display Writeback
>>>>> +
>>>>> + FB
>>>>> + Frame Buffer
>>>>> +
>>>>> + FBC
>>>>> + Frame Buffer Compression
>>>>> +
>>>>> + FEC
>>>>> + Forward Error Correction
>>>>> +
>>>>> + FRL
>>>>> + Fixed Rate Link
>>>>> +
>>>>> + GCO
>>>>> + Graphical Controller Object
>>>>> +
>>>>> + GMC
>>>>> + Graphic Memory Controller
>>>>> +
>>>>> + GSL
>>>>> + Global Swap Lock
>>>>> +
>>>>> + iGPU
>>>>> + integrated GPU
>>>>> +
>>>>> + IH
>>>>> + Interrupt Handler
>>>>> +
>>>>> + ISR
>>>>> + Interrupt Service Request
>>>>> +
>>>>> + ISV
>>>>> + Independent Software Vendor
>>>>> +
>>>>> + KMD
>>>>> + Kernel Mode Driver
>>>>> +
>>>>> + LB
>>>>> + Line Buffer
>>>>> +
>>>>> + LFC
>>>>> + Low Framerate Compensation
>>>>> +
>>>>> + LTTPR
>>>>> + Link Training Tunable Phy Repeater
>>>>> +
>>>>> + LUT
>>>>> + Lookup Table
>>>>> +
>>>>> + MALL
>>>>> + Memory Access at Last Level
>>>>> +
>>>>> + MC
>>>>> + Memory Controller
>>>>> +
>>>>> + MPC
>>>>> + Multiple pipes and plane combine
>>>>> +
>>>>> + MPO
>>>>> + Multi Plane Overlay
>>>>> +
>>>>> + MST
>>>>> + Multi Stream Transport
>>>>> +
>>>>> + NBP State
>>>>> + Northbridge Power State
>>>>> +
>>>>> + NBIO
>>>>> + North Bridge Input/Output
>>>>> +
>>>>> + ODM
>>>>> + Output Data Mapping
>>>>> +
>>>>> + OPM
>>>>> + Output Protection Manager
>>>>> +
>>>>> + OPP
>>>>> + Output Plane Processor
>>>>> +
>>>>> + OPTC
>>>>> + Output Pipe Timing Combiner
>>>>> +
>>>>> + OTG
>>>>> + Output Timing Generator
>>>>> +
>>>>> + PCON
>>>>> + Power Controller
>>>>> +
>>>>> + PGFSM
>>>>> + Power Gate Finite State Machine
>>>>> +
>>>>> + PSR
>>>>> + Panel Self Refresh
>>>>> +
>>>>> + SCL
>>>>> + Scaler
>>>>> +
>>>>> + SDP
>>>>> + Scalable Data Port
>>>>> +
>>>>> + SLS
>>>>> + Single Large Surface
>>>>> +
>>>>> + SST
>>>>> + Single Stream Transport
>>>>> +
>>>>> + TMDS
>>>>> + Transition-Minimized Differential Signaling
>>>>> +
>>>>> + TMZ
>>>>> + Trusted Memory Zone
>>>>> +
>>>>> + TTU
>>>>> + Time to Underflow
>>>>> +
>>>>> + VRR
>>>>> + Variable Refresh Rate
>>>>> +
>>>>> + UVD
>>>>> + Unified Video Decoder
>>>>> diff --git a/Documentation/gpu/amdgpu/display/index.rst
>>>>> b/Documentation/gpu/amdgpu/display/index.rst
>>>>> index fe2ecad8df81..e23c752ee5f5 100644
>>>>> --- a/Documentation/gpu/amdgpu/display/index.rst
>>>>> +++ b/Documentation/gpu/amdgpu/display/index.rst
>>>>> @@ -26,3 +26,4 @@ table of content:
>>>>> display-manager.rst
>>>>> dc-debug.rst
>>>>> dcn-overview.rst
>>>>> + dc-glossary.rst
>>>>> diff --git a/Documentation/gpu/amdgpu/index.rst
>>>>> b/Documentation/gpu/amdgpu/index.rst
>>>>> index 5c8cbf514097..ff38c360b04e 100644
>>>>> --- a/Documentation/gpu/amdgpu/index.rst
>>>>> +++ b/Documentation/gpu/amdgpu/index.rst
>>>>> @@ -334,3 +334,10 @@ smartshift_bias
>>>>>
>>>>> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
>>>>> :doc: smartshift_bias
>>>>> +
>>>>> +AMDGPU Glossary
>>>>> +===============
>>>>> +
>>>>> +.. toctree::
>>>>> +
>>>>> + amdgpu-glossary.rst
>>>>> --
>>>>> 2.25.1
>>>>>
>>>>
>>>> --
>>>> Daniel Vetter
>>>> Software Engineer, Intel Corporation
>>>> http://blog.ffwll.ch/>>>
>>
^ permalink raw reply [flat|nested] 31+ messages in thread
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2021-12-02 16:01 [PATCH v2 0/6] Expand display core documentation Rodrigo Siqueira
2021-12-02 16:01 ` Rodrigo Siqueira
2021-12-02 16:01 ` [PATCH v2 1/6] Documentation/gpu: Reorganize DC documentation Rodrigo Siqueira
2021-12-02 16:01 ` Rodrigo Siqueira
2021-12-02 16:01 ` [PATCH v2 2/6] Documentation/gpu: Document amdgpu_dm_visual_confirm debugfs entry Rodrigo Siqueira
2021-12-02 16:01 ` Rodrigo Siqueira
2021-12-02 16:01 ` [PATCH v2 3/6] Documentation/gpu: Document pipe split visual confirmation Rodrigo Siqueira
2021-12-02 16:01 ` Rodrigo Siqueira
2021-12-02 16:01 ` [PATCH v2 4/6] Documentation/gpu: How to collect DTN log Rodrigo Siqueira
2021-12-02 16:01 ` Rodrigo Siqueira
2021-12-02 16:01 ` [PATCH v2 5/6] Documentation/gpu: Add basic overview of DC pipeline Rodrigo Siqueira
2021-12-03 21:06 ` Yann Dirson
2021-12-03 21:06 ` Yann Dirson
2021-12-03 21:06 ` Yann Dirson
2021-12-02 16:01 ` [PATCH v2 6/6] Documentation/gpu: Add amdgpu and dc glossary Rodrigo Siqueira
2021-12-02 16:01 ` Rodrigo Siqueira
2021-12-07 18:19 ` Daniel Vetter
2021-12-07 18:19 ` Daniel Vetter
2021-12-07 18:19 ` Daniel Vetter
2021-12-07 19:49 ` Yann Dirson
2021-12-07 19:49 ` Yann Dirson
2021-12-07 19:49 ` Yann Dirson
2021-12-08 15:46 ` Rodrigo Siqueira Jordao
2021-12-08 15:46 ` Rodrigo Siqueira Jordao
2021-12-08 15:46 ` Rodrigo Siqueira Jordao
2021-12-08 16:16 ` Yann Dirson
2021-12-08 16:16 ` Yann Dirson
2021-12-08 16:16 ` Yann Dirson
2021-12-08 16:29 ` Rodrigo Siqueira Jordao
2021-12-08 16:29 ` Rodrigo Siqueira Jordao
2021-12-08 16:29 ` Rodrigo Siqueira Jordao
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