* [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages
@ 2021-12-02 9:24 Tejas Upadhyay
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Tejas Upadhyay
` (6 more replies)
0 siblings, 7 replies; 12+ messages in thread
From: Tejas Upadhyay @ 2021-12-02 9:24 UTC (permalink / raw)
To: intel-gfx
Replace filling the GGTT entirely with scratch pages to avoid invalid
accesses from VT-d overfetch of scanout by only surrounding scanout vma
with guard pages. This eliminates the 100+ms delay in resume where we
have to repopulate the GGTT with scratch.
This should also help in avoiding slow suspend/resume on GEN11/12
platforms. Which will also resolve issues with following reported
errors : "slow framebuffer consoles issue impacts Linux S3"
V2: solved checkpatch warning
Chris Wilson (3):
drm/i915: Wrap all access to i915_vma.node.start|size
drm/i915: Introduce guard pages to i915_vma
drm/i915: Refine VT-d scanout workaround
drivers/gpu/drm/i915/display/intel_dpt.c | 4 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 6 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 34 ++++++------
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 15 ++---
.../drm/i915/gem/selftests/i915_gem_context.c | 19 +++++--
.../drm/i915/gem/selftests/i915_gem_mman.c | 2 +-
.../drm/i915/gem/selftests/igt_gem_utils.c | 6 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 8 +--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 42 +++++---------
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 5 +-
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 8 +--
drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 +++---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 ++---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 16 +++---
.../drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 12 ++--
.../gpu/drm/i915/gt/selftest_workarounds.c | 8 +--
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 55 ++++++++++++++-----
drivers/gpu/drm/i915/i915_vma.h | 24 +++++++-
drivers/gpu/drm/i915/i915_vma_types.h | 3 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 +++-
drivers/gpu/drm/i915/selftests/i915_request.c | 20 +++----
drivers/gpu/drm/i915/selftests/igt_spinner.c | 8 +--
37 files changed, 226 insertions(+), 159 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH V2 1/3] drm/i915: Wrap all access to i915_vma.node.start|size
2021-12-02 9:24 [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Tejas Upadhyay
@ 2021-12-02 9:24 ` Tejas Upadhyay
2021-12-03 10:14 ` Ramalingam C
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 2/3] drm/i915: Introduce guard pages to i915_vma Tejas Upadhyay
` (5 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Tejas Upadhyay @ 2021-12-02 9:24 UTC (permalink / raw)
To: intel-gfx
From: Chris Wilson <chris@chris-wilson.co.uk>
We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_node
allocation. That is we will offset the vma->pages so that the first page
is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
All users must then not use i915_vma.node.start directly, but compute
the guard offset, thus all users are converted to use a
i915_vma_offset() wrapper.
The notable exceptions are the selftests that are testing exact
behaviour of i915_vma_pin/i915_vma_insert.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpt.c | 4 +--
drivers/gpu/drm/i915/display/intel_fbdev.c | 6 ++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 34 ++++++++++---------
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 +--
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 15 ++++----
.../drm/i915/gem/selftests/i915_gem_context.c | 19 +++++++----
.../drm/i915/gem/selftests/i915_gem_mman.c | 2 +-
.../drm/i915/gem/selftests/igt_gem_utils.c | 6 ++--
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 8 ++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 5 +--
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 5 +--
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 8 ++---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 +++++-----
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 ++++----
drivers/gpu/drm/i915/gt/selftest_lrc.c | 16 ++++-----
.../drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 12 +++----
.../gpu/drm/i915/gt/selftest_workarounds.c | 8 ++---
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +--
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 21 ++++++------
drivers/gpu/drm/i915/i915_vma.h | 23 +++++++++++--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 ++++++-
drivers/gpu/drm/i915/selftests/i915_request.c | 20 +++++------
drivers/gpu/drm/i915/selftests/igt_spinner.c | 8 ++---
34 files changed, 169 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c
index 963ca7155b06..1bb99ef4ce2d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -64,7 +64,7 @@ static void dpt_insert_entries(struct i915_address_space *vm,
* not to allow the user to override access to a read only page.
*/
- i = vma->node.start / I915_GTT_PAGE_SIZE;
+ i = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, sgt_iter, vma->pages)
gen8_set_pte(&base[i++], pte_encode | addr);
}
@@ -104,7 +104,7 @@ static void dpt_bind_vma(struct i915_address_space *vm,
static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
{
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_vma_offset(vma), vma->size);
}
static void dpt_cleanup(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..0583dcd538ae 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -261,8 +261,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
- info->fix.smem_len = vma->node.size;
+ (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma));
+ info->fix.smem_len = vma->size;
}
vaddr = i915_vma_pin_iomap(vma);
@@ -273,7 +273,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
goto out_unpin;
}
info->screen_base = vaddr;
- info->screen_size = vma->node.size;
+ info->screen_size = vma->size;
drm_fb_helper_fill_info(info, &ifbdev->helper, sizes);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 6a0ed537c199..d024b88da608 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -376,22 +376,24 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
const struct i915_vma *vma,
unsigned int flags)
{
- if (vma->node.size < entry->pad_to_size)
+ const u64 start = i915_vma_offset(vma);
+ const u64 size = i915_vma_size(vma);
+
+ if (size < entry->pad_to_size)
return true;
- if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
+ if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
return true;
- if (flags & EXEC_OBJECT_PINNED &&
- vma->node.start != entry->offset)
+ if (flags & EXEC_OBJECT_PINNED && start != entry->offset)
return true;
if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
- vma->node.start < BATCH_OFFSET_BIAS)
+ start < BATCH_OFFSET_BIAS)
return true;
if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
- (vma->node.start + vma->node.size + 4095) >> 32)
+ (start + size + 4095) >> 32)
return true;
if (flags & __EXEC_OBJECT_NEEDS_MAP &&
@@ -437,7 +439,7 @@ eb_pin_vma(struct i915_execbuffer *eb,
int err;
if (vma->node.size)
- pin_flags = vma->node.start;
+ pin_flags = __i915_vma_offset(vma);
else
pin_flags = entry->offset & PIN_OFFSET_MASK;
@@ -677,8 +679,8 @@ static int eb_reserve_vma(struct i915_execbuffer *eb,
if (err)
return err;
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
@@ -990,8 +992,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb)
return err;
if (!err) {
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
+ if (entry->offset != i915_vma_offset(vma)) {
+ entry->offset = i915_vma_offset(vma) | UPDATE;
eb->args->flags |= __EXEC_HAS_RELOC;
}
} else {
@@ -1073,7 +1075,7 @@ static inline u64
relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
const struct i915_vma *target)
{
- return gen8_canonical_addr((int)reloc->delta + target->node.start);
+ return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target));
}
static void reloc_cache_init(struct reloc_cache *cache,
@@ -1229,7 +1231,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
if (err) /* no inactive aperture space, use cpu reloc */
return NULL;
} else {
- cache->node.start = vma->node.start;
+ cache->node.start = i915_ggtt_offset(vma);
cache->node.mm = (void *)vma;
}
}
@@ -1387,7 +1389,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
* more work needs to be done.
*/
if (!DBG_FORCE_RELOC &&
- gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
+ gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset)
return 0;
/* Check that the relocation address is valid... */
@@ -2331,7 +2333,7 @@ static int eb_request_submit(struct i915_execbuffer *eb,
}
err = rq->context->engine->emit_bb_start(rq,
- batch->node.start +
+ i915_vma_offset(batch) +
eb->batch_start_offset,
batch_len,
eb->batch_flags);
@@ -2342,7 +2344,7 @@ static int eb_request_submit(struct i915_execbuffer *eb,
GEM_BUG_ON(intel_context_is_parallel(rq->context));
GEM_BUG_ON(eb->batch_start_offset);
err = rq->context->engine->emit_bb_start(rq,
- eb->trampoline->node.start +
+ i915_vma_offset(eb->trampoline) +
batch_len, 0, 0);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 65fc6ff5f59d..5d3fa137389e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -378,7 +378,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
- (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT,
+ (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
min_t(u64, vma->size, area->vm_end - area->vm_start),
&ggtt->iomap);
if (ret)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 157a9765f483..7738e97d43b0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -406,7 +406,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
mutex_lock(&i915->ggtt.vm.mutex);
list_for_each_entry_safe(vma, next,
&i915->ggtt.vm.bound_list, vm_link) {
- unsigned long count = vma->node.size >> PAGE_SHIFT;
+ unsigned long count = i915_vma_size(vma) >> PAGE_SHIFT;
if (!vma->iomap || i915_vma_is_active(vma))
continue;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index ef4d0f7dc118..1e49c7c69d80 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -166,11 +166,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma,
return true;
size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return false;
alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
- if (!IS_ALIGNED(vma->node.start, alignment))
+ if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment))
return false;
return true;
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index c69c7d45aabc..c9361ffeb5d4 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -401,7 +401,7 @@ static int igt_check_page_sizes(struct i915_vma *vma)
* Maintaining alignment is required to utilise huge pages in the ppGGT.
*/
if (i915_gem_object_is_lmem(obj) &&
- IS_ALIGNED(vma->node.start, SZ_2M) &&
+ IS_ALIGNED(i915_vma_offset(vma), SZ_2M) &&
vma->page_sizes.sg & SZ_2M &&
vma->page_sizes.gtt < SZ_2M) {
pr_err("gtt pages mismatch for LMEM, expected 2M GTT pages, sg(%u), gtt(%u)\n",
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 8402ed925a69..d383b9f53a77 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -94,14 +94,14 @@ static int prepare_blit(const struct tiled_blits *t,
*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
*cs++ = 0;
*cs++ = t->height << 16 | t->width;
- *cs++ = lower_32_bits(dst->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(dst->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(dst->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(dst->vma));
*cs++ = 0;
*cs++ = src_pitch;
- *cs++ = lower_32_bits(src->vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(src->vma));
if (use_64b_reloc)
- *cs++ = upper_32_bits(src->vma->node.start);
+ *cs++ = upper_32_bits(i915_vma_offset(src->vma));
*cs++ = MI_BATCH_BUFFER_END;
@@ -317,7 +317,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
{
int err;
- if (drm_mm_node_allocated(&vma->node) && vma->node.start != addr) {
+ if (drm_mm_node_allocated(&vma->node) && i915_vma_offset(vma) != addr) {
err = i915_vma_unbind(vma);
if (err)
return err;
@@ -327,6 +327,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
if (err)
return err;
+ GEM_BUG_ON(i915_vma_offset(vma) != addr);
return 0;
}
@@ -373,8 +374,8 @@ tiled_blit(struct tiled_blits *t,
err = move_to_active(dst->vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- t->batch->node.start,
- t->batch->node.size,
+ i915_vma_offset(t->batch),
+ i915_vma_size(t->batch),
0);
i915_request_get(rq);
i915_request_add(rq);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index b32f7fed2d9c..fe01a7d92362 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -895,8 +895,8 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
*cmd = MI_BATCH_BUFFER_END;
__i915_gem_object_flush_map(rpcs, 0, 64);
@@ -984,7 +984,8 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
}
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
if (err)
goto skip_request;
@@ -1553,7 +1554,10 @@ static int write_to_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
+ 0);
if (err)
goto skip_request;
@@ -1660,7 +1664,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
*cmd++ = offset;
*cmd++ = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
*cmd++ = reg;
- *cmd++ = vma->node.start + result;
+ *cmd++ = i915_vma_offset(vma) + result;
*cmd = MI_BATCH_BUFFER_END;
i915_gem_object_flush_map(obj);
@@ -1691,7 +1695,10 @@ static int read_from_scratch(struct i915_gem_context *ctx,
goto skip_request;
}
- err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, flags);
+ err = engine->emit_bb_start(rq,
+ i915_vma_offset(vma),
+ i915_vma_size(vma),
+ flags);
if (err)
goto skip_request;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 6d30cdfa80f3..762881791e25 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -1196,7 +1196,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
if (err == 0)
err = i915_vma_move_to_active(vma, rq, 0);
- err = engine->emit_bb_start(rq, vma->node.start, 0, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0);
i915_request_get(rq);
i915_request_add(rq);
diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
index b35c1219c852..4390d69bd746 100644
--- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
+++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
@@ -61,8 +61,8 @@ igt_emit_store_dw(struct i915_vma *vma,
goto err;
}
- GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > vma->node.size);
- offset += vma->node.start;
+ GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > i915_vma_size(vma));
+ offset += i915_vma_offset(vma);
for (n = 0; n < count; n++) {
if (ver >= 8) {
@@ -150,7 +150,7 @@ int igt_gpu_fill_dw(struct intel_context *ce,
flags |= I915_DISPATCH_SECURE;
err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
+ i915_vma_offset(batch), i915_vma_size(batch),
flags);
skip_request:
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 4a166d25fe60..72a8725e6f8a 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -110,7 +110,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
{
struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_directory * const pd = ppgtt->pd;
- unsigned int first_entry = vma->node.start / I915_GTT_PAGE_SIZE;
+ unsigned int first_entry = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
unsigned int act_pt = first_entry / GEN6_PTES;
unsigned int act_pte = first_entry % GEN6_PTES;
const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index 21f08e53889c..a14f962aaa85 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -105,7 +105,7 @@ static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)
static u32 batch_addr(const struct batch_chunk *bc)
{
- return bc->vma->node.start;
+ return i915_vma_offset(bc->vma);
}
static void batch_add(struct batch_chunk *bc, const u32 d)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9966e9dc5218..dd2ab23a123c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -460,7 +460,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
{
const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
unsigned int rem = sg_dma_len(iter->sg);
- u64 start = vma->node.start;
+ u64 start = i915_vma_offset(vma);
GEM_BUG_ON(!i915_vm_is_4lvl(vma->vm));
@@ -542,8 +542,8 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
if (maybe_64K != -1 &&
(index == I915_PDES ||
(i915_vm_has_scratch_64K(vma->vm) &&
- !iter->sg && IS_ALIGNED(vma->node.start +
- vma->node.size,
+ !iter->sg && IS_ALIGNED(i915_vma_offset(vma) +
+ i915_vma_size(vma),
I915_GTT_PAGE_SIZE_2M)))) {
vaddr = px_vaddr(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
@@ -587,7 +587,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
gen8_ppgtt_insert_huge(vma, &iter, cache_level, flags);
} else {
- u64 idx = vma->node.start >> GEN8_PTE_SHIFT;
+ u64 idx = i915_vma_offset(vma) >> GEN8_PTE_SHIFT;
do {
struct i915_page_directory * const pdp =
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 110d3944f9a2..07133f0c529e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -458,7 +458,8 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
unsigned int flags = (cache_level == I915_CACHE_NONE) ?
AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
- intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
+ intel_gtt_insert_sg_entries(vma->pages,
+ i915_ggtt_offset(vma) >> PAGE_SHIFT,
flags);
}
@@ -649,7 +650,7 @@ static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
struct i915_vma *vma)
{
if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_ggtt_offset(vma), vma->size);
if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND))
ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index f8948de72036..b6fea674e6a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -215,7 +215,8 @@ static int fence_update(struct i915_fence_reg *fence,
return ret;
}
- fence->start = vma->node.start;
+ GEM_BUG_ON(vma->fence_size > i915_vma_size(vma));
+ fence->start = i915_ggtt_offset(vma);
fence->size = vma->fence_size;
fence->stride = i915_gem_object_get_stride(vma->obj);
fence->tiling = i915_gem_object_get_tiling(vma->obj);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 4396bfd630d8..4773c95db012 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -186,7 +186,8 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
u32 pte_flags;
if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) {
- vm->allocate_va_range(vm, stash, vma->node.start, vma->size);
+ GEM_BUG_ON(vma->size > i915_vma_size(vma));
+ vm->allocate_va_range(vm, stash, i915_vma_offset(vma), vma->size);
set_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma));
}
@@ -204,7 +205,7 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
{
if (test_and_clear_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma)))
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, i915_vma_offset(vma), vma->size);
}
static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index b575cd6e0b7a..2630fe6c8142 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -61,7 +61,7 @@ static int render_state_setup(struct intel_renderstate *so,
u32 s = rodata->batch[i];
if (i * 4 == rodata->reloc[reloc_index]) {
- u64 r = s + so->vma->node.start;
+ u64 r = s + i915_vma_offset(so->vma);
s = lower_32_bits(r);
if (HAS_64BIT_RELOC(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 3e6fac0340ef..2c4c5c095c56 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -886,7 +886,7 @@ static int clear_residuals(struct i915_request *rq)
}
ret = engine->emit_bb_start(rq,
- engine->wa_ctx.vma->node.start, 0,
+ i915_vma_offset(engine->wa_ctx.vma), 0,
0);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 64abf5feabfa..9e28873a7e45 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -165,7 +165,7 @@ static int perf_mi_bb_start(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- batch->node.start, 8,
+ i915_vma_offset(batch), 8,
0);
if (err)
goto out;
@@ -305,7 +305,7 @@ static int perf_mi_noop(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- base->node.start, 8,
+ i915_vma_offset(base), 8,
0);
if (err)
goto out;
@@ -315,8 +315,8 @@ static int perf_mi_noop(void *arg)
goto out;
err = rq->engine->emit_bb_start(rq,
- nop->node.start,
- nop->node.size,
+ i915_vma_offset(nop),
+ i915_vma_size(nop),
0);
if (err)
goto out;
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index b367ecfa42de..b803123df073 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -2732,11 +2732,11 @@ static int create_gang(struct intel_engine_cs *engine,
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_EQ_SDD;
*cs++ = 0;
- *cs++ = lower_32_bits(vma->node.start);
- *cs++ = upper_32_bits(vma->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(vma));
+ *cs++ = upper_32_bits(i915_vma_offset(vma));
if (*prev) {
- u64 offset = (*prev)->batch->node.start;
+ u64 offset = i915_vma_offset((*prev)->batch);
/* Terminate the spinner in the next lower priority batch. */
*cs++ = MI_STORE_DWORD_IMM_GEN4;
@@ -2764,7 +2764,7 @@ static int create_gang(struct intel_engine_cs *engine,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
i915_request_add(rq);
@@ -3092,7 +3092,7 @@ create_gpr_user(struct intel_engine_cs *engine,
*cs++ = MI_MATH_ADD;
*cs++ = MI_MATH_STORE(MI_MATH_REG(i), MI_MATH_REG_ACCU);
- addr = result->node.start + offset + i * sizeof(*cs);
+ addr = i915_vma_offset(result) + offset + i * sizeof(*cs);
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = CS_GPR(engine, 2 * i);
*cs++ = lower_32_bits(addr);
@@ -3102,8 +3102,8 @@ create_gpr_user(struct intel_engine_cs *engine,
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_GTE_SDD;
*cs++ = i;
- *cs++ = lower_32_bits(result->node.start);
- *cs++ = upper_32_bits(result->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(result));
+ *cs++ = upper_32_bits(i915_vma_offset(result));
}
*cs++ = MI_BATCH_BUFFER_END;
@@ -3187,7 +3187,7 @@ create_gpr_client(struct intel_engine_cs *engine,
err = i915_vma_move_to_active(batch, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- batch->node.start,
+ i915_vma_offset(batch),
PAGE_SIZE, 0);
i915_vma_unlock(batch);
i915_vma_unpin(batch);
@@ -3519,7 +3519,7 @@ static int smoke_submit(struct preempt_smoke *smoke,
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_vma_unlock(vma);
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index e5ad4d5a91c0..b0236c4d615c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -94,7 +94,8 @@ static int hang_init(struct hang *h, struct intel_gt *gt)
static u64 hws_address(const struct i915_vma *hws,
const struct i915_request *rq)
{
- return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context);
+ return i915_vma_offset(hws) +
+ offset_in_page(sizeof(u32) * rq->fence.context);
}
static int move_to_active(struct i915_vma *vma,
@@ -194,8 +195,8 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
} else if (GRAPHICS_VER(gt->i915) >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
@@ -208,7 +209,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else if (GRAPHICS_VER(gt->i915) >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
@@ -221,7 +222,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
} else {
*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -233,7 +234,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
- *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
}
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
intel_gt_chipset_flush(engine->gt);
@@ -248,7 +249,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
if (GRAPHICS_VER(gt->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = rq->engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
cancel_rq:
if (err) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index b0977a3b699b..ca2f2dec7089 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -955,8 +955,8 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
while (len--) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = hw[dw];
- *cs++ = lower_32_bits(scratch->node.start + x);
- *cs++ = upper_32_bits(scratch->node.start + x);
+ *cs++ = lower_32_bits(i915_vma_offset(scratch) + x);
+ *cs++ = upper_32_bits(i915_vma_offset(scratch) + x);
dw += 2;
x += 4;
@@ -1038,8 +1038,8 @@ record_registers(struct intel_context *ce,
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(b_before->node.start);
- *cs++ = upper_32_bits(b_before->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(b_before));
+ *cs++ = upper_32_bits(i915_vma_offset(b_before));
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
*cs++ = MI_SEMAPHORE_WAIT |
@@ -1054,8 +1054,8 @@ record_registers(struct intel_context *ce,
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(b_after->node.start);
- *cs++ = upper_32_bits(b_after->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(b_after));
+ *cs++ = upper_32_bits(i915_vma_offset(b_after));
intel_ring_advance(rq, cs);
@@ -1163,8 +1163,8 @@ static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
- *cs++ = lower_32_bits(batch->node.start);
- *cs++ = upper_32_bits(batch->node.start);
+ *cs++ = lower_32_bits(i915_vma_offset(batch));
+ *cs++ = upper_32_bits(i915_vma_offset(batch));
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
index 041954408d0f..8d29f6b979bd 100644
--- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
@@ -50,7 +50,7 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
} else {
*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
}
- *cs++ = vma->node.start + 4000;
+ *cs++ = i915_vma_offset(vma) + 4000;
*cs++ = STACK_MAGIC;
*cs++ = MI_BATCH_BUFFER_END;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 7ee2513e15f9..d242ed23e609 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -119,14 +119,14 @@ create_spin_counter(struct intel_engine_cs *engine,
if (srm) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8;
*cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));
- *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + end * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
}
}
*cs++ = MI_BATCH_BUFFER_START_GEN8;
- *cs++ = lower_32_bits(vma->node.start + loop * sizeof(*cs));
- *cs++ = upper_32_bits(vma->node.start + loop * sizeof(*cs));
+ *cs++ = lower_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
+ *cs++ = upper_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
GEM_BUG_ON(cs - base > end);
i915_gem_object_flush_map(obj);
@@ -655,7 +655,7 @@ int live_rps_frequency_cs(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
@@ -796,7 +796,7 @@ int live_rps_frequency_srm(void *arg)
err = i915_vma_move_to_active(vma, rq, 0);
if (!err)
err = rq->engine->emit_bb_start(rq,
- vma->node.start,
+ i915_vma_offset(vma),
PAGE_SIZE, 0);
i915_request_add(rq);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 962e91ba3be4..cd027e98e409 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -521,8 +521,8 @@ static int check_dirty_whitelist(struct intel_context *ce)
for (i = 0; i < engine->whitelist.count; i++) {
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
+ u64 addr = i915_vma_offset(scratch);
struct i915_gem_ww_ctx ww;
- u64 addr = scratch->node.start;
struct i915_request *rq;
u32 srm, lrm, rsvd;
u32 expect;
@@ -645,7 +645,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
goto err_request;
err = engine->emit_bb_start(rq,
- batch->node.start, PAGE_SIZE,
+ i915_vma_offset(batch), PAGE_SIZE,
0);
if (err)
goto err_request;
@@ -877,7 +877,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
}
for (i = 0; i < engine->whitelist.count; i++) {
- u64 offset = results->node.start + sizeof(u32) * i;
+ u64 offset = i915_vma_offset(results) + sizeof(u32) * i;
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
/* Clear non priv flags */
@@ -951,7 +951,7 @@ static int scrub_whitelisted_registers(struct intel_context *ce)
goto err_request;
/* Perform the writes from an unprivileged "user" batch */
- err = engine->emit_bb_start(rq, batch->node.start, 0, 0);
+ err = engine->emit_bb_start(rq, i915_vma_offset(batch), 0, 0);
err_request:
err = request_add_sync(rq, err);
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index e0403ce9ce69..c2109006df8b 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1459,8 +1459,8 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
/* Defer failure until attempted use */
jump_whitelist = alloc_whitelist(batch_length);
- shadow_addr = gen8_canonical_addr(shadow->node.start);
- batch_addr = gen8_canonical_addr(batch->node.start + batch_offset);
+ shadow_addr = gen8_canonical_addr(i915_vma_offset(shadow));
+ batch_addr = gen8_canonical_addr(i915_vma_offset(batch) + batch_offset);
/*
* We use the batch length as size because the shadow object is as
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 390d541f64ea..b082af695d4e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -170,7 +170,7 @@ i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
stringify_vma_type(vma),
- vma->node.start, vma->node.size,
+ i915_vma_offset(vma), i915_vma_size(vma),
stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
switch (vma->ggtt_view.type) {
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2f01b8c0284c..d6c7d90ce5cc 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2015,7 +2015,7 @@ emit_oa_config(struct i915_perf_stream *stream,
goto err_add_request;
err = rq->engine->emit_bb_start(rq,
- vma->node.start, 0,
+ i915_vma_offset(vma), 0,
I915_DISPATCH_SECURE);
if (err)
goto err_add_request;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 927f0d4f8e11..10473ce8a047 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -399,7 +399,7 @@ int i915_vma_bind(struct i915_vma *vma,
u32 vma_flags;
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(vma->size > vma->node.size);
+ GEM_BUG_ON(vma->size > i915_vma_size(vma));
if (GEM_DEBUG_WARN_ON(range_overflows(vma->node.start,
vma->node.size,
@@ -494,8 +494,8 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
vma->obj->base.size);
else
ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
- vma->node.start,
- vma->node.size);
+ i915_vma_offset(vma),
+ i915_vma_size(vma));
if (ptr == NULL) {
err = -ENOMEM;
goto err;
@@ -569,22 +569,22 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
if (test_bit(I915_VMA_ERROR_BIT, __i915_vma_flags(vma)))
return true;
- if (vma->node.size < size)
+ if (i915_vma_size(vma) < size)
return true;
GEM_BUG_ON(alignment && !is_power_of_2(alignment));
- if (alignment && !IS_ALIGNED(vma->node.start, alignment))
+ if (alignment && !IS_ALIGNED(i915_vma_offset(vma), alignment))
return true;
if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma))
return true;
if (flags & PIN_OFFSET_BIAS &&
- vma->node.start < (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) < (flags & PIN_OFFSET_MASK))
return true;
if (flags & PIN_OFFSET_FIXED &&
- vma->node.start != (flags & PIN_OFFSET_MASK))
+ i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
return true;
return false;
@@ -597,10 +597,11 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!vma->fence_size);
- fenceable = (vma->node.size >= vma->fence_size &&
- IS_ALIGNED(vma->node.start, vma->fence_alignment));
+ fenceable = (i915_vma_size(vma) >= vma->fence_size &&
+ IS_ALIGNED(i915_vma_offset(vma), vma->fence_alignment));
- mappable = vma->node.start + vma->fence_size <= i915_vm_to_ggtt(vma->vm)->mappable_end;
+ mappable = i915_ggtt_offset(vma) + vma->fence_size <=
+ i915_vm_to_ggtt(vma->vm)->mappable_end;
if (mappable && fenceable)
set_bit(I915_VMA_CAN_FENCE_BIT, __i915_vma_flags(vma));
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 4033aa08d5e4..1d13d619ff86 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -125,13 +125,30 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
return !list_empty(&vma->closed_link);
}
+static inline u64 i915_vma_size(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return vma->node.size;
+}
+
+static inline u64 __i915_vma_offset(const struct i915_vma *vma)
+{
+ return vma->node.start;
+}
+
+static inline u64 i915_vma_offset(const struct i915_vma *vma)
+{
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ return __i915_vma_offset(vma);
+}
+
static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
{
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- GEM_BUG_ON(upper_32_bits(vma->node.start));
- GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1));
- return lower_32_bits(vma->node.start);
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma)));
+ GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma) + i915_vma_size(vma) - 1));
+ return lower_32_bits(i915_vma_offset(vma));
}
static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 46f4236039a9..89528c0d19f4 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -245,6 +245,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
if (!mock_vma)
return -ENOMEM;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &mock_vma->node.flags);
+ if (i915_is_ggtt(vm))
+ __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(mock_vma));
+
/* Keep creating larger objects until one cannot fit into the hole */
for (size = 12; (hole_end - hole_start) >> size; size++) {
I915_RND_SUBSTATE(prng, seed_prng);
@@ -1982,6 +1986,7 @@ static int igt_cs_tlb(void *arg)
goto end;
/* Prime the TLB with the dummy pages */
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
for (i = 0; i < count; i++) {
vma->node.start = offset + i * PAGE_SIZE;
vm->insert_entries(vm, vma, I915_CACHE_NONE, 0);
@@ -1995,8 +2000,10 @@ static int igt_cs_tlb(void *arg)
}
vma->ops->clear_pages(vma);
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
+ &vma->node.flags);
- err = context_sync(ce);
+ err = context_sync(ce);
if (err) {
pr_err("%s: dummy setup timed out\n",
ce->engine->name);
@@ -2014,6 +2021,7 @@ static int igt_cs_tlb(void *arg)
goto end;
/* Replace the TLB with target batches */
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
for (i = 0; i < count; i++) {
struct i915_request *rq;
u32 *cs = batch + i * 64 / sizeof(*cs);
@@ -2048,6 +2056,8 @@ static int igt_cs_tlb(void *arg)
end_spin(batch, count - 1);
vma->ops->clear_pages(vma);
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
+ &vma->node.flags);
err = context_sync(ce);
if (err) {
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index 9979ef9197cd..737d29bbc3b5 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -879,8 +879,8 @@ empty_request(struct intel_engine_cs *engine,
return request;
err = engine->emit_bb_start(request,
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
I915_DISPATCH_SECURE);
if (err)
goto out_request;
@@ -1000,14 +1000,14 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
if (ver >= 8) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
- *cmd++ = lower_32_bits(vma->node.start);
- *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
+ *cmd++ = upper_32_bits(i915_vma_offset(vma));
} else if (ver >= 6) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
} else {
*cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = lower_32_bits(i915_vma_offset(vma));
}
*cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */
@@ -1091,8 +1091,8 @@ static int live_all_engines(void *arg)
GEM_BUG_ON(err);
err = engine->emit_bb_start(request[idx],
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
GEM_BUG_ON(err);
request[idx]->batch = batch;
@@ -1221,8 +1221,8 @@ static int live_sequential_engines(void *arg)
GEM_BUG_ON(err);
err = engine->emit_bb_start(request[idx],
- batch->node.start,
- batch->node.size,
+ i915_vma_offset(batch),
+ i915_vma_size(batch),
0);
GEM_BUG_ON(err);
request[idx]->batch = batch;
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 24d87d0fc747..d5939f1f14e4 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -115,7 +115,7 @@ static unsigned int seqno_offset(u64 fence)
static u64 hws_address(const struct i915_vma *hws,
const struct i915_request *rq)
{
- return hws->node.start + seqno_offset(rq->fence.context);
+ return i915_vma_offset(hws) + seqno_offset(rq->fence.context);
}
static int move_to_active(struct i915_vma *vma,
@@ -202,8 +202,8 @@ igt_spinner_create_request(struct igt_spinner *spin,
*batch++ = MI_BATCH_BUFFER_START;
else
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
- *batch++ = lower_32_bits(vma->node.start);
- *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = lower_32_bits(i915_vma_offset(vma));
+ *batch++ = upper_32_bits(i915_vma_offset(vma));
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
@@ -218,7 +218,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
flags = 0;
if (GRAPHICS_VER(rq->engine->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
cancel_rq:
if (err) {
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH V2 2/3] drm/i915: Introduce guard pages to i915_vma
2021-12-02 9:24 [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Tejas Upadhyay
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Tejas Upadhyay
@ 2021-12-02 9:24 ` Tejas Upadhyay
2021-12-03 10:54 ` Ramalingam C
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 3/3] drm/i915: Refine VT-d scanout workaround Tejas Upadhyay
` (4 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Tejas Upadhyay @ 2021-12-02 9:24 UTC (permalink / raw)
To: intel-gfx
From: Chris Wilson <chris@chris-wilson.co.uk>
Introduce the concept of padding the i915_vma with guard pages before
and aft. The major consequence is that all ordinary uses of i915_vma
must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
directly, as the drm_mm_node will include the guard pages that surround
our object.
The biggest connundrum is how exactly to mix requesting a fixed address
with guard pages, particularly through the existing uABI. The user does
not know about guard pages, so such must be transparent to the user, and
so the execobj.offset must be that of the object itself excluding the
guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
The caveat is that some placements will be impossible with guard pages,
as wrap arounds need to be avoided, and the vma itself will require a
larger node. We must we not report EINVAL but ENOSPC as these are
unavailable locations within the GTT rather than conflicting user
requirements.
In the next patch, we start using guard pages for scanout objects. While
these are limited to GGTT vma, on a few platforms these vma (or at least
an alias of the vma) is shared with userspace, so we may leak the
existence of such guards if we are not careful to ensure that the
execobj.offset is transparent and excludes the guards. (On such platforms
like ivb, without full-ppgtt, userspace has to use relocations so the
presence of more untouchable regions within its GTT such be of no further
issue.)
v2: Include the guard range in the overflow checks and placement
restrictions.
v3: Fix the check on the placement upper bound. The request user offset
is relative to the guard offset (not the node.start) and so we should
not include the initial guard offset again when computing the upper
bound of the node.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++++++++++--
drivers/gpu/drm/i915/i915_vma.c | 26 +++++++++++++++++++++-----
drivers/gpu/drm/i915/i915_vma.h | 5 +++--
drivers/gpu/drm/i915/i915_vma_types.h | 3 ++-
4 files changed, 36 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 07133f0c529e..282ed6dd3ca2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -256,8 +256,12 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
gte = (gen8_pte_t __iomem *)ggtt->gsm;
gte += vma->node.start / I915_GTT_PAGE_SIZE;
- end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
+ end = gte + vma->guard / I915_GTT_PAGE_SIZE;
+ while (gte < end)
+ gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+ end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, iter, vma->pages)
gen8_set_pte(gte++, pte_encode | addr);
GEM_BUG_ON(gte > end);
@@ -307,8 +311,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
gte = (gen6_pte_t __iomem *)ggtt->gsm;
gte += vma->node.start / I915_GTT_PAGE_SIZE;
- end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
+ end = gte + vma->guard / I915_GTT_PAGE_SIZE;
+ while (gte < end)
+ gen8_set_pte(gte++, vm->scratch[0]->encode);
+
+ end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, iter, vma->pages)
iowrite32(vm->pte_encode(addr, level, flags), gte++);
GEM_BUG_ON(gte > end);
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 10473ce8a047..080ffa583edf 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -658,7 +658,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color)
static int
i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
- unsigned long color;
+ unsigned long color, guard;
u64 start, end;
int ret;
@@ -666,7 +666,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
size = max(size, vma->size);
- alignment = max(alignment, vma->display_alignment);
+ alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
if (flags & PIN_MAPPABLE) {
size = max_t(typeof(size), size, vma->fence_size);
alignment = max_t(typeof(alignment),
@@ -677,6 +677,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
GEM_BUG_ON(!is_power_of_2(alignment));
+ guard = vma->guard; /* retain guard across rebinds */
+ guard = ALIGN(guard, alignment);
+
start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
@@ -686,12 +689,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
if (flags & PIN_ZONE_4G)
end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);
GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
+ GEM_BUG_ON(2 * guard > end);
/* If binding the object/GGTT view requires more space than the entire
* aperture has, reject it early before evicting everything in a vain
* attempt to find space.
*/
- if (size > end) {
+ if (size > end - 2 * guard) {
DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu > %s aperture=%llu\n",
size, flags & PIN_MAPPABLE ? "mappable" : "total",
end);
@@ -707,13 +711,24 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
if (!IS_ALIGNED(offset, alignment) ||
range_overflows(offset, size, end))
return -EINVAL;
+ /*
+ * The caller knows not of the guard added by others and
+ * requests for the offset of the start of its buffer
+ * to be fixed, which may not be the same as the position
+ * of the vma->node due to the guard pages.
+ */
+ if (offset < guard || offset + size > end - guard)
+ return -ENOSPC;
+
ret = i915_gem_gtt_reserve(vma->vm, &vma->node,
- size, offset, color,
- flags);
+ size + 2 * guard,
+ offset - guard,
+ color, flags);
if (ret)
return ret;
} else {
+ size += 2 * guard;
/*
* We only support huge gtt pages through the 48b PPGTT,
* however we also don't want to force any alignment for
@@ -760,6 +775,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, color));
list_add_tail(&vma->vm_link, &vma->vm->bound_list);
+ vma->guard = guard;
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 1d13d619ff86..d35ce4e7170c 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -128,12 +128,13 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
static inline u64 i915_vma_size(const struct i915_vma *vma)
{
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
- return vma->node.size;
+ return vma->node.size - 2 * vma->guard;
}
static inline u64 __i915_vma_offset(const struct i915_vma *vma)
{
- return vma->node.start;
+ /* The actual start of the vma->pages is after the guard pages. */
+ return vma->node.start + vma->guard;
}
static inline u64 i915_vma_offset(const struct i915_vma *vma)
diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h
index f03fa96a1701..a224daf1044e 100644
--- a/drivers/gpu/drm/i915/i915_vma_types.h
+++ b/drivers/gpu/drm/i915/i915_vma_types.h
@@ -195,14 +195,15 @@ struct i915_vma {
struct i915_fence_reg *fence;
u64 size;
- u64 display_alignment;
struct i915_page_sizes page_sizes;
/* mmap-offset associated with fencing for this vma */
struct i915_mmap_offset *mmo;
+ u32 guard; /* padding allocated around vma->pages within the node */
u32 fence_size;
u32 fence_alignment;
+ u32 display_alignment;
/**
* Count of the number of times this vma has been opened by different
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH V2 3/3] drm/i915: Refine VT-d scanout workaround
2021-12-02 9:24 [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Tejas Upadhyay
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Tejas Upadhyay
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 2/3] drm/i915: Introduce guard pages to i915_vma Tejas Upadhyay
@ 2021-12-02 9:24 ` Tejas Upadhyay
2021-12-03 11:05 ` Ramalingam C
2021-12-02 9:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Replace VT-d workaround with guard pages (rev2) Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Tejas Upadhyay @ 2021-12-02 9:24 UTC (permalink / raw)
To: intel-gfx
From: Chris Wilson <chris@chris-wilson.co.uk>
VT-d may cause overfetch of the scanout PTE, both before and after the
vma (depending on the scanout orientation). bspec recommends that we
provide a tile-row in either directions, and suggests using 168 PTE,
warning that the accesses will wrap around the ends of the GGTT.
Currently, we fill the entire GGTT with scratch pages when using VT-d to
always ensure there are valid entries around every vma, including
scanout. However, writing every PTE is slow as on recent devices we
perform 8MiB of uncached writes, incurring an extra 100ms during resume.
If instead we focus on only putting guard pages around scanout, we can
avoid touching the whole GGTT. To avoid having to introduce extra nodes
around each scanout vma, we adjust the scanout drm_mm_node to be smaller
than the allocated space, and fixup the extra PTE during dma binding.
v2: Move the guard from modifying drm_mm_node.start which is still used
by the drm_mm itself, into an adjustment of node.start at the point of
use.
v3: Pass the requested guard padding from the caller, so we can drop the
VT-d w/a knowledge from the i915_vma allocator.
v4: Bump minimum padding to 168 PTE and cautiously ensure that a full
tile row around the vma is included with the guard.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++++++++++
drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +---------------------
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/i915_vma.c | 8 +++++++
4 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 26532c07d467..03876af45c8b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -16,6 +16,8 @@
#include "i915_gem_lmem.h"
#include "i915_gem_mman.h"
+#define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */
+
static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
@@ -423,6 +425,17 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
if (ret)
return ERR_PTR(ret);
+ /* VT-d may overfetch before/after the vma, so pad with scratch */
+ if (intel_scanout_needs_vtd_wa(i915)) {
+ unsigned int guard = VTD_GUARD;
+
+ if (i915_gem_object_is_tiled(obj))
+ guard = max(guard,
+ i915_gem_object_get_tile_row_size(obj));
+
+ flags |= PIN_OFFSET_GUARD | guard;
+ }
+
/*
* As the user may map the buffer once pinned in the display plane
* (e.g. libkms for the bootup splash), we have to ensure that we
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 282ed6dd3ca2..4a0f916ab03f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -337,27 +337,6 @@ static void nop_clear_range(struct i915_address_space *vm,
{
}
-static void gen8_ggtt_clear_range(struct i915_address_space *vm,
- u64 start, u64 length)
-{
- struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
- unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
- unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
- const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
- gen8_pte_t __iomem *gtt_base =
- (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
- const int max_entries = ggtt_total_entries(ggtt) - first_entry;
- int i;
-
- if (WARN(num_entries > max_entries,
- "First entry = %d; Num entries = %d (max=%d)\n",
- first_entry, num_entries, max_entries))
- num_entries = max_entries;
-
- for (i = 0; i < num_entries; i++)
- gen8_set_pte(>t_base[i], scratch_pte);
-}
-
static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
{
/*
@@ -956,8 +935,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.cleanup = gen6_gmch_remove;
ggtt->vm.insert_page = gen8_ggtt_insert_page;
ggtt->vm.clear_range = nop_clear_range;
- if (intel_scanout_needs_vtd_wa(i915))
- ggtt->vm.clear_range = gen8_ggtt_clear_range;
ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
@@ -1105,7 +1082,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
ggtt->vm.clear_range = nop_clear_range;
- if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
+ if (!HAS_FULL_PPGTT(i915))
ggtt->vm.clear_range = gen6_ggtt_clear_range;
ggtt->vm.insert_page = gen6_ggtt_insert_page;
ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c9b0ee5e1d23..f3ae9afdee15 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -41,6 +41,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
#define PIN_HIGH BIT_ULL(5)
#define PIN_OFFSET_BIAS BIT_ULL(6)
#define PIN_OFFSET_FIXED BIT_ULL(7)
+#define PIN_OFFSET_GUARD BIT_ULL(8)
#define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
#define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 080ffa583edf..d92a9f938c68 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -587,6 +587,9 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
return true;
+ if (flags & PIN_OFFSET_GUARD && vma->guard < (flags & PIN_OFFSET_MASK))
+ return true;
+
return false;
}
@@ -664,6 +667,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND));
GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
+ GEM_BUG_ON(hweight64(flags & (PIN_OFFSET_GUARD | PIN_OFFSET_FIXED | PIN_OFFSET_BIAS)) > 1);
size = max(size, vma->size);
alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
@@ -678,6 +682,10 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(!is_power_of_2(alignment));
guard = vma->guard; /* retain guard across rebinds */
+ if (flags & PIN_OFFSET_GUARD) {
+ GEM_BUG_ON(overflows_type(flags & PIN_OFFSET_MASK, u32));
+ guard = max_t(u32, guard, flags & PIN_OFFSET_MASK);
+ }
guard = ALIGN(guard, alignment);
start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Replace VT-d workaround with guard pages (rev2)
2021-12-02 9:24 [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Tejas Upadhyay
` (2 preceding siblings ...)
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 3/3] drm/i915: Refine VT-d scanout workaround Tejas Upadhyay
@ 2021-12-02 9:39 ` Patchwork
2021-12-02 10:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2021-12-02 9:39 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
== Series Details ==
Series: Replace VT-d workaround with guard pages (rev2)
URL : https://patchwork.freedesktop.org/series/97492/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Replace VT-d workaround with guard pages (rev2)
2021-12-02 9:24 [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Tejas Upadhyay
` (3 preceding siblings ...)
2021-12-02 9:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Replace VT-d workaround with guard pages (rev2) Patchwork
@ 2021-12-02 10:07 ` Patchwork
2021-12-02 11:43 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-12-03 11:11 ` [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Ramalingam C
6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2021-12-02 10:07 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5589 bytes --]
== Series Details ==
Series: Replace VT-d workaround with guard pages (rev2)
URL : https://patchwork.freedesktop.org/series/97492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10953 -> Patchwork_21727
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/index.html
Participating hosts (38 -> 32)
------------------------------
Additional (1): fi-bdw-gvtdvm
Missing (7): fi-tgl-dsi bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-jsl-2 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_21727 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@write:
- fi-bdw-gvtdvm: NOTRUN -> [SKIP][1] ([fdo#109271]) +5 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-bdw-gvtdvm/igt@fbdev@write.html
* igt@gem_exec_suspend@basic-s0:
- fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][2] ([i915#146] / [i915#2539])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-bdw-gvtdvm/igt@gem_exec_suspend@basic-s0.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html
* igt@i915_selftest@live:
- fi-skl-6600u: NOTRUN -> [INCOMPLETE][5] ([i915#198])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@i915_selftest@live.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1:
- fi-blb-e6850: [PASS][8] -> [FAIL][9] ([i915#2122])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-blb-e6850/igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-blb-e6850/igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#533])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4: [FAIL][11] ([i915#1888]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: [INCOMPLETE][13] ([i915#4547]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][15] ([i915#4269]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_10953 -> Patchwork_21727
CI-20190529: 20190529
CI_DRM_10953: 494fe33df24acee4952c6ea1c946320aac86b7ba @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6298: f062f4ae60ecf47af4b037c8f9952a1360662579 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21727: 09a8cc42ebd136f3ad6c1ed9ccdc2ce3d4be60d5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
09a8cc42ebd1 drm/i915: Refine VT-d scanout workaround
d1611e08ea88 drm/i915: Introduce guard pages to i915_vma
af97001166c8 drm/i915: Wrap all access to i915_vma.node.start|size
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/index.html
[-- Attachment #2: Type: text/html, Size: 6833 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Replace VT-d workaround with guard pages (rev2)
2021-12-02 9:24 [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Tejas Upadhyay
` (4 preceding siblings ...)
2021-12-02 10:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-12-02 11:43 ` Patchwork
2021-12-03 11:11 ` [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Ramalingam C
6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2021-12-02 11:43 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30270 bytes --]
== Series Details ==
Series: Replace VT-d workaround with guard pages (rev2)
URL : https://patchwork.freedesktop.org/series/97492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10953_full -> Patchwork_21727_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_21727_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [FAIL][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4386])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl2/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl1/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl1/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl1/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl2/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl2/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl8/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl8/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl8/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl7/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl7/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl6/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl6/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl6/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl4/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl7/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl7/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl7/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl6/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl6/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl6/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl3/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl3/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl3/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl3/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl2/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl2/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl2/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl1/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl1/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl1/boot.html
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [FAIL][72], [PASS][73], [PASS][74], [PASS][75]) ([i915#4392]) -> ([PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk9/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk9/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk8/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk8/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk7/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk7/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk7/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk7/boot.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk6/boot.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk6/boot.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk6/boot.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk5/boot.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk5/boot.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk5/boot.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk4/boot.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk4/boot.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk3/boot.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk3/boot.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk2/boot.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk2/boot.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk2/boot.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk2/boot.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk1/boot.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk1/boot.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk1/boot.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk2/boot.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk2/boot.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk3/boot.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk3/boot.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk4/boot.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk4/boot.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk4/boot.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk5/boot.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk2/boot.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk1/boot.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk1/boot.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk5/boot.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk5/boot.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk5/boot.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk6/boot.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk6/boot.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk7/boot.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk7/boot.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk7/boot.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk8/boot.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk8/boot.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk8/boot.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk9/boot.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk9/boot.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk9/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: NOTRUN -> [SKIP][101] ([i915#4525])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb4/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][102] ([i915#2846])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][103] -> [FAIL][104] ([i915#2842]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][105] -> [FAIL][106] ([i915#2842])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [PASS][107] -> [FAIL][108] ([i915#2842])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl6/igt@gem_exec_fair@basic-none@vecs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-tglb: [PASS][109] -> [FAIL][110] ([i915#2842]) +2 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-tglb3/igt@gem_exec_fair@basic-pace@vecs0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-tglb8/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][111] -> [FAIL][112] ([i915#2842])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-iclb: NOTRUN -> [SKIP][113] ([fdo#109283])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb4/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-glk: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#4613]) +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk3/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-apl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#4613]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@random:
- shard-tglb: NOTRUN -> [SKIP][116] ([i915#4613])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-tglb6/igt@gem_lmem_swapping@random.html
- shard-kbl: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#4613]) +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-kbl2/igt@gem_lmem_swapping@random.html
- shard-skl: NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#4613])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-skl5/igt@gem_lmem_swapping@random.html
- shard-iclb: NOTRUN -> [SKIP][119] ([i915#4613])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb6/igt@gem_lmem_swapping@random.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> [WARN][120] ([i915#2658])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk4/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@create-regular-context-2:
- shard-iclb: NOTRUN -> [SKIP][121] ([i915#4270])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb4/igt@gem_pxp@create-regular-context-2.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][122] ([fdo#109271]) +108 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-kbl2/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][123] ([i915#3318])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-iclb: NOTRUN -> [SKIP][124] ([fdo#109289]) +1 similar issue
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb6/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@bb-large:
- shard-apl: [PASS][125] -> [TIMEOUT][126] ([i915#4639])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl3/igt@gen9_exec_parse@bb-large.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl7/igt@gen9_exec_parse@bb-large.html
* igt@i915_module_load@reload-no-display:
- shard-tglb: [PASS][127] -> [DMESG-WARN][128] ([i915#2867])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-tglb1/igt@i915_module_load@reload-no-display.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-tglb3/igt@i915_module_load@reload-no-display.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][129] -> [FAIL][130] ([i915#454])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][131] ([fdo#110892])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb4/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_selftest@live@gt_pm:
- shard-glk: NOTRUN -> [DMESG-FAIL][132] ([i915#3987])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk4/igt@i915_selftest@live@gt_pm.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][133] ([fdo#109271] / [i915#3777]) +2 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-kbl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][134] ([fdo#109271] / [i915#3886]) +3 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk3/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
- shard-apl: NOTRUN -> [SKIP][135] ([fdo#109271] / [i915#3886])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][136] ([fdo#109278] / [i915#3886])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb6/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][137] ([fdo#109271] / [i915#3886]) +7 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-kbl3/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-crc-single:
- shard-glk: NOTRUN -> [SKIP][138] ([fdo#109271] / [fdo#111827]) +3 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk3/igt@kms_chamelium@hdmi-crc-single.html
* igt@kms_chamelium@hdmi-hpd-fast:
- shard-skl: NOTRUN -> [SKIP][139] ([fdo#109271] / [fdo#111827]) +1 similar issue
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-skl5/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][140] ([fdo#109271] / [fdo#111827]) +12 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-kbl2/igt@kms_chamelium@hdmi-hpd-storm.html
- shard-tglb: NOTRUN -> [SKIP][141] ([fdo#109284] / [fdo#111827]) +2 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-tglb6/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-iclb: NOTRUN -> [SKIP][142] ([fdo#109284] / [fdo#111827]) +4 similar issues
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb6/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_chamelium@vga-edid-read:
- shard-apl: NOTRUN -> [SKIP][143] ([fdo#109271] / [fdo#111827]) +6 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/igt@kms_chamelium@vga-edid-read.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][144] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb4/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_content_protection@lic:
- shard-iclb: NOTRUN -> [SKIP][145] ([fdo#109300] / [fdo#111066])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb6/igt@kms_content_protection@lic.html
- shard-tglb: NOTRUN -> [SKIP][146] ([fdo#111828])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-tglb6/igt@kms_content_protection@lic.html
- shard-kbl: NOTRUN -> [TIMEOUT][147] ([i915#1319])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-kbl2/igt@kms_content_protection@lic.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][148] ([i915#1319])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen:
- shard-apl: NOTRUN -> [SKIP][149] ([fdo#109271]) +70 similar issues
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][150] ([i915#180])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-iclb: NOTRUN -> [SKIP][151] ([fdo#109274] / [fdo#109278])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-tglb: [PASS][152] -> [FAIL][153] ([i915#2346])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-skl: [PASS][154] -> [FAIL][155] ([i915#2346]) +1 similar issue
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-glk: NOTRUN -> [SKIP][156] ([fdo#109271] / [i915#533]) +1 similar issue
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk4/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: NOTRUN -> [INCOMPLETE][157] ([i915#180] / [i915#1982])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-modeset:
- shard-iclb: NOTRUN -> [SKIP][158] ([fdo#109274])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb4/igt@kms_flip@2x-flip-vs-modeset.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][159] -> [FAIL][160] ([i915#2122])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][161] -> [DMESG-WARN][162] ([i915#180]) +5 similar issues
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][163] ([fdo#109271] / [i915#2672]) +1 similar issue
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][164] ([fdo#109271]) +1 similar issue
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-skl6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-glk: NOTRUN -> [SKIP][165] ([fdo#109271]) +54 similar issues
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][166] ([fdo#109280]) +4 similar issues
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][167] -> [FAIL][168] ([i915#1188])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-skl6/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: [PASS][169] -> [DMESG-WARN][170] ([i915#180]) +1 similar issue
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-apl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][171] ([fdo#108145] / [i915#265])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk3/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-glk: NOTRUN -> [FAIL][172] ([i915#265])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk4/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][173] ([fdo#108145] / [i915#265])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][174] ([fdo#108145] / [i915#265])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
- shard-iclb: NOTRUN -> [SKIP][175] ([fdo#109278]) +6 similar issues
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb4/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][176] ([fdo#109271] / [i915#658]) +1 similar issue
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-kbl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][177] ([fdo#109271] / [i915#658])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl4/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: NOTRUN -> [SKIP][178] ([fdo#109441])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][179] -> [SKIP][180] ([fdo#109441]) +1 similar issue
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-iclb2/igt@kms_psr@psr2_suspend.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb1/igt@kms_psr@psr2_suspend.html
* igt@kms_selftest@all@check_plane_state:
- shard-kbl: NOTRUN -> [INCOMPLETE][181] ([i915#4663])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-kbl7/igt@kms_selftest@all@check_plane_state.html
* igt@kms_setmode@basic:
- shard-glk: [PASS][182] -> [FAIL][183] ([i915#31])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-glk1/igt@kms_setmode@basic.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-glk2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][184] -> [DMESG-WARN][185] ([i915#180] / [i915#295])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][186] ([fdo#109271] / [i915#533])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-apl8/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-iclb: NOTRUN -> [SKIP][187] ([i915#2437])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-iclb4/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@polling-parameterized:
- shard-tglb: [PASS][188] -> [FAIL][189] ([i915#1542])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/shard-tglb5/igt@perf@polling-parameterized.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/shard-tglb6/igt@perf@polling-parameterized.html
* igt@perf@short-reads:
- shard-skl: [PASS][190] -> [FAIL][191] ([i915#51])
[190]: https://intel-gfx-ci
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21727/index.html
[-- Attachment #2: Type: text/html, Size: 33058 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH V2 1/3] drm/i915: Wrap all access to i915_vma.node.start|size
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Tejas Upadhyay
@ 2021-12-03 10:14 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2021-12-03 10:14 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
On 2021-12-02 at 14:54:22 +0530, Tejas Upadhyay wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> We already wrap i915_vma.node.start for use with the GGTT, as there we
> can perform additional sanity checks that the node belongs to the GGTT
> and fits within the 32b registers. In the next couple of patches, we
> will introduce guard pages around the objects _inside_ the drm_mm_node
> allocation. That is we will offset the vma->pages so that the first page
> is at drm_mm_node.start + vma->guard (not 0 as is currently the case).
> All users must then not use i915_vma.node.start directly, but compute
> the guard offset, thus all users are converted to use a
> i915_vma_offset() wrapper.
>
> The notable exceptions are the selftests that are testing exact
> behaviour of i915_vma_pin/i915_vma_insert.
There is not change log for v2.
Apart from that Looks good to me.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpt.c | 4 +--
> drivers/gpu/drm/i915/display/intel_fbdev.c | 6 ++--
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 34 ++++++++++---------
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 +--
> .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
> .../i915/gem/selftests/i915_gem_client_blt.c | 15 ++++----
> .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++++++----
> .../drm/i915/gem/selftests/i915_gem_mman.c | 2 +-
> .../drm/i915/gem/selftests/igt_gem_utils.c | 6 ++--
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 8 ++---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 5 +--
> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 5 +--
> drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 8 ++---
> drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 +++++-----
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 ++++----
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 16 ++++-----
> .../drm/i915/gt/selftest_ring_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_rps.c | 12 +++----
> .../gpu/drm/i915/gt/selftest_workarounds.c | 8 ++---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +--
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/i915_vma.c | 21 ++++++------
> drivers/gpu/drm/i915/i915_vma.h | 23 +++++++++++--
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 ++++++-
> drivers/gpu/drm/i915/selftests/i915_request.c | 20 +++++------
> drivers/gpu/drm/i915/selftests/igt_spinner.c | 8 ++---
> 34 files changed, 169 insertions(+), 127 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c
> index 963ca7155b06..1bb99ef4ce2d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c
> @@ -64,7 +64,7 @@ static void dpt_insert_entries(struct i915_address_space *vm,
> * not to allow the user to override access to a read only page.
> */
>
> - i = vma->node.start / I915_GTT_PAGE_SIZE;
> + i = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
> for_each_sgt_daddr(addr, sgt_iter, vma->pages)
> gen8_set_pte(&base[i++], pte_encode | addr);
> }
> @@ -104,7 +104,7 @@ static void dpt_bind_vma(struct i915_address_space *vm,
>
> static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
> {
> - vm->clear_range(vm, vma->node.start, vma->size);
> + vm->clear_range(vm, i915_vma_offset(vma), vma->size);
> }
>
> static void dpt_cleanup(struct i915_address_space *vm)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
> index adc3a81be9f7..0583dcd538ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
> @@ -261,8 +261,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
>
> /* Our framebuffer is the entirety of fbdev's system memory */
> info->fix.smem_start =
> - (unsigned long)(ggtt->gmadr.start + vma->node.start);
> - info->fix.smem_len = vma->node.size;
> + (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma));
> + info->fix.smem_len = vma->size;
> }
>
> vaddr = i915_vma_pin_iomap(vma);
> @@ -273,7 +273,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
> goto out_unpin;
> }
> info->screen_base = vaddr;
> - info->screen_size = vma->node.size;
> + info->screen_size = vma->size;
>
> drm_fb_helper_fill_info(info, &ifbdev->helper, sizes);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 6a0ed537c199..d024b88da608 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -376,22 +376,24 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
> const struct i915_vma *vma,
> unsigned int flags)
> {
> - if (vma->node.size < entry->pad_to_size)
> + const u64 start = i915_vma_offset(vma);
> + const u64 size = i915_vma_size(vma);
> +
> + if (size < entry->pad_to_size)
> return true;
>
> - if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
> + if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
> return true;
>
> - if (flags & EXEC_OBJECT_PINNED &&
> - vma->node.start != entry->offset)
> + if (flags & EXEC_OBJECT_PINNED && start != entry->offset)
> return true;
>
> if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
> - vma->node.start < BATCH_OFFSET_BIAS)
> + start < BATCH_OFFSET_BIAS)
> return true;
>
> if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
> - (vma->node.start + vma->node.size + 4095) >> 32)
> + (start + size + 4095) >> 32)
> return true;
>
> if (flags & __EXEC_OBJECT_NEEDS_MAP &&
> @@ -437,7 +439,7 @@ eb_pin_vma(struct i915_execbuffer *eb,
> int err;
>
> if (vma->node.size)
> - pin_flags = vma->node.start;
> + pin_flags = __i915_vma_offset(vma);
> else
> pin_flags = entry->offset & PIN_OFFSET_MASK;
>
> @@ -677,8 +679,8 @@ static int eb_reserve_vma(struct i915_execbuffer *eb,
> if (err)
> return err;
>
> - if (entry->offset != vma->node.start) {
> - entry->offset = vma->node.start | UPDATE;
> + if (entry->offset != i915_vma_offset(vma)) {
> + entry->offset = i915_vma_offset(vma) | UPDATE;
> eb->args->flags |= __EXEC_HAS_RELOC;
> }
>
> @@ -990,8 +992,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb)
> return err;
>
> if (!err) {
> - if (entry->offset != vma->node.start) {
> - entry->offset = vma->node.start | UPDATE;
> + if (entry->offset != i915_vma_offset(vma)) {
> + entry->offset = i915_vma_offset(vma) | UPDATE;
> eb->args->flags |= __EXEC_HAS_RELOC;
> }
> } else {
> @@ -1073,7 +1075,7 @@ static inline u64
> relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
> const struct i915_vma *target)
> {
> - return gen8_canonical_addr((int)reloc->delta + target->node.start);
> + return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target));
> }
>
> static void reloc_cache_init(struct reloc_cache *cache,
> @@ -1229,7 +1231,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
> if (err) /* no inactive aperture space, use cpu reloc */
> return NULL;
> } else {
> - cache->node.start = vma->node.start;
> + cache->node.start = i915_ggtt_offset(vma);
> cache->node.mm = (void *)vma;
> }
> }
> @@ -1387,7 +1389,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
> * more work needs to be done.
> */
> if (!DBG_FORCE_RELOC &&
> - gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
> + gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset)
> return 0;
>
> /* Check that the relocation address is valid... */
> @@ -2331,7 +2333,7 @@ static int eb_request_submit(struct i915_execbuffer *eb,
> }
>
> err = rq->context->engine->emit_bb_start(rq,
> - batch->node.start +
> + i915_vma_offset(batch) +
> eb->batch_start_offset,
> batch_len,
> eb->batch_flags);
> @@ -2342,7 +2344,7 @@ static int eb_request_submit(struct i915_execbuffer *eb,
> GEM_BUG_ON(intel_context_is_parallel(rq->context));
> GEM_BUG_ON(eb->batch_start_offset);
> err = rq->context->engine->emit_bb_start(rq,
> - eb->trampoline->node.start +
> + i915_vma_offset(eb->trampoline) +
> batch_len, 0, 0);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index 65fc6ff5f59d..5d3fa137389e 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -378,7 +378,7 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
> /* Finally, remap it using the new GTT offset */
> ret = remap_io_mapping(area,
> area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
> - (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT,
> + (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
> min_t(u64, vma->size, area->vm_end - area->vm_start),
> &ggtt->iomap);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> index 157a9765f483..7738e97d43b0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> @@ -406,7 +406,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
> mutex_lock(&i915->ggtt.vm.mutex);
> list_for_each_entry_safe(vma, next,
> &i915->ggtt.vm.bound_list, vm_link) {
> - unsigned long count = vma->node.size >> PAGE_SHIFT;
> + unsigned long count = i915_vma_size(vma) >> PAGE_SHIFT;
>
> if (!vma->iomap || i915_vma_is_active(vma))
> continue;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> index ef4d0f7dc118..1e49c7c69d80 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> @@ -166,11 +166,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma,
> return true;
>
> size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
> - if (vma->node.size < size)
> + if (i915_vma_size(vma) < size)
> return false;
>
> alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
> - if (!IS_ALIGNED(vma->node.start, alignment))
> + if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment))
> return false;
>
> return true;
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index c69c7d45aabc..c9361ffeb5d4 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> @@ -401,7 +401,7 @@ static int igt_check_page_sizes(struct i915_vma *vma)
> * Maintaining alignment is required to utilise huge pages in the ppGGT.
> */
> if (i915_gem_object_is_lmem(obj) &&
> - IS_ALIGNED(vma->node.start, SZ_2M) &&
> + IS_ALIGNED(i915_vma_offset(vma), SZ_2M) &&
> vma->page_sizes.sg & SZ_2M &&
> vma->page_sizes.gtt < SZ_2M) {
> pr_err("gtt pages mismatch for LMEM, expected 2M GTT pages, sg(%u), gtt(%u)\n",
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> index 8402ed925a69..d383b9f53a77 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> @@ -94,14 +94,14 @@ static int prepare_blit(const struct tiled_blits *t,
> *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
> *cs++ = 0;
> *cs++ = t->height << 16 | t->width;
> - *cs++ = lower_32_bits(dst->vma->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(dst->vma));
> if (use_64b_reloc)
> - *cs++ = upper_32_bits(dst->vma->node.start);
> + *cs++ = upper_32_bits(i915_vma_offset(dst->vma));
> *cs++ = 0;
> *cs++ = src_pitch;
> - *cs++ = lower_32_bits(src->vma->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(src->vma));
> if (use_64b_reloc)
> - *cs++ = upper_32_bits(src->vma->node.start);
> + *cs++ = upper_32_bits(i915_vma_offset(src->vma));
>
> *cs++ = MI_BATCH_BUFFER_END;
>
> @@ -317,7 +317,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
> {
> int err;
>
> - if (drm_mm_node_allocated(&vma->node) && vma->node.start != addr) {
> + if (drm_mm_node_allocated(&vma->node) && i915_vma_offset(vma) != addr) {
> err = i915_vma_unbind(vma);
> if (err)
> return err;
> @@ -327,6 +327,7 @@ static int pin_buffer(struct i915_vma *vma, u64 addr)
> if (err)
> return err;
>
> + GEM_BUG_ON(i915_vma_offset(vma) != addr);
> return 0;
> }
>
> @@ -373,8 +374,8 @@ tiled_blit(struct tiled_blits *t,
> err = move_to_active(dst->vma, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - t->batch->node.start,
> - t->batch->node.size,
> + i915_vma_offset(t->batch),
> + i915_vma_size(t->batch),
> 0);
> i915_request_get(rq);
> i915_request_add(rq);
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index b32f7fed2d9c..fe01a7d92362 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -895,8 +895,8 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
>
> *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
> *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
> - *cmd++ = lower_32_bits(vma->node.start);
> - *cmd++ = upper_32_bits(vma->node.start);
> + *cmd++ = lower_32_bits(i915_vma_offset(vma));
> + *cmd++ = upper_32_bits(i915_vma_offset(vma));
> *cmd = MI_BATCH_BUFFER_END;
>
> __i915_gem_object_flush_map(rpcs, 0, 64);
> @@ -984,7 +984,8 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
> }
>
> err = rq->engine->emit_bb_start(rq,
> - batch->node.start, batch->node.size,
> + i915_vma_offset(batch),
> + i915_vma_size(batch),
> 0);
> if (err)
> goto skip_request;
> @@ -1553,7 +1554,10 @@ static int write_to_scratch(struct i915_gem_context *ctx,
> goto skip_request;
> }
>
> - err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
> + err = engine->emit_bb_start(rq,
> + i915_vma_offset(vma),
> + i915_vma_size(vma),
> + 0);
> if (err)
> goto skip_request;
>
> @@ -1660,7 +1664,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
> *cmd++ = offset;
> *cmd++ = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> *cmd++ = reg;
> - *cmd++ = vma->node.start + result;
> + *cmd++ = i915_vma_offset(vma) + result;
> *cmd = MI_BATCH_BUFFER_END;
>
> i915_gem_object_flush_map(obj);
> @@ -1691,7 +1695,10 @@ static int read_from_scratch(struct i915_gem_context *ctx,
> goto skip_request;
> }
>
> - err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, flags);
> + err = engine->emit_bb_start(rq,
> + i915_vma_offset(vma),
> + i915_vma_size(vma),
> + flags);
> if (err)
> goto skip_request;
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> index 6d30cdfa80f3..762881791e25 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> @@ -1196,7 +1196,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
> if (err == 0)
> err = i915_vma_move_to_active(vma, rq, 0);
>
> - err = engine->emit_bb_start(rq, vma->node.start, 0, 0);
> + err = engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0);
> i915_request_get(rq);
> i915_request_add(rq);
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
> index b35c1219c852..4390d69bd746 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
> @@ -61,8 +61,8 @@ igt_emit_store_dw(struct i915_vma *vma,
> goto err;
> }
>
> - GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > vma->node.size);
> - offset += vma->node.start;
> + GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > i915_vma_size(vma));
> + offset += i915_vma_offset(vma);
>
> for (n = 0; n < count; n++) {
> if (ver >= 8) {
> @@ -150,7 +150,7 @@ int igt_gpu_fill_dw(struct intel_context *ce,
> flags |= I915_DISPATCH_SECURE;
>
> err = rq->engine->emit_bb_start(rq,
> - batch->node.start, batch->node.size,
> + i915_vma_offset(batch), i915_vma_size(batch),
> flags);
>
> skip_request:
> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> index 4a166d25fe60..72a8725e6f8a 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> @@ -110,7 +110,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
> {
> struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> struct i915_page_directory * const pd = ppgtt->pd;
> - unsigned int first_entry = vma->node.start / I915_GTT_PAGE_SIZE;
> + unsigned int first_entry = i915_vma_offset(vma) / I915_GTT_PAGE_SIZE;
> unsigned int act_pt = first_entry / GEN6_PTES;
> unsigned int act_pte = first_entry % GEN6_PTES;
> const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> index 21f08e53889c..a14f962aaa85 100644
> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> @@ -105,7 +105,7 @@ static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)
>
> static u32 batch_addr(const struct batch_chunk *bc)
> {
> - return bc->vma->node.start;
> + return i915_vma_offset(bc->vma);
> }
>
> static void batch_add(struct batch_chunk *bc, const u32 d)
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 9966e9dc5218..dd2ab23a123c 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -460,7 +460,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
> {
> const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
> unsigned int rem = sg_dma_len(iter->sg);
> - u64 start = vma->node.start;
> + u64 start = i915_vma_offset(vma);
>
> GEM_BUG_ON(!i915_vm_is_4lvl(vma->vm));
>
> @@ -542,8 +542,8 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
> if (maybe_64K != -1 &&
> (index == I915_PDES ||
> (i915_vm_has_scratch_64K(vma->vm) &&
> - !iter->sg && IS_ALIGNED(vma->node.start +
> - vma->node.size,
> + !iter->sg && IS_ALIGNED(i915_vma_offset(vma) +
> + i915_vma_size(vma),
> I915_GTT_PAGE_SIZE_2M)))) {
> vaddr = px_vaddr(pd);
> vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
> @@ -587,7 +587,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
> if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
> gen8_ppgtt_insert_huge(vma, &iter, cache_level, flags);
> } else {
> - u64 idx = vma->node.start >> GEN8_PTE_SHIFT;
> + u64 idx = i915_vma_offset(vma) >> GEN8_PTE_SHIFT;
>
> do {
> struct i915_page_directory * const pdp =
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 110d3944f9a2..07133f0c529e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -458,7 +458,8 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
> unsigned int flags = (cache_level == I915_CACHE_NONE) ?
> AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
>
> - intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
> + intel_gtt_insert_sg_entries(vma->pages,
> + i915_ggtt_offset(vma) >> PAGE_SHIFT,
> flags);
> }
>
> @@ -649,7 +650,7 @@ static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
> struct i915_vma *vma)
> {
> if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
> - vm->clear_range(vm, vma->node.start, vma->size);
> + vm->clear_range(vm, i915_ggtt_offset(vma), vma->size);
>
> if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND))
> ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index f8948de72036..b6fea674e6a5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -215,7 +215,8 @@ static int fence_update(struct i915_fence_reg *fence,
> return ret;
> }
>
> - fence->start = vma->node.start;
> + GEM_BUG_ON(vma->fence_size > i915_vma_size(vma));
> + fence->start = i915_ggtt_offset(vma);
> fence->size = vma->fence_size;
> fence->stride = i915_gem_object_get_stride(vma->obj);
> fence->tiling = i915_gem_object_get_tiling(vma->obj);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index 4396bfd630d8..4773c95db012 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -186,7 +186,8 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
> u32 pte_flags;
>
> if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) {
> - vm->allocate_va_range(vm, stash, vma->node.start, vma->size);
> + GEM_BUG_ON(vma->size > i915_vma_size(vma));
> + vm->allocate_va_range(vm, stash, i915_vma_offset(vma), vma->size);
> set_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma));
> }
>
> @@ -204,7 +205,7 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
> void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
> {
> if (test_and_clear_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma)))
> - vm->clear_range(vm, vma->node.start, vma->size);
> + vm->clear_range(vm, i915_vma_offset(vma), vma->size);
> }
>
> static unsigned long pd_count(u64 size, int shift)
> diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> index b575cd6e0b7a..2630fe6c8142 100644
> --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> @@ -61,7 +61,7 @@ static int render_state_setup(struct intel_renderstate *so,
> u32 s = rodata->batch[i];
>
> if (i * 4 == rodata->reloc[reloc_index]) {
> - u64 r = s + so->vma->node.start;
> + u64 r = s + i915_vma_offset(so->vma);
>
> s = lower_32_bits(r);
> if (HAS_64BIT_RELOC(i915)) {
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 3e6fac0340ef..2c4c5c095c56 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -886,7 +886,7 @@ static int clear_residuals(struct i915_request *rq)
> }
>
> ret = engine->emit_bb_start(rq,
> - engine->wa_ctx.vma->node.start, 0,
> + i915_vma_offset(engine->wa_ctx.vma), 0,
> 0);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> index 64abf5feabfa..9e28873a7e45 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> @@ -165,7 +165,7 @@ static int perf_mi_bb_start(void *arg)
> goto out;
>
> err = rq->engine->emit_bb_start(rq,
> - batch->node.start, 8,
> + i915_vma_offset(batch), 8,
> 0);
> if (err)
> goto out;
> @@ -305,7 +305,7 @@ static int perf_mi_noop(void *arg)
> goto out;
>
> err = rq->engine->emit_bb_start(rq,
> - base->node.start, 8,
> + i915_vma_offset(base), 8,
> 0);
> if (err)
> goto out;
> @@ -315,8 +315,8 @@ static int perf_mi_noop(void *arg)
> goto out;
>
> err = rq->engine->emit_bb_start(rq,
> - nop->node.start,
> - nop->node.size,
> + i915_vma_offset(nop),
> + i915_vma_size(nop),
> 0);
> if (err)
> goto out;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> index b367ecfa42de..b803123df073 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> @@ -2732,11 +2732,11 @@ static int create_gang(struct intel_engine_cs *engine,
> MI_SEMAPHORE_POLL |
> MI_SEMAPHORE_SAD_EQ_SDD;
> *cs++ = 0;
> - *cs++ = lower_32_bits(vma->node.start);
> - *cs++ = upper_32_bits(vma->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(vma));
> + *cs++ = upper_32_bits(i915_vma_offset(vma));
>
> if (*prev) {
> - u64 offset = (*prev)->batch->node.start;
> + u64 offset = i915_vma_offset((*prev)->batch);
>
> /* Terminate the spinner in the next lower priority batch. */
> *cs++ = MI_STORE_DWORD_IMM_GEN4;
> @@ -2764,7 +2764,7 @@ static int create_gang(struct intel_engine_cs *engine,
> err = i915_vma_move_to_active(vma, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - vma->node.start,
> + i915_vma_offset(vma),
> PAGE_SIZE, 0);
> i915_vma_unlock(vma);
> i915_request_add(rq);
> @@ -3092,7 +3092,7 @@ create_gpr_user(struct intel_engine_cs *engine,
> *cs++ = MI_MATH_ADD;
> *cs++ = MI_MATH_STORE(MI_MATH_REG(i), MI_MATH_REG_ACCU);
>
> - addr = result->node.start + offset + i * sizeof(*cs);
> + addr = i915_vma_offset(result) + offset + i * sizeof(*cs);
> *cs++ = MI_STORE_REGISTER_MEM_GEN8;
> *cs++ = CS_GPR(engine, 2 * i);
> *cs++ = lower_32_bits(addr);
> @@ -3102,8 +3102,8 @@ create_gpr_user(struct intel_engine_cs *engine,
> MI_SEMAPHORE_POLL |
> MI_SEMAPHORE_SAD_GTE_SDD;
> *cs++ = i;
> - *cs++ = lower_32_bits(result->node.start);
> - *cs++ = upper_32_bits(result->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(result));
> + *cs++ = upper_32_bits(i915_vma_offset(result));
> }
>
> *cs++ = MI_BATCH_BUFFER_END;
> @@ -3187,7 +3187,7 @@ create_gpr_client(struct intel_engine_cs *engine,
> err = i915_vma_move_to_active(batch, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - batch->node.start,
> + i915_vma_offset(batch),
> PAGE_SIZE, 0);
> i915_vma_unlock(batch);
> i915_vma_unpin(batch);
> @@ -3519,7 +3519,7 @@ static int smoke_submit(struct preempt_smoke *smoke,
> err = i915_vma_move_to_active(vma, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - vma->node.start,
> + i915_vma_offset(vma),
> PAGE_SIZE, 0);
> i915_vma_unlock(vma);
> }
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index e5ad4d5a91c0..b0236c4d615c 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -94,7 +94,8 @@ static int hang_init(struct hang *h, struct intel_gt *gt)
> static u64 hws_address(const struct i915_vma *hws,
> const struct i915_request *rq)
> {
> - return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context);
> + return i915_vma_offset(hws) +
> + offset_in_page(sizeof(u32) * rq->fence.context);
> }
>
> static int move_to_active(struct i915_vma *vma,
> @@ -194,8 +195,8 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>
> *batch++ = MI_NOOP;
> *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
> - *batch++ = lower_32_bits(vma->node.start);
> - *batch++ = upper_32_bits(vma->node.start);
> + *batch++ = lower_32_bits(i915_vma_offset(vma));
> + *batch++ = upper_32_bits(i915_vma_offset(vma));
> } else if (GRAPHICS_VER(gt->i915) >= 6) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = 0;
> @@ -208,7 +209,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>
> *batch++ = MI_NOOP;
> *batch++ = MI_BATCH_BUFFER_START | 1 << 8;
> - *batch++ = lower_32_bits(vma->node.start);
> + *batch++ = lower_32_bits(i915_vma_offset(vma));
> } else if (GRAPHICS_VER(gt->i915) >= 4) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *batch++ = 0;
> @@ -221,7 +222,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>
> *batch++ = MI_NOOP;
> *batch++ = MI_BATCH_BUFFER_START | 2 << 6;
> - *batch++ = lower_32_bits(vma->node.start);
> + *batch++ = lower_32_bits(i915_vma_offset(vma));
> } else {
> *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> *batch++ = lower_32_bits(hws_address(hws, rq));
> @@ -233,7 +234,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>
> *batch++ = MI_NOOP;
> *batch++ = MI_BATCH_BUFFER_START | 2 << 6;
> - *batch++ = lower_32_bits(vma->node.start);
> + *batch++ = lower_32_bits(i915_vma_offset(vma));
> }
> *batch++ = MI_BATCH_BUFFER_END; /* not reached */
> intel_gt_chipset_flush(engine->gt);
> @@ -248,7 +249,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> if (GRAPHICS_VER(gt->i915) <= 5)
> flags |= I915_DISPATCH_SECURE;
>
> - err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
> + err = rq->engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
>
> cancel_rq:
> if (err) {
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index b0977a3b699b..ca2f2dec7089 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -955,8 +955,8 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
> while (len--) {
> *cs++ = MI_STORE_REGISTER_MEM_GEN8;
> *cs++ = hw[dw];
> - *cs++ = lower_32_bits(scratch->node.start + x);
> - *cs++ = upper_32_bits(scratch->node.start + x);
> + *cs++ = lower_32_bits(i915_vma_offset(scratch) + x);
> + *cs++ = upper_32_bits(i915_vma_offset(scratch) + x);
>
> dw += 2;
> x += 4;
> @@ -1038,8 +1038,8 @@ record_registers(struct intel_context *ce,
>
> *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
> - *cs++ = lower_32_bits(b_before->node.start);
> - *cs++ = upper_32_bits(b_before->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(b_before));
> + *cs++ = upper_32_bits(i915_vma_offset(b_before));
>
> *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> *cs++ = MI_SEMAPHORE_WAIT |
> @@ -1054,8 +1054,8 @@ record_registers(struct intel_context *ce,
>
> *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
> - *cs++ = lower_32_bits(b_after->node.start);
> - *cs++ = upper_32_bits(b_after->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(b_after));
> + *cs++ = upper_32_bits(i915_vma_offset(b_after));
>
> intel_ring_advance(rq, cs);
>
> @@ -1163,8 +1163,8 @@ static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)
>
> *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
> - *cs++ = lower_32_bits(batch->node.start);
> - *cs++ = upper_32_bits(batch->node.start);
> + *cs++ = lower_32_bits(i915_vma_offset(batch));
> + *cs++ = upper_32_bits(i915_vma_offset(batch));
>
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
> diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> index 041954408d0f..8d29f6b979bd 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> @@ -50,7 +50,7 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
> } else {
> *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> }
> - *cs++ = vma->node.start + 4000;
> + *cs++ = i915_vma_offset(vma) + 4000;
> *cs++ = STACK_MAGIC;
>
> *cs++ = MI_BATCH_BUFFER_END;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
> index 7ee2513e15f9..d242ed23e609 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rps.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
> @@ -119,14 +119,14 @@ create_spin_counter(struct intel_engine_cs *engine,
> if (srm) {
> *cs++ = MI_STORE_REGISTER_MEM_GEN8;
> *cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));
> - *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs));
> - *cs++ = upper_32_bits(vma->node.start + end * sizeof(*cs));
> + *cs++ = lower_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
> + *cs++ = upper_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
> }
> }
>
> *cs++ = MI_BATCH_BUFFER_START_GEN8;
> - *cs++ = lower_32_bits(vma->node.start + loop * sizeof(*cs));
> - *cs++ = upper_32_bits(vma->node.start + loop * sizeof(*cs));
> + *cs++ = lower_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
> + *cs++ = upper_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
> GEM_BUG_ON(cs - base > end);
>
> i915_gem_object_flush_map(obj);
> @@ -655,7 +655,7 @@ int live_rps_frequency_cs(void *arg)
> err = i915_vma_move_to_active(vma, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - vma->node.start,
> + i915_vma_offset(vma),
> PAGE_SIZE, 0);
> i915_request_add(rq);
> if (err)
> @@ -796,7 +796,7 @@ int live_rps_frequency_srm(void *arg)
> err = i915_vma_move_to_active(vma, rq, 0);
> if (!err)
> err = rq->engine->emit_bb_start(rq,
> - vma->node.start,
> + i915_vma_offset(vma),
> PAGE_SIZE, 0);
> i915_request_add(rq);
> if (err)
> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> index 962e91ba3be4..cd027e98e409 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> @@ -521,8 +521,8 @@ static int check_dirty_whitelist(struct intel_context *ce)
>
> for (i = 0; i < engine->whitelist.count; i++) {
> u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
> + u64 addr = i915_vma_offset(scratch);
> struct i915_gem_ww_ctx ww;
> - u64 addr = scratch->node.start;
> struct i915_request *rq;
> u32 srm, lrm, rsvd;
> u32 expect;
> @@ -645,7 +645,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
> goto err_request;
>
> err = engine->emit_bb_start(rq,
> - batch->node.start, PAGE_SIZE,
> + i915_vma_offset(batch), PAGE_SIZE,
> 0);
> if (err)
> goto err_request;
> @@ -877,7 +877,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
> }
>
> for (i = 0; i < engine->whitelist.count; i++) {
> - u64 offset = results->node.start + sizeof(u32) * i;
> + u64 offset = i915_vma_offset(results) + sizeof(u32) * i;
> u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
>
> /* Clear non priv flags */
> @@ -951,7 +951,7 @@ static int scrub_whitelisted_registers(struct intel_context *ce)
> goto err_request;
>
> /* Perform the writes from an unprivileged "user" batch */
> - err = engine->emit_bb_start(rq, batch->node.start, 0, 0);
> + err = engine->emit_bb_start(rq, i915_vma_offset(batch), 0, 0);
>
> err_request:
> err = request_add_sync(rq, err);
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index e0403ce9ce69..c2109006df8b 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -1459,8 +1459,8 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
> /* Defer failure until attempted use */
> jump_whitelist = alloc_whitelist(batch_length);
>
> - shadow_addr = gen8_canonical_addr(shadow->node.start);
> - batch_addr = gen8_canonical_addr(batch->node.start + batch_offset);
> + shadow_addr = gen8_canonical_addr(i915_vma_offset(shadow));
> + batch_addr = gen8_canonical_addr(i915_vma_offset(batch) + batch_offset);
>
> /*
> * We use the batch length as size because the shadow object is as
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 390d541f64ea..b082af695d4e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -170,7 +170,7 @@ i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
>
> seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
> stringify_vma_type(vma),
> - vma->node.start, vma->node.size,
> + i915_vma_offset(vma), i915_vma_size(vma),
> stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
> if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
> switch (vma->ggtt_view.type) {
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 2f01b8c0284c..d6c7d90ce5cc 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2015,7 +2015,7 @@ emit_oa_config(struct i915_perf_stream *stream,
> goto err_add_request;
>
> err = rq->engine->emit_bb_start(rq,
> - vma->node.start, 0,
> + i915_vma_offset(vma), 0,
> I915_DISPATCH_SECURE);
> if (err)
> goto err_add_request;
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 927f0d4f8e11..10473ce8a047 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -399,7 +399,7 @@ int i915_vma_bind(struct i915_vma *vma,
> u32 vma_flags;
>
> GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> - GEM_BUG_ON(vma->size > vma->node.size);
> + GEM_BUG_ON(vma->size > i915_vma_size(vma));
>
> if (GEM_DEBUG_WARN_ON(range_overflows(vma->node.start,
> vma->node.size,
> @@ -494,8 +494,8 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
> vma->obj->base.size);
> else
> ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
> - vma->node.start,
> - vma->node.size);
> + i915_vma_offset(vma),
> + i915_vma_size(vma));
> if (ptr == NULL) {
> err = -ENOMEM;
> goto err;
> @@ -569,22 +569,22 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
> if (test_bit(I915_VMA_ERROR_BIT, __i915_vma_flags(vma)))
> return true;
>
> - if (vma->node.size < size)
> + if (i915_vma_size(vma) < size)
> return true;
>
> GEM_BUG_ON(alignment && !is_power_of_2(alignment));
> - if (alignment && !IS_ALIGNED(vma->node.start, alignment))
> + if (alignment && !IS_ALIGNED(i915_vma_offset(vma), alignment))
> return true;
>
> if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma))
> return true;
>
> if (flags & PIN_OFFSET_BIAS &&
> - vma->node.start < (flags & PIN_OFFSET_MASK))
> + i915_vma_offset(vma) < (flags & PIN_OFFSET_MASK))
> return true;
>
> if (flags & PIN_OFFSET_FIXED &&
> - vma->node.start != (flags & PIN_OFFSET_MASK))
> + i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
> return true;
>
> return false;
> @@ -597,10 +597,11 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
> GEM_BUG_ON(!i915_vma_is_ggtt(vma));
> GEM_BUG_ON(!vma->fence_size);
>
> - fenceable = (vma->node.size >= vma->fence_size &&
> - IS_ALIGNED(vma->node.start, vma->fence_alignment));
> + fenceable = (i915_vma_size(vma) >= vma->fence_size &&
> + IS_ALIGNED(i915_vma_offset(vma), vma->fence_alignment));
>
> - mappable = vma->node.start + vma->fence_size <= i915_vm_to_ggtt(vma->vm)->mappable_end;
> + mappable = i915_ggtt_offset(vma) + vma->fence_size <=
> + i915_vm_to_ggtt(vma->vm)->mappable_end;
>
> if (mappable && fenceable)
> set_bit(I915_VMA_CAN_FENCE_BIT, __i915_vma_flags(vma));
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index 4033aa08d5e4..1d13d619ff86 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -125,13 +125,30 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
> return !list_empty(&vma->closed_link);
> }
>
> +static inline u64 i915_vma_size(const struct i915_vma *vma)
> +{
> + GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> + return vma->node.size;
> +}
> +
> +static inline u64 __i915_vma_offset(const struct i915_vma *vma)
> +{
> + return vma->node.start;
> +}
> +
> +static inline u64 i915_vma_offset(const struct i915_vma *vma)
> +{
> + GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> + return __i915_vma_offset(vma);
> +}
> +
> static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
> {
> GEM_BUG_ON(!i915_vma_is_ggtt(vma));
> GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> - GEM_BUG_ON(upper_32_bits(vma->node.start));
> - GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1));
> - return lower_32_bits(vma->node.start);
> + GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma)));
> + GEM_BUG_ON(upper_32_bits(i915_vma_offset(vma) + i915_vma_size(vma) - 1));
> + return lower_32_bits(i915_vma_offset(vma));
> }
>
> static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> index 46f4236039a9..89528c0d19f4 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> @@ -245,6 +245,10 @@ static int lowlevel_hole(struct i915_address_space *vm,
> if (!mock_vma)
> return -ENOMEM;
>
> + __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &mock_vma->node.flags);
> + if (i915_is_ggtt(vm))
> + __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(mock_vma));
> +
> /* Keep creating larger objects until one cannot fit into the hole */
> for (size = 12; (hole_end - hole_start) >> size; size++) {
> I915_RND_SUBSTATE(prng, seed_prng);
> @@ -1982,6 +1986,7 @@ static int igt_cs_tlb(void *arg)
> goto end;
>
> /* Prime the TLB with the dummy pages */
> + __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
> for (i = 0; i < count; i++) {
> vma->node.start = offset + i * PAGE_SIZE;
> vm->insert_entries(vm, vma, I915_CACHE_NONE, 0);
> @@ -1995,8 +2000,10 @@ static int igt_cs_tlb(void *arg)
> }
>
> vma->ops->clear_pages(vma);
> + __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
> + &vma->node.flags);
>
> - err = context_sync(ce);
> + err = context_sync(ce);
> if (err) {
> pr_err("%s: dummy setup timed out\n",
> ce->engine->name);
> @@ -2014,6 +2021,7 @@ static int igt_cs_tlb(void *arg)
> goto end;
>
> /* Replace the TLB with target batches */
> + __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &vma->node.flags);
> for (i = 0; i < count; i++) {
> struct i915_request *rq;
> u32 *cs = batch + i * 64 / sizeof(*cs);
> @@ -2048,6 +2056,8 @@ static int igt_cs_tlb(void *arg)
> end_spin(batch, count - 1);
>
> vma->ops->clear_pages(vma);
> + __clear_bit(DRM_MM_NODE_ALLOCATED_BIT,
> + &vma->node.flags);
>
> err = context_sync(ce);
> if (err) {
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
> index 9979ef9197cd..737d29bbc3b5 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_request.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_request.c
> @@ -879,8 +879,8 @@ empty_request(struct intel_engine_cs *engine,
> return request;
>
> err = engine->emit_bb_start(request,
> - batch->node.start,
> - batch->node.size,
> + i915_vma_offset(batch),
> + i915_vma_size(batch),
> I915_DISPATCH_SECURE);
> if (err)
> goto out_request;
> @@ -1000,14 +1000,14 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
>
> if (ver >= 8) {
> *cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
> - *cmd++ = lower_32_bits(vma->node.start);
> - *cmd++ = upper_32_bits(vma->node.start);
> + *cmd++ = lower_32_bits(i915_vma_offset(vma));
> + *cmd++ = upper_32_bits(i915_vma_offset(vma));
> } else if (ver >= 6) {
> *cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
> - *cmd++ = lower_32_bits(vma->node.start);
> + *cmd++ = lower_32_bits(i915_vma_offset(vma));
> } else {
> *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
> - *cmd++ = lower_32_bits(vma->node.start);
> + *cmd++ = lower_32_bits(i915_vma_offset(vma));
> }
> *cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */
>
> @@ -1091,8 +1091,8 @@ static int live_all_engines(void *arg)
> GEM_BUG_ON(err);
>
> err = engine->emit_bb_start(request[idx],
> - batch->node.start,
> - batch->node.size,
> + i915_vma_offset(batch),
> + i915_vma_size(batch),
> 0);
> GEM_BUG_ON(err);
> request[idx]->batch = batch;
> @@ -1221,8 +1221,8 @@ static int live_sequential_engines(void *arg)
> GEM_BUG_ON(err);
>
> err = engine->emit_bb_start(request[idx],
> - batch->node.start,
> - batch->node.size,
> + i915_vma_offset(batch),
> + i915_vma_size(batch),
> 0);
> GEM_BUG_ON(err);
> request[idx]->batch = batch;
> diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> index 24d87d0fc747..d5939f1f14e4 100644
> --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
> +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> @@ -115,7 +115,7 @@ static unsigned int seqno_offset(u64 fence)
> static u64 hws_address(const struct i915_vma *hws,
> const struct i915_request *rq)
> {
> - return hws->node.start + seqno_offset(rq->fence.context);
> + return i915_vma_offset(hws) + seqno_offset(rq->fence.context);
> }
>
> static int move_to_active(struct i915_vma *vma,
> @@ -202,8 +202,8 @@ igt_spinner_create_request(struct igt_spinner *spin,
> *batch++ = MI_BATCH_BUFFER_START;
> else
> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
> - *batch++ = lower_32_bits(vma->node.start);
> - *batch++ = upper_32_bits(vma->node.start);
> + *batch++ = lower_32_bits(i915_vma_offset(vma));
> + *batch++ = upper_32_bits(i915_vma_offset(vma));
>
> *batch++ = MI_BATCH_BUFFER_END; /* not reached */
>
> @@ -218,7 +218,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
> flags = 0;
> if (GRAPHICS_VER(rq->engine->i915) <= 5)
> flags |= I915_DISPATCH_SECURE;
> - err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
> + err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
>
> cancel_rq:
> if (err) {
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH V2 2/3] drm/i915: Introduce guard pages to i915_vma
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 2/3] drm/i915: Introduce guard pages to i915_vma Tejas Upadhyay
@ 2021-12-03 10:54 ` Ramalingam C
2021-12-03 10:57 ` Ramalingam C
0 siblings, 1 reply; 12+ messages in thread
From: Ramalingam C @ 2021-12-03 10:54 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
On 2021-12-02 at 14:54:23 +0530, Tejas Upadhyay wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> Introduce the concept of padding the i915_vma with guard pages before
> and aft. The major consequence is that all ordinary uses of i915_vma
> must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
> directly, as the drm_mm_node will include the guard pages that surround
> our object.
>
> The biggest connundrum is how exactly to mix requesting a fixed address
> with guard pages, particularly through the existing uABI. The user does
> not know about guard pages, so such must be transparent to the user, and
> so the execobj.offset must be that of the object itself excluding the
> guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
> The caveat is that some placements will be impossible with guard pages,
> as wrap arounds need to be avoided, and the vma itself will require a
> larger node. We must we not report EINVAL but ENOSPC as these are
> unavailable locations within the GTT rather than conflicting user
> requirements.
>
> In the next patch, we start using guard pages for scanout objects. While
> these are limited to GGTT vma, on a few platforms these vma (or at least
> an alias of the vma) is shared with userspace, so we may leak the
> existence of such guards if we are not careful to ensure that the
> execobj.offset is transparent and excludes the guards. (On such platforms
> like ivb, without full-ppgtt, userspace has to use relocations so the
> presence of more untouchable regions within its GTT such be of no further
> issue.)
>
> v2: Include the guard range in the overflow checks and placement
> restrictions.
>
> v3: Fix the check on the placement upper bound. The request user offset
> is relative to the guard offset (not the node.start) and so we should
> not include the initial guard offset again when computing the upper
> bound of the node.
Commit subject says v2 but we have teh change log for v3.
Patch looks good to me.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++++++++++--
> drivers/gpu/drm/i915/i915_vma.c | 26 +++++++++++++++++++++-----
> drivers/gpu/drm/i915/i915_vma.h | 5 +++--
> drivers/gpu/drm/i915/i915_vma_types.h | 3 ++-
> 4 files changed, 36 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 07133f0c529e..282ed6dd3ca2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -256,8 +256,12 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
>
> gte = (gen8_pte_t __iomem *)ggtt->gsm;
> gte += vma->node.start / I915_GTT_PAGE_SIZE;
> - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
>
> + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> + while (gte < end)
> + gen8_set_pte(gte++, vm->scratch[0]->encode);
> +
> + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> for_each_sgt_daddr(addr, iter, vma->pages)
> gen8_set_pte(gte++, pte_encode | addr);
> GEM_BUG_ON(gte > end);
> @@ -307,8 +311,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
>
> gte = (gen6_pte_t __iomem *)ggtt->gsm;
> gte += vma->node.start / I915_GTT_PAGE_SIZE;
> - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
>
> + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> + while (gte < end)
> + gen8_set_pte(gte++, vm->scratch[0]->encode);
> +
> + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> for_each_sgt_daddr(addr, iter, vma->pages)
> iowrite32(vm->pte_encode(addr, level, flags), gte++);
> GEM_BUG_ON(gte > end);
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 10473ce8a047..080ffa583edf 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -658,7 +658,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color)
> static int
> i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> {
> - unsigned long color;
> + unsigned long color, guard;
> u64 start, end;
> int ret;
>
> @@ -666,7 +666,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
>
> size = max(size, vma->size);
> - alignment = max(alignment, vma->display_alignment);
> + alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
> if (flags & PIN_MAPPABLE) {
> size = max_t(typeof(size), size, vma->fence_size);
> alignment = max_t(typeof(alignment),
> @@ -677,6 +677,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
> GEM_BUG_ON(!is_power_of_2(alignment));
>
> + guard = vma->guard; /* retain guard across rebinds */
> + guard = ALIGN(guard, alignment);
> +
> start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
> GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
>
> @@ -686,12 +689,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> if (flags & PIN_ZONE_4G)
> end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);
> GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
> + GEM_BUG_ON(2 * guard > end);
>
> /* If binding the object/GGTT view requires more space than the entire
> * aperture has, reject it early before evicting everything in a vain
> * attempt to find space.
> */
> - if (size > end) {
> + if (size > end - 2 * guard) {
> DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu > %s aperture=%llu\n",
> size, flags & PIN_MAPPABLE ? "mappable" : "total",
> end);
> @@ -707,13 +711,24 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> if (!IS_ALIGNED(offset, alignment) ||
> range_overflows(offset, size, end))
> return -EINVAL;
> + /*
> + * The caller knows not of the guard added by others and
> + * requests for the offset of the start of its buffer
> + * to be fixed, which may not be the same as the position
> + * of the vma->node due to the guard pages.
> + */
> + if (offset < guard || offset + size > end - guard)
> + return -ENOSPC;
> +
>
> ret = i915_gem_gtt_reserve(vma->vm, &vma->node,
> - size, offset, color,
> - flags);
> + size + 2 * guard,
> + offset - guard,
> + color, flags);
> if (ret)
> return ret;
> } else {
> + size += 2 * guard;
> /*
> * We only support huge gtt pages through the 48b PPGTT,
> * however we also don't want to force any alignment for
> @@ -760,6 +775,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, color));
>
> list_add_tail(&vma->vm_link, &vma->vm->bound_list);
> + vma->guard = guard;
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index 1d13d619ff86..d35ce4e7170c 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -128,12 +128,13 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
> static inline u64 i915_vma_size(const struct i915_vma *vma)
> {
> GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> - return vma->node.size;
> + return vma->node.size - 2 * vma->guard;
> }
>
> static inline u64 __i915_vma_offset(const struct i915_vma *vma)
> {
> - return vma->node.start;
> + /* The actual start of the vma->pages is after the guard pages. */
> + return vma->node.start + vma->guard;
> }
>
> static inline u64 i915_vma_offset(const struct i915_vma *vma)
> diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h
> index f03fa96a1701..a224daf1044e 100644
> --- a/drivers/gpu/drm/i915/i915_vma_types.h
> +++ b/drivers/gpu/drm/i915/i915_vma_types.h
> @@ -195,14 +195,15 @@ struct i915_vma {
> struct i915_fence_reg *fence;
>
> u64 size;
> - u64 display_alignment;
> struct i915_page_sizes page_sizes;
>
> /* mmap-offset associated with fencing for this vma */
> struct i915_mmap_offset *mmo;
>
> + u32 guard; /* padding allocated around vma->pages within the node */
> u32 fence_size;
> u32 fence_alignment;
> + u32 display_alignment;
>
> /**
> * Count of the number of times this vma has been opened by different
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH V2 2/3] drm/i915: Introduce guard pages to i915_vma
2021-12-03 10:54 ` Ramalingam C
@ 2021-12-03 10:57 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2021-12-03 10:57 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
On 2021-12-03 at 16:24:24 +0530, Ramalingam C wrote:
> On 2021-12-02 at 14:54:23 +0530, Tejas Upadhyay wrote:
> > From: Chris Wilson <chris@chris-wilson.co.uk>
> >
> > Introduce the concept of padding the i915_vma with guard pages before
> > and aft. The major consequence is that all ordinary uses of i915_vma
> > must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
> > directly, as the drm_mm_node will include the guard pages that surround
> > our object.
> >
> > The biggest connundrum is how exactly to mix requesting a fixed address
> > with guard pages, particularly through the existing uABI. The user does
> > not know about guard pages, so such must be transparent to the user, and
> > so the execobj.offset must be that of the object itself excluding the
> > guard. So a PIN_OFFSET_FIXED must then be exclusive of the guard pages.
> > The caveat is that some placements will be impossible with guard pages,
> > as wrap arounds need to be avoided, and the vma itself will require a
> > larger node. We must we not report EINVAL but ENOSPC as these are
Possibly you might want to remove extra "we".
Ram
> > unavailable locations within the GTT rather than conflicting user
> > requirements.
> >
> > In the next patch, we start using guard pages for scanout objects. While
> > these are limited to GGTT vma, on a few platforms these vma (or at least
> > an alias of the vma) is shared with userspace, so we may leak the
> > existence of such guards if we are not careful to ensure that the
> > execobj.offset is transparent and excludes the guards. (On such platforms
> > like ivb, without full-ppgtt, userspace has to use relocations so the
> > presence of more untouchable regions within its GTT such be of no further
> > issue.)
> >
> > v2: Include the guard range in the overflow checks and placement
> > restrictions.
> >
> > v3: Fix the check on the placement upper bound. The request user offset
> > is relative to the guard offset (not the node.start) and so we should
> > not include the initial guard offset again when computing the upper
> > bound of the node.
> Commit subject says v2 but we have teh change log for v3.
>
> Patch looks good to me.
>
> Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Matthew Auld <matthew.auld@intel.com>
> > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++++++++++--
> > drivers/gpu/drm/i915/i915_vma.c | 26 +++++++++++++++++++++-----
> > drivers/gpu/drm/i915/i915_vma.h | 5 +++--
> > drivers/gpu/drm/i915/i915_vma_types.h | 3 ++-
> > 4 files changed, 36 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > index 07133f0c529e..282ed6dd3ca2 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > @@ -256,8 +256,12 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
> >
> > gte = (gen8_pte_t __iomem *)ggtt->gsm;
> > gte += vma->node.start / I915_GTT_PAGE_SIZE;
> > - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
> >
> > + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> > + while (gte < end)
> > + gen8_set_pte(gte++, vm->scratch[0]->encode);
> > +
> > + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> > for_each_sgt_daddr(addr, iter, vma->pages)
> > gen8_set_pte(gte++, pte_encode | addr);
> > GEM_BUG_ON(gte > end);
> > @@ -307,8 +311,12 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
> >
> > gte = (gen6_pte_t __iomem *)ggtt->gsm;
> > gte += vma->node.start / I915_GTT_PAGE_SIZE;
> > - end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
> >
> > + end = gte + vma->guard / I915_GTT_PAGE_SIZE;
> > + while (gte < end)
> > + gen8_set_pte(gte++, vm->scratch[0]->encode);
> > +
> > + end += (vma->node.size - vma->guard) / I915_GTT_PAGE_SIZE;
> > for_each_sgt_daddr(addr, iter, vma->pages)
> > iowrite32(vm->pte_encode(addr, level, flags), gte++);
> > GEM_BUG_ON(gte > end);
> > diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> > index 10473ce8a047..080ffa583edf 100644
> > --- a/drivers/gpu/drm/i915/i915_vma.c
> > +++ b/drivers/gpu/drm/i915/i915_vma.c
> > @@ -658,7 +658,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color)
> > static int
> > i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > {
> > - unsigned long color;
> > + unsigned long color, guard;
> > u64 start, end;
> > int ret;
> >
> > @@ -666,7 +666,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
> >
> > size = max(size, vma->size);
> > - alignment = max(alignment, vma->display_alignment);
> > + alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
> > if (flags & PIN_MAPPABLE) {
> > size = max_t(typeof(size), size, vma->fence_size);
> > alignment = max_t(typeof(alignment),
> > @@ -677,6 +677,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
> > GEM_BUG_ON(!is_power_of_2(alignment));
> >
> > + guard = vma->guard; /* retain guard across rebinds */
> > + guard = ALIGN(guard, alignment);
> > +
> > start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
> > GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
> >
> > @@ -686,12 +689,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > if (flags & PIN_ZONE_4G)
> > end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);
> > GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
> > + GEM_BUG_ON(2 * guard > end);
> >
> > /* If binding the object/GGTT view requires more space than the entire
> > * aperture has, reject it early before evicting everything in a vain
> > * attempt to find space.
> > */
> > - if (size > end) {
> > + if (size > end - 2 * guard) {
> > DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu > %s aperture=%llu\n",
> > size, flags & PIN_MAPPABLE ? "mappable" : "total",
> > end);
> > @@ -707,13 +711,24 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > if (!IS_ALIGNED(offset, alignment) ||
> > range_overflows(offset, size, end))
> > return -EINVAL;
> > + /*
> > + * The caller knows not of the guard added by others and
> > + * requests for the offset of the start of its buffer
> > + * to be fixed, which may not be the same as the position
> > + * of the vma->node due to the guard pages.
> > + */
> > + if (offset < guard || offset + size > end - guard)
> > + return -ENOSPC;
> > +
> >
> > ret = i915_gem_gtt_reserve(vma->vm, &vma->node,
> > - size, offset, color,
> > - flags);
> > + size + 2 * guard,
> > + offset - guard,
> > + color, flags);
> > if (ret)
> > return ret;
> > } else {
> > + size += 2 * guard;
> > /*
> > * We only support huge gtt pages through the 48b PPGTT,
> > * however we also don't want to force any alignment for
> > @@ -760,6 +775,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> > GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, color));
> >
> > list_add_tail(&vma->vm_link, &vma->vm->bound_list);
> > + vma->guard = guard;
> >
> > return 0;
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> > index 1d13d619ff86..d35ce4e7170c 100644
> > --- a/drivers/gpu/drm/i915/i915_vma.h
> > +++ b/drivers/gpu/drm/i915/i915_vma.h
> > @@ -128,12 +128,13 @@ static inline bool i915_vma_is_closed(const struct i915_vma *vma)
> > static inline u64 i915_vma_size(const struct i915_vma *vma)
> > {
> > GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> > - return vma->node.size;
> > + return vma->node.size - 2 * vma->guard;
> > }
> >
> > static inline u64 __i915_vma_offset(const struct i915_vma *vma)
> > {
> > - return vma->node.start;
> > + /* The actual start of the vma->pages is after the guard pages. */
> > + return vma->node.start + vma->guard;
> > }
> >
> > static inline u64 i915_vma_offset(const struct i915_vma *vma)
> > diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h
> > index f03fa96a1701..a224daf1044e 100644
> > --- a/drivers/gpu/drm/i915/i915_vma_types.h
> > +++ b/drivers/gpu/drm/i915/i915_vma_types.h
> > @@ -195,14 +195,15 @@ struct i915_vma {
> > struct i915_fence_reg *fence;
> >
> > u64 size;
> > - u64 display_alignment;
> > struct i915_page_sizes page_sizes;
> >
> > /* mmap-offset associated with fencing for this vma */
> > struct i915_mmap_offset *mmo;
> >
> > + u32 guard; /* padding allocated around vma->pages within the node */
> > u32 fence_size;
> > u32 fence_alignment;
> > + u32 display_alignment;
> >
> > /**
> > * Count of the number of times this vma has been opened by different
> > --
> > 2.31.1
> >
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH V2 3/3] drm/i915: Refine VT-d scanout workaround
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 3/3] drm/i915: Refine VT-d scanout workaround Tejas Upadhyay
@ 2021-12-03 11:05 ` Ramalingam C
0 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2021-12-03 11:05 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
On 2021-12-02 at 14:54:24 +0530, Tejas Upadhyay wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> VT-d may cause overfetch of the scanout PTE, both before and after the
> vma (depending on the scanout orientation). bspec recommends that we
> provide a tile-row in either directions, and suggests using 168 PTE,
> warning that the accesses will wrap around the ends of the GGTT.
> Currently, we fill the entire GGTT with scratch pages when using VT-d to
> always ensure there are valid entries around every vma, including
> scanout. However, writing every PTE is slow as on recent devices we
> perform 8MiB of uncached writes, incurring an extra 100ms during resume.
>
> If instead we focus on only putting guard pages around scanout, we can
> avoid touching the whole GGTT. To avoid having to introduce extra nodes
> around each scanout vma, we adjust the scanout drm_mm_node to be smaller
> than the allocated space, and fixup the extra PTE during dma binding.
>
> v2: Move the guard from modifying drm_mm_node.start which is still used
> by the drm_mm itself, into an adjustment of node.start at the point of
> use.
>
> v3: Pass the requested guard padding from the caller, so we can drop the
> VT-d w/a knowledge from the i915_vma allocator.
>
> v4: Bump minimum padding to 168 PTE and cautiously ensure that a full
> tile row around the vma is included with the guard.
Looks good to me
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++++++++++
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +---------------------
> drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
> drivers/gpu/drm/i915/i915_vma.c | 8 +++++++
> 4 files changed, 23 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> index 26532c07d467..03876af45c8b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> @@ -16,6 +16,8 @@
> #include "i915_gem_lmem.h"
> #include "i915_gem_mman.h"
>
> +#define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */
> +
> static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> @@ -423,6 +425,17 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
> if (ret)
> return ERR_PTR(ret);
>
> + /* VT-d may overfetch before/after the vma, so pad with scratch */
> + if (intel_scanout_needs_vtd_wa(i915)) {
> + unsigned int guard = VTD_GUARD;
> +
> + if (i915_gem_object_is_tiled(obj))
> + guard = max(guard,
> + i915_gem_object_get_tile_row_size(obj));
> +
> + flags |= PIN_OFFSET_GUARD | guard;
> + }
> +
> /*
> * As the user may map the buffer once pinned in the display plane
> * (e.g. libkms for the bootup splash), we have to ensure that we
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 282ed6dd3ca2..4a0f916ab03f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -337,27 +337,6 @@ static void nop_clear_range(struct i915_address_space *vm,
> {
> }
>
> -static void gen8_ggtt_clear_range(struct i915_address_space *vm,
> - u64 start, u64 length)
> -{
> - struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> - unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
> - unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
> - const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
> - gen8_pte_t __iomem *gtt_base =
> - (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
> - const int max_entries = ggtt_total_entries(ggtt) - first_entry;
> - int i;
> -
> - if (WARN(num_entries > max_entries,
> - "First entry = %d; Num entries = %d (max=%d)\n",
> - first_entry, num_entries, max_entries))
> - num_entries = max_entries;
> -
> - for (i = 0; i < num_entries; i++)
> - gen8_set_pte(>t_base[i], scratch_pte);
> -}
> -
> static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
> {
> /*
> @@ -956,8 +935,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> ggtt->vm.cleanup = gen6_gmch_remove;
> ggtt->vm.insert_page = gen8_ggtt_insert_page;
> ggtt->vm.clear_range = nop_clear_range;
> - if (intel_scanout_needs_vtd_wa(i915))
> - ggtt->vm.clear_range = gen8_ggtt_clear_range;
>
> ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
>
> @@ -1105,7 +1082,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
> ggtt->vm.alloc_pt_dma = alloc_pt_dma;
>
> ggtt->vm.clear_range = nop_clear_range;
> - if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
> + if (!HAS_FULL_PPGTT(i915))
> ggtt->vm.clear_range = gen6_ggtt_clear_range;
> ggtt->vm.insert_page = gen6_ggtt_insert_page;
> ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index c9b0ee5e1d23..f3ae9afdee15 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -41,6 +41,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
> #define PIN_HIGH BIT_ULL(5)
> #define PIN_OFFSET_BIAS BIT_ULL(6)
> #define PIN_OFFSET_FIXED BIT_ULL(7)
> +#define PIN_OFFSET_GUARD BIT_ULL(8)
>
> #define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
> #define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 080ffa583edf..d92a9f938c68 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -587,6 +587,9 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
> i915_vma_offset(vma) != (flags & PIN_OFFSET_MASK))
> return true;
>
> + if (flags & PIN_OFFSET_GUARD && vma->guard < (flags & PIN_OFFSET_MASK))
> + return true;
> +
> return false;
> }
>
> @@ -664,6 +667,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
>
> GEM_BUG_ON(i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND));
> GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
> + GEM_BUG_ON(hweight64(flags & (PIN_OFFSET_GUARD | PIN_OFFSET_FIXED | PIN_OFFSET_BIAS)) > 1);
>
> size = max(size, vma->size);
> alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
> @@ -678,6 +682,10 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> GEM_BUG_ON(!is_power_of_2(alignment));
>
> guard = vma->guard; /* retain guard across rebinds */
> + if (flags & PIN_OFFSET_GUARD) {
> + GEM_BUG_ON(overflows_type(flags & PIN_OFFSET_MASK, u32));
> + guard = max_t(u32, guard, flags & PIN_OFFSET_MASK);
> + }
> guard = ALIGN(guard, alignment);
>
> start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages
2021-12-02 9:24 [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Tejas Upadhyay
` (5 preceding siblings ...)
2021-12-02 11:43 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-12-03 11:11 ` Ramalingam C
6 siblings, 0 replies; 12+ messages in thread
From: Ramalingam C @ 2021-12-03 11:11 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
On 2021-12-02 at 14:54:21 +0530, Tejas Upadhyay wrote:
> Replace filling the GGTT entirely with scratch pages to avoid invalid
> accesses from VT-d overfetch of scanout by only surrounding scanout vma
> with guard pages. This eliminates the 100+ms delay in resume where we
> have to repopulate the GGTT with scratch.
>
> This should also help in avoiding slow suspend/resume on GEN11/12
> platforms. Which will also resolve issues with following reported
> errors : "slow framebuffer consoles issue impacts Linux S3"
Please remove the R-b tag received not from upstreaming review and
change logs for the iterations happened somewhere else.
Ram.
>
> V2: solved checkpatch warning
>
> Chris Wilson (3):
> drm/i915: Wrap all access to i915_vma.node.start|size
> drm/i915: Introduce guard pages to i915_vma
> drm/i915: Refine VT-d scanout workaround
>
> drivers/gpu/drm/i915/display/intel_dpt.c | 4 +-
> drivers/gpu/drm/i915/display/intel_fbdev.c | 6 +-
> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++++
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 34 ++++++------
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 +-
> .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
> .../i915/gem/selftests/i915_gem_client_blt.c | 15 ++---
> .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++++--
> .../drm/i915/gem/selftests/i915_gem_mman.c | 2 +-
> .../drm/i915/gem/selftests/igt_gem_utils.c | 6 +-
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 8 +--
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 42 +++++---------
> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 8 +--
> drivers/gpu/drm/i915/gt/selftest_execlists.c | 18 +++---
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 ++---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 16 +++---
> .../drm/i915/gt/selftest_ring_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_rps.c | 12 ++--
> .../gpu/drm/i915/gt/selftest_workarounds.c | 8 +--
> drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/i915_vma.c | 55 ++++++++++++++-----
> drivers/gpu/drm/i915/i915_vma.h | 24 +++++++-
> drivers/gpu/drm/i915/i915_vma_types.h | 3 +-
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 12 +++-
> drivers/gpu/drm/i915/selftests/i915_request.c | 20 +++----
> drivers/gpu/drm/i915/selftests/igt_spinner.c | 8 +--
> 37 files changed, 226 insertions(+), 159 deletions(-)
>
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-12-03 11:08 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-02 9:24 [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Tejas Upadhyay
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 1/3] drm/i915: Wrap all access to i915_vma.node.start|size Tejas Upadhyay
2021-12-03 10:14 ` Ramalingam C
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 2/3] drm/i915: Introduce guard pages to i915_vma Tejas Upadhyay
2021-12-03 10:54 ` Ramalingam C
2021-12-03 10:57 ` Ramalingam C
2021-12-02 9:24 ` [Intel-gfx] [PATCH V2 3/3] drm/i915: Refine VT-d scanout workaround Tejas Upadhyay
2021-12-03 11:05 ` Ramalingam C
2021-12-02 9:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Replace VT-d workaround with guard pages (rev2) Patchwork
2021-12-02 10:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-12-02 11:43 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-12-03 11:11 ` [Intel-gfx] [PATCH 0/3] Replace VT-d workaround with guard pages Ramalingam C
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