* [PATCH 0/6] Add Mali-G31 GPU support for RZ/G2L SoC
@ 2021-12-03 11:51 ` Biju Das
0 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2021-12-03 11:51 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring
Cc: devicetree, Chris Paterson, Geert Uytterhoeven,
Prabhakar Mahadev Lad, dri-devel, Biju Das, linux-renesas-soc,
Biju Das, linux-clk
RZ/G2L SoC embeds Mali-G31 bifrost GPU.
This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa21.3.0 +
out of tree patch for (du + DSI) + mesa configurtion for RZ/G2L.
Tested the kmscube application.
test logs:-
root@smarc-rzg2l:~# kmscube
Using display 0xaaaadb6e7d30 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
....
===================================
^C
root@smarc-rzg2l:~# cat /proc/interrupts | grep gpu
84: 8 0 GICv3 185 Level panfrost-gpu
root@smarc-rzg2l:~# cat /proc/interrupts | grep panfrost
82: 587287 0 GICv3 186 Level panfrost-job
83: 2 0 GICv3 187 Level panfrost-mmu
84: 8 0 GICv3 185 Level panfrost-gpu
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 0 72
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 0 0
125000000: 0 0 0 0 0 0 0 1 68
200000000: 0 0 0 0 0 0 0 1 68
250000000: 1 0 0 0 0 0 0 0 84
400000000: 0 0 0 0 0 0 0 0 0
500000000: 0 0 0 1 1 1 0 0 736
Total transition : 6
root@smarc-rzg2l:~# kmscube
Using display 0xaaaaf7a421b0 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
......
===================================
root@smarc-rzg2l:~#
root@smarc-rzg2l:~#
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 1 144
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 9 524
125000000: 0 0 9 0 0 0 0 3 2544
200000000: 0 0 0 11 0 0 0 46 3304
250000000: 1 0 0 0 33 0 0 0 7496
400000000: 0 0 0 0 16 19 0 0 2024
500000000: 1 0 0 1 8 15 35 0 4032
Total transition : 208
Mesa patch for RZ/G2L
---------------------
src/gallium/targets/dri/meson.build
+ 'rcar-du_dri.so',
src/gallium/targets/dri/target.c
+DEFINE_LOADER_DRM_ENTRYPOINT(rcar_du)
Biju Das (6):
clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
clk: renesas: r9a07g044: Add mux and divider for G clock
clk: renesas: r9a07g044: Add GPU clock and reset entries
dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
.../bindings/gpu/arm,mali-bifrost.yaml | 32 +++++++++-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 64 +++++++++++++++++++
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 ++++
drivers/clk/renesas/r9a07g044-cpg.c | 19 +++++-
drivers/clk/renesas/rzg2l-cpg.h | 4 ++
5 files changed, 128 insertions(+), 4 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 1/6] clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
2021-12-03 11:51 ` Biju Das
(?)
@ 2021-12-03 11:51 ` Biju Das
2021-12-06 13:08 ` Geert Uytterhoeven
-1 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2021-12-03 11:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree
mentioned in the hardware manual(Rev.1.00 Sep, 2021).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index a91ccad6329b..0962f25cd3f0 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -32,9 +32,9 @@ enum clk_ids {
CLK_PLL3_400,
CLK_PLL3_533,
CLK_PLL3_DIV2,
+ CLK_PLL3_DIV2_2,
CLK_PLL3_DIV2_4,
CLK_PLL3_DIV2_4_2,
- CLK_PLL3_DIV4,
CLK_SEL_PLL3_3,
CLK_DIV_PLL3_C,
CLK_PLL4,
@@ -106,9 +106,9 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
+ DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
- DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 1/6] clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
2021-12-03 11:51 ` [PATCH 1/6] clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro Biju Das
@ 2021-12-06 13:08 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2021-12-06 13:08 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Fri, Dec 3, 2021 at 12:52 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree
> mentioned in the hardware manual(Rev.1.00 Sep, 2021).
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/6] clk: renesas: r9a07g044: Add mux and divider for G clock
2021-12-03 11:51 ` Biju Das
(?)
(?)
@ 2021-12-03 11:51 ` Biju Das
2021-12-06 13:08 ` Geert Uytterhoeven
-1 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2021-12-03 11:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
G clock is sourced from PLL3 and PLL6. The output of the mux is
connected to divider.
This patch adds a mux and divider for getting different rates from
this clock sources.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 6 ++++++
drivers/clk/renesas/rzg2l-cpg.h | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 0962f25cd3f0..85132b6c97b7 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -50,6 +50,7 @@ enum clk_ids {
CLK_PLL2_SDHI_266,
CLK_SD0_DIV4,
CLK_SD1_DIV4,
+ CLK_SEL_GPU2,
/* Module Clocks */
MOD_CLK_BASE,
@@ -77,6 +78,7 @@ static const struct clk_div_table dtable_1_32[] = {
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
+static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
/* External Clock Inputs */
@@ -116,6 +118,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
+ DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,
+ sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),
/* Core output clk */
DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
@@ -141,6 +145,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
sel_shdi, ARRAY_SIZE(sel_shdi)),
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
+ DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
+ CLK_DIVIDER_HIWORD_MASK),
};
static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index fce4a8f35410..5729d102034b 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -12,9 +12,11 @@
#define CPG_PL1_DDIV (0x200)
#define CPG_PL2_DDIV (0x204)
#define CPG_PL3A_DDIV (0x208)
+#define CPG_PL6_DDIV (0x210)
#define CPG_PL2SDHI_DSEL (0x218)
#define CPG_CLKSTATUS (0x280)
#define CPG_PL3_SSEL (0x408)
+#define CPG_PL6_SSEL (0x414)
#define CPG_PL6_ETH_SSEL (0x418)
#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
@@ -35,12 +37,14 @@
#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
#define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3)
+#define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2)
#define SEL_PLL_PACK(offset, bitpos, size) \
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
#define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)
#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
+#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)
#define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)
#define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2)
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 2/6] clk: renesas: r9a07g044: Add mux and divider for G clock
2021-12-03 11:51 ` [PATCH 2/6] clk: renesas: r9a07g044: Add mux and divider for G clock Biju Das
@ 2021-12-06 13:08 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2021-12-06 13:08 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Prabhakar Mahadev Lad
On Fri, Dec 3, 2021 at 12:52 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> G clock is sourced from PLL3 and PLL6. The output of the mux is
> connected to divider.
>
> This patch adds a mux and divider for getting different rates from
> this clock sources.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/6] clk: renesas: r9a07g044: Add GPU clock and reset entries
2021-12-03 11:51 ` Biju Das
` (2 preceding siblings ...)
(?)
@ 2021-12-03 11:51 ` Biju Das
2021-12-06 13:10 ` Geert Uytterhoeven
-1 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2021-12-03 11:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add GPU clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 85132b6c97b7..79042bf46fe8 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -198,6 +198,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
0x554, 6),
DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
0x554, 7),
+ DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
+ 0x558, 0),
+ DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
+ 0x558, 1),
+ DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
+ 0x558, 2),
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
0x570, 0),
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
@@ -285,6 +291,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
+ DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
+ DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
+ DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 3/6] clk: renesas: r9a07g044: Add GPU clock and reset entries
2021-12-03 11:51 ` [PATCH 3/6] clk: renesas: r9a07g044: Add GPU clock and reset entries Biju Das
@ 2021-12-06 13:10 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2021-12-06 13:10 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Fri, Dec 3, 2021 at 12:52 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add GPU clock and reset entries to CPG driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/6] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
2021-12-03 11:51 ` Biju Das
@ 2021-12-03 11:51 ` Biju Das
-1 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2021-12-03 11:51 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring
Cc: Biju Das, dri-devel, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU,
add a compatible string for it.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/gpu/arm,mali-bifrost.yaml | 32 +++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index 6f98dd55fb4c..c9fac2498f5e 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -19,6 +19,7 @@ properties:
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- realtek,rtd1619-mali
+ - renesas,r9a07g044-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
@@ -27,19 +28,30 @@ properties:
maxItems: 1
interrupts:
+ minItems: 3
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
+ - description: EVENT interrupt
interrupt-names:
+ minItems: 3
items:
- const: job
- const: mmu
- const: gpu
+ - const: event
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: gpu
+ - const: bus
+ - const: bus_ace
mali-supply: true
@@ -52,7 +64,8 @@ properties:
maxItems: 3
resets:
- maxItems: 2
+ minItems: 1
+ maxItems: 3
"#cooling-cells":
const: 2
@@ -113,6 +126,21 @@ allOf:
- sram-supply
- power-domains
- power-domain-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a07g044-mali
+ then:
+ properties:
+ interrupt-names:
+ minItems: 4
+ clock-names:
+ minItems: 3
+ required:
+ - clock-names
+ - power-domains
+ - resets
else:
properties:
power-domains:
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 4/6] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
@ 2021-12-03 11:51 ` Biju Das
0 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2021-12-03 11:51 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring
Cc: devicetree, Chris Paterson, Geert Uytterhoeven,
Prabhakar Mahadev Lad, dri-devel, Biju Das, linux-renesas-soc,
Biju Das
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU,
add a compatible string for it.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/gpu/arm,mali-bifrost.yaml | 32 +++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index 6f98dd55fb4c..c9fac2498f5e 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -19,6 +19,7 @@ properties:
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- realtek,rtd1619-mali
+ - renesas,r9a07g044-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
@@ -27,19 +28,30 @@ properties:
maxItems: 1
interrupts:
+ minItems: 3
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
+ - description: EVENT interrupt
interrupt-names:
+ minItems: 3
items:
- const: job
- const: mmu
- const: gpu
+ - const: event
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: gpu
+ - const: bus
+ - const: bus_ace
mali-supply: true
@@ -52,7 +64,8 @@ properties:
maxItems: 3
resets:
- maxItems: 2
+ minItems: 1
+ maxItems: 3
"#cooling-cells":
const: 2
@@ -113,6 +126,21 @@ allOf:
- sram-supply
- power-domains
- power-domain-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a07g044-mali
+ then:
+ properties:
+ interrupt-names:
+ minItems: 4
+ clock-names:
+ minItems: 3
+ required:
+ - clock-names
+ - power-domains
+ - resets
else:
properties:
power-domains:
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 4/6] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
2021-12-03 11:51 ` Biju Das
@ 2021-12-06 13:24 ` Geert Uytterhoeven
-1 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2021-12-06 13:24 UTC (permalink / raw)
To: Biju Das
Cc: David Airlie, Daniel Vetter, Rob Herring, DRI Development,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
Hi Biju,
On Fri, Dec 3, 2021 at 12:52 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU,
> add a compatible string for it.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> @@ -52,7 +64,8 @@ properties:
> maxItems: 3
>
> resets:
> - maxItems: 2
> + minItems: 1
2, as before?
> + maxItems: 3
Perhaps you should add reset-names?
>
> "#cooling-cells":
> const: 2
> @@ -113,6 +126,21 @@ allOf:
> - sram-supply
> - power-domains
> - power-domain-names
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a07g044-mali
> + then:
> + properties:
> + interrupt-names:
> + minItems: 4
> + clock-names:
> + minItems: 3
> + required:
> + - clock-names
> + - power-domains
> + - resets
reset-names
> else:
> properties:
> power-domains:
The rest looks good to me, but I'm no Mali expert.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 4/6] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
@ 2021-12-06 13:24 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2021-12-06 13:24 UTC (permalink / raw)
To: Biju Das
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, David Airlie, Prabhakar Mahadev Lad,
DRI Development, Biju Das, Linux-Renesas, Rob Herring
Hi Biju,
On Fri, Dec 3, 2021 at 12:52 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU,
> add a compatible string for it.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> @@ -52,7 +64,8 @@ properties:
> maxItems: 3
>
> resets:
> - maxItems: 2
> + minItems: 1
2, as before?
> + maxItems: 3
Perhaps you should add reset-names?
>
> "#cooling-cells":
> const: 2
> @@ -113,6 +126,21 @@ allOf:
> - sram-supply
> - power-domains
> - power-domain-names
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a07g044-mali
> + then:
> + properties:
> + interrupt-names:
> + minItems: 4
> + clock-names:
> + minItems: 3
> + required:
> + - clock-names
> + - power-domains
> + - resets
reset-names
> else:
> properties:
> power-domains:
The rest looks good to me, but I'm no Mali expert.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: [PATCH 4/6] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
2021-12-06 13:24 ` Geert Uytterhoeven
@ 2021-12-06 13:47 ` Biju Das
-1 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2021-12-06 13:47 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: David Airlie, Daniel Vetter, Rob Herring, DRI Development,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 4/6] dt-bindings: gpu: mali-bifrost: Document RZ/G2L
> support
>
> Hi Biju,
>
> On Fri, Dec 3, 2021 at 12:52 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31
> > GPU, add a compatible string for it.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
>
> > @@ -52,7 +64,8 @@ properties:
> > maxItems: 3
> >
> > resets:
> > - maxItems: 2
> > + minItems: 1
>
> 2, as before?
OK. Will do.
>
> > + maxItems: 3
>
> Perhaps you should add reset-names?
Agreed. Will remove max items add reset-names instead ("rst", "axi_rst", "ace_rst")
>
> >
> > "#cooling-cells":
> > const: 2
> > @@ -113,6 +126,21 @@ allOf:
> > - sram-supply
> > - power-domains
> > - power-domain-names
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r9a07g044-mali
> > + then:
> > + properties:
> > + interrupt-names:
> > + minItems: 4
> > + clock-names:
> > + minItems: 3
> > + required:
> > + - clock-names
> > + - power-domains
> > + - resets
>
> reset-names
Ok.
Regards,
Biju
>
> > else:
> > properties:
> > power-domains:
>
> The rest looks good to me, but I'm no Mali expert.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: [PATCH 4/6] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
@ 2021-12-06 13:47 ` Biju Das
0 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2021-12-06 13:47 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, David Airlie, Prabhakar Mahadev Lad,
DRI Development, Biju Das, Linux-Renesas, Rob Herring
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 4/6] dt-bindings: gpu: mali-bifrost: Document RZ/G2L
> support
>
> Hi Biju,
>
> On Fri, Dec 3, 2021 at 12:52 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31
> > GPU, add a compatible string for it.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
>
> > @@ -52,7 +64,8 @@ properties:
> > maxItems: 3
> >
> > resets:
> > - maxItems: 2
> > + minItems: 1
>
> 2, as before?
OK. Will do.
>
> > + maxItems: 3
>
> Perhaps you should add reset-names?
Agreed. Will remove max items add reset-names instead ("rst", "axi_rst", "ace_rst")
>
> >
> > "#cooling-cells":
> > const: 2
> > @@ -113,6 +126,21 @@ allOf:
> > - sram-supply
> > - power-domains
> > - power-domain-names
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r9a07g044-mali
> > + then:
> > + properties:
> > + interrupt-names:
> > + minItems: 4
> > + clock-names:
> > + minItems: 3
> > + required:
> > + - clock-names
> > + - power-domains
> > + - resets
>
> reset-names
Ok.
Regards,
Biju
>
> > else:
> > properties:
> > power-domains:
>
> The rest looks good to me, but I'm no Mali expert.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 5/6] arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
2021-12-03 11:51 ` Biju Das
` (4 preceding siblings ...)
(?)
@ 2021-12-03 11:51 ` Biju Das
2021-12-06 13:30 ` Geert Uytterhoeven
-1 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2021-12-03 11:51 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add Mali-G31 GPU node to SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 64 ++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 439870930fb3..908e7f044cb0 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -111,6 +111,50 @@
};
};
+ gpu_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-62500000 {
+ opp-hz = /bits/ 64 <62500000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ opp-microvolt = <1100000>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -627,6 +671,26 @@
dma-channels = <16>;
};
+ gpu: gpu@11840000 {
+ compatible = "renesas,r9a07g044-mali",
+ "arm,mali-bifrost";
+ reg = <0x0 0x11840000 0x0 0x10000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu", "event";
+ clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
+ <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
+ <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
+ clock-names = "gpu", "bus", "bus_ace";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_GPU_RESETN>,
+ <&cpg R9A07G044_GPU_AXI_RESETN>,
+ <&cpg R9A07G044_GPU_ACE_RESETN>;
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 5/6] arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
2021-12-03 11:51 ` [PATCH 5/6] arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node Biju Das
@ 2021-12-06 13:30 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2021-12-06 13:30 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Fri, Dec 3, 2021 at 12:52 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add Mali-G31 GPU node to SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 6/6] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
2021-12-03 11:51 ` Biju Das
` (5 preceding siblings ...)
(?)
@ 2021-12-03 11:51 ` Biju Das
2021-12-06 13:34 ` Geert Uytterhoeven
-1 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2021-12-03 11:51 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add vdd core regulator (1.1 V).
This patch add regulator support for gpu.
On the H/W manual nothing mentioned about gpu
regulator. So using vdd core regulator for gpu.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index 41fdae7ba66b..9112e79079a1 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -52,6 +52,15 @@
regulator-always-on;
};
+ reg_1p1v: regulator-vdd-core {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
@@ -130,6 +139,10 @@
clock-frequency = <24000000>;
};
+&gpu {
+ mali-supply = <®_1p1v>;
+};
+
&ostm1 {
status = "okay";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 6/6] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
2021-12-03 11:51 ` [PATCH 6/6] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator Biju Das
@ 2021-12-06 13:34 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2021-12-06 13:34 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Fri, Dec 3, 2021 at 12:52 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add vdd core regulator (1.1 V).
>
> This patch add regulator support for gpu.
>
> On the H/W manual nothing mentioned about gpu
> regulator. So using vdd core regulator for gpu.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread