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From: Bjorn Helgaas <helgaas@kernel.org>
To: "Marek Behún" <kabel@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	pali@kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v4 02/11] PCI: pci-bridge-emul: Add definitions for missing capabilities registers
Date: Fri, 3 Dec 2021 10:45:34 -0600	[thread overview]
Message-ID: <20211203164534.GA3004622@bhelgaas> (raw)
In-Reply-To: <20211130172913.9727-3-kabel@kernel.org>

On Tue, Nov 30, 2021 at 06:29:04PM +0100, Marek Behún wrote:
> From: Pali Rohár <pali@kernel.org>
> 
> pci-bridge-emul driver already allocates buffer for capabilities up to the
> PCI_EXP_SLTSTA2 register, but does not define bit access behavior for these
> registers. Add these missing definitions.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Signed-off-by: Marek Behún <kabel@kernel.org>
> ---
>  drivers/pci/pci-bridge-emul.c | 43 +++++++++++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
> 
> diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
> index a4af1a533d71..0d1177e52a43 100644
> --- a/drivers/pci/pci-bridge-emul.c
> +++ b/drivers/pci/pci-bridge-emul.c
> @@ -251,6 +251,49 @@ struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] =
>  		.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
>  		.w1c = PCI_EXP_RTSTA_PME,
>  	},
> +
> +	[PCI_EXP_DEVCAP2 / 4] = {
> +		/*
> +		 * Device capabilities 2 register has reserved bits [30:27].
> +		 * Also bits [26:24] are reserved for non-upstream ports.
> +		 */
> +		.ro = BIT(31) | GENMASK(23, 0),
> +	},
> +
> +	[PCI_EXP_DEVCTL2 / 4] = {
> +		/*
> +		 * Device control 2 register is RW. Bit 11 is reserved for
> +		 * non-upstream ports.
> +		 *
> +		 * Device status 2 register is reserved.
> +		 */
> +		.rw = GENMASK(15, 12) | GENMASK(10, 0),
> +	},
> +
> +	[PCI_EXP_LNKCAP2 / 4] = {
> +		/* Link capabilities 2 register has reserved bits [30:25] and 0. */

Rewrap (also below).

> +		.ro = BIT(31) | GENMASK(24, 1),
> +	},
> +
> +	[PCI_EXP_LNKCTL2 / 4] = {
> +		/*
> +		 * Link control 2 register is RW.
> +		 *
> +		 * Link status 2 register has bits 5, 15 W1C;
> +		 * bits 10, 11 reserved and others are RO.
> +		 */
> +		.rw = GENMASK(15, 0),
> +		.w1c = (BIT(15) | BIT(5)) << 16,
> +		.ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
> +	},
> +
> +	[PCI_EXP_SLTCAP2 / 4] = {
> +		/* Slot capabilities 2 register is reserved. */
> +	},
> +
> +	[PCI_EXP_SLTCTL2 / 4] = {
> +		/* Both Slot control 2 and Slot status 2 registers are reserved. */
> +	},
>  };
>  
>  /*
> -- 
> 2.32.0
> 

  reply	other threads:[~2021-12-03 16:45 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-30 17:29 [PATCH v4 00/11] PCI: aardvark controller fixes BATCH 3 Marek Behún
2021-11-30 17:29 ` [PATCH v4 01/11] PCI: pci-bridge-emul: Add description for class_revision field Marek Behún
2021-12-03 16:36   ` Bjorn Helgaas
2021-12-03 18:52     ` Marek Behún
2021-11-30 17:29 ` [PATCH v4 02/11] PCI: pci-bridge-emul: Add definitions for missing capabilities registers Marek Behún
2021-12-03 16:45   ` Bjorn Helgaas [this message]
2021-11-30 17:29 ` [PATCH v4 03/11] PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers on emulated bridge Marek Behún
2021-11-30 17:29 ` [PATCH v4 04/11] PCI: aardvark: Clear all MSIs at setup Marek Behún
2021-11-30 17:29 ` [PATCH v4 05/11] PCI: aardvark: Comment actions in driver remove method Marek Behún
2021-11-30 17:29 ` [PATCH v4 06/11] PCI: aardvark: Disable bus mastering when unbinding driver Marek Behún
2021-11-30 17:29 ` [PATCH v4 07/11] PCI: aardvark: Mask all interrupts " Marek Behún
2021-11-30 17:29 ` [PATCH v4 08/11] PCI: aardvark: Fix memory leak in driver unbind Marek Behún
2021-11-30 17:29 ` [PATCH v4 09/11] PCI: aardvark: Assert PERST# when unbinding driver Marek Behún
2021-11-30 17:29 ` [PATCH v4 10/11] PCI: aardvark: Disable link training " Marek Behún
2021-11-30 17:29 ` [PATCH v4 11/11] PCI: aardvark: Disable common PHY " Marek Behún
2021-12-02 10:01 ` [PATCH v4 00/11] PCI: aardvark controller fixes BATCH 3 Lorenzo Pieralisi

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