[PATCH v2 0/3] arm64: Add two HWCAPs for Arm v8.7 FP behaviour

[PATCH v2 0/3] arm64: Add two HWCAPs for Arm v8.7 FP behaviour

[Joey Gouly]

This series adds new HWCAPs for two Arm v8.7 features:
  - FEAT_AFP: Alternate floating-point behavior for specific
    floating point instructions.
  - FEAT_RPRES: Increased precision of Reciprocal Estimate and
    Reciprocal Square Root Estimate from an 8-bit mantissa to a
    12-bit mantissa.

These features can be enabled by userspace by setting some new bits
in FPCR. These new bits are FPCR.{NEP, AH, FIZ}. Since these must be
explicitly enabled by userspace, this should not affect existing
applications.

This has been tested with:
  - FVP: combinations of both features, including mismatched CPUs
  - qemu: regression test, neither feature is supported
  - juno: regression test, neither feature is supported

Changes since v1 [1]:
  - Switch WFxT supported bit to the new value in ID_AA64ISAR2_EL1

Thanks,
Joey

Joey Gouly (3):
  arm64: cpufeature: add HWCAP for FEAT_AFP
  arm64: add ID_AA64ISAR2_EL1 sys register
  arm64: cpufeature: add HWCAP for FEAT_RPRES

 Documentation/arm64/cpu-feature-registers.rst | 17 +++++++++++++++++
 Documentation/arm64/elf_hwcaps.rst            |  8 ++++++++
 arch/arm64/include/asm/cpu.h                  |  1 +
 arch/arm64/include/asm/hwcap.h                |  2 ++
 arch/arm64/include/asm/sysreg.h               | 11 +++++++++++
 arch/arm64/include/uapi/asm/hwcap.h           |  2 ++
 arch/arm64/kernel/cpufeature.c                | 13 +++++++++++++
 arch/arm64/kernel/cpuinfo.c                   |  3 +++
 arch/arm64/kvm/sys_regs.c                     |  2 +-
 9 files changed, 58 insertions(+), 1 deletion(-)

-- 
2.17.1


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[PATCH v2 1/3] arm64: cpufeature: add HWCAP for FEAT_AFP

[Joey Gouly]

Add a new HWCAP to detect the Alternate Floating-point Behaviour
feature (FEAT_AFP), introduced in Armv8.7.

Also expose this to userspace in the ID_AA64MMFR1_EL1 feature register.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 Documentation/arm64/cpu-feature-registers.rst | 9 +++++++++
 Documentation/arm64/elf_hwcaps.rst            | 4 ++++
 arch/arm64/include/asm/hwcap.h                | 1 +
 arch/arm64/include/asm/sysreg.h               | 1 +
 arch/arm64/include/uapi/asm/hwcap.h           | 1 +
 arch/arm64/kernel/cpufeature.c                | 2 ++
 arch/arm64/kernel/cpuinfo.c                   | 1 +
 7 files changed, 19 insertions(+)

diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst
index 9f9b8fd06089..1b19d20c2dbd 100644
--- a/Documentation/arm64/cpu-feature-registers.rst
+++ b/Documentation/arm64/cpu-feature-registers.rst
@@ -275,6 +275,15 @@ infrastructure:
      | SVEVer                       | [3-0]   |    y    |
      +------------------------------+---------+---------+
 
+  8) ID_AA64MMFR1_EL1 - Memory model feature register 1
+
+     +------------------------------+---------+---------+
+     | Name                         |  bits   | visible |
+     +------------------------------+---------+---------+
+     | AFP                          | [47-44] |    y    |
+     +------------------------------+---------+---------+
+
+
 Appendix I: Example
 -------------------
 
diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
index af106af8e1c0..247728d37911 100644
--- a/Documentation/arm64/elf_hwcaps.rst
+++ b/Documentation/arm64/elf_hwcaps.rst
@@ -251,6 +251,10 @@ HWCAP2_ECV
 
     Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.
 
+HWCAP2_AFP
+
+    Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001.
+
 4. Unused AT_HWCAP bits
 -----------------------
 
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index b100e0055eab..2809df2fdd63 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -106,6 +106,7 @@
 #define KERNEL_HWCAP_BTI		__khwcap2_feature(BTI)
 #define KERNEL_HWCAP_MTE		__khwcap2_feature(MTE)
 #define KERNEL_HWCAP_ECV		__khwcap2_feature(ECV)
+#define KERNEL_HWCAP_AFP		__khwcap2_feature(AFP)
 
 /*
  * This yields a mask that user programs can use to figure out what
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 16b3f1a1d468..adcab9009f9d 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -889,6 +889,7 @@
 #endif
 
 /* id_aa64mmfr1 */
+#define ID_AA64MMFR1_AFP_SHIFT		44
 #define ID_AA64MMFR1_ETS_SHIFT		36
 #define ID_AA64MMFR1_TWED_SHIFT		32
 #define ID_AA64MMFR1_XNX_SHIFT		28
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index 7b23b16f21ce..180da7396549 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -76,5 +76,6 @@
 #define HWCAP2_BTI		(1 << 17)
 #define HWCAP2_MTE		(1 << 18)
 #define HWCAP2_ECV		(1 << 19)
+#define HWCAP2_AFP		(1 << 20)
 
 #endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 6f3e677d88f1..71ff5a4afb0f 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -325,6 +325,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
+	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
@@ -2476,6 +2477,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
 #endif /* CONFIG_ARM64_MTE */
 	HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
+	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
 	{},
 };
 
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 6e27b759056a..0e52014019f6 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -95,6 +95,7 @@ static const char *const hwcap_str[] = {
 	[KERNEL_HWCAP_BTI]		= "bti",
 	[KERNEL_HWCAP_MTE]		= "mte",
 	[KERNEL_HWCAP_ECV]		= "ecv",
+	[KERNEL_HWCAP_AFP]		= "afp",
 };
 
 #ifdef CONFIG_COMPAT
-- 
2.17.1


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[PATCH v2 2/3] arm64: add ID_AA64ISAR2_EL1 sys register

[Joey Gouly]

This is a new ID register, introduced in 8.7.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Reiji Watanabe <reijiw@google.com>
---
 arch/arm64/include/asm/cpu.h    |  1 +
 arch/arm64/include/asm/sysreg.h | 10 ++++++++++
 arch/arm64/kernel/cpufeature.c  |  9 +++++++++
 arch/arm64/kernel/cpuinfo.c     |  1 +
 arch/arm64/kvm/sys_regs.c       |  2 +-
 5 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index 0f6d16faa540..a58e366f0b07 100644
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -51,6 +51,7 @@ struct cpuinfo_arm64 {
 	u64		reg_id_aa64dfr1;
 	u64		reg_id_aa64isar0;
 	u64		reg_id_aa64isar1;
+	u64		reg_id_aa64isar2;
 	u64		reg_id_aa64mmfr0;
 	u64		reg_id_aa64mmfr1;
 	u64		reg_id_aa64mmfr2;
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index adcab9009f9d..5393a00340f5 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -182,6 +182,7 @@
 
 #define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
 #define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
+#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)
 
 #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
 #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
@@ -771,6 +772,15 @@
 #define ID_AA64ISAR1_GPI_NI			0x0
 #define ID_AA64ISAR1_GPI_IMP_DEF		0x1
 
+/* id_aa64isar2 */
+#define ID_AA64ISAR2_RPRES_SHIFT	4
+#define ID_AA64ISAR2_WFXT_SHIFT		0
+
+#define ID_AA64ISAR2_RPRES_8BIT		0x0
+#define ID_AA64ISAR2_RPRES_12BIT	0x1
+#define ID_AA64ISAR2_WFXT_NI		0x0
+#define ID_AA64ISAR2_WFXT_SUPPORTED	0x2
+
 /* id_aa64pfr0 */
 #define ID_AA64PFR0_CSV3_SHIFT		60
 #define ID_AA64PFR0_CSV2_SHIFT		56
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 71ff5a4afb0f..c36018310da5 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -225,6 +225,10 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 	ARM64_FTR_END,
 };
 
+static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
+	ARM64_FTR_END,
+};
+
 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
@@ -638,6 +642,7 @@ static const struct __ftr_reg_entry {
 	ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
 			       &id_aa64isar1_override),
+	ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
 
 	/* Op1 = 0, CRn = 0, CRm = 7 */
 	ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
@@ -934,6 +939,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
 	init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 	init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 	init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
+	init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
 	init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 	init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 	init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
@@ -1152,6 +1158,8 @@ void update_cpu_features(int cpu,
 				      info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 	taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 				      info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
+	taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
+				      info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
 
 	/*
 	 * Differing PARange support is fine as long as all peripherals and
@@ -1273,6 +1281,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id)
 	read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 	read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 	read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
+	read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
 
 	read_sysreg_case(SYS_CNTFRQ_EL0);
 	read_sysreg_case(SYS_CTR_EL0);
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 0e52014019f6..f2f8fe02f39c 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -392,6 +392,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
 	info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
 	info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
 	info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
+	info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
 	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
 	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
 	info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index e3ec1a44f94d..4dc2fba316ff 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1525,7 +1525,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	/* CRm=6 */
 	ID_SANITISED(ID_AA64ISAR0_EL1),
 	ID_SANITISED(ID_AA64ISAR1_EL1),
-	ID_UNALLOCATED(6,2),
+	ID_SANITISED(ID_AA64ISAR2_EL1),
 	ID_UNALLOCATED(6,3),
 	ID_UNALLOCATED(6,4),
 	ID_UNALLOCATED(6,5),
-- 
2.17.1


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[PATCH v2 3/3] arm64: cpufeature: add HWCAP for FEAT_RPRES

[Joey Gouly]

Add a new HWCAP to detect the Increased precision of Reciprocal Estimate
and Reciprocal Square Root Estimate feature (FEAT_RPRES), introduced in Armv8.7.

Also expose this to userspace in the ID_AA64ISAR2_EL1 feature register.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
---
 Documentation/arm64/cpu-feature-registers.rst | 8 ++++++++
 Documentation/arm64/elf_hwcaps.rst            | 4 ++++
 arch/arm64/include/asm/hwcap.h                | 1 +
 arch/arm64/include/uapi/asm/hwcap.h           | 1 +
 arch/arm64/kernel/cpufeature.c                | 2 ++
 arch/arm64/kernel/cpuinfo.c                   | 1 +
 6 files changed, 17 insertions(+)

diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst
index 1b19d20c2dbd..749ae970c319 100644
--- a/Documentation/arm64/cpu-feature-registers.rst
+++ b/Documentation/arm64/cpu-feature-registers.rst
@@ -283,6 +283,14 @@ infrastructure:
      | AFP                          | [47-44] |    y    |
      +------------------------------+---------+---------+
 
+  9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+
+     +------------------------------+---------+---------+
+     | Name                         |  bits   | visible |
+     +------------------------------+---------+---------+
+     | RPRES                        | [7-4]   |    y    |
+     +------------------------------+---------+---------+
+
 
 Appendix I: Example
 -------------------
diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
index 247728d37911..b72ff17d600a 100644
--- a/Documentation/arm64/elf_hwcaps.rst
+++ b/Documentation/arm64/elf_hwcaps.rst
@@ -255,6 +255,10 @@ HWCAP2_AFP
 
     Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001.
 
+HWCAP2_RPRES
+
+    Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.
+
 4. Unused AT_HWCAP bits
 -----------------------
 
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 2809df2fdd63..f68fbb207473 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -107,6 +107,7 @@
 #define KERNEL_HWCAP_MTE		__khwcap2_feature(MTE)
 #define KERNEL_HWCAP_ECV		__khwcap2_feature(ECV)
 #define KERNEL_HWCAP_AFP		__khwcap2_feature(AFP)
+#define KERNEL_HWCAP_RPRES		__khwcap2_feature(RPRES)
 
 /*
  * This yields a mask that user programs can use to figure out what
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index 180da7396549..f03731847d9d 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -77,5 +77,6 @@
 #define HWCAP2_MTE		(1 << 18)
 #define HWCAP2_ECV		(1 << 19)
 #define HWCAP2_AFP		(1 << 20)
+#define HWCAP2_RPRES		(1 << 21)
 
 #endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index c36018310da5..a46ab3b1c4d5 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -226,6 +226,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
+	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
 	ARM64_FTR_END,
 };
 
@@ -2487,6 +2488,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 #endif /* CONFIG_ARM64_MTE */
 	HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
 	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
+	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
 	{},
 };
 
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index f2f8fe02f39c..591c18a889a5 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -96,6 +96,7 @@ static const char *const hwcap_str[] = {
 	[KERNEL_HWCAP_MTE]		= "mte",
 	[KERNEL_HWCAP_ECV]		= "ecv",
 	[KERNEL_HWCAP_AFP]		= "afp",
+	[KERNEL_HWCAP_RPRES]		= "rpres",
 };
 
 #ifdef CONFIG_COMPAT
-- 
2.17.1


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Re: [PATCH v2 2/3] arm64: add ID_AA64ISAR2_EL1 sys register

[Marc Zyngier]

Hi Joey,

On Tue, 07 Dec 2021 12:42:25 +0000,
Joey Gouly <joey.gouly@arm.com> wrote:
> 
> This is a new ID register, introduced in 8.7.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: James Morse <james.morse@arm.com>
> Cc: Alexandru Elisei <alexandru.elisei@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Reiji Watanabe <reijiw@google.com>
> ---
>  arch/arm64/include/asm/cpu.h    |  1 +
>  arch/arm64/include/asm/sysreg.h | 10 ++++++++++
>  arch/arm64/kernel/cpufeature.c  |  9 +++++++++
>  arch/arm64/kernel/cpuinfo.c     |  1 +
>  arch/arm64/kvm/sys_regs.c       |  2 +-
>  5 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> index 0f6d16faa540..a58e366f0b07 100644
> --- a/arch/arm64/include/asm/cpu.h
> +++ b/arch/arm64/include/asm/cpu.h
> @@ -51,6 +51,7 @@ struct cpuinfo_arm64 {
>  	u64		reg_id_aa64dfr1;
>  	u64		reg_id_aa64isar0;
>  	u64		reg_id_aa64isar1;
> +	u64		reg_id_aa64isar2;
>  	u64		reg_id_aa64mmfr0;
>  	u64		reg_id_aa64mmfr1;
>  	u64		reg_id_aa64mmfr2;
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index adcab9009f9d..5393a00340f5 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -182,6 +182,7 @@
>  
>  #define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
>  #define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
> +#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)
>  
>  #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
>  #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
> @@ -771,6 +772,15 @@
>  #define ID_AA64ISAR1_GPI_NI			0x0
>  #define ID_AA64ISAR1_GPI_IMP_DEF		0x1
>  
> +/* id_aa64isar2 */
> +#define ID_AA64ISAR2_RPRES_SHIFT	4
> +#define ID_AA64ISAR2_WFXT_SHIFT		0
> +
> +#define ID_AA64ISAR2_RPRES_8BIT		0x0
> +#define ID_AA64ISAR2_RPRES_12BIT	0x1
> +#define ID_AA64ISAR2_WFXT_NI		0x0
> +#define ID_AA64ISAR2_WFXT_SUPPORTED	0x2

Maybe I wasn't clear in my earlier comment: you need to enumerate all
the architecturally valid values:

#define ID_AA64ISAR2_WFXT_NI		0x0
#define ID_AA64ISAR2_WFXT_V1		0x1
#define ID_AA64ISAR2_WFXT_V2		0x2

where WFXT_V1 represent the original FEAT_WFxT, and WFXT_V2 the new,
more usable FEAT_WFxT2. Even if the original FEAT_WFxT is deprecated,
it still exists, and is still the only mandatory option for v8.7.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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Re: [PATCH v2 2/3] arm64: add ID_AA64ISAR2_EL1 sys register

[Joey Gouly]

Hi Marc,

On Tue, Dec 07, 2021 at 12:54:32PM +0000, Marc Zyngier wrote:
> Hi Joey,
> 
> On Tue, 07 Dec 2021 12:42:25 +0000,

[...]

> > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > index adcab9009f9d..5393a00340f5 100644
> > --- a/arch/arm64/include/asm/sysreg.h
> > +++ b/arch/arm64/include/asm/sysreg.h
> > @@ -182,6 +182,7 @@
> >  
> >  #define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
> >  #define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
> > +#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)
> >  
> >  #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
> >  #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
> > @@ -771,6 +772,15 @@
> >  #define ID_AA64ISAR1_GPI_NI			0x0
> >  #define ID_AA64ISAR1_GPI_IMP_DEF		0x1
> >  
> > +/* id_aa64isar2 */
> > +#define ID_AA64ISAR2_RPRES_SHIFT	4
> > +#define ID_AA64ISAR2_WFXT_SHIFT		0
> > +
> > +#define ID_AA64ISAR2_RPRES_8BIT		0x0
> > +#define ID_AA64ISAR2_RPRES_12BIT	0x1
> > +#define ID_AA64ISAR2_WFXT_NI		0x0
> > +#define ID_AA64ISAR2_WFXT_SUPPORTED	0x2
> 
> Maybe I wasn't clear in my earlier comment: you need to enumerate all
> the architecturally valid values:
> 
> #define ID_AA64ISAR2_WFXT_NI		0x0
> #define ID_AA64ISAR2_WFXT_V1		0x1
> #define ID_AA64ISAR2_WFXT_V2		0x2
> 
> where WFXT_V1 represent the original FEAT_WFxT, and WFXT_V2 the new,
> more usable FEAT_WFxT2. Even if the original FEAT_WFxT is deprecated,
> it still exists, and is still the only mandatory option for v8.7.

The 0b001 behaviour has been removed from the architecture and is now listed as
reserved, but this has not made it's way into an ARM ARM. The only permitted
values are 0b000 and 0b0001 (mandatory in v8.7)

This can be seen from the documentation here:
  https://developer.arm.com/documentation/ddi0601/2021-09/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en

Thanks,
Joey

> 
> Thanks,
> 
> 	M.
> 
> -- 
> Without deviation from the norm, progress is not possible.

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Re: [PATCH v2 2/3] arm64: add ID_AA64ISAR2_EL1 sys register

[Marc Zyngier]

On Tue, 07 Dec 2021 14:31:21 +0000,
Joey Gouly <joey.gouly@arm.com> wrote:
> 
> Hi Marc,
> 
> On Tue, Dec 07, 2021 at 12:54:32PM +0000, Marc Zyngier wrote:
> > Hi Joey,
> > 
> > On Tue, 07 Dec 2021 12:42:25 +0000,
> 
> [...]
> 
> > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > > index adcab9009f9d..5393a00340f5 100644
> > > --- a/arch/arm64/include/asm/sysreg.h
> > > +++ b/arch/arm64/include/asm/sysreg.h
> > > @@ -182,6 +182,7 @@
> > >  
> > >  #define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
> > >  #define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
> > > +#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)
> > >  
> > >  #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
> > >  #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
> > > @@ -771,6 +772,15 @@
> > >  #define ID_AA64ISAR1_GPI_NI			0x0
> > >  #define ID_AA64ISAR1_GPI_IMP_DEF		0x1
> > >  
> > > +/* id_aa64isar2 */
> > > +#define ID_AA64ISAR2_RPRES_SHIFT	4
> > > +#define ID_AA64ISAR2_WFXT_SHIFT		0
> > > +
> > > +#define ID_AA64ISAR2_RPRES_8BIT		0x0
> > > +#define ID_AA64ISAR2_RPRES_12BIT	0x1
> > > +#define ID_AA64ISAR2_WFXT_NI		0x0
> > > +#define ID_AA64ISAR2_WFXT_SUPPORTED	0x2
> > 
> > Maybe I wasn't clear in my earlier comment: you need to enumerate all
> > the architecturally valid values:
> > 
> > #define ID_AA64ISAR2_WFXT_NI		0x0
> > #define ID_AA64ISAR2_WFXT_V1		0x1
> > #define ID_AA64ISAR2_WFXT_V2		0x2
> > 
> > where WFXT_V1 represent the original FEAT_WFxT, and WFXT_V2 the new,
> > more usable FEAT_WFxT2. Even if the original FEAT_WFxT is deprecated,
> > it still exists, and is still the only mandatory option for v8.7.
> 
> The 0b001 behaviour has been removed from the architecture and is
> now listed as reserved, but this has not made it's way into an ARM
> ARM. The only permitted values are 0b000 and 0b0001 (mandatory in
> v8.7)

0b0010, right?

> 
> This can be seen from the documentation here:
>   https://developer.arm.com/documentation/ddi0601/2021-09/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en

Yay for retrospective changes to the architecture! :D I guess that
nobody dared building the broken version, so it's all good. Maybe add
a small comment to that effect, so that people looking at outdated
material don't get confused?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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Re: [PATCH v2 2/3] arm64: add ID_AA64ISAR2_EL1 sys register

[Joey Gouly]

On Tue, Dec 07, 2021 at 02:49:02PM +0000, Marc Zyngier wrote:
> On Tue, 07 Dec 2021 14:31:21 +0000,
> Joey Gouly <joey.gouly@arm.com> wrote:
> > 
> > Hi Marc,
> > 
> > On Tue, Dec 07, 2021 at 12:54:32PM +0000, Marc Zyngier wrote:
> > > Hi Joey,
> > > 
> > > On Tue, 07 Dec 2021 12:42:25 +0000,
> > 
> > [...]
> > 
> > > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > > > index adcab9009f9d..5393a00340f5 100644
> > > > --- a/arch/arm64/include/asm/sysreg.h
> > > > +++ b/arch/arm64/include/asm/sysreg.h
> > > > @@ -182,6 +182,7 @@
> > > >  
> > > >  #define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
> > > >  #define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
> > > > +#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)
> > > >  
> > > >  #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
> > > >  #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
> > > > @@ -771,6 +772,15 @@
> > > >  #define ID_AA64ISAR1_GPI_NI			0x0
> > > >  #define ID_AA64ISAR1_GPI_IMP_DEF		0x1
> > > >  
> > > > +/* id_aa64isar2 */
> > > > +#define ID_AA64ISAR2_RPRES_SHIFT	4
> > > > +#define ID_AA64ISAR2_WFXT_SHIFT		0
> > > > +
> > > > +#define ID_AA64ISAR2_RPRES_8BIT		0x0
> > > > +#define ID_AA64ISAR2_RPRES_12BIT	0x1
> > > > +#define ID_AA64ISAR2_WFXT_NI		0x0
> > > > +#define ID_AA64ISAR2_WFXT_SUPPORTED	0x2
> > > 
> > > Maybe I wasn't clear in my earlier comment: you need to enumerate all
> > > the architecturally valid values:
> > > 
> > > #define ID_AA64ISAR2_WFXT_NI		0x0
> > > #define ID_AA64ISAR2_WFXT_V1		0x1
> > > #define ID_AA64ISAR2_WFXT_V2		0x2
> > > 
> > > where WFXT_V1 represent the original FEAT_WFxT, and WFXT_V2 the new,
> > > more usable FEAT_WFxT2. Even if the original FEAT_WFxT is deprecated,
> > > it still exists, and is still the only mandatory option for v8.7.
> > 
> > The 0b001 behaviour has been removed from the architecture and is
> > now listed as reserved, but this has not made it's way into an ARM
> > ARM. The only permitted values are 0b000 and 0b0001 (mandatory in
> > v8.7)
> 
> 0b0010, right?

Sigh.. yes. Typing is hard!

> 
> > 
> > This can be seen from the documentation here:
> >   https://developer.arm.com/documentation/ddi0601/2021-09/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en
> 
> Yay for retrospective changes to the architecture! :D I guess that
> nobody dared building the broken version, so it's all good. Maybe add
> a small comment to that effect, so that people looking at outdated
> material don't get confused?

Good idea, will add a comment for v3.

Thanks,
Joey

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