* [igt-dev] [PATCH v4 0/2] tests/amdgpu: Introduce DSC tests
@ 2021-12-07 16:43 Rodrigo Siqueira
2021-12-07 16:43 ` [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property Rodrigo Siqueira
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Rodrigo Siqueira @ 2021-12-07 16:43 UTC (permalink / raw)
To: igt-dev; +Cc: Mikita Lipski, Hersen Wu, Roman Li, Hayden Goodfellow
This patchset introduces a set of DSC tests focused on AMDGPU.
Changes since v3:
- Rebase and fix conflicts
Eryk Brol (1):
tests/amdgpu: Introduces DP DSC test
Rodrigo Siqueira (1):
lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
lib/igt_amd.c | 494 +++++++++++++++++++++++++--
lib/igt_amd.h | 35 ++
lib/igt_kms.c | 1 +
lib/igt_kms.h | 1 +
tests/amdgpu/amd_dp_dsc.c | 685 ++++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
6 files changed, 1195 insertions(+), 22 deletions(-)
create mode 100644 tests/amdgpu/amd_dp_dsc.c
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
2021-12-07 16:43 [igt-dev] [PATCH v4 0/2] tests/amdgpu: Introduce DSC tests Rodrigo Siqueira
@ 2021-12-07 16:43 ` Rodrigo Siqueira
2021-12-09 1:48 ` Rodrigo Siqueira Jordao
2021-12-07 16:43 ` [igt-dev] [PATCH v4 2/2] tests/amdgpu: Introduces DP DSC test Rodrigo Siqueira
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Rodrigo Siqueira @ 2021-12-07 16:43 UTC (permalink / raw)
To: igt-dev
Cc: Petri Latvala, Mikita Lipski, Hersen Wu, Roman Li, Hayden Goodfellow
This preparation work introduces a new CRTC property named
DSC_SLICE_HEIGHT, which will be required for amdgpu DSC tests.
Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
lib/igt_kms.c | 1 +
lib/igt_kms.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 34a2aa00..fdadb6d6 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -593,6 +593,7 @@ const char * const igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
[IGT_CRTC_ACTIVE] = "ACTIVE",
[IGT_CRTC_OUT_FENCE_PTR] = "OUT_FENCE_PTR",
[IGT_CRTC_VRR_ENABLED] = "VRR_ENABLED",
+ [IGT_CRTC_DSC_SLICE_HEIGHT] = "DSC_SLICE_HEIGHT",
};
const char * const igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index e9ecd21e..5c7d7481 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -125,6 +125,7 @@ enum igt_atomic_crtc_properties {
IGT_CRTC_ACTIVE,
IGT_CRTC_OUT_FENCE_PTR,
IGT_CRTC_VRR_ENABLED,
+ IGT_CRTC_DSC_SLICE_HEIGHT,
IGT_NUM_CRTC_PROPS
};
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [igt-dev] [PATCH v4 2/2] tests/amdgpu: Introduces DP DSC test
2021-12-07 16:43 [igt-dev] [PATCH v4 0/2] tests/amdgpu: Introduce DSC tests Rodrigo Siqueira
2021-12-07 16:43 ` [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property Rodrigo Siqueira
@ 2021-12-07 16:43 ` Rodrigo Siqueira
2021-12-07 19:21 ` [igt-dev] ✓ Fi.CI.BAT: success for tests/amdgpu: Introduce DSC tests (rev2) Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Siqueira @ 2021-12-07 16:43 UTC (permalink / raw)
To: igt-dev; +Cc: Eryk Brol, Roman Li, Hersen Wu, Hayden Goodfellow, Mikita Lipski
From: Eryk Brol <eryk.brol@amd.com>
This commit adds a DP DSC test that checks:
* Forces DSC on/off and ensures it is reset properly
* Check DSC slice height property
* Verify various DSC slice dimensions
* Tests various combinations of link_rate + lane_count and logs if DSC
enabled/disabled Tests different bpc settings and logs if DSC is
enabled/disabled
Change since V2:
- Remove IGT_CRTC_DSC_SLICE_HEIGHT crtc property from this commit
Change since V1:
- Rebase
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Choi <Nicholas.Choi@amd.com>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Hayden Goodfellow <hayden.goodfellow@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Roman Li <roman.li@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
---
lib/igt_amd.c | 494 +++++++++++++++++++++++++--
lib/igt_amd.h | 35 ++
tests/amdgpu/amd_dp_dsc.c | 685 ++++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
4 files changed, 1193 insertions(+), 22 deletions(-)
create mode 100644 tests/amdgpu/amd_dp_dsc.c
diff --git a/lib/igt_amd.c b/lib/igt_amd.c
index f1bfb421..4bcfd594 100644
--- a/lib/igt_amd.c
+++ b/lib/igt_amd.c
@@ -251,11 +251,11 @@ bool igt_amd_is_tiled(uint64_t modifier)
}
/**
- * igt_amd_output_has_hpd: check if connector has HPD debugfs entry
+ * igt_amd_output_has_dsc: check if connector has dsc debugfs entry
* @drm_fd: DRM file descriptor
* @connector_name: The connector's name, on which we're reading the status
*/
-static bool igt_amd_output_has_hpd(int drm_fd, char *connector_name)
+static bool igt_amd_output_has_dsc(int drm_fd, char *connector_name)
{
int fd;
int res;
@@ -267,9 +267,9 @@ static bool igt_amd_output_has_hpd(int drm_fd, char *connector_name)
return false;
}
- res = fstatat(fd, DEBUGFS_HPD_TRIGGER, &stat, 0);
+ res = fstatat(fd, DEBUGFS_DSC_CLOCK_EN , &stat, 0);
if (res != 0) {
- igt_info("%s debugfs not supported\n", DEBUGFS_HPD_TRIGGER);
+ igt_info("%s debugfs not supported\n", DEBUGFS_DSC_CLOCK_EN);
close(fd);
return false;
}
@@ -279,49 +279,499 @@ static bool igt_amd_output_has_hpd(int drm_fd, char *connector_name)
}
/**
- * igt_amd_require_hpd: Checks if connectors have HPD debugfs
+ * is_dp_dsc_supported: Checks if connector is DSC capable
+ * @display: A pointer to an #igt_display_t structure
+ * @drm_fd: DRM file descriptor
+ */
+bool is_dp_dsc_supported(int drm_fd, char *connector_name)
+{
+ char buf[512];
+ int fd, ret;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+
+ if (fd < 0) {
+ igt_info("Couldn't open connector %s debugfs directory\n",
+ connector_name);
+ return false;
+ }
+
+ ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_FEC_SUPPORT, buf, sizeof(buf));
+ close(fd);
+
+ igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
+ DEBUGFS_DSC_FEC_SUPPORT, connector_name);
+
+ return strstr(buf, "DSC_Sink_Support: yes");
+}
+
+/**
+ * is_dp_fec_supported: Checks if connector is FEC capable
+ * @display: A pointer to an #igt_display_t structure
+ * @drm_fd: DRM file descriptor
+ */
+bool is_dp_fec_supported(int drm_fd, char *connector_name)
+{
+ char buf[512];
+ int fd, ret;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+
+ if (fd < 0) {
+ igt_info("Couldn't open connector %s debugfs directory\n",
+ connector_name);
+ return false;
+ }
+
+ ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_FEC_SUPPORT, buf, sizeof(buf));
+ close(fd);
+
+ igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
+ DEBUGFS_DSC_FEC_SUPPORT, connector_name);
+
+ return strstr(buf, "FEC_Sink_Support: yes");
+}
+
+/**
+ * igt_amd_require_dsc: Checks if connectors have DSC debugfs
* @display: A pointer to an #igt_display_t structure
* @drm_fd: DRM file descriptor
*
- * Checks if the AMDGPU driver has support the 'trigger_hotplug'
- * entry for HPD. Skip test if HPD is not supported.
+ * Checks if the AMDGPU driver has support of debugfs entries for
+ * DSC. Skip test if DSC is not supported.
*/
-void igt_amd_require_hpd(igt_display_t *display, int drm_fd)
+void igt_amd_require_dsc(igt_display_t *display, int drm_fd)
{
igt_output_t *output;
for_each_connected_output(display, output) {
- if (igt_amd_output_has_hpd(drm_fd, output->name))
+ if (igt_amd_output_has_dsc(drm_fd, output->name))
return;
}
- igt_skip("No HPD debugfs support.\n");
+ igt_skip("No DSC debugfs support.\n");
}
/**
- * igt_amd_trigger_hotplut: Triggers a debugfs HPD
+ * igt_amd_read_dsc_clock_status: Read the DSC Clock Enable debugfs
* @drm_fd: DRM file descriptor
- * @connector_name: The connector's name, which we trigger the hotplug on
+ * @connector_name: The connector's name, which we use to read status on
*
- * igt_amd_require_hpd should be called before calling this.
*/
-int igt_amd_trigger_hotplug(int drm_fd, char *connector_name)
+int igt_amd_read_dsc_clock_status(int drm_fd, char *connector_name)
+{
+ char buf[4];
+ int fd, ret;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ if (fd < 0) {
+ igt_info("Couldn't open connector %s debugfs directory\n",
+ connector_name);
+ return false;
+ }
+ ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_CLOCK_EN, buf, sizeof(buf));
+ close(fd);
+
+ igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
+ DEBUGFS_DSC_CLOCK_EN, connector_name);
+
+ return strtol(buf, NULL, 0);
+}
+
+
+/**
+ * igt_amd_write_dsc_clock_en: Write the DSC Clock Enable debugfs
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we use to read status on
+ * @dsc_force: DSC force parameter, 0 - DSC automatic, 1 - DSC force on,
+ * 2 - DSC force off
+ *
+ */
+void igt_amd_write_dsc_clock_en(int drm_fd, char *connector_name, int dsc_force)
+{
+ int fd, dsc_fd;
+ char src[4];
+ int wr_len;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ igt_assert(fd >= 0);
+ dsc_fd = openat(fd, DEBUGFS_DSC_CLOCK_EN, O_WRONLY);
+ close(fd);
+ igt_assert(dsc_fd >= 0);
+
+ if (dsc_force == DSC_FORCE_ON)
+ snprintf(src, sizeof(src), "%d", 1);
+ else if (dsc_force == DSC_FORCE_OFF)
+ snprintf(src, sizeof(src), "%d", 2);
+ else
+ snprintf(src, sizeof(src), "%d", 0);
+
+ igt_info("DSC Clock force, write %s > dsc_clock_en\n", src);
+
+ wr_len = write(dsc_fd, src, strlen(src));
+ close(dsc_fd);
+ igt_assert_eq(wr_len, strlen(src));
+}
+
+/**
+ * igt_amd_write_dsc_param_slice_height: Write the DSC Slice Height debugfs
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we use to read status on
+ * @slice_height: DSC slice height parameter, accepts any positive integer,
+ * if parameter is negative - it will not write to debugfs.
+ *
+ */
+void igt_amd_write_dsc_param_slice_height(int drm_fd, char *connector_name, int slice_height)
+{
+ int fd, dsc_fd;
+ char src[32];
+ int wr_len;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ igt_assert(fd >= 0);
+ dsc_fd = openat(fd, DEBUGFS_DSC_SLICE_HEIGHT, O_WRONLY);
+ close(fd);
+ igt_assert(dsc_fd >= 0);
+
+ if (slice_height >= 0) {
+ snprintf(src, sizeof(src), "%#x", slice_height);
+ } else {
+ igt_warn("DSC SLICE HEIGHT, slice height parameter is invalid (%d)\n", slice_height);
+ goto exit;
+ }
+
+ igt_info("DSC SLICE HEIGHT, write %s > dsc_slice_height\n", src);
+
+ wr_len = write(dsc_fd, src, strlen(src));
+ igt_assert_eq(wr_len, strlen(src));
+exit:
+ close(dsc_fd);
+}
+
+/**
+ * igt_amd_read_dsc_param_slice_height: Read the DSC Slice Height debugfs
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we use to read status on
+ *
+ */
+int igt_amd_read_dsc_param_slice_height(int drm_fd, char *connector_name)
+{
+ char buf[32];
+ int fd, ret;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ if (fd < 0) {
+ igt_info("Couldn't open connector %s debugfs directory\n",
+ connector_name);
+ return false;
+ }
+ ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_SLICE_HEIGHT, buf, sizeof(buf));
+ close(fd);
+
+ igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
+ DEBUGFS_DSC_SLICE_HEIGHT, connector_name);
+
+ return strtol(buf, NULL, 0);
+}
+
+/**
+ * igt_amd_write_dsc_param_slice_width: Write the DSC Slice Width debugfs
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we use to read status on
+ * @slice_width: DSC slice width parameter, accepts any positive integer,
+ * if parameter is negative - it will not write to debugfs.
+ *
+ */
+void igt_amd_write_dsc_param_slice_width(int drm_fd, char *connector_name, int slice_width)
{
- int fd, hpd_fd;
+ int fd, dsc_fd;
+ char src[32];
int wr_len;
- const char *enable_hpd = "1";
fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
igt_assert(fd >= 0);
- hpd_fd = openat(fd, DEBUGFS_HPD_TRIGGER, O_WRONLY);
+ dsc_fd = openat(fd, DEBUGFS_DSC_SLICE_WIDTH, O_WRONLY);
+ close(fd);
+ igt_assert(dsc_fd >= 0);
+
+ if (slice_width >= 0) {
+ snprintf(src, sizeof(src), "%#x", slice_width);
+ } else {
+ igt_warn("DSC SLICE WIDTH, slice width parameter is invalid (%d)\n", slice_width);
+ goto exit;
+ }
+
+ igt_info("DSC SLICE WIDTH, write %s > dsc_slice_width\n", src);
+
+ wr_len = write(dsc_fd, src, strlen(src));
+ igt_assert_eq(wr_len, strlen(src));
+exit:
+ close(dsc_fd);
+}
+
+/**
+ * igt_amd_read_dsc_param_slice_width: Read the DSC Slice Width debugfs
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we use to read status on
+ *
+ */
+int igt_amd_read_dsc_param_slice_width(int drm_fd, char *connector_name)
+{
+ char buf[32];
+ int fd, ret;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ if (fd < 0) {
+ igt_info("Couldn't open connector %s debugfs directory\n",
+ connector_name);
+ return false;
+ }
+ ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_SLICE_WIDTH, buf, sizeof(buf));
close(fd);
- igt_assert(hpd_fd >= 0);
- wr_len = write(hpd_fd, enable_hpd, strlen(enable_hpd));
- close(hpd_fd);
- igt_assert_eq(wr_len, strlen(enable_hpd));
+ igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
+ DEBUGFS_DSC_SLICE_WIDTH, connector_name);
+
+ return strtol(buf, NULL, 0);
+}
+
+/**
+ * igt_amd_write_dsc_param_bpp: Write the DSC Bits Per Pixel debugfs
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we use to read status on
+ * @bpp: DSC bits per pixel parameter, accepts any positive integer,
+ * if parameter is negative - it will not write to debugfs.
+ *
+ */
+void igt_amd_write_dsc_param_bpp(int drm_fd, char *connector_name, int bpp)
+{
+ int fd, dsc_fd;
+ char src[32];
+ int wr_len;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ igt_assert(fd >= 0);
+ dsc_fd = openat(fd, DEBUGFS_DSC_BITS_PER_PIXEL, O_WRONLY);
+ close(fd);
+ igt_assert(dsc_fd >= 0);
+
+ if (bpp >= 0) {
+ snprintf(src, sizeof(src), "%#x", bpp);
+ } else {
+ igt_warn("DSC BITS PER PIXEL, bits per pixel parameter is invalid (%d)\n", bpp);
+ goto exit;
+ }
+
+ igt_info("DSC BITS PER PIXEL, write %s > dsc_bits_per_pixel\n", src);
+
+ wr_len = write(dsc_fd, src, strlen(src));
+ igt_assert_eq(wr_len, strlen(src));
+exit:
+ close(dsc_fd);
+}
+
+/**
+ * igt_amd_read_dsc_param_bpp: Read the DSC Bits Per Pixel debugfs
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we use to read status on
+ *
+ */
+int igt_amd_read_dsc_param_bpp(int drm_fd, char *connector_name)
+{
+ char buf[32];
+ int fd, ret;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ if (fd < 0) {
+ igt_info("Couldn't open connector %s debugfs directory\n",
+ connector_name);
+ return false;
+ }
+ ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_BITS_PER_PIXEL, buf, sizeof(buf));
+ close(fd);
+
+ igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
+ DEBUGFS_DSC_BITS_PER_PIXEL, connector_name);
+
+ return strtol(buf, NULL, 0);
+}
+
+/**
+ * igt_amd_read_dsc_param_pic_width: Read the DSC Picture Width debugfs
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we use to read status on
+ *
+ */
+int igt_amd_read_dsc_param_pic_width(int drm_fd, char *connector_name)
+{
+ char buf[4];
+ int fd, ret;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ if (fd < 0) {
+ igt_info("Couldn't open connector %s debugfs directory\n",
+ connector_name);
+ return false;
+ }
+ ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_PIC_WIDTH, buf, sizeof(buf));
+ close(fd);
+
+ igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
+ DEBUGFS_DSC_PIC_WIDTH, connector_name);
+
+ return strtol(buf, NULL, 0);
+}
+
+/**
+ * igt_amd_read_dsc_param_pic_height: Read the DSC Picture Height debugfs
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we use to read status on
+ *
+ */
+int igt_amd_read_dsc_param_pic_height(int drm_fd, char *connector_name)
+{
+ char buf[4];
+ int fd, ret;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ if (fd < 0) {
+ igt_info("Couldn't open connector %s debugfs directory\n",
+ connector_name);
+ return false;
+ }
+ ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_PIC_HEIGHT, buf, sizeof(buf));
+ close(fd);
+
+ igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
+ DEBUGFS_DSC_PIC_HEIGHT, connector_name);
+
+ return strtol(buf, NULL, 0);
+}
+
+/**
+ * igt_amd_read_dsc_param_chunk_size: Read the DSC Chunk Size debugfs
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we use to read status on
+ *
+ */
+int igt_amd_read_dsc_param_chunk_size(int drm_fd, char *connector_name)
+{
+ char buf[4];
+ int fd, ret;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ if (fd < 0) {
+ igt_info("Couldn't open connector %s debugfs directory\n",
+ connector_name);
+ return false;
+ }
+ ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_CHUNK_SIZE, buf, sizeof(buf));
+ close(fd);
+
+ igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
+ DEBUGFS_DSC_CHUNK_SIZE, connector_name);
+
+ return strtol(buf, NULL, 0);
+}
+
+/**
+ * igt_amd_read_dsc_param_slice_bpg: Read the DSC Slice BPG Offset debugfs
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we use to read status on
+ *
+ */
+int igt_amd_read_dsc_param_slice_bpg(int drm_fd, char *connector_name)
+{
+ char buf[4];
+ int fd, ret;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ if (fd < 0) {
+ igt_info("Couldn't open connector %s debugfs directory\n",
+ connector_name);
+ return false;
+ }
+ ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_SLICE_BPG, buf, sizeof(buf));
+ close(fd);
+
+ igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
+ DEBUGFS_DSC_SLICE_BPG, connector_name);
+
+ return strtol(buf, NULL, 0);
+}
+
+/**
+ * igt_amd_output_has_hpd: check if connector has HPD debugfs entry
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, on which we're reading the status
+ */
+static bool igt_amd_output_has_hpd(int drm_fd, char *connector_name)
+{
+ int fd;
+ int res;
+ struct stat stat;
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ if (fd < 0) {
+ igt_info("output %s: debugfs not found\n", connector_name);
+ return false;
+ }
+
+ res = fstatat(fd, DEBUGFS_HPD_TRIGGER, &stat, 0);
+ if (res != 0) {
+ igt_info("%s debugfs not supported\n", DEBUGFS_HPD_TRIGGER);
+ close(fd);
+ return false;
+ }
+
+ close(fd);
+ return true;
+}
+
+/**
+ * igt_amd_require_hpd: Checks if connectors have HPD debugfs
+ * @display: A pointer to an #igt_display_t structure
+ * @drm_fd: DRM file descriptor
+ *
+ * Checks if the AMDGPU driver has support the 'trigger_hotplug'
+ * entry for HPD. Skip test if HPD is not supported.
+ */
+void igt_amd_require_hpd(igt_display_t *display, int drm_fd)
+{
+ igt_output_t *output;
+
+ for_each_connected_output(display, output) {
+ if (igt_amd_output_has_hpd(drm_fd, output->name))
+ return;
+ }
+
+ igt_skip("No HPD debugfs support.\n");
+}
+
+/**
+ * igt_amd_trigger_hotplut: Triggers a debugfs HPD
+ * @drm_fd: DRM file descriptor
+ * @connector_name: The connector's name, which we trigger the hotplug on
+ *
+ * igt_amd_require_hpd should be called before calling this.
+ */
+int igt_amd_trigger_hotplug(int drm_fd, char *connector_name)
+{
+ int fd, hpd_fd;
+ int wr_len;
+ const char *enable_hpd = "1";
+
+ fd = igt_debugfs_connector_dir(drm_fd, connector_name, O_RDONLY);
+ igt_assert(fd >= 0);
+ hpd_fd = openat(fd, DEBUGFS_HPD_TRIGGER, O_WRONLY);
+ close(fd);
+ igt_assert(hpd_fd >= 0);
+
+ wr_len = write(hpd_fd, enable_hpd, strlen(enable_hpd));
+ close(hpd_fd);
+ igt_assert_eq(wr_len, strlen(enable_hpd));
- return 0;
+ return 0;
}
/*
diff --git a/lib/igt_amd.h b/lib/igt_amd.h
index e5bdbf33..7a91cbff 100644
--- a/lib/igt_amd.h
+++ b/lib/igt_amd.h
@@ -27,9 +27,27 @@
#include "igt.h"
#include "igt_fb.h"
+/* Read & Write DSC parameters */
+#define DEBUGFS_DSC_CLOCK_EN "dsc_clock_en"
+#define DEBUGFS_DSC_SLICE_WIDTH "dsc_slice_width"
+#define DEBUGFS_DSC_SLICE_HEIGHT "dsc_slice_height"
+#define DEBUGFS_DSC_BITS_PER_PIXEL "dsc_bits_per_pixel"
+/* Read only DSC parameters */
+#define DEBUGFS_DSC_PIC_WIDTH "dsc_pic_width"
+#define DEBUGFS_DSC_PIC_HEIGHT "dsc_pic_height"
+#define DEBUGFS_DSC_CHUNK_SIZE "dsc_chunk_size"
+#define DEBUGFS_DSC_SLICE_BPG "dsc_slice_bpg"
+#define DEBUGFS_DSC_FEC_SUPPORT "dp_dsc_fec_support"
+
#define DEBUGFS_DP_LINK_SETTINGS "link_settings"
#define DEBUGFS_HPD_TRIGGER "trigger_hotplug"
+enum amd_dsc_clock_force {
+ DSC_AUTOMATIC = 0,
+ DSC_FORCE_ON,
+ DSC_FORCE_OFF,
+};
+
enum dc_lane_count {
LANE_COUNT_UNKNOWN = 0,
LANE_COUNT_ONE = 1,
@@ -80,6 +98,23 @@ void igt_amd_fb_convert_plane_to_tiled(struct igt_fb *dst, void *dst_buf,
struct igt_fb *src, void *src_buf);
bool igt_amd_is_tiled(uint64_t modifier);
+/* IGT DSC helper functions */
+bool is_dp_dsc_supported(int drm_fd, char *connector_name);
+bool is_dp_fec_supported(int drm_fd, char *connector_name);
+void igt_amd_require_dsc(igt_display_t *display, int drm_fd);
+int igt_amd_read_dsc_clock_status(int drm_fd, char *connector_name);
+void igt_amd_write_dsc_clock_en(int drm_fd, char *connector_name, int dsc_force);
+void igt_amd_write_dsc_param_slice_height(int drm_fd, char *connector_name, int slice_height);
+int igt_amd_read_dsc_param_slice_height(int drm_fd, char *connector_name);
+void igt_amd_write_dsc_param_slice_width(int drm_fd, char *connector_name, int slice_width);
+int igt_amd_read_dsc_param_slice_width(int drm_fd, char *connector_name);
+void igt_amd_write_dsc_param_bpp(int drm_fd, char *connector_name, int bpp);
+int igt_amd_read_dsc_param_bpp(int drm_fd, char *connector_name);
+int igt_amd_read_dsc_param_pic_width(int drm_fd, char *connector_name);
+int igt_amd_read_dsc_param_pic_height(int drm_fd, char *connector_name);
+int igt_amd_read_dsc_param_chunk_size(int drm_fd, char *connector_name);
+int igt_amd_read_dsc_param_slice_bpg(int drm_fd, char *connector_name);
+
/* IGT HPD helper functions */
void igt_amd_require_hpd(igt_display_t *display, int drm_fd);
int igt_amd_trigger_hotplug(int drm_fd, char *connector_name);
diff --git a/tests/amdgpu/amd_dp_dsc.c b/tests/amdgpu/amd_dp_dsc.c
new file mode 100644
index 00000000..d73425e2
--- /dev/null
+++ b/tests/amdgpu/amd_dp_dsc.c
@@ -0,0 +1,685 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "igt_amd.h"
+#include "sw_sync.h"
+#include <fcntl.h>
+#include <signal.h>
+
+#define NUM_SLICE_SLOTS 4
+
+/* Maximumm pipes on any AMD ASIC. */
+#define MAX_PIPES 6
+
+/* Common test data. */
+typedef struct data {
+ igt_display_t display;
+ igt_plane_t *primary[MAX_PIPES];
+ igt_output_t *output[MAX_PIPES];
+ igt_pipe_t *pipe[MAX_PIPES];
+ igt_pipe_crc_t *pipe_crc[MAX_PIPES];
+ drmModeModeInfo mode[MAX_PIPES];
+ enum pipe pipe_id[MAX_PIPES];
+ int fd;
+} data_t;
+
+/* BPC connector state. */
+typedef struct output_bpc {
+ unsigned int current;
+ unsigned int maximum;
+} output_bpc_t;
+
+/* Common test cleanup. */
+static void test_fini(data_t *data)
+{
+ igt_display_t *display = &data->display;
+ int i;
+
+ for (i = 0; i < display->n_pipes; ++i) {
+ igt_pipe_crc_free(data->pipe_crc[i]);
+ }
+
+ igt_display_reset(display);
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+}
+
+/* Common test setup. */
+static void test_init(data_t *data)
+{
+ igt_display_t *display = &data->display;
+ int i, n;
+
+ for (i = 0; i < display->n_pipes; ++i) {
+ data->pipe_id[i] = PIPE_A + i;
+ data->pipe[i] = &data->display.pipes[data->pipe_id[i]];
+ data->primary[i] = igt_pipe_get_plane_type(
+ data->pipe[i], DRM_PLANE_TYPE_PRIMARY);
+ data->pipe_crc[i] =
+ igt_pipe_crc_new(data->fd, data->pipe_id[i], "auto");
+ }
+
+ for (i = 0, n = 0; i < display->n_outputs && n < display->n_pipes; ++i) {
+ igt_output_t *output = &display->outputs[i];
+ data->output[n] = output;
+
+ /* Only allow physically connected displays for the tests. */
+ if (!igt_output_is_connected(output))
+ continue;
+
+ /* Ensure that outpus are DP, DSC & FEC capable*/
+ if (!(is_dp_fec_supported(data->fd, output->name) &&
+ is_dp_dsc_supported(data->fd, output->name)))
+ continue;
+
+ if (output->config.connector->connector_type !=
+ DRM_MODE_CONNECTOR_DisplayPort)
+ continue;
+
+ igt_assert(kmstest_get_connector_default_mode(
+ data->fd, output->config.connector, &data->mode[n]));
+
+ n += 1;
+ }
+
+ igt_display_reset(display);
+}
+
+static void test_dsc_enable(data_t *data)
+{
+ bool dsc_on, dsc_after, dsc_before;
+ igt_display_t *display = &data->display;
+ igt_output_t *output;
+ igt_fb_t ref_fb;
+ int i, test_conn_cnt = 0;
+
+ test_init(data);
+ igt_enable_connectors(data->fd);
+
+ for (i = 0; i < display->n_pipes; i++) {
+ /* Setup the output */
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+
+ igt_create_pattern_fb(data->fd,
+ data->mode[i].hdisplay,
+ data->mode[i].vdisplay,
+ DRM_FORMAT_XRGB8888,
+ 0,
+ &ref_fb);
+ igt_output_set_pipe(output, data->pipe_id[i]);
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+ test_conn_cnt++;
+
+ /* Save pipe's initial DSC state */
+ dsc_before = igt_amd_read_dsc_clock_status(data->fd, output->name);
+
+ /* Force enable DSC */
+ igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_FORCE_ON);
+
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ /* Check if DSC is enabled */
+ dsc_on = igt_amd_read_dsc_clock_status(data->fd, output->name) == 1;
+
+ /* Revert DSC to automatic state */
+ igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_FORCE_OFF);
+
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+ igt_display_commit_atomic(display,DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ dsc_after = igt_amd_read_dsc_clock_status(data->fd, output->name);
+
+ /* Revert DSC back to automatic mechanism by disabling state overwrites*/
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+
+ igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_AUTOMATIC);
+
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ igt_assert_f(dsc_on, "Enabling DSC on pipe failed.\n");
+ igt_assert_f(dsc_after == dsc_before, "Reverting DSC to initial state failed.\n");
+
+ /* Cleanup fb */
+ igt_remove_fb(data->fd, &ref_fb);
+ }
+
+ test_fini(data);
+ igt_skip_on(test_conn_cnt == 0);
+}
+
+static void test_dsc_slice_height_property(data_t *data)
+{
+ bool dsc_on, dsc_after, dsc_before;
+ int slice_height_on, slice_height_off;
+ igt_display_t *display = &data->display;
+ igt_output_t *output;
+ igt_fb_t ref_fb;
+ int i, test_conn_cnt = 0;
+
+ test_init(data);
+ igt_enable_connectors(data->fd);
+
+ for (i = 0; i < display->n_pipes; i++) {
+ /* Setup the output */
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+
+ igt_create_pattern_fb(data->fd,
+ data->mode[i].hdisplay,
+ data->mode[i].vdisplay,
+ DRM_FORMAT_XRGB8888,
+ 0,
+ &ref_fb);
+ igt_output_set_pipe(output, data->pipe_id[i]);
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+ test_conn_cnt++;
+
+ /* Save pipe's initial DSC state */
+ dsc_before = igt_amd_read_dsc_clock_status(data->fd, output->name);
+
+ /* Force enable DSC */
+ igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_FORCE_ON);
+
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ /* Check if DSC is enabled */
+ dsc_on = igt_amd_read_dsc_clock_status(data->fd, output->name) == 1;
+
+ slice_height_on = igt_pipe_get_prop(display, data->pipe_id[i], IGT_CRTC_DSC_SLICE_HEIGHT);
+
+ /* Revert DSC to automatic state */
+ igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_FORCE_OFF);
+
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ dsc_after = igt_amd_read_dsc_clock_status(data->fd, output->name);
+
+ slice_height_off = igt_pipe_get_prop(display, data->pipe_id[i], IGT_CRTC_DSC_SLICE_HEIGHT);
+
+ /* Revert DSC back to automatic mechanism by disabling state overwrites*/
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+
+ igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_AUTOMATIC);
+
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ igt_assert_f(dsc_on, "Enabling DSC on pipe failed.\n");
+ igt_assert_f(slice_height_on > 0, "DSC Slice property was not set properly.\n");
+ igt_assert_f(dsc_after == dsc_before, "Reverting DSC to initial state failed.\n");
+ igt_assert_f(slice_height_off == 0, "DSC Slice property was not reset properly.\n");
+
+ /* Cleanup fb */
+ igt_remove_fb(data->fd, &ref_fb);
+ }
+
+ test_fini(data);
+ igt_skip_on(test_conn_cnt == 0);
+}
+
+static bool update_slice_height(data_t *data, int v_addressable,
+ int *num_slices, igt_output_t *output, int conn_idx, igt_fb_t ref_fb)
+{
+ int i;
+ bool pass = true;
+
+ for(i = 0; i < NUM_SLICE_SLOTS; i++) {
+ int act_slice_height;
+ int slice_height = v_addressable / num_slices[i] + (v_addressable % num_slices[i]);
+
+ /* Overwrite DSC slice height */
+ igt_amd_write_dsc_param_slice_height(data->fd, output->name, slice_height);
+ igt_plane_set_fb(data->primary[conn_idx], &ref_fb);
+ igt_display_commit_atomic(&data->display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ igt_info("Forcing slice height: slice height %d num slices vertical %d\n", slice_height, num_slices[i]);
+
+ act_slice_height = igt_amd_read_dsc_param_slice_height(data->fd, output->name);
+
+ igt_info("Reading slice height: actual slice height %d VS assigned slice height %d\n", act_slice_height, slice_height);
+
+ pass = (slice_height == act_slice_height);
+
+ if (!pass)
+ break;
+ }
+
+ igt_amd_write_dsc_param_slice_height(data->fd, output->name, 0);
+ igt_plane_set_fb(data->primary[conn_idx], &ref_fb);
+ igt_display_commit_atomic(&data->display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ return pass;
+}
+
+static bool update_slice_width(data_t *data, int h_addressable,
+ int *num_slices, igt_output_t *output, int conn_idx, igt_fb_t ref_fb)
+{
+ int i;
+ bool pass = true;
+
+ for(i = 0; i < NUM_SLICE_SLOTS; i++) {
+ int act_slice_width;
+ int slice_width = h_addressable / num_slices[i] + (h_addressable % num_slices[i]);
+
+ /* Overwrite DSC slice width */
+ igt_amd_write_dsc_param_slice_width(data->fd, output->name, slice_width);
+ igt_plane_set_fb(data->primary[conn_idx], &ref_fb);
+ igt_display_commit_atomic(&data->display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ igt_info("Forcing slice width: slice width %d num slices horisontal %d\n", slice_width, num_slices[i]);
+
+ act_slice_width = igt_amd_read_dsc_param_slice_width(data->fd, output->name);
+
+ igt_info("Reading slice width: actual slice width %d VS assigned slice width %d\n", act_slice_width, slice_width);
+
+ pass = (slice_width == act_slice_width);
+
+ if (!pass)
+ break;
+ }
+
+ igt_amd_write_dsc_param_slice_width(data->fd, output->name, 0);
+ igt_plane_set_fb(data->primary[conn_idx], &ref_fb);
+ igt_display_commit_atomic(&data->display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ return pass;
+}
+
+static void test_dsc_slice_dimensions_change(data_t *data)
+{
+ bool dsc_on, dsc_after, dsc_before;
+ igt_output_t *output;
+ igt_display_t *display = &data->display;
+ igt_fb_t ref_fb;
+ int num_slices [] = { 1, 2, 4, 8 };
+ int h_addressable, v_addressable;
+ bool ret_slice_height= false, ret_slice_width = false;
+ int i, test_conn_cnt = 0;
+
+ test_init(data);
+ igt_enable_connectors(data->fd);
+
+ for (i = 0; i < display->n_pipes; i++) {
+ /* Setup the output */
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+
+ igt_create_pattern_fb(data->fd,
+ data->mode[i].hdisplay,
+ data->mode[i].vdisplay,
+ DRM_FORMAT_XRGB8888,
+ 0,
+ &ref_fb);
+ igt_output_set_pipe(output, data->pipe_id[i]);
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+ test_conn_cnt++;
+
+ h_addressable = data->mode->hdisplay;
+ v_addressable = data->mode->vdisplay;
+
+ igt_info("Mode info: v_ative %d h_active %d\n", v_addressable, h_addressable);
+
+ /* Save pipe's initial DSC state */
+ dsc_before = igt_amd_read_dsc_clock_status(data->fd, output->name);
+
+ /* Force enable DSC */
+ igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_FORCE_ON);
+
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ /* Check if DSC is enabled */
+ dsc_on = igt_amd_read_dsc_clock_status(data->fd, output->name) == 1;
+
+ if (dsc_on) {
+ ret_slice_height = update_slice_height(data, v_addressable, num_slices, output, i, ref_fb);
+ ret_slice_width = update_slice_width(data, h_addressable, num_slices, output, i, ref_fb);
+ }
+
+ /* Force disable DSC */
+ igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_FORCE_OFF);
+
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ dsc_after = igt_amd_read_dsc_clock_status(data->fd, output->name);
+
+ /* Revert DSC back to automatic mechanism by disabling state overwrites*/
+ igt_plane_set_fb(data->primary[i], &ref_fb);
+
+ igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_AUTOMATIC);
+
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ igt_assert_f(dsc_on, "Enabling DSC on pipe failed.\n");
+ igt_assert_f(ret_slice_height, "Changing slice height failed.\n");
+ igt_assert_f(ret_slice_width, "Changing slice width failed.\n");
+ igt_assert_f(dsc_after == dsc_before, "Reverting DSC to initial state failed.\n");
+
+ /* Cleanup fb */
+ igt_remove_fb(data->fd, &ref_fb);
+ }
+
+ test_fini(data);
+ igt_skip_on(test_conn_cnt == 0);
+}
+
+static void test_dsc_link_settings(data_t *data)
+{
+ igt_output_t *output;
+ igt_fb_t ref_fb[MAX_PIPES];
+ igt_crc_t ref_crc[MAX_PIPES], new_crc[MAX_PIPES];
+ int lane_count[4], link_rate[4], link_spread[4];
+ igt_display_t *display = &data->display;
+ int i, lc, lr;
+ bool dsc_on;
+ const enum dc_lane_count lane_count_vals[] =
+ {
+ LANE_COUNT_TWO,
+ LANE_COUNT_FOUR
+ };
+ const enum dc_link_rate link_rate_vals[] =
+ {
+ LINK_RATE_LOW,
+ LINK_RATE_HIGH,
+ LINK_RATE_HIGH2,
+ LINK_RATE_HIGH3
+ };
+
+ test_init(data);
+
+ /* Setup all outputs */
+ for (i = 0; i < display->n_pipes; i++) {
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+
+ igt_create_pattern_fb(data->fd,
+ data->mode[i].hdisplay,
+ data->mode[i].vdisplay,
+ DRM_FORMAT_XRGB8888,
+ 0,
+ &ref_fb[i]);
+ igt_output_set_pipe(output, data->pipe_id[i]);
+ igt_plane_set_fb(data->primary[i], &ref_fb[i]);
+ }
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+ /* Collect reference CRCs */
+ for (i = 0; i < display->n_pipes; i++) {
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+
+ igt_pipe_crc_collect_crc(data->pipe_crc[i], &ref_crc[i]);
+ }
+
+ for (lc = 0; lc < ARRAY_SIZE(lane_count_vals); lc++) {
+ for (lr = 0; lr < ARRAY_SIZE(link_rate_vals); lr++) {
+ /* Write new link_settings */
+ for (i = 0; i < display->n_pipes; i++) {
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+
+ /* Write lower link settings */
+ igt_info("Applying lane count: %d, link rate 0x%02x, on default training\n",
+ lane_count_vals[lc], link_rate_vals[lr]);
+ igt_amd_write_link_settings(data->fd, output->name,
+ lane_count_vals[lc],
+ link_rate_vals[lr],
+ LINK_TRAINING_DEFAULT);
+ usleep(500 * MSEC_PER_SEC);
+ }
+
+ /* Trigger commit after writing new link settings */
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+
+ for (i = 0; i < display->n_pipes; i++) {
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+
+ /* Verify lower link settings */
+ igt_amd_read_link_settings(data->fd, output->name,
+ lane_count,
+ link_rate,
+ link_spread);
+
+ igt_assert_f(lane_count[0] == lane_count_vals[lc], "Lowering lane count settings failed\n");
+ igt_assert_f(link_rate[0] == link_rate_vals[lr], "Lowering link rate settings failed\n");
+
+ /* Log current mode and DSC status */
+ dsc_on = igt_amd_read_dsc_clock_status(data->fd, output->name) == 1;
+ igt_info("Current mode is: %dx%d @%dHz -- DSC is: %s\n",
+ data->mode[i].hdisplay,
+ data->mode[i].vdisplay,
+ data->mode[i].vrefresh,
+ dsc_on ? "ON" : "OFF");
+
+ igt_pipe_crc_collect_crc(data->pipe_crc[i], &new_crc[i]);
+ igt_assert_crc_equal(&ref_crc[i], &new_crc[i]);
+ }
+ }
+ }
+
+ /* Cleanup all fbs */
+ for (i = 0; i < display->n_pipes; i++) {
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+ igt_remove_fb(data->fd, &ref_fb[i]);
+ }
+
+ test_fini(data);
+}
+
+/* Returns the current and maximum bpc from the connector debugfs. */
+static output_bpc_t get_output_bpc(int data_fd, char *connector_name)
+{
+ char buf[256];
+ char *start_loc;
+ int fd, res;
+ output_bpc_t info;
+
+ fd = igt_debugfs_connector_dir(data_fd, connector_name, O_RDONLY);
+ igt_assert(fd >= 0);
+
+ res = igt_debugfs_simple_read(fd, "output_bpc", buf, sizeof(buf));
+
+ igt_require(res > 0);
+
+ close(fd);
+
+ igt_assert(start_loc = strstr(buf, "Current: "));
+ igt_assert_eq(sscanf(start_loc, "Current: %u", &info.current), 1);
+
+ igt_assert(start_loc = strstr(buf, "Maximum: "));
+ igt_assert_eq(sscanf(start_loc, "Maximum: %u", &info.maximum), 1);
+
+ return info;
+}
+
+/* Verifies that connector has the correct output bpc */
+static void assert_output_bpc(int data_fd, char *connector_name, unsigned int bpc)
+{
+ output_bpc_t info = get_output_bpc(data_fd, connector_name);
+
+ igt_require_f(info.maximum >= bpc,
+ "Monitor doesn't support %u bpc, max is %u\n", bpc,
+ info.maximum);
+
+ igt_assert_eq(info.current, bpc);
+}
+
+/* Returns the highest bpc this dispaly supports */
+static int get_max_supported_bpc(int data_fd, char *connector_name)
+{
+ output_bpc_t info = get_output_bpc(data_fd, connector_name);
+ return info.maximum;
+}
+
+static void test_dsc_bpc(data_t *data)
+{
+ igt_output_t *output;
+ igt_fb_t ref_fb[MAX_PIPES];
+ igt_crc_t test_crc;
+ igt_display_t *display = &data->display;
+ int i, bpc, max_supported_bpc[MAX_PIPES];
+ bool dsc_on;
+ const int bpc_vals[] = {12, 10, 8};
+
+ test_init(data);
+
+ /* Find max supported bpc */
+ for (i = 0; i < display->n_pipes; i++) {
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+ igt_info("Checking bpc support of conn %s\n", output->name);
+ max_supported_bpc[i] = get_max_supported_bpc(data->fd, output->name);
+ }
+
+ /* Setup all outputs */
+ for (bpc = 0; bpc < ARRAY_SIZE(bpc_vals); bpc++) {
+ igt_info("Testing bpc = %d\n", bpc_vals[bpc]);
+
+ for (i = 0; i < display->n_pipes; i++) {
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+
+ if (max_supported_bpc[i] < bpc_vals[bpc]) {
+ igt_info("Display doesn't support bpc of %d, max is %d. Skipping to next bpc value.\n", bpc_vals[bpc], max_supported_bpc[i]);
+ continue;
+ }
+ igt_info("Setting bpc = %d\n", bpc_vals[bpc]);
+ igt_output_set_prop_value(output, IGT_CONNECTOR_MAX_BPC, bpc_vals[bpc]);
+ igt_create_pattern_fb(data->fd,
+ data->mode[i].hdisplay,
+ data->mode[i].vdisplay,
+ DRM_FORMAT_XRGB8888,
+ 0,
+ &ref_fb[i]);
+ igt_output_set_pipe(output, data->pipe_id[i]);
+ igt_plane_set_fb(data->primary[i], &ref_fb[i]);
+ }
+
+ igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
+
+ for (i = 0; i < display->n_pipes; i++) {
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+
+ if (max_supported_bpc[i] < bpc_vals[bpc])
+ continue;
+
+ /* Check that crc is non-zero */
+ igt_pipe_crc_collect_crc(data->pipe_crc[i], &test_crc);
+ igt_assert(test_crc.crc[0] && test_crc.crc[1] && test_crc.crc[2]);
+
+ /* Check current bpc */
+ igt_info("Verifying display %s has correct bpc\n", output->name);
+ assert_output_bpc(data->fd, output->name, bpc_vals[bpc]);
+
+ /* Log current mode and DSC status */
+ dsc_on = igt_amd_read_dsc_clock_status(data->fd, output->name) == 1;
+ igt_info("Current mode is: %dx%d @%dHz -- DSC is: %s\n",
+ data->mode[i].hdisplay,
+ data->mode[i].vdisplay,
+ data->mode[i].vrefresh,
+ dsc_on ? "ON" : "OFF");
+ }
+
+ /* Cleanup all fbs */
+ for (i = 0; i < display->n_pipes; i++) {
+ output = data->output[i];
+ if (!output || !igt_output_is_connected(output))
+ continue;
+
+ if (max_supported_bpc[i] < bpc_vals[bpc])
+ continue;
+
+ igt_remove_fb(data->fd, &ref_fb[i]);
+ }
+ }
+
+ test_fini(data);
+}
+
+igt_main
+{
+ data_t data = { 0 };
+
+ igt_skip_on_simulation();
+
+ igt_fixture
+ {
+ data.fd = drm_open_driver_master(DRIVER_ANY);
+
+ igt_display_require(&data.display, data.fd);
+ igt_require(data.display.is_atomic);
+ igt_display_require_output(&data.display);
+
+ igt_amd_require_dsc(&data.display, data.fd);
+ kmstest_set_vt_graphics_mode();
+ }
+
+ igt_describe("Forces DSC on/off & ensures it is reset properly");
+ igt_subtest("dsc-enable-basic")
+ test_dsc_enable(&data);
+
+ igt_describe("Tests DSC slice height property & ensures it is reset properly on DSC enable/disable");
+ igt_subtest("dsc-slice-height-property")
+ test_dsc_slice_height_property(&data);
+
+ igt_describe("Tests various DSC slice dimensions");
+ igt_subtest("dsc-slice-dimensions-change")
+ test_dsc_slice_dimensions_change(&data);
+
+ igt_describe("Tests various combinations of link_rate + lane_count and logs if DSC enabled/disabled");
+ igt_subtest("dsc-link-settings")
+ test_dsc_link_settings(&data);
+
+ igt_describe("Tests different bpc settings and logs if DSC is enabled/disabled");
+ igt_subtest("dsc-bpc")
+ test_dsc_bpc(&data);
+
+ igt_fixture
+ {
+ igt_reset_connectors();
+ igt_display_fini(&data.display);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index d232e490..d8e8ddfb 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -17,6 +17,7 @@ if libdrm_amdgpu.found()
'amd_link_settings',
'amd_vrr_range',
'amd_mode_switch',
+ 'amd_dp_dsc',
'amd_psr',
'amd_plane',
]
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for tests/amdgpu: Introduce DSC tests (rev2)
2021-12-07 16:43 [igt-dev] [PATCH v4 0/2] tests/amdgpu: Introduce DSC tests Rodrigo Siqueira
2021-12-07 16:43 ` [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property Rodrigo Siqueira
2021-12-07 16:43 ` [igt-dev] [PATCH v4 2/2] tests/amdgpu: Introduces DP DSC test Rodrigo Siqueira
@ 2021-12-07 19:21 ` Patchwork
2021-12-08 1:59 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2021-12-09 16:38 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2021-12-07 19:21 UTC (permalink / raw)
To: Rodrigo Siqueira; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 5861 bytes --]
== Series Details ==
Series: tests/amdgpu: Introduce DSC tests (rev2)
URL : https://patchwork.freedesktop.org/series/97470/
State : success
== Summary ==
CI Bug Log - changes from IGT_6302 -> IGTPW_6475
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/index.html
Participating hosts (37 -> 34)
------------------------------
Additional (1): fi-icl-u2
Missing (4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Known issues
------------
Here are the changes found in IGTPW_6475 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][2] ([i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [PASS][4] -> [INCOMPLETE][5] ([i915#4432])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][6] ([fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][7] ([fdo#109278]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][8] ([fdo#109285])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [PASS][9] -> [INCOMPLETE][10] ([i915#198] / [i915#4547])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#3301])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][12] ([i915#2722] / [i915#3363] / [i915#4312])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-skl-6600u/igt@runner@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][13] ([i915#3928] / [i915#4312])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-rkl-guc/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][14] ([i915#1888]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-soraka: [DMESG-WARN][16] ([i915#1982]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6302 -> IGTPW_6475
CI-20190529: 20190529
CI_DRM_10970: 9368928e088bcfb4bebd54c2ae18603988f40c26 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_6475: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/index.html
IGT_6302: dca7c7bc5ee0a862a8af711b2dacfb18a3108a7c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Testlist changes ==
+igt@amdgpu/amd_dp_dsc@dsc-bpc
+igt@amdgpu/amd_dp_dsc@dsc-enable-basic
+igt@amdgpu/amd_dp_dsc@dsc-link-settings
+igt@amdgpu/amd_dp_dsc@dsc-slice-dimensions-change
+igt@amdgpu/amd_dp_dsc@dsc-slice-height-property
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/index.html
[-- Attachment #2: Type: text/html, Size: 6871 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for tests/amdgpu: Introduce DSC tests (rev2)
2021-12-07 16:43 [igt-dev] [PATCH v4 0/2] tests/amdgpu: Introduce DSC tests Rodrigo Siqueira
` (2 preceding siblings ...)
2021-12-07 19:21 ` [igt-dev] ✓ Fi.CI.BAT: success for tests/amdgpu: Introduce DSC tests (rev2) Patchwork
@ 2021-12-08 1:59 ` Patchwork
2021-12-09 16:38 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2021-12-08 1:59 UTC (permalink / raw)
To: Rodrigo Siqueira; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 30258 bytes --]
== Series Details ==
Series: tests/amdgpu: Introduce DSC tests (rev2)
URL : https://patchwork.freedesktop.org/series/97470/
State : failure
== Summary ==
CI Bug Log - changes from IGT_6302_full -> IGTPW_6475_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_6475_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_6475_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/index.html
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_6475_full:
### IGT changes ###
#### Possible regressions ####
* igt@sysfs_heartbeat_interval@precise@vecs0:
- shard-apl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-apl6/igt@sysfs_heartbeat_interval@precise@vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl6/igt@sysfs_heartbeat_interval@precise@vecs0.html
Known issues
------------
Here are the changes found in IGTPW_6475_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglb: NOTRUN -> [SKIP][3] ([i915#4525])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_endless@dispatch@vecs0:
- shard-tglb: [PASS][4] -> [INCOMPLETE][5] ([i915#3778])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-tglb2/igt@gem_exec_endless@dispatch@vecs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@gem_exec_endless@dispatch@vecs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb3/igt@gem_exec_fair@basic-pace@bcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
- shard-kbl: [PASS][13] -> [SKIP][14] ([fdo#109271])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@no-bsd:
- shard-tglb: NOTRUN -> [SKIP][17] ([fdo#109283])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@gem_exec_params@no-bsd.html
* igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109283])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb6/igt@gem_exec_params@no-vebox.html
* igt@gem_lmem_swapping@heavy-random:
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl3/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl6/igt@gem_lmem_swapping@parallel-multi.html
- shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk9/igt@gem_lmem_swapping@parallel-multi.html
- shard-iclb: NOTRUN -> [SKIP][22] ([i915#4613])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@gem_lmem_swapping@parallel-multi.html
- shard-tglb: NOTRUN -> [SKIP][23] ([i915#4613])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_pwrite@basic-exhaustion:
- shard-iclb: NOTRUN -> [WARN][24] ([i915#2658])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#4270])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb7/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#4270])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gem_render_copy@y-tiled-to-vebox-linear:
- shard-iclb: NOTRUN -> [SKIP][27] ([i915#768]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb6/igt@gem_render_copy@y-tiled-to-vebox-linear.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#3297])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@gem_userptr_blits@unsync-unmap-after-close.html
- shard-iclb: NOTRUN -> [SKIP][29] ([i915#3297])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen3_render_tiledy_blits:
- shard-tglb: NOTRUN -> [SKIP][30] ([fdo#109289]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@gen3_render_tiledy_blits.html
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109289]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb6/igt@gen3_render_tiledy_blits.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-tglb: NOTRUN -> [SKIP][32] ([i915#2856]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@shadow-peek:
- shard-iclb: NOTRUN -> [SKIP][33] ([i915#2856]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][34] -> [SKIP][35] ([i915#4281])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-tglb: NOTRUN -> [SKIP][36] ([fdo#109506] / [i915#2411]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@pc8-residency:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109293] / [fdo#109506])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@i915_pm_rpm@pc8-residency.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-tglb: NOTRUN -> [SKIP][38] ([fdo#109303])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@i915_query@query-topology-known-pci-ids.html
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109303])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb5/igt@i915_query@query-topology-known-pci-ids.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][40] -> [DMESG-WARN][41] ([i915#180]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-apl7/igt@i915_suspend@sysfs-reader.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl2/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@linear-64bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][42] ([fdo#110725] / [fdo#111614]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@kms_big_fb@linear-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#111614]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#110723]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb5/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][45] ([fdo#111615]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3777])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_joiner@basic:
- shard-tglb: NOTRUN -> [SKIP][47] ([i915#2705])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb1/igt@kms_big_joiner@basic.html
- shard-iclb: NOTRUN -> [SKIP][48] ([i915#2705])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +9 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#111615] / [i915#3689]) +4 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#3689]) +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#3886]) +4 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk5/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
- shard-tglb: NOTRUN -> [SKIP][53] ([i915#3689] / [i915#3886]) +4 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109278] / [i915#3886]) +7 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#3886]) +5 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cdclk@mode-transition:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271]) +84 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl1/igt@kms_cdclk@mode-transition.html
- shard-iclb: NOTRUN -> [SKIP][57] ([i915#3742])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@kms_cdclk@mode-transition.html
- shard-tglb: NOTRUN -> [SKIP][58] ([i915#3742])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb1/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-glk: NOTRUN -> [SKIP][59] ([fdo#109271] / [fdo#111827]) +5 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk4/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-snb: NOTRUN -> [SKIP][60] ([fdo#109271] / [fdo#111827]) +5 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-snb7/igt@kms_chamelium@hdmi-mode-timings.html
- shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109284] / [fdo#111827]) +6 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][62] ([fdo#109271] / [fdo#111827]) +15 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl2/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color@pipe-d-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109278] / [i915#1149])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@kms_color@pipe-d-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-b-ctm-0-5:
- shard-tglb: NOTRUN -> [SKIP][64] ([fdo#109284] / [fdo#111827]) +8 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [fdo#111827]) +8 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl1/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-d-gamma:
- shard-iclb: NOTRUN -> [SKIP][66] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@kms_color_chamelium@pipe-d-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen:
- shard-tglb: NOTRUN -> [SKIP][67] ([i915#3319]) +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][68] ([fdo#109278] / [fdo#109279]) +3 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
- shard-tglb: NOTRUN -> [SKIP][69] ([fdo#109279] / [i915#3359]) +4 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#3359]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement.html
* igt@kms_cursor_edge_walk@pipe-d-64x64-left-edge:
- shard-kbl: NOTRUN -> [SKIP][71] ([fdo#109271]) +156 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl1/igt@kms_cursor_edge_walk@pipe-d-64x64-left-edge.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglb: NOTRUN -> [SKIP][72] ([i915#4103])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-iclb: NOTRUN -> [SKIP][73] ([fdo#109274] / [fdo#109278]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109274]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb6/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][75] -> [DMESG-WARN][76] ([i915#180]) +11 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-tglb: NOTRUN -> [SKIP][77] ([i915#2587])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2672])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs:
- shard-apl: NOTRUN -> [DMESG-WARN][79] ([i915#1226])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl4/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-tglb: NOTRUN -> [SKIP][80] ([fdo#111825]) +28 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
- shard-iclb: NOTRUN -> [SKIP][81] ([fdo#109280]) +14 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-glk: NOTRUN -> [SKIP][82] ([fdo#109271]) +52 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-iclb: NOTRUN -> [SKIP][83] ([i915#1839])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#533]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl7/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-glk: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#533])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk1/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
- shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#533])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl1/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-kbl: NOTRUN -> [DMESG-WARN][87] ([i915#180])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][88] ([fdo#108145] / [i915#265])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
- shard-kbl: NOTRUN -> [FAIL][89] ([fdo#108145] / [i915#265])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
- shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109278]) +22 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb7/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-b-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][91] ([fdo#111615] / [fdo#112054])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@kms_plane_lowres@pipe-b-tiling-yf.html
- shard-iclb: NOTRUN -> [SKIP][92] ([i915#3536])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@kms_plane_lowres@pipe-b-tiling-yf.html
* igt@kms_plane_lowres@pipe-d-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][93] ([i915#3536])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@kms_plane_lowres@pipe-d-tiling-none.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#658]) +4 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
- shard-apl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#658]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-tglb: NOTRUN -> [SKIP][96] ([i915#2920]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: NOTRUN -> [SKIP][97] ([i915#658]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-tglb: NOTRUN -> [SKIP][98] ([i915#1911])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@kms_psr2_su@page_flip-nv12.html
- shard-glk: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#658])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk3/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][100] -> [SKIP][101] ([fdo#109441]) +3 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
- shard-snb: NOTRUN -> [SKIP][102] ([fdo#109271]) +105 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-snb6/igt@kms_universal_plane@disable-primary-vs-flip-pipe-d.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][103] ([i915#180] / [i915#295])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-kbl: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#2437]) +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl4/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][105] ([i915#2530])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame.html
* igt@nouveau_crc@pipe-a-source-outp-inactive:
- shard-tglb: NOTRUN -> [SKIP][106] ([i915#2530])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@nouveau_crc@pipe-a-source-outp-inactive.html
* igt@prime_nv_api@nv_i915_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][107] ([fdo#109291]) +4 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@prime_nv_api@nv_i915_import_twice_check_flink_name.html
* igt@prime_nv_pcopy@test1_macro:
- shard-tglb: NOTRUN -> [SKIP][108] ([fdo#109291]) +3 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb5/igt@prime_nv_pcopy@test1_macro.html
* igt@sysfs_clients@sema-50:
- shard-iclb: NOTRUN -> [SKIP][109] ([i915#2994])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@sysfs_clients@sema-50.html
- shard-kbl: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#2994]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl2/igt@sysfs_clients@sema-50.html
- shard-apl: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2994])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl3/igt@sysfs_clients@sema-50.html
- shard-glk: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#2994])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk3/igt@sysfs_clients@sema-50.html
* igt@sysfs_clients@split-10:
- shard-tglb: NOTRUN -> [SKIP][113] ([i915#2994]) +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@gem_eio@in-flight-10ms:
- shard-iclb: [TIMEOUT][114] ([i915#3070]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb4/igt@gem_eio@in-flight-10ms.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb6/igt@gem_eio@in-flight-10ms.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglb: [FAIL][116] ([i915#2842]) -> [PASS][117] +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-tglb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][118] ([i915#2842]) -> [PASS][119] +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][120] ([i915#2842]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
- shard-glk: [FAIL][122] ([i915#2842]) -> [PASS][123] +3 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-glk3/igt@gem_exec_fair@basic-pace@vecs0.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk2/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][124] ([i915#2849]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][126] ([i915#454]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb5/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-iclb: [INCOMPLETE][128] -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb4/igt@i915_pm_rpm@debugfs-forcewake-user.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb5/igt@i915_pm_rpm@debugfs-forcewake-user.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [DMESG-WARN][130] ([i915#118]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-glk4/igt@kms_big_fb@linear-32bpp-rotate-0.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk9/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [DMESG-WARN][132] ([i915#180]) -> [PASS][133] +1 similar issue
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-glk: [FAIL][134] ([i915#1888] / [i915#2546]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/index.html
[-- Attachment #2: Type: text/html, Size: 33828 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
2021-12-07 16:43 ` [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property Rodrigo Siqueira
@ 2021-12-09 1:48 ` Rodrigo Siqueira Jordao
2021-12-09 6:23 ` Vudum, Lakshminarayana
2021-12-09 11:16 ` Petri Latvala
0 siblings, 2 replies; 12+ messages in thread
From: Rodrigo Siqueira Jordao @ 2021-12-09 1:48 UTC (permalink / raw)
To: Petri Latvala; +Cc: igt-dev, Vudum, Lakshminarayana
On 2021-12-07 11:43 a.m., Rodrigo Siqueira wrote:
> This preparation work introduces a new CRTC property named
> DSC_SLICE_HEIGHT, which will be required for amdgpu DSC tests.
>
> Cc: Petri Latvala <petri.latvala@intel.com>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
> lib/igt_kms.c | 1 +
> lib/igt_kms.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> index 34a2aa00..fdadb6d6 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -593,6 +593,7 @@ const char * const igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
> [IGT_CRTC_ACTIVE] = "ACTIVE",
> [IGT_CRTC_OUT_FENCE_PTR] = "OUT_FENCE_PTR",
> [IGT_CRTC_VRR_ENABLED] = "VRR_ENABLED",
> + [IGT_CRTC_DSC_SLICE_HEIGHT] = "DSC_SLICE_HEIGHT",
> };
>
> const char * const igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
> diff --git a/lib/igt_kms.h b/lib/igt_kms.h
> index e9ecd21e..5c7d7481 100644
> --- a/lib/igt_kms.h
> +++ b/lib/igt_kms.h
> @@ -125,6 +125,7 @@ enum igt_atomic_crtc_properties {
> IGT_CRTC_ACTIVE,
> IGT_CRTC_OUT_FENCE_PTR,
> IGT_CRTC_VRR_ENABLED,
> + IGT_CRTC_DSC_SLICE_HEIGHT,
> IGT_NUM_CRTC_PROPS
> };
>
>
Hi Petri,
I followed your advice to search for IGT_NUM_CRTC_PROPS, and only
igt_kms.{h,c} and kms_atomic uses it.
In the lib/igt_kms.c, the occurrences of IGT_NUM_CRTC_PROPS appears in
the function igt_fill_pipe_props() as a parameter, in its turn, it call
drmModeObjectGetProperties and drmModeGetProperty. Finally, it only
populates the prop array based on the returned value from the driver. I
suppose we are safe here; I don't see how this patch could regress
something in this function. The other places where this function appears
are in the loop condition, but all of them look correct to me.
Finally, the other place we can see it is in the kms_atomic, but again
the for loop looks correct.
However, IGT CI failed:
https://patchwork.freedesktop.org/series/97470/#rev2
The potential new issue pointed by the CI is:
Possible new issues
Here are the unknown changes that may have been introduced in
IGTPW_6475_full:
IGT changes
Possible regressions
igt@sysfs_heartbeat_interval@precise@vecs0:
shard-apl: PASS -> FAIL
And the log says:
Stack trace:
#0 ../lib/igt_core.c:1745 __igt_fail_assert()
#1 ../tests/i915/sysfs_heartbeat_interval.c:156 __test_timeout()
#2 [<unknown>+0xd0]
Dynamic subtest vecs0: FAIL (1.713s)
After I resubmitted this patch, I also noticed that I got a different CI
error from the one from the V1. The reported error looks a little bit
inconsistent.
Petri, do you think this can be a false-positive, or am I missing
something? Maybe re-trigger IGT.CI can help?
Thanks
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
2021-12-09 1:48 ` Rodrigo Siqueira Jordao
@ 2021-12-09 6:23 ` Vudum, Lakshminarayana
2021-12-09 11:16 ` Petri Latvala
1 sibling, 0 replies; 12+ messages in thread
From: Vudum, Lakshminarayana @ 2021-12-09 6:23 UTC (permalink / raw)
To: Rodrigo Siqueira Jordao, Latvala, Petri; +Cc: igt-dev
https://patchwork.freedesktop.org/series/97470/#rev2
Possible regressions
igt@sysfs_heartbeat_interval@precise@vecs0:
shard-apl: PASS -> FAIL
Regression from rev2 is same as https://gitlab.freedesktop.org/drm/intel/-/issues/1755
igt@sysfs_timeslice_duration@timeout@.*| igt@sysfs_heartbeat_interval@precise@vecs0 - fail - Failed assertion: wait_for_reset(spin[0]->out_fence) == 0, error: -62 != 0, Resetting vecs0 for preemption time out
I can re-report the rev2 results.
Lakshmi.
-----Original Message-----
From: Rodrigo Siqueira Jordao <rjordrigo@amd.com>
Sent: Wednesday, December 8, 2021 5:48 PM
To: Latvala, Petri <petri.latvala@intel.com>
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>; igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
On 2021-12-07 11:43 a.m., Rodrigo Siqueira wrote:
> This preparation work introduces a new CRTC property named
> DSC_SLICE_HEIGHT, which will be required for amdgpu DSC tests.
>
> Cc: Petri Latvala <petri.latvala@intel.com>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
> lib/igt_kms.c | 1 +
> lib/igt_kms.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c index 34a2aa00..fdadb6d6
> 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -593,6 +593,7 @@ const char * const igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
> [IGT_CRTC_ACTIVE] = "ACTIVE",
> [IGT_CRTC_OUT_FENCE_PTR] = "OUT_FENCE_PTR",
> [IGT_CRTC_VRR_ENABLED] = "VRR_ENABLED",
> + [IGT_CRTC_DSC_SLICE_HEIGHT] = "DSC_SLICE_HEIGHT",
> };
>
> const char * const igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS]
> = { diff --git a/lib/igt_kms.h b/lib/igt_kms.h index
> e9ecd21e..5c7d7481 100644
> --- a/lib/igt_kms.h
> +++ b/lib/igt_kms.h
> @@ -125,6 +125,7 @@ enum igt_atomic_crtc_properties {
> IGT_CRTC_ACTIVE,
> IGT_CRTC_OUT_FENCE_PTR,
> IGT_CRTC_VRR_ENABLED,
> + IGT_CRTC_DSC_SLICE_HEIGHT,
> IGT_NUM_CRTC_PROPS
> };
>
>
Hi Petri,
I followed your advice to search for IGT_NUM_CRTC_PROPS, and only igt_kms.{h,c} and kms_atomic uses it.
In the lib/igt_kms.c, the occurrences of IGT_NUM_CRTC_PROPS appears in the function igt_fill_pipe_props() as a parameter, in its turn, it call drmModeObjectGetProperties and drmModeGetProperty. Finally, it only populates the prop array based on the returned value from the driver. I suppose we are safe here; I don't see how this patch could regress something in this function. The other places where this function appears are in the loop condition, but all of them look correct to me.
Finally, the other place we can see it is in the kms_atomic, but again the for loop looks correct.
However, IGT CI failed:
https://patchwork.freedesktop.org/series/97470/#rev2
The potential new issue pointed by the CI is:
Possible new issues
Here are the unknown changes that may have been introduced in
IGTPW_6475_full:
IGT changes
Possible regressions
igt@sysfs_heartbeat_interval@precise@vecs0:
shard-apl: PASS -> FAIL
And the log says:
Stack trace:
#0 ../lib/igt_core.c:1745 __igt_fail_assert()
#1 ../tests/i915/sysfs_heartbeat_interval.c:156 __test_timeout()
#2 [<unknown>+0xd0]
Dynamic subtest vecs0: FAIL (1.713s)
After I resubmitted this patch, I also noticed that I got a different CI error from the one from the V1. The reported error looks a little bit inconsistent.
Petri, do you think this can be a false-positive, or am I missing something? Maybe re-trigger IGT.CI can help?
Thanks
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
2021-12-09 1:48 ` Rodrigo Siqueira Jordao
2021-12-09 6:23 ` Vudum, Lakshminarayana
@ 2021-12-09 11:16 ` Petri Latvala
2021-12-09 17:06 ` Vudum, Lakshminarayana
1 sibling, 1 reply; 12+ messages in thread
From: Petri Latvala @ 2021-12-09 11:16 UTC (permalink / raw)
To: Rodrigo Siqueira Jordao; +Cc: igt-dev, Vudum, Lakshminarayana
On Wed, Dec 08, 2021 at 08:48:17PM -0500, Rodrigo Siqueira Jordao wrote:
>
>
> On 2021-12-07 11:43 a.m., Rodrigo Siqueira wrote:
> > This preparation work introduces a new CRTC property named
> > DSC_SLICE_HEIGHT, which will be required for amdgpu DSC tests.
> >
> > Cc: Petri Latvala <petri.latvala@intel.com>
> > Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> > ---
> > lib/igt_kms.c | 1 +
> > lib/igt_kms.h | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> > index 34a2aa00..fdadb6d6 100644
> > --- a/lib/igt_kms.c
> > +++ b/lib/igt_kms.c
> > @@ -593,6 +593,7 @@ const char * const igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
> > [IGT_CRTC_ACTIVE] = "ACTIVE",
> > [IGT_CRTC_OUT_FENCE_PTR] = "OUT_FENCE_PTR",
> > [IGT_CRTC_VRR_ENABLED] = "VRR_ENABLED",
> > + [IGT_CRTC_DSC_SLICE_HEIGHT] = "DSC_SLICE_HEIGHT",
> > };
> > const char * const igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
> > diff --git a/lib/igt_kms.h b/lib/igt_kms.h
> > index e9ecd21e..5c7d7481 100644
> > --- a/lib/igt_kms.h
> > +++ b/lib/igt_kms.h
> > @@ -125,6 +125,7 @@ enum igt_atomic_crtc_properties {
> > IGT_CRTC_ACTIVE,
> > IGT_CRTC_OUT_FENCE_PTR,
> > IGT_CRTC_VRR_ENABLED,
> > + IGT_CRTC_DSC_SLICE_HEIGHT,
> > IGT_NUM_CRTC_PROPS
> > };
> >
>
> Hi Petri,
>
> I followed your advice to search for IGT_NUM_CRTC_PROPS, and only
> igt_kms.{h,c} and kms_atomic uses it.
>
> In the lib/igt_kms.c, the occurrences of IGT_NUM_CRTC_PROPS appears in the
> function igt_fill_pipe_props() as a parameter, in its turn, it call
> drmModeObjectGetProperties and drmModeGetProperty. Finally, it only
> populates the prop array based on the returned value from the driver. I
> suppose we are safe here; I don't see how this patch could regress something
> in this function. The other places where this function appears are in the
> loop condition, but all of them look correct to me.
Yeah that looks correct, thanks.
>
> Finally, the other place we can see it is in the kms_atomic, but again the
> for loop looks correct.
>
> However, IGT CI failed:
>
> https://patchwork.freedesktop.org/series/97470/#rev2
>
> The potential new issue pointed by the CI is:
>
> Possible new issues
> Here are the unknown changes that may have been introduced in
> IGTPW_6475_full:
>
> IGT changes
> Possible regressions
> igt@sysfs_heartbeat_interval@precise@vecs0:
> shard-apl: PASS -> FAIL
>
> And the log says:
>
> Stack trace:
> #0 ../lib/igt_core.c:1745 __igt_fail_assert()
> #1 ../tests/i915/sysfs_heartbeat_interval.c:156 __test_timeout()
> #2 [<unknown>+0xd0]
> Dynamic subtest vecs0: FAIL (1.713s)
>
> After I resubmitted this patch, I also noticed that I got a different CI
> error from the one from the V1. The reported error looks a little bit
> inconsistent.
>
> Petri, do you think this can be a false-positive, or am I missing something?
> Maybe re-trigger IGT.CI can help?
Looks like false positives to me and I believe Lakshmi already
addressed those for you.
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for tests/amdgpu: Introduce DSC tests (rev2)
2021-12-07 16:43 [igt-dev] [PATCH v4 0/2] tests/amdgpu: Introduce DSC tests Rodrigo Siqueira
` (3 preceding siblings ...)
2021-12-08 1:59 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-12-09 16:38 ` Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2021-12-09 16:38 UTC (permalink / raw)
To: Rodrigo Siqueira; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 30258 bytes --]
== Series Details ==
Series: tests/amdgpu: Introduce DSC tests (rev2)
URL : https://patchwork.freedesktop.org/series/97470/
State : success
== Summary ==
CI Bug Log - changes from IGT_6302_full -> IGTPW_6475_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/index.html
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in IGTPW_6475_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglb: NOTRUN -> [SKIP][1] ([i915#4525])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_endless@dispatch@vecs0:
- shard-tglb: [PASS][2] -> [INCOMPLETE][3] ([i915#3778])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-tglb2/igt@gem_exec_endless@dispatch@vecs0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@gem_exec_endless@dispatch@vecs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb3/igt@gem_exec_fair@basic-pace@bcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
- shard-kbl: [PASS][11] -> [SKIP][12] ([fdo#109271])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@no-bsd:
- shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109283])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@gem_exec_params@no-bsd.html
* igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][16] ([fdo#109283])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb6/igt@gem_exec_params@no-vebox.html
* igt@gem_lmem_swapping@heavy-random:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl3/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl6/igt@gem_lmem_swapping@parallel-multi.html
- shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk9/igt@gem_lmem_swapping@parallel-multi.html
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4613])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@gem_lmem_swapping@parallel-multi.html
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#4613])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_pwrite@basic-exhaustion:
- shard-iclb: NOTRUN -> [WARN][22] ([i915#2658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-iclb: NOTRUN -> [SKIP][23] ([i915#4270])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb7/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-tglb: NOTRUN -> [SKIP][24] ([i915#4270])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gem_render_copy@y-tiled-to-vebox-linear:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#768]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb6/igt@gem_render_copy@y-tiled-to-vebox-linear.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#3297])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@gem_userptr_blits@unsync-unmap-after-close.html
- shard-iclb: NOTRUN -> [SKIP][27] ([i915#3297])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen3_render_tiledy_blits:
- shard-tglb: NOTRUN -> [SKIP][28] ([fdo#109289]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@gen3_render_tiledy_blits.html
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109289]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb6/igt@gen3_render_tiledy_blits.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#2856]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@shadow-peek:
- shard-iclb: NOTRUN -> [SKIP][31] ([i915#2856]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][32] -> [SKIP][33] ([i915#4281])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-tglb: NOTRUN -> [SKIP][34] ([fdo#109506] / [i915#2411]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@pc8-residency:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109293] / [fdo#109506])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@i915_pm_rpm@pc8-residency.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-tglb: NOTRUN -> [SKIP][36] ([fdo#109303])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@i915_query@query-topology-known-pci-ids.html
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109303])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb5/igt@i915_query@query-topology-known-pci-ids.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][38] -> [DMESG-WARN][39] ([i915#180]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-apl7/igt@i915_suspend@sysfs-reader.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl2/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@linear-64bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#110725] / [fdo#111614]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@kms_big_fb@linear-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#111614]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][42] ([fdo#110723]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb5/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#111615]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3777])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_joiner@basic:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#2705])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb1/igt@kms_big_joiner@basic.html
- shard-iclb: NOTRUN -> [SKIP][46] ([i915#2705])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +9 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#111615] / [i915#3689]) +4 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#3689]) +4 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3886]) +4 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk5/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#3689] / [i915#3886]) +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109278] / [i915#3886]) +7 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
- shard-apl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#3886]) +5 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cdclk@mode-transition:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271]) +84 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl1/igt@kms_cdclk@mode-transition.html
- shard-iclb: NOTRUN -> [SKIP][55] ([i915#3742])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@kms_cdclk@mode-transition.html
- shard-tglb: NOTRUN -> [SKIP][56] ([i915#3742])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb1/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-glk: NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +5 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk4/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-snb: NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +5 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-snb7/igt@kms_chamelium@hdmi-mode-timings.html
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109284] / [fdo#111827]) +6 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][60] ([fdo#109271] / [fdo#111827]) +15 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl2/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color@pipe-d-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109278] / [i915#1149])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@kms_color@pipe-d-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-b-ctm-0-5:
- shard-tglb: NOTRUN -> [SKIP][62] ([fdo#109284] / [fdo#111827]) +8 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271] / [fdo#111827]) +8 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl1/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-d-gamma:
- shard-iclb: NOTRUN -> [SKIP][64] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@kms_color_chamelium@pipe-d-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#3319]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][66] ([fdo#109278] / [fdo#109279]) +3 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
- shard-tglb: NOTRUN -> [SKIP][67] ([fdo#109279] / [i915#3359]) +4 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][68] ([i915#3359]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement.html
* igt@kms_cursor_edge_walk@pipe-d-64x64-left-edge:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271]) +156 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl1/igt@kms_cursor_edge_walk@pipe-d-64x64-left-edge.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#4103])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109274] / [fdo#109278]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-iclb: NOTRUN -> [SKIP][72] ([fdo#109274]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb6/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][73] -> [DMESG-WARN][74] ([i915#180]) +11 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#2587])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2672])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs:
- shard-apl: NOTRUN -> [DMESG-WARN][77] ([i915#1226])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl4/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-tglb: NOTRUN -> [SKIP][78] ([fdo#111825]) +28 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109280]) +14 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-glk: NOTRUN -> [SKIP][80] ([fdo#109271]) +52 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-iclb: NOTRUN -> [SKIP][81] ([i915#1839])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#533]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl7/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-glk: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#533])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk1/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
- shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#533])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl1/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-kbl: NOTRUN -> [DMESG-WARN][85] ([i915#180])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][86] ([fdo#108145] / [i915#265])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
- shard-kbl: NOTRUN -> [FAIL][87] ([fdo#108145] / [i915#265])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
- shard-iclb: NOTRUN -> [SKIP][88] ([fdo#109278]) +22 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb7/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-b-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][89] ([fdo#111615] / [fdo#112054])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@kms_plane_lowres@pipe-b-tiling-yf.html
- shard-iclb: NOTRUN -> [SKIP][90] ([i915#3536])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@kms_plane_lowres@pipe-b-tiling-yf.html
* igt@kms_plane_lowres@pipe-d-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][91] ([i915#3536])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb8/igt@kms_plane_lowres@pipe-d-tiling-none.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#658]) +4 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
- shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#658]) +2 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-tglb: NOTRUN -> [SKIP][94] ([i915#2920]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: NOTRUN -> [SKIP][95] ([i915#658]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-tglb: NOTRUN -> [SKIP][96] ([i915#1911])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb3/igt@kms_psr2_su@page_flip-nv12.html
- shard-glk: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#658])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk3/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][98] -> [SKIP][99] ([fdo#109441]) +3 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
- shard-snb: NOTRUN -> [SKIP][100] ([fdo#109271]) +105 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-snb6/igt@kms_universal_plane@disable-primary-vs-flip-pipe-d.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][101] ([i915#180] / [i915#295])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-kbl: NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#2437]) +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl4/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][103] ([i915#2530])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame.html
* igt@nouveau_crc@pipe-a-source-outp-inactive:
- shard-tglb: NOTRUN -> [SKIP][104] ([i915#2530])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@nouveau_crc@pipe-a-source-outp-inactive.html
* igt@prime_nv_api@nv_i915_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109291]) +4 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb4/igt@prime_nv_api@nv_i915_import_twice_check_flink_name.html
* igt@prime_nv_pcopy@test1_macro:
- shard-tglb: NOTRUN -> [SKIP][106] ([fdo#109291]) +3 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb5/igt@prime_nv_pcopy@test1_macro.html
* igt@sysfs_clients@sema-50:
- shard-iclb: NOTRUN -> [SKIP][107] ([i915#2994])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@sysfs_clients@sema-50.html
- shard-kbl: NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#2994]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl2/igt@sysfs_clients@sema-50.html
- shard-apl: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#2994])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl3/igt@sysfs_clients@sema-50.html
- shard-glk: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#2994])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk3/igt@sysfs_clients@sema-50.html
* igt@sysfs_clients@split-10:
- shard-tglb: NOTRUN -> [SKIP][111] ([i915#2994]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb2/igt@sysfs_clients@split-10.html
* igt@sysfs_heartbeat_interval@precise@vecs0:
- shard-apl: [PASS][112] -> [FAIL][113] ([i915#1755])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-apl6/igt@sysfs_heartbeat_interval@precise@vecs0.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl6/igt@sysfs_heartbeat_interval@precise@vecs0.html
#### Possible fixes ####
* igt@gem_eio@in-flight-10ms:
- shard-iclb: [TIMEOUT][114] ([i915#3070]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb4/igt@gem_eio@in-flight-10ms.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb6/igt@gem_eio@in-flight-10ms.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglb: [FAIL][116] ([i915#2842]) -> [PASS][117] +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-tglb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-tglb6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][118] ([i915#2842]) -> [PASS][119] +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][120] ([i915#2842]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
- shard-glk: [FAIL][122] ([i915#2842]) -> [PASS][123] +3 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-glk3/igt@gem_exec_fair@basic-pace@vecs0.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk2/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][124] ([i915#2849]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][126] ([i915#454]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb5/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-iclb: [INCOMPLETE][128] -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb4/igt@i915_pm_rpm@debugfs-forcewake-user.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-iclb5/igt@i915_pm_rpm@debugfs-forcewake-user.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [DMESG-WARN][130] ([i915#118]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-glk4/igt@kms_big_fb@linear-32bpp-rotate-0.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk9/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [DMESG-WARN][132] ([i915#180]) -> [PASS][133] +1 similar issue
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-glk: [FAIL][134] ([i915#1888] / [i915#2546]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-glk2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/shard-glk7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html
- shard-iclb: [FAIL][136] ([i915#2546]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6302/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html
[137]: https://intel
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6475/index.html
[-- Attachment #2: Type: text/html, Size: 33834 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
2021-12-09 11:16 ` Petri Latvala
@ 2021-12-09 17:06 ` Vudum, Lakshminarayana
2021-12-09 22:41 ` Navare, Manasi D
0 siblings, 1 reply; 12+ messages in thread
From: Vudum, Lakshminarayana @ 2021-12-09 17:06 UTC (permalink / raw)
To: Latvala, Petri, Rodrigo Siqueira Jordao; +Cc: igt-dev
Re-reported.
-----Original Message-----
From: Latvala, Petri <petri.latvala@intel.com>
Sent: Thursday, December 9, 2021 3:16 AM
To: Rodrigo Siqueira Jordao <rjordrigo@amd.com>
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>; igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
On Wed, Dec 08, 2021 at 08:48:17PM -0500, Rodrigo Siqueira Jordao wrote:
>
>
> On 2021-12-07 11:43 a.m., Rodrigo Siqueira wrote:
> > This preparation work introduces a new CRTC property named
> > DSC_SLICE_HEIGHT, which will be required for amdgpu DSC tests.
> >
> > Cc: Petri Latvala <petri.latvala@intel.com>
> > Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> > ---
> > lib/igt_kms.c | 1 +
> > lib/igt_kms.h | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/lib/igt_kms.c b/lib/igt_kms.c index 34a2aa00..fdadb6d6
> > 100644
> > --- a/lib/igt_kms.c
> > +++ b/lib/igt_kms.c
> > @@ -593,6 +593,7 @@ const char * const igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
> > [IGT_CRTC_ACTIVE] = "ACTIVE",
> > [IGT_CRTC_OUT_FENCE_PTR] = "OUT_FENCE_PTR",
> > [IGT_CRTC_VRR_ENABLED] = "VRR_ENABLED",
> > + [IGT_CRTC_DSC_SLICE_HEIGHT] = "DSC_SLICE_HEIGHT",
> > };
> > const char * const
> > igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = { diff --git
> > a/lib/igt_kms.h b/lib/igt_kms.h index e9ecd21e..5c7d7481 100644
> > --- a/lib/igt_kms.h
> > +++ b/lib/igt_kms.h
> > @@ -125,6 +125,7 @@ enum igt_atomic_crtc_properties {
> > IGT_CRTC_ACTIVE,
> > IGT_CRTC_OUT_FENCE_PTR,
> > IGT_CRTC_VRR_ENABLED,
> > + IGT_CRTC_DSC_SLICE_HEIGHT,
> > IGT_NUM_CRTC_PROPS
> > };
> >
>
> Hi Petri,
>
> I followed your advice to search for IGT_NUM_CRTC_PROPS, and only
> igt_kms.{h,c} and kms_atomic uses it.
>
> In the lib/igt_kms.c, the occurrences of IGT_NUM_CRTC_PROPS appears in
> the function igt_fill_pipe_props() as a parameter, in its turn, it
> call drmModeObjectGetProperties and drmModeGetProperty. Finally, it
> only populates the prop array based on the returned value from the
> driver. I suppose we are safe here; I don't see how this patch could
> regress something in this function. The other places where this
> function appears are in the loop condition, but all of them look correct to me.
Yeah that looks correct, thanks.
>
> Finally, the other place we can see it is in the kms_atomic, but again
> the for loop looks correct.
>
> However, IGT CI failed:
>
> https://patchwork.freedesktop.org/series/97470/#rev2
>
> The potential new issue pointed by the CI is:
>
> Possible new issues
> Here are the unknown changes that may have been introduced in
> IGTPW_6475_full:
>
> IGT changes
> Possible regressions
> igt@sysfs_heartbeat_interval@precise@vecs0:
> shard-apl: PASS -> FAIL
>
> And the log says:
>
> Stack trace:
> #0 ../lib/igt_core.c:1745 __igt_fail_assert()
> #1 ../tests/i915/sysfs_heartbeat_interval.c:156 __test_timeout()
> #2 [<unknown>+0xd0]
> Dynamic subtest vecs0: FAIL (1.713s)
>
> After I resubmitted this patch, I also noticed that I got a different
> CI error from the one from the V1. The reported error looks a little
> bit inconsistent.
>
> Petri, do you think this can be a false-positive, or am I missing something?
> Maybe re-trigger IGT.CI can help?
Looks like false positives to me and I believe Lakshmi already addressed those for you.
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
2021-12-09 17:06 ` Vudum, Lakshminarayana
@ 2021-12-09 22:41 ` Navare, Manasi D
2021-12-10 16:22 ` Harry Wentland
0 siblings, 1 reply; 12+ messages in thread
From: Navare, Manasi D @ 2021-12-09 22:41 UTC (permalink / raw)
To: Vudum, Lakshminarayana, Latvala, Petri, Rodrigo Siqueira Jordao; +Cc: igt-dev
Hi Rodrigo,
Is the DSC Slice height added so that the userspace can control it through the CRTC property, and in that case what is the advantage or the need for userspace to control the dsc slice height, IMO it should be seamless to end users.
If its only for AMD DSC tests, can you accomplish this through a debugfs node?
Regards
Manasi
-----Original Message-----
From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Vudum, Lakshminarayana
Sent: Thursday, December 9, 2021 9:06 AM
To: Latvala, Petri <petri.latvala@intel.com>; Rodrigo Siqueira Jordao <rjordrigo@amd.com>
Cc: igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
Re-reported.
-----Original Message-----
From: Latvala, Petri <petri.latvala@intel.com>
Sent: Thursday, December 9, 2021 3:16 AM
To: Rodrigo Siqueira Jordao <rjordrigo@amd.com>
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>; igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
On Wed, Dec 08, 2021 at 08:48:17PM -0500, Rodrigo Siqueira Jordao wrote:
>
>
> On 2021-12-07 11:43 a.m., Rodrigo Siqueira wrote:
> > This preparation work introduces a new CRTC property named
> > DSC_SLICE_HEIGHT, which will be required for amdgpu DSC tests.
> >
> > Cc: Petri Latvala <petri.latvala@intel.com>
> > Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> > ---
> > lib/igt_kms.c | 1 +
> > lib/igt_kms.h | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/lib/igt_kms.c b/lib/igt_kms.c index 34a2aa00..fdadb6d6
> > 100644
> > --- a/lib/igt_kms.c
> > +++ b/lib/igt_kms.c
> > @@ -593,6 +593,7 @@ const char * const igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
> > [IGT_CRTC_ACTIVE] = "ACTIVE",
> > [IGT_CRTC_OUT_FENCE_PTR] = "OUT_FENCE_PTR",
> > [IGT_CRTC_VRR_ENABLED] = "VRR_ENABLED",
> > + [IGT_CRTC_DSC_SLICE_HEIGHT] = "DSC_SLICE_HEIGHT",
> > };
> > const char * const
> > igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = { diff --git
> > a/lib/igt_kms.h b/lib/igt_kms.h index e9ecd21e..5c7d7481 100644
> > --- a/lib/igt_kms.h
> > +++ b/lib/igt_kms.h
> > @@ -125,6 +125,7 @@ enum igt_atomic_crtc_properties {
> > IGT_CRTC_ACTIVE,
> > IGT_CRTC_OUT_FENCE_PTR,
> > IGT_CRTC_VRR_ENABLED,
> > + IGT_CRTC_DSC_SLICE_HEIGHT,
> > IGT_NUM_CRTC_PROPS
> > };
> >
>
> Hi Petri,
>
> I followed your advice to search for IGT_NUM_CRTC_PROPS, and only
> igt_kms.{h,c} and kms_atomic uses it.
>
> In the lib/igt_kms.c, the occurrences of IGT_NUM_CRTC_PROPS appears in
> the function igt_fill_pipe_props() as a parameter, in its turn, it
> call drmModeObjectGetProperties and drmModeGetProperty. Finally, it
> only populates the prop array based on the returned value from the
> driver. I suppose we are safe here; I don't see how this patch could
> regress something in this function. The other places where this
> function appears are in the loop condition, but all of them look correct to me.
Yeah that looks correct, thanks.
>
> Finally, the other place we can see it is in the kms_atomic, but again
> the for loop looks correct.
>
> However, IGT CI failed:
>
> https://patchwork.freedesktop.org/series/97470/#rev2
>
> The potential new issue pointed by the CI is:
>
> Possible new issues
> Here are the unknown changes that may have been introduced in
> IGTPW_6475_full:
>
> IGT changes
> Possible regressions
> igt@sysfs_heartbeat_interval@precise@vecs0:
> shard-apl: PASS -> FAIL
>
> And the log says:
>
> Stack trace:
> #0 ../lib/igt_core.c:1745 __igt_fail_assert()
> #1 ../tests/i915/sysfs_heartbeat_interval.c:156 __test_timeout()
> #2 [<unknown>+0xd0]
> Dynamic subtest vecs0: FAIL (1.713s)
>
> After I resubmitted this patch, I also noticed that I got a different
> CI error from the one from the V1. The reported error looks a little
> bit inconsistent.
>
> Petri, do you think this can be a false-positive, or am I missing something?
> Maybe re-trigger IGT.CI can help?
Looks like false positives to me and I believe Lakshmi already addressed those for you.
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
2021-12-09 22:41 ` Navare, Manasi D
@ 2021-12-10 16:22 ` Harry Wentland
0 siblings, 0 replies; 12+ messages in thread
From: Harry Wentland @ 2021-12-10 16:22 UTC (permalink / raw)
To: Navare, Manasi D, Vudum, Lakshminarayana, Latvala, Petri,
Rodrigo Siqueira Jordao
Cc: igt-dev
On 2021-12-09 17:41, Navare, Manasi D wrote:
> Hi Rodrigo,
>
> Is the DSC Slice height added so that the userspace can control it through the CRTC property, and in that case what is the advantage or the need for userspace to control the dsc slice height, IMO it should be seamless to end users.
> If its only for AMD DSC tests, can you accomplish this through a debugfs node?
>
You're right, this isn't needed. We had this property
as a read-only property in an internal repo but it
never went upstream, and shouldn't be upstream.
Siqueira, please drop this patch and any work that's
trying to use DSC_SLICE_HEIGHT.
Thanks,
Harry
> Regards
> Manasi
>
> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Vudum, Lakshminarayana
> Sent: Thursday, December 9, 2021 9:06 AM
> To: Latvala, Petri <petri.latvala@intel.com>; Rodrigo Siqueira Jordao <rjordrigo@amd.com>
> Cc: igt-dev@lists.freedesktop.org
> Subject: Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
>
> Re-reported.
>
> -----Original Message-----
> From: Latvala, Petri <petri.latvala@intel.com>
> Sent: Thursday, December 9, 2021 3:16 AM
> To: Rodrigo Siqueira Jordao <rjordrigo@amd.com>
> Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>; igt-dev@lists.freedesktop.org
> Subject: Re: [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property
>
> On Wed, Dec 08, 2021 at 08:48:17PM -0500, Rodrigo Siqueira Jordao wrote:
>>
>>
>> On 2021-12-07 11:43 a.m., Rodrigo Siqueira wrote:
>>> This preparation work introduces a new CRTC property named
>>> DSC_SLICE_HEIGHT, which will be required for amdgpu DSC tests.
>>>
>>> Cc: Petri Latvala <petri.latvala@intel.com>
>>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>>> ---
>>> lib/igt_kms.c | 1 +
>>> lib/igt_kms.h | 1 +
>>> 2 files changed, 2 insertions(+)
>>>
>>> diff --git a/lib/igt_kms.c b/lib/igt_kms.c index 34a2aa00..fdadb6d6
>>> 100644
>>> --- a/lib/igt_kms.c
>>> +++ b/lib/igt_kms.c
>>> @@ -593,6 +593,7 @@ const char * const igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
>>> [IGT_CRTC_ACTIVE] = "ACTIVE",
>>> [IGT_CRTC_OUT_FENCE_PTR] = "OUT_FENCE_PTR",
>>> [IGT_CRTC_VRR_ENABLED] = "VRR_ENABLED",
>>> + [IGT_CRTC_DSC_SLICE_HEIGHT] = "DSC_SLICE_HEIGHT",
>>> };
>>> const char * const
>>> igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = { diff --git
>>> a/lib/igt_kms.h b/lib/igt_kms.h index e9ecd21e..5c7d7481 100644
>>> --- a/lib/igt_kms.h
>>> +++ b/lib/igt_kms.h
>>> @@ -125,6 +125,7 @@ enum igt_atomic_crtc_properties {
>>> IGT_CRTC_ACTIVE,
>>> IGT_CRTC_OUT_FENCE_PTR,
>>> IGT_CRTC_VRR_ENABLED,
>>> + IGT_CRTC_DSC_SLICE_HEIGHT,
>>> IGT_NUM_CRTC_PROPS
>>> };
>>>
>>
>> Hi Petri,
>>
>> I followed your advice to search for IGT_NUM_CRTC_PROPS, and only
>> igt_kms.{h,c} and kms_atomic uses it.
>>
>> In the lib/igt_kms.c, the occurrences of IGT_NUM_CRTC_PROPS appears in
>> the function igt_fill_pipe_props() as a parameter, in its turn, it
>> call drmModeObjectGetProperties and drmModeGetProperty. Finally, it
>> only populates the prop array based on the returned value from the
>> driver. I suppose we are safe here; I don't see how this patch could
>> regress something in this function. The other places where this
>> function appears are in the loop condition, but all of them look correct to me.
>
> Yeah that looks correct, thanks.
>
>>
>> Finally, the other place we can see it is in the kms_atomic, but again
>> the for loop looks correct.
>>
>> However, IGT CI failed:
>>
>> https://patchwork.freedesktop.org/series/97470/#rev2>>>
>> The potential new issue pointed by the CI is:
>>
>> Possible new issues
>> Here are the unknown changes that may have been introduced in
>> IGTPW_6475_full:
>>
>> IGT changes
>> Possible regressions
>> igt@sysfs_heartbeat_interval@precise@vecs0:
>> shard-apl: PASS -> FAIL
>>
>> And the log says:
>>
>> Stack trace:
>> #0 ../lib/igt_core.c:1745 __igt_fail_assert()
>> #1 ../tests/i915/sysfs_heartbeat_interval.c:156 __test_timeout()
>> #2 [<unknown>+0xd0]
>> Dynamic subtest vecs0: FAIL (1.713s)
>>
>> After I resubmitted this patch, I also noticed that I got a different
>> CI error from the one from the V1. The reported error looks a little
>> bit inconsistent.
>>
>> Petri, do you think this can be a false-positive, or am I missing something?
>> Maybe re-trigger IGT.CI can help?
>
> Looks like false positives to me and I believe Lakshmi already addressed those for you.
>
>
> Reviewed-by: Petri Latvala <petri.latvala@intel.com>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-12-10 16:22 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-07 16:43 [igt-dev] [PATCH v4 0/2] tests/amdgpu: Introduce DSC tests Rodrigo Siqueira
2021-12-07 16:43 ` [igt-dev] [PATCH v4 1/2] lib/kms: Add DSC_SLICE_HEIGHT to CRTC property Rodrigo Siqueira
2021-12-09 1:48 ` Rodrigo Siqueira Jordao
2021-12-09 6:23 ` Vudum, Lakshminarayana
2021-12-09 11:16 ` Petri Latvala
2021-12-09 17:06 ` Vudum, Lakshminarayana
2021-12-09 22:41 ` Navare, Manasi D
2021-12-10 16:22 ` Harry Wentland
2021-12-07 16:43 ` [igt-dev] [PATCH v4 2/2] tests/amdgpu: Introduces DP DSC test Rodrigo Siqueira
2021-12-07 19:21 ` [igt-dev] ✓ Fi.CI.BAT: success for tests/amdgpu: Introduce DSC tests (rev2) Patchwork
2021-12-08 1:59 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2021-12-09 16:38 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
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