* [PATCH 0/4] Basic enabling of 64k page support
@ 2021-12-07 16:51 ` Ramalingam C
0 siblings, 0 replies; 20+ messages in thread
From: Ramalingam C @ 2021-12-07 16:51 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Hellstrom Thomas, Andi, Chris_intel_ID
Preparational patches for 64k page support.
Matthew Auld (3):
drm/i915/xehpsdv: set min page-size to 64K
drm/i915/gtt/xehpsdv: move scratch page to system memory
drm/i915: enforce min page size for scratch
Stuart Summers (1):
drm/i915: Add has_64k_pages flag
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 +++++-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 23 +++++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++++++++++++-
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 ++++-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 ++
11 files changed, 56 insertions(+), 5 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 0/4] Basic enabling of 64k page support
@ 2021-12-07 16:51 ` Ramalingam C
0 siblings, 0 replies; 20+ messages in thread
From: Ramalingam C @ 2021-12-07 16:51 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Hellstrom Thomas, Andi, Chris_intel_ID
Preparational patches for 64k page support.
Matthew Auld (3):
drm/i915/xehpsdv: set min page-size to 64K
drm/i915/gtt/xehpsdv: move scratch page to system memory
drm/i915: enforce min page size for scratch
Stuart Summers (1):
drm/i915: Add has_64k_pages flag
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 +++++-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 23 +++++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++++++++++++-
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 ++++-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 ++
11 files changed, 56 insertions(+), 5 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/4] drm/i915: Add has_64k_pages flag
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
@ 2021-12-07 16:51 ` Ramalingam C
-1 siblings, 0 replies; 20+ messages in thread
From: Ramalingam C @ 2021-12-07 16:51 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: Andi, Lucas De Marchi, Chris_intel_ID, Stuart Summers, Hellstrom Thomas
From: Stuart Summers <stuart.summers@intel.com>
Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 85bb8d3107f0..6132163e1cb3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1528,6 +1528,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_MSLICES(dev_priv) \
(INTEL_INFO(dev_priv)->has_mslices)
+#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
+
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6aaa7c644c9b..634282edadb7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1029,6 +1029,7 @@ static const struct intel_device_info xehpsdv_info = {
DGFX_FEATURES,
PLATFORM(INTEL_XEHPSDV),
.display = { },
+ .has_64k_pages = 1,
.pipe_mask = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
@@ -1047,6 +1048,7 @@ static const struct intel_device_info dg2_info = {
.graphics.rel = 55,
.media.rel = 55,
PLATFORM(INTEL_DG2),
+ .has_64k_pages = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 669f0d26c3c3..f38ac5bd837b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -123,6 +123,7 @@ enum intel_ppgtt_type {
func(is_dgfx); \
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
+ func(has_64k_pages); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_global_mocs); \
--
2.20.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 1/4] drm/i915: Add has_64k_pages flag
@ 2021-12-07 16:51 ` Ramalingam C
0 siblings, 0 replies; 20+ messages in thread
From: Ramalingam C @ 2021-12-07 16:51 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: Andi, Lucas De Marchi, Chris_intel_ID, Hellstrom Thomas
From: Stuart Summers <stuart.summers@intel.com>
Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 85bb8d3107f0..6132163e1cb3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1528,6 +1528,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_MSLICES(dev_priv) \
(INTEL_INFO(dev_priv)->has_mslices)
+#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
+
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6aaa7c644c9b..634282edadb7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1029,6 +1029,7 @@ static const struct intel_device_info xehpsdv_info = {
DGFX_FEATURES,
PLATFORM(INTEL_XEHPSDV),
.display = { },
+ .has_64k_pages = 1,
.pipe_mask = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
@@ -1047,6 +1048,7 @@ static const struct intel_device_info dg2_info = {
.graphics.rel = 55,
.media.rel = 55,
PLATFORM(INTEL_DG2),
+ .has_64k_pages = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 669f0d26c3c3..f38ac5bd837b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -123,6 +123,7 @@ enum intel_ppgtt_type {
func(is_dgfx); \
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
+ func(has_64k_pages); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_global_mocs); \
--
2.20.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/4] drm/i915/xehpsdv: set min page-size to 64K
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
@ 2021-12-07 16:51 ` Ramalingam C
-1 siblings, 0 replies; 20+ messages in thread
From: Ramalingam C @ 2021-12-07 16:51 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: Andi, Lucas De Marchi, Chris_intel_ID, Hellstrom Thomas,
Matthew Auld, Rodrigo Vivi
From: Matthew Auld <matthew.auld@intel.com>
LMEM should be allocated at 64K granularity, since 4K page support will
eventually be dropped for LMEM when using the PPGTT.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 +++++-
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 ++++-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index bce03d74a0b4..ba90ab47d838 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -780,6 +780,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
struct intel_uncore *uncore = &i915->uncore;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_memory_region *mem;
+ resource_size_t min_page_size;
resource_size_t io_start;
resource_size_t lmem_size;
u64 lmem_base;
@@ -791,8 +792,11 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
lmem_size = pci_resource_len(pdev, 2) - lmem_base;
io_start = pci_resource_start(pdev, 2) + lmem_base;
+ min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
+ I915_GTT_PAGE_SIZE_4K;
+
mem = intel_memory_region_create(i915, lmem_base, lmem_size,
- I915_GTT_PAGE_SIZE_4K, io_start,
+ min_page_size, io_start,
type, instance,
&i915_region_stolen_lmem_ops);
if (IS_ERR(mem))
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 9ea49e0a27c0..fde2dcb59809 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -197,6 +197,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_memory_region *mem;
+ resource_size_t min_page_size;
resource_size_t io_start;
resource_size_t lmem_size;
int err;
@@ -211,10 +212,12 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
return ERR_PTR(-ENODEV);
+ min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
+ I915_GTT_PAGE_SIZE_4K;
mem = intel_memory_region_create(i915,
0,
lmem_size,
- I915_GTT_PAGE_SIZE_4K,
+ min_page_size,
io_start,
INTEL_MEMORY_LOCAL,
0,
--
2.20.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915/xehpsdv: set min page-size to 64K
@ 2021-12-07 16:51 ` Ramalingam C
0 siblings, 0 replies; 20+ messages in thread
From: Ramalingam C @ 2021-12-07 16:51 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: Andi, Lucas De Marchi, Chris_intel_ID, Hellstrom Thomas, Matthew Auld
From: Matthew Auld <matthew.auld@intel.com>
LMEM should be allocated at 64K granularity, since 4K page support will
eventually be dropped for LMEM when using the PPGTT.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 +++++-
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 ++++-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index bce03d74a0b4..ba90ab47d838 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -780,6 +780,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
struct intel_uncore *uncore = &i915->uncore;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_memory_region *mem;
+ resource_size_t min_page_size;
resource_size_t io_start;
resource_size_t lmem_size;
u64 lmem_base;
@@ -791,8 +792,11 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
lmem_size = pci_resource_len(pdev, 2) - lmem_base;
io_start = pci_resource_start(pdev, 2) + lmem_base;
+ min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
+ I915_GTT_PAGE_SIZE_4K;
+
mem = intel_memory_region_create(i915, lmem_base, lmem_size,
- I915_GTT_PAGE_SIZE_4K, io_start,
+ min_page_size, io_start,
type, instance,
&i915_region_stolen_lmem_ops);
if (IS_ERR(mem))
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 9ea49e0a27c0..fde2dcb59809 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -197,6 +197,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_memory_region *mem;
+ resource_size_t min_page_size;
resource_size_t io_start;
resource_size_t lmem_size;
int err;
@@ -211,10 +212,12 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
return ERR_PTR(-ENODEV);
+ min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
+ I915_GTT_PAGE_SIZE_4K;
mem = intel_memory_region_create(i915,
0,
lmem_size,
- I915_GTT_PAGE_SIZE_4K,
+ min_page_size,
io_start,
INTEL_MEMORY_LOCAL,
0,
--
2.20.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/4] drm/i915/gtt/xehpsdv: move scratch page to system memory
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
@ 2021-12-07 16:51 ` Ramalingam C
-1 siblings, 0 replies; 20+ messages in thread
From: Ramalingam C @ 2021-12-07 16:51 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Hellstrom Thomas, Andi, Matthew Auld, Chris_intel_ID
From: Matthew Auld <matthew.auld@intel.com>
On some platforms the hw has dropped support for 4K GTT pages when
dealing with LMEM, and due to the design of 64K GTT pages in the hw, we
can only mark the *entire* page-table as operating in 64K GTT mode,
since the enable bit is still on the pde, and not the pte. And since we
we still need to allow 4K GTT pages for SMEM objects, we can't have a
"normal" 4K page-table with scratch pointing to LMEM, since that's
undefined from the hw pov. The simplest solution is to just move the 64K
scratch page to SMEM on such platforms and call it a day, since that
should work for all configurations.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 23 +++++++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 ++
6 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 4a166d25fe60..c0d149f04949 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -454,6 +454,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
ppgtt->base.vm.alloc_pt_dma = alloc_pt_dma;
+ ppgtt->base.vm.alloc_scratch_dma = alloc_pt_dma;
ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
err = gen6_ppgtt_init_scratch(ppgtt);
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 95c02096a61b..b012c50f7ce7 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -776,10 +776,29 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
*/
ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
- if (HAS_LMEM(gt->i915))
+ if (HAS_LMEM(gt->i915)) {
ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
- else
+
+ /*
+ * On some platforms the hw has dropped support for 4K GTT pages
+ * when dealing with LMEM, and due to the design of 64K GTT
+ * pages in the hw, we can only mark the *entire* page-table as
+ * operating in 64K GTT mode, since the enable bit is still on
+ * the pde, and not the pte. And since we still need to allow
+ * 4K GTT pages for SMEM objects, we can't have a "normal" 4K
+ * page-table with scratch pointing to LMEM, since that's
+ * undefined from the hw pov. The simplest solution is to just
+ * move the 64K scratch page to SMEM on such platforms and call
+ * it a day, since that should work for all configurations.
+ */
+ if (HAS_64K_PAGES(gt->i915))
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
+ else
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_lmem;
+ } else {
ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
+ }
err = gen8_init_scratch(&ppgtt->vm);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index cbc6d2b1fd9e..d85a1050f4a8 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -941,6 +941,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
size = gen8_get_total_gtt_size(snb_gmch_ctl);
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
@@ -1094,6 +1095,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
ggtt->vm.clear_range = nop_clear_range;
if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
@@ -1146,6 +1148,7 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
if (needs_idle_maps(i915)) {
drm_notice(&i915->drm,
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 0dd254cb1f69..1428e2b9075a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -301,7 +301,7 @@ int setup_scratch_page(struct i915_address_space *vm)
do {
struct drm_i915_gem_object *obj;
- obj = vm->alloc_pt_dma(vm, size);
+ obj = vm->alloc_scratch_dma(vm, size);
if (IS_ERR(obj))
goto skip;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 51afe66d00f2..15b98321e89a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -268,6 +268,8 @@ struct i915_address_space {
struct drm_i915_gem_object *
(*alloc_pt_dma)(struct i915_address_space *vm, int sz);
+ struct drm_i915_gem_object *
+ (*alloc_scratch_dma)(struct i915_address_space *vm, int sz);
u64 (*pte_encode)(dma_addr_t addr,
enum i915_cache_level level,
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c
index cc047ec594f9..32ca8962d0ab 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
@@ -78,6 +78,7 @@ struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name)
i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
ppgtt->vm.clear_range = mock_clear_range;
ppgtt->vm.insert_page = mock_insert_page;
@@ -118,6 +119,7 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt)
ggtt->vm.total = 4096 * PAGE_SIZE;
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
ggtt->vm.clear_range = mock_clear_range;
ggtt->vm.insert_page = mock_insert_page;
--
2.20.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/gtt/xehpsdv: move scratch page to system memory
@ 2021-12-07 16:51 ` Ramalingam C
0 siblings, 0 replies; 20+ messages in thread
From: Ramalingam C @ 2021-12-07 16:51 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Hellstrom Thomas, Andi, Matthew Auld, Chris_intel_ID
From: Matthew Auld <matthew.auld@intel.com>
On some platforms the hw has dropped support for 4K GTT pages when
dealing with LMEM, and due to the design of 64K GTT pages in the hw, we
can only mark the *entire* page-table as operating in 64K GTT mode,
since the enable bit is still on the pde, and not the pte. And since we
we still need to allow 4K GTT pages for SMEM objects, we can't have a
"normal" 4K page-table with scratch pointing to LMEM, since that's
undefined from the hw pov. The simplest solution is to just move the 64K
scratch page to SMEM on such platforms and call it a day, since that
should work for all configurations.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 23 +++++++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 ++
6 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 4a166d25fe60..c0d149f04949 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -454,6 +454,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
ppgtt->base.vm.alloc_pt_dma = alloc_pt_dma;
+ ppgtt->base.vm.alloc_scratch_dma = alloc_pt_dma;
ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
err = gen6_ppgtt_init_scratch(ppgtt);
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 95c02096a61b..b012c50f7ce7 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -776,10 +776,29 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
*/
ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
- if (HAS_LMEM(gt->i915))
+ if (HAS_LMEM(gt->i915)) {
ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
- else
+
+ /*
+ * On some platforms the hw has dropped support for 4K GTT pages
+ * when dealing with LMEM, and due to the design of 64K GTT
+ * pages in the hw, we can only mark the *entire* page-table as
+ * operating in 64K GTT mode, since the enable bit is still on
+ * the pde, and not the pte. And since we still need to allow
+ * 4K GTT pages for SMEM objects, we can't have a "normal" 4K
+ * page-table with scratch pointing to LMEM, since that's
+ * undefined from the hw pov. The simplest solution is to just
+ * move the 64K scratch page to SMEM on such platforms and call
+ * it a day, since that should work for all configurations.
+ */
+ if (HAS_64K_PAGES(gt->i915))
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
+ else
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_lmem;
+ } else {
ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
+ }
err = gen8_init_scratch(&ppgtt->vm);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index cbc6d2b1fd9e..d85a1050f4a8 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -941,6 +941,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
size = gen8_get_total_gtt_size(snb_gmch_ctl);
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
@@ -1094,6 +1095,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
ggtt->vm.clear_range = nop_clear_range;
if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
@@ -1146,6 +1148,7 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
if (needs_idle_maps(i915)) {
drm_notice(&i915->drm,
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 0dd254cb1f69..1428e2b9075a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -301,7 +301,7 @@ int setup_scratch_page(struct i915_address_space *vm)
do {
struct drm_i915_gem_object *obj;
- obj = vm->alloc_pt_dma(vm, size);
+ obj = vm->alloc_scratch_dma(vm, size);
if (IS_ERR(obj))
goto skip;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 51afe66d00f2..15b98321e89a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -268,6 +268,8 @@ struct i915_address_space {
struct drm_i915_gem_object *
(*alloc_pt_dma)(struct i915_address_space *vm, int sz);
+ struct drm_i915_gem_object *
+ (*alloc_scratch_dma)(struct i915_address_space *vm, int sz);
u64 (*pte_encode)(dma_addr_t addr,
enum i915_cache_level level,
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c
index cc047ec594f9..32ca8962d0ab 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
@@ -78,6 +78,7 @@ struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name)
i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
ppgtt->vm.clear_range = mock_clear_range;
ppgtt->vm.insert_page = mock_insert_page;
@@ -118,6 +119,7 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt)
ggtt->vm.total = 4096 * PAGE_SIZE;
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
ggtt->vm.clear_range = mock_clear_range;
ggtt->vm.insert_page = mock_insert_page;
--
2.20.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 4/4] drm/i915: enforce min page size for scratch
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
@ 2021-12-07 16:51 ` Ramalingam C
-1 siblings, 0 replies; 20+ messages in thread
From: Ramalingam C @ 2021-12-07 16:51 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Hellstrom Thomas, Andi, Matthew Auld, Chris_intel_ID
From: Matthew Auld <matthew.auld@intel.com>
If the device needs 64K minimum GTT pages for device local-memory,
like on XEHPSDV, then we need to fail the allocation if we can't
meet it, instead of falling back to 4K pages, otherwise we can't
safely support the insertion of device local-memory pages for
this vm, since the HW expects the correct physical alignment and
size for every PTE, if we mark the page-table as 64K GTT mode.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 1428e2b9075a..869b771a5fdc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -337,6 +337,18 @@ int setup_scratch_page(struct i915_address_space *vm)
if (size == I915_GTT_PAGE_SIZE_4K)
return -ENOMEM;
+ /*
+ * If we need 64K minimum GTT pages for device local-memory,
+ * like on XEHPSDV, then we need to fail the allocation here,
+ * otherwise we can't safely support the insertion of
+ * local-memory pages for this vm, since the HW expects the
+ * correct physical alignment and size when the page-table is
+ * operating in 64K GTT mode, which includes any scratch PTEs,
+ * since userpsace can still touch them.
+ */
+ if (HAS_64K_PAGES(vm->i915))
+ return -ENOMEM;
+
size = I915_GTT_PAGE_SIZE_4K;
} while (1);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: enforce min page size for scratch
@ 2021-12-07 16:51 ` Ramalingam C
0 siblings, 0 replies; 20+ messages in thread
From: Ramalingam C @ 2021-12-07 16:51 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Hellstrom Thomas, Andi, Matthew Auld, Chris_intel_ID
From: Matthew Auld <matthew.auld@intel.com>
If the device needs 64K minimum GTT pages for device local-memory,
like on XEHPSDV, then we need to fail the allocation if we can't
meet it, instead of falling back to 4K pages, otherwise we can't
safely support the insertion of device local-memory pages for
this vm, since the HW expects the correct physical alignment and
size for every PTE, if we mark the page-table as 64K GTT mode.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 1428e2b9075a..869b771a5fdc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -337,6 +337,18 @@ int setup_scratch_page(struct i915_address_space *vm)
if (size == I915_GTT_PAGE_SIZE_4K)
return -ENOMEM;
+ /*
+ * If we need 64K minimum GTT pages for device local-memory,
+ * like on XEHPSDV, then we need to fail the allocation here,
+ * otherwise we can't safely support the insertion of
+ * local-memory pages for this vm, since the HW expects the
+ * correct physical alignment and size when the page-table is
+ * operating in 64K GTT mode, which includes any scratch PTEs,
+ * since userpsace can still touch them.
+ */
+ if (HAS_64K_PAGES(vm->i915))
+ return -ENOMEM;
+
size = I915_GTT_PAGE_SIZE_4K;
} while (1);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Basic enabling of 64k page support
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
` (4 preceding siblings ...)
(?)
@ 2021-12-07 20:01 ` Patchwork
-1 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-12-07 20:01 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
== Series Details ==
Series: Basic enabling of 64k page support
URL : https://patchwork.freedesktop.org/series/97666/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Basic enabling of 64k page support
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
` (5 preceding siblings ...)
(?)
@ 2021-12-07 20:29 ` Patchwork
-1 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-12-07 20:29 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8394 bytes --]
== Series Details ==
Series: Basic enabling of 64k page support
URL : https://patchwork.freedesktop.org/series/97666/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10970 -> Patchwork_21775
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/index.html
Participating hosts (42 -> 33)
------------------------------
Additional (1): fi-kbl-soraka
Missing (10): bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_21775 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4: [PASS][2] -> [FAIL][3] ([i915#1888])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html
* igt@i915_module_load@reload:
- fi-tgl-1115g4: [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/fi-tgl-1115g4/igt@i915_module_load@reload.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-tgl-1115g4/igt@i915_module_load@reload.html
* igt@i915_selftest@live:
- fi-skl-6600u: NOTRUN -> [INCOMPLETE][10] ([i915#198])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-skl-6600u/igt@i915_selftest@live.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][11] ([i915#1886] / [i915#2291])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-skl-6600u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][15] -> [DMESG-WARN][16] ([i915#4269])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#533])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][19] ([i915#1888]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [FAIL][21] ([i915#4547]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-FAIL][23] ([i915#295]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][25] ([i915#295]) -> [PASS][26] +10 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
#### Warnings ####
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][27] ([i915#3363] / [i915#4312]) -> [FAIL][28] ([i915#1436] / [i915#2722] / [i915#3363] / [i915#4312])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/fi-skl-6600u/igt@runner@aborted.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/fi-skl-6600u/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_10970 -> Patchwork_21775
CI-20190529: 20190529
CI_DRM_10970: 9368928e088bcfb4bebd54c2ae18603988f40c26 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6301: dcf994172ae04d57adc851668c39e37945f195fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21775: bc5551be17c06de1ce14a53b7b42f72c5bdc0de7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bc5551be17c0 drm/i915: enforce min page size for scratch
b45c19eeb52d drm/i915/gtt/xehpsdv: move scratch page to system memory
37f6d19fa95b drm/i915/xehpsdv: set min page-size to 64K
f29321303f1d drm/i915: Add has_64k_pages flag
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/index.html
[-- Attachment #2: Type: text/html, Size: 10615 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Basic enabling of 64k page support
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
` (6 preceding siblings ...)
(?)
@ 2021-12-08 3:46 ` Patchwork
-1 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-12-08 3:46 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30257 bytes --]
== Series Details ==
Series: Basic enabling of 64k page support
URL : https://patchwork.freedesktop.org/series/97666/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10970_full -> Patchwork_21775_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_21775_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][1] ([i915#3002])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl4/igt@gem_create@create-massive.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][2] -> [FAIL][3] ([i915#2846])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-glk7/igt@gem_exec_fair@basic-deadline.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-glk8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][4] ([i915#2842]) +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][5] -> [SKIP][6] ([fdo#109271])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-iclb7/igt@gem_exec_fair@basic-pace@vcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
- shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-tglb8/igt@gem_exec_fair@basic-pace@vcs1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-tglb6/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][16] -> [SKIP][17] ([i915#2190])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-tglb8/igt@gem_huc_copy@huc-copy.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl10/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl4/igt@gem_lmem_swapping@parallel-random-verify.html
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4613])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_pread@exhaustion:
- shard-iclb: NOTRUN -> [WARN][21] ([i915#2658])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-kbl: NOTRUN -> [WARN][22] ([i915#2658]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][23] ([i915#768])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb6/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3323])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl4/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#3297])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: NOTRUN -> [DMESG-WARN][26] ([i915#180])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen9_exec_parse@bb-start-param:
- shard-iclb: NOTRUN -> [SKIP][27] ([i915#2856])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-tglb: NOTRUN -> [SKIP][28] ([fdo#111644] / [i915#1397] / [i915#2411])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-tglb6/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#110892])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][30] -> [INCOMPLETE][31] ([i915#3921])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-snb4/igt@i915_selftest@live@hangcheck.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#110725] / [fdo#111614]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-apl7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][34] ([fdo#111614])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-tglb6/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#110723])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl1/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109278] / [i915#3886]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3886]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl10/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3689] / [i915#3886])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-tglb6/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@common-hpd-after-suspend:
- shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl10/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-iclb: NOTRUN -> [SKIP][42] ([fdo#109284] / [fdo#111827]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +10 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl4/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-d-ctm-0-75:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-apl7/igt@kms_color_chamelium@pipe-d-ctm-0-75.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][46] ([i915#1319])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl4/igt@kms_content_protection@atomic-dpms.html
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109300] / [fdo#111066])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- shard-snb: [PASS][48] -> [SKIP][49] ([fdo#109271])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-snb4/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-snb7/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-offscreen:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3359])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-32x10-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
- shard-kbl: NOTRUN -> [SKIP][51] ([fdo#109271]) +94 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl2/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109274] / [fdo#109278]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipa-varying-size:
- shard-skl: [PASS][53] -> [DMESG-WARN][54] ([i915#1982]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-skl6/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl10/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [PASS][55] -> [FAIL][56] ([i915#2346])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-kbl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#533]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl2/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#533])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl10/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglb: NOTRUN -> [SKIP][59] ([fdo#111825] / [i915#3966])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-tglb6/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271]) +35 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-apl6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-wf_vblank:
- shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109274]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_flip@2x-flip-vs-wf_vblank.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-tglb: NOTRUN -> [SKIP][62] ([fdo#111825]) +4 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-tglb6/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271]) +61 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render:
- shard-iclb: NOTRUN -> [SKIP][64] ([fdo#109280]) +7 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-apl: NOTRUN -> [FAIL][65] ([i915#1188])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-apl7/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][66] -> [DMESG-WARN][67] ([i915#180]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_invalid_mode@bad-hsync-start:
- shard-glk: [PASS][68] -> [DMESG-WARN][69] ([i915#118]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-glk4/igt@kms_invalid_mode@bad-hsync-start.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-glk7/igt@kms_invalid_mode@bad-hsync-start.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-iclb: NOTRUN -> [SKIP][70] ([fdo#109278]) +13 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [PASS][71] -> [DMESG-WARN][72] ([i915#180]) +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][73] -> [FAIL][74] ([fdo#108145] / [i915#265])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][76] ([fdo#108145] / [i915#265])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-a-tiling-none:
- shard-iclb: NOTRUN -> [SKIP][77] ([i915#3536])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-none.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-iclb: NOTRUN -> [SKIP][78] ([i915#658]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-apl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-skl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#658])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl10/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][82] -> [SKIP][83] ([fdo#109441]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: NOTRUN -> [SKIP][84] ([fdo#109441])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb6/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_setmode@basic:
- shard-glk: [PASS][85] -> [FAIL][86] ([i915#31])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-glk5/igt@kms_setmode@basic.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-glk3/igt@kms_setmode@basic.html
* igt@kms_vrr@flip-dpms:
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109502])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@kms_vrr@flip-dpms.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2437])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-apl7/igt@kms_writeback@writeback-fb-id.html
* igt@perf_pmu@rc6-suspend:
- shard-skl: [PASS][89] -> [INCOMPLETE][90] ([i915#198])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-skl9/igt@perf_pmu@rc6-suspend.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl4/igt@perf_pmu@rc6-suspend.html
* igt@prime_nv_api@nv_self_import_to_different_fd:
- shard-iclb: NOTRUN -> [SKIP][91] ([fdo#109291])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@prime_nv_api@nv_self_import_to_different_fd.html
* igt@prime_vgem@fence-write-hang:
- shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109295])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb4/igt@prime_vgem@fence-write-hang.html
* igt@sysfs_clients@fair-3:
- shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2994])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-apl7/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@pidname:
- shard-skl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#2994])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl10/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [TIMEOUT][95] ([i915#3063]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-tglb1/igt@gem_eio@in-flight-contexts-immediate.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-tglb8/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][97] ([i915#2842]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [FAIL][99] ([i915#2842]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [FAIL][101] ([i915#2842]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-iclb7/igt@gem_exec_fair@basic-pace@vecs0.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb2/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [DMESG-WARN][103] ([i915#1436] / [i915#716]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-skl6/igt@gen9_exec_parse@allowed-all.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl10/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][105] ([i915#454]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_suspend@forcewake:
- shard-skl: [INCOMPLETE][107] ([i915#636]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-skl1/igt@i915_suspend@forcewake.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl4/igt@i915_suspend@forcewake.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [FAIL][109] ([i915#2521]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- {shard-rkl}: [SKIP][111] ([i915#1845]) -> [PASS][112] +18 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-rkl-6/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}: ([SKIP][113], [SKIP][114]) ([i915#1845]) -> [PASS][115] +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-4/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-rkl-6/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color@pipe-a-ctm-blue-to-red:
- {shard-rkl}: ([SKIP][116], [SKIP][117]) ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][118] +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-4/igt@kms_color@pipe-a-ctm-blue-to-red.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-1/igt@kms_color@pipe-a-ctm-blue-to-red.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-rkl-6/igt@kms_color@pipe-a-ctm-blue-to-red.html
* igt@kms_color@pipe-b-ctm-0-5:
- {shard-rkl}: [SKIP][119] ([i915#1149] / [i915#1849] / [i915#4070]) -> [PASS][120] +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-1/igt@kms_color@pipe-b-ctm-0-5.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_color@pipe-c-ctm-0-25:
- shard-skl: [DMESG-WARN][121] ([i915#1982]) -> [PASS][122] +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-skl3/igt@kms_color@pipe-c-ctm-0-25.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl3/igt@kms_color@pipe-c-ctm-0-25.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-random:
- {shard-rkl}: [SKIP][123] ([fdo#112022] / [i915#4070]) -> [PASS][124] +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-1/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- {shard-rkl}: ([SKIP][125], [SKIP][126]) ([fdo#111825] / [i915#4070]) -> [PASS][127] +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-4/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-1/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-rkl-6/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: [FAIL][128] ([i915#2346]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_cursor_legacy@short-flip-after-cursor-toggle:
- {shard-rkl}: [SKIP][130] ([fdo#111825] / [i915#4070]) -> [PASS][131] +2 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-1/igt@kms_cursor_legacy@short-flip-after-cursor-toggle.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-rkl-6/igt@kms_cursor_legacy@short-flip-after-cursor-toggle.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled:
- {shard-rkl}: ([SKIP][132], [SKIP][133]) ([fdo#111314] / [i915#4098]) -> [PASS][134]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-4/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-1/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled:
- {shard-rkl}: [SKIP][135] ([fdo#111314]) -> [PASS][136] +2 similar issues
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-rkl-1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][137] ([i915#79]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl: [DMESG-WARN][139] ([i915#180]) -> [PASS][140] +3 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/shard-apl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-iclb: [SKIP][141] ([i915#3701]) -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10970/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
[142]: https://intel-gfx-ci
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21775/index.html
[-- Attachment #2: Type: text/html, Size: 33485 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Add has_64k_pages flag
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
(?)
@ 2021-12-08 12:43 ` Thomas Hellström (Intel)
2021-12-08 12:59 ` Matthew Auld
-1 siblings, 1 reply; 20+ messages in thread
From: Thomas Hellström (Intel) @ 2021-12-08 12:43 UTC (permalink / raw)
To: Ramalingam C, intel-gfx, dri-devel
Cc: Lucas De Marchi, Hellstrom Thomas, Andi, Chris_intel_ID
Hi,
On 12/7/21 17:51, Ramalingam C wrote:
> From: Stuart Summers <stuart.summers@intel.com>
>
> Add a new platform flag, has_64k_pages, for platforms supporting
> base page sizes of 64k.
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 3 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 85bb8d3107f0..6132163e1cb3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1528,6 +1528,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_MSLICES(dev_priv) \
> (INTEL_INFO(dev_priv)->has_mslices)
>
> +#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
> +
Could we please have some documentation of the exact meaning of this flag.
Like, smallest page size of LMEM is 64K. Hardware supports 64k pages etc?
for future reference.
/Thomas
> #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
>
> #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 6aaa7c644c9b..634282edadb7 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1029,6 +1029,7 @@ static const struct intel_device_info xehpsdv_info = {
> DGFX_FEATURES,
> PLATFORM(INTEL_XEHPSDV),
> .display = { },
> + .has_64k_pages = 1,
> .pipe_mask = 0,
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) |
> @@ -1047,6 +1048,7 @@ static const struct intel_device_info dg2_info = {
> .graphics.rel = 55,
> .media.rel = 55,
> PLATFORM(INTEL_DG2),
> + .has_64k_pages = 1,
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) |
> BIT(VECS0) | BIT(VECS1) |
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 669f0d26c3c3..f38ac5bd837b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -123,6 +123,7 @@ enum intel_ppgtt_type {
> func(is_dgfx); \
> /* Keep has_* in alphabetical order */ \
> func(has_64bit_reloc); \
> + func(has_64k_pages); \
> func(gpu_reset_clobbers_display); \
> func(has_reset_engine); \
> func(has_global_mocs); \
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915/xehpsdv: set min page-size to 64K
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
(?)
@ 2021-12-08 12:50 ` Thomas Hellström (Intel)
-1 siblings, 0 replies; 20+ messages in thread
From: Thomas Hellström (Intel) @ 2021-12-08 12:50 UTC (permalink / raw)
To: Ramalingam C, intel-gfx, dri-devel
Cc: Lucas De Marchi, Hellstrom Thomas, Andi, Matthew Auld, Chris_intel_ID
On 12/7/21 17:51, Ramalingam C wrote:
> From: Matthew Auld <matthew.auld@intel.com>
>
> LMEM should be allocated at 64K granularity, since 4K page support will
> eventually be dropped for LMEM when using the PPGTT.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Thomas Hellstrom <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 +++++-
> drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 ++++-
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index bce03d74a0b4..ba90ab47d838 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -780,6 +780,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
> struct intel_uncore *uncore = &i915->uncore;
> struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> struct intel_memory_region *mem;
> + resource_size_t min_page_size;
> resource_size_t io_start;
> resource_size_t lmem_size;
> u64 lmem_base;
> @@ -791,8 +792,11 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
> lmem_size = pci_resource_len(pdev, 2) - lmem_base;
> io_start = pci_resource_start(pdev, 2) + lmem_base;
>
> + min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
> + I915_GTT_PAGE_SIZE_4K;
> +
> mem = intel_memory_region_create(i915, lmem_base, lmem_size,
> - I915_GTT_PAGE_SIZE_4K, io_start,
> + min_page_size, io_start,
> type, instance,
> &i915_region_stolen_lmem_ops);
> if (IS_ERR(mem))
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index 9ea49e0a27c0..fde2dcb59809 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -197,6 +197,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
> struct intel_uncore *uncore = gt->uncore;
> struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> struct intel_memory_region *mem;
> + resource_size_t min_page_size;
> resource_size_t io_start;
> resource_size_t lmem_size;
> int err;
> @@ -211,10 +212,12 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
> if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
> return ERR_PTR(-ENODEV);
>
> + min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
> + I915_GTT_PAGE_SIZE_4K;
> mem = intel_memory_region_create(i915,
> 0,
> lmem_size,
> - I915_GTT_PAGE_SIZE_4K,
> + min_page_size,
> io_start,
> INTEL_MEMORY_LOCAL,
> 0,
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Add has_64k_pages flag
2021-12-08 12:43 ` Thomas Hellström (Intel)
@ 2021-12-08 12:59 ` Matthew Auld
2021-12-08 13:22 ` Thomas Hellström (Intel)
0 siblings, 1 reply; 20+ messages in thread
From: Matthew Auld @ 2021-12-08 12:59 UTC (permalink / raw)
To: thomas_os
Cc: Andi, intel-gfx, Lucas De Marchi, dri-devel, Hellstrom Thomas,
Chris_intel_ID
On Wed, 8 Dec 2021 at 12:43, Thomas Hellström (Intel)
<thomas_os@shipmail.org> wrote:
>
> Hi,
>
> On 12/7/21 17:51, Ramalingam C wrote:
> > From: Stuart Summers <stuart.summers@intel.com>
> >
> > Add a new platform flag, has_64k_pages, for platforms supporting
> > base page sizes of 64k.
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_pci.c | 2 ++
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > 3 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 85bb8d3107f0..6132163e1cb3 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1528,6 +1528,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define HAS_MSLICES(dev_priv) \
> > (INTEL_INFO(dev_priv)->has_mslices)
> >
> > +#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
> > +
>
> Could we please have some documentation of the exact meaning of this flag.
> Like, smallest page size of LMEM is 64K. Hardware supports 64k pages etc?
Something like: "Set if the device requires 64K GTT page sizes or
larger for device local memory access. Also implies that we require or
at least support the compact PT layout for the ppGTT when using 64K
GTT pages."
>
> for future reference.
>
> /Thomas
>
>
>
>
>
> > #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
> >
> > #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 6aaa7c644c9b..634282edadb7 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1029,6 +1029,7 @@ static const struct intel_device_info xehpsdv_info = {
> > DGFX_FEATURES,
> > PLATFORM(INTEL_XEHPSDV),
> > .display = { },
> > + .has_64k_pages = 1,
> > .pipe_mask = 0,
> > .platform_engine_mask =
> > BIT(RCS0) | BIT(BCS0) |
> > @@ -1047,6 +1048,7 @@ static const struct intel_device_info dg2_info = {
> > .graphics.rel = 55,
> > .media.rel = 55,
> > PLATFORM(INTEL_DG2),
> > + .has_64k_pages = 1,
> > .platform_engine_mask =
> > BIT(RCS0) | BIT(BCS0) |
> > BIT(VECS0) | BIT(VECS1) |
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 669f0d26c3c3..f38ac5bd837b 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -123,6 +123,7 @@ enum intel_ppgtt_type {
> > func(is_dgfx); \
> > /* Keep has_* in alphabetical order */ \
> > func(has_64bit_reloc); \
> > + func(has_64k_pages); \
> > func(gpu_reset_clobbers_display); \
> > func(has_reset_engine); \
> > func(has_global_mocs); \
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Add has_64k_pages flag
2021-12-08 12:59 ` Matthew Auld
@ 2021-12-08 13:22 ` Thomas Hellström (Intel)
0 siblings, 0 replies; 20+ messages in thread
From: Thomas Hellström (Intel) @ 2021-12-08 13:22 UTC (permalink / raw)
To: Matthew Auld
Cc: Andi, intel-gfx, Lucas De Marchi, dri-devel, Hellstrom Thomas,
Chris_intel_ID
On 12/8/21 13:59, Matthew Auld wrote:
> On Wed, 8 Dec 2021 at 12:43, Thomas Hellström (Intel)
> <thomas_os@shipmail.org> wrote:
>> Hi,
>>
>> On 12/7/21 17:51, Ramalingam C wrote:
>>> From: Stuart Summers <stuart.summers@intel.com>
>>>
>>> Add a new platform flag, has_64k_pages, for platforms supporting
>>> base page sizes of 64k.
>>>
>>> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>>> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>>> drivers/gpu/drm/i915/i915_pci.c | 2 ++
>>> drivers/gpu/drm/i915/intel_device_info.h | 1 +
>>> 3 files changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index 85bb8d3107f0..6132163e1cb3 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1528,6 +1528,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>> #define HAS_MSLICES(dev_priv) \
>>> (INTEL_INFO(dev_priv)->has_mslices)
>>>
>>> +#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
>>> +
>> Could we please have some documentation of the exact meaning of this flag.
>> Like, smallest page size of LMEM is 64K. Hardware supports 64k pages etc?
> Something like: "Set if the device requires 64K GTT page sizes or
> larger for device local memory access. Also implies that we require or
> at least support the compact PT layout for the ppGTT when using 64K
> GTT pages."
Sounds great.
Thanks,
Thomas
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/gtt/xehpsdv: move scratch page to system memory
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
(?)
@ 2021-12-08 13:26 ` Thomas Hellström
-1 siblings, 0 replies; 20+ messages in thread
From: Thomas Hellström @ 2021-12-08 13:26 UTC (permalink / raw)
To: Ramalingam C, intel-gfx, dri-devel
Cc: Hellstrom Thomas, Andi, Matthew Auld, Chris_intel_ID
On 12/7/21 17:51, Ramalingam C wrote:
> From: Matthew Auld <matthew.auld@intel.com>
>
> On some platforms the hw has dropped support for 4K GTT pages when
> dealing with LMEM, and due to the design of 64K GTT pages in the hw, we
> can only mark the *entire* page-table as operating in 64K GTT mode,
> since the enable bit is still on the pde, and not the pte. And since we
> we
we we
> still need to allow 4K GTT pages for SMEM objects, we can't have a
> "normal" 4K page-table with scratch pointing to LMEM, since that's
> undefined from the hw pov. The simplest solution is to just move the 64K
> scratch page to SMEM on such platforms and call it a day, since that
> should work for all configurations.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
LGTM.
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 23 +++++++++++++++++++++--
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +++
> drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
> drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 ++
> 6 files changed, 30 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> index 4a166d25fe60..c0d149f04949 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> @@ -454,6 +454,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
> ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
>
> ppgtt->base.vm.alloc_pt_dma = alloc_pt_dma;
> + ppgtt->base.vm.alloc_scratch_dma = alloc_pt_dma;
> ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
>
> err = gen6_ppgtt_init_scratch(ppgtt);
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 95c02096a61b..b012c50f7ce7 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -776,10 +776,29 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> */
> ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
>
> - if (HAS_LMEM(gt->i915))
> + if (HAS_LMEM(gt->i915)) {
> ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
> - else
> +
> + /*
> + * On some platforms the hw has dropped support for 4K GTT pages
> + * when dealing with LMEM, and due to the design of 64K GTT
> + * pages in the hw, we can only mark the *entire* page-table as
> + * operating in 64K GTT mode, since the enable bit is still on
> + * the pde, and not the pte. And since we still need to allow
> + * 4K GTT pages for SMEM objects, we can't have a "normal" 4K
> + * page-table with scratch pointing to LMEM, since that's
> + * undefined from the hw pov. The simplest solution is to just
> + * move the 64K scratch page to SMEM on such platforms and call
> + * it a day, since that should work for all configurations.
> + */
> + if (HAS_64K_PAGES(gt->i915))
> + ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
> + else
> + ppgtt->vm.alloc_scratch_dma = alloc_pt_lmem;
> + } else {
> ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
> + ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
> + }
>
> err = gen8_init_scratch(&ppgtt->vm);
> if (err)
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index cbc6d2b1fd9e..d85a1050f4a8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -941,6 +941,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> size = gen8_get_total_gtt_size(snb_gmch_ctl);
>
> ggtt->vm.alloc_pt_dma = alloc_pt_dma;
> + ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
> ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
>
> ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
> @@ -1094,6 +1095,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
> ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
>
> ggtt->vm.alloc_pt_dma = alloc_pt_dma;
> + ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
>
> ggtt->vm.clear_range = nop_clear_range;
> if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
> @@ -1146,6 +1148,7 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
> (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
>
> ggtt->vm.alloc_pt_dma = alloc_pt_dma;
> + ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
>
> if (needs_idle_maps(i915)) {
> drm_notice(&i915->drm,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 0dd254cb1f69..1428e2b9075a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -301,7 +301,7 @@ int setup_scratch_page(struct i915_address_space *vm)
> do {
> struct drm_i915_gem_object *obj;
>
> - obj = vm->alloc_pt_dma(vm, size);
> + obj = vm->alloc_scratch_dma(vm, size);
> if (IS_ERR(obj))
> goto skip;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 51afe66d00f2..15b98321e89a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -268,6 +268,8 @@ struct i915_address_space {
>
> struct drm_i915_gem_object *
> (*alloc_pt_dma)(struct i915_address_space *vm, int sz);
> + struct drm_i915_gem_object *
> + (*alloc_scratch_dma)(struct i915_address_space *vm, int sz);
>
> u64 (*pte_encode)(dma_addr_t addr,
> enum i915_cache_level level,
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c
> index cc047ec594f9..32ca8962d0ab 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
> @@ -78,6 +78,7 @@ struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name)
> i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
>
> ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
> + ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
>
> ppgtt->vm.clear_range = mock_clear_range;
> ppgtt->vm.insert_page = mock_insert_page;
> @@ -118,6 +119,7 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt)
> ggtt->vm.total = 4096 * PAGE_SIZE;
>
> ggtt->vm.alloc_pt_dma = alloc_pt_dma;
> + ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
>
> ggtt->vm.clear_range = mock_clear_range;
> ggtt->vm.insert_page = mock_insert_page;
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: enforce min page size for scratch
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
(?)
@ 2021-12-08 13:32 ` Thomas Hellström
-1 siblings, 0 replies; 20+ messages in thread
From: Thomas Hellström @ 2021-12-08 13:32 UTC (permalink / raw)
To: Ramalingam C, intel-gfx, dri-devel
Cc: Hellstrom Thomas, Andi, Matthew Auld, Chris_intel_ID
On 12/7/21 17:51, Ramalingam C wrote:
> From: Matthew Auld <matthew.auld@intel.com>
>
> If the device needs 64K minimum GTT pages for device local-memory,
> like on XEHPSDV, then we need to fail the allocation if we can't
> meet it, instead of falling back to 4K pages, otherwise we can't
> safely support the insertion of device local-memory pages for
> this vm, since the HW expects the correct physical alignment and
> size for every PTE, if we mark the page-table as 64K GTT mode.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gtt.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 1428e2b9075a..869b771a5fdc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -337,6 +337,18 @@ int setup_scratch_page(struct i915_address_space *vm)
> if (size == I915_GTT_PAGE_SIZE_4K)
> return -ENOMEM;
>
> + /*
> + * If we need 64K minimum GTT pages for device local-memory,
> + * like on XEHPSDV, then we need to fail the allocation here,
> + * otherwise we can't safely support the insertion of
> + * local-memory pages for this vm, since the HW expects the
> + * correct physical alignment and size when the page-table is
> + * operating in 64K GTT mode, which includes any scratch PTEs,
> + * since userpsace can still touch them.
s/userpsace/userspace/
LGTM.
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> + */
> + if (HAS_64K_PAGES(vm->i915))
> + return -ENOMEM;
> +
> size = I915_GTT_PAGE_SIZE_4K;
> } while (1);
> }
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 4/4] drm/i915: enforce min page size for scratch
2021-12-08 14:16 [PATCH 0/4] drm/i915: " Ramalingam C
@ 2021-12-08 14:16 ` Ramalingam C
0 siblings, 0 replies; 20+ messages in thread
From: Ramalingam C @ 2021-12-08 14:16 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: Hellstrom Thomas, Matthew Auld, Thomas Hellström
From: Matthew Auld <matthew.auld@intel.com>
If the device needs 64K minimum GTT pages for device local-memory,
like on XEHPSDV, then we need to fail the allocation if we can't
meet it, instead of falling back to 4K pages, otherwise we can't
safely support the insertion of device local-memory pages for
this vm, since the HW expects the correct physical alignment and
size for every PTE, if we mark the page-table as 64K GTT mode.
v2: s/userpsace/userspace [Thomas]
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 1428e2b9075a..b30e4478f098 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -337,6 +337,18 @@ int setup_scratch_page(struct i915_address_space *vm)
if (size == I915_GTT_PAGE_SIZE_4K)
return -ENOMEM;
+ /*
+ * If we need 64K minimum GTT pages for device local-memory,
+ * like on XEHPSDV, then we need to fail the allocation here,
+ * otherwise we can't safely support the insertion of
+ * local-memory pages for this vm, since the HW expects the
+ * correct physical alignment and size when the page-table is
+ * operating in 64K GTT mode, which includes any scratch PTEs,
+ * since userspace can still touch them.
+ */
+ if (HAS_64K_PAGES(vm->i915))
+ return -ENOMEM;
+
size = I915_GTT_PAGE_SIZE_4K;
} while (1);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
end of thread, other threads:[~2021-12-08 14:16 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-07 16:51 [PATCH 0/4] Basic enabling of 64k page support Ramalingam C
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
2021-12-07 16:51 ` [PATCH 1/4] drm/i915: Add has_64k_pages flag Ramalingam C
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
2021-12-08 12:43 ` Thomas Hellström (Intel)
2021-12-08 12:59 ` Matthew Auld
2021-12-08 13:22 ` Thomas Hellström (Intel)
2021-12-07 16:51 ` [PATCH 2/4] drm/i915/xehpsdv: set min page-size to 64K Ramalingam C
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
2021-12-08 12:50 ` Thomas Hellström (Intel)
2021-12-07 16:51 ` [PATCH 3/4] drm/i915/gtt/xehpsdv: move scratch page to system memory Ramalingam C
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
2021-12-08 13:26 ` Thomas Hellström
2021-12-07 16:51 ` [PATCH 4/4] drm/i915: enforce min page size for scratch Ramalingam C
2021-12-07 16:51 ` [Intel-gfx] " Ramalingam C
2021-12-08 13:32 ` Thomas Hellström
2021-12-07 20:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Basic enabling of 64k page support Patchwork
2021-12-07 20:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-12-08 3:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-12-08 14:16 [PATCH 0/4] drm/i915: " Ramalingam C
2021-12-08 14:16 ` [PATCH 4/4] drm/i915: enforce min page size for scratch Ramalingam C
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.