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* [PATCH 0/3] target/ppc: Minor fixes to exception code
@ 2021-12-08 12:30 Fabiano Rosas
  2021-12-08 12:30 ` [PATCH 1/3] target/ppc: Fix MPCxxx FPU interrupt address Fabiano Rosas
                   ` (4 more replies)
  0 siblings, 5 replies; 10+ messages in thread
From: Fabiano Rosas @ 2021-12-08 12:30 UTC (permalink / raw)
  To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david

These are just some minor fixes to the exception code that I collected
over the past few months.

Fabiano Rosas (3):
  target/ppc: Fix MPCxxx FPU interrupt address
  target/ppc: Remove 603e exception model
  target/ppc: Set 601v exception model id

 target/ppc/cpu-qom.h     |  2 --
 target/ppc/cpu_init.c    | 37 +++++--------------------------------
 target/ppc/excp_helper.c |  1 -
 3 files changed, 5 insertions(+), 35 deletions(-)

-- 
2.33.1



^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 1/3] target/ppc: Fix MPCxxx FPU interrupt address
  2021-12-08 12:30 [PATCH 0/3] target/ppc: Minor fixes to exception code Fabiano Rosas
@ 2021-12-08 12:30 ` Fabiano Rosas
  2021-12-09  7:57   ` Cédric Le Goater
  2021-12-15 16:47   ` Cédric Le Goater
  2021-12-08 12:30 ` [PATCH 2/3] target/ppc: Remove 603e exception model Fabiano Rosas
                   ` (3 subsequent siblings)
  4 siblings, 2 replies; 10+ messages in thread
From: Fabiano Rosas @ 2021-12-08 12:30 UTC (permalink / raw)
  To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david

The Floating-point Unavailable and Decrementer interrupts are being
registered at the same 0x900 address. The FPU should be at 0x800
instead.

Verified on MPC555, MPC860 and MPC885 user manuals.

Reported-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/cpu_init.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 6695985e9b..55af48769a 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2180,7 +2180,7 @@ static void init_excp_MPC5xx(CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
-    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
+    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
@@ -2207,7 +2207,7 @@ static void init_excp_MPC8xx(CPUPPCState *env)
     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
-    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
+    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
-- 
2.33.1



^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH 2/3] target/ppc: Remove 603e exception model
  2021-12-08 12:30 [PATCH 0/3] target/ppc: Minor fixes to exception code Fabiano Rosas
  2021-12-08 12:30 ` [PATCH 1/3] target/ppc: Fix MPCxxx FPU interrupt address Fabiano Rosas
@ 2021-12-08 12:30 ` Fabiano Rosas
  2021-12-09  7:58   ` Cédric Le Goater
  2021-12-08 12:30 ` [PATCH 3/3] target/ppc: Set 601v exception model id Fabiano Rosas
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 10+ messages in thread
From: Fabiano Rosas @ 2021-12-08 12:30 UTC (permalink / raw)
  To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david

The 603e uses the same exception code as 603 so we don't need a
dedicated entry for it.

This is only a removal of redundant code, no functional change.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/cpu-qom.h     |  2 --
 target/ppc/cpu_init.c    | 32 ++------------------------------
 target/ppc/excp_helper.c |  1 -
 3 files changed, 2 insertions(+), 33 deletions(-)

diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 5800fa324e..e585912571 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -94,8 +94,6 @@ enum powerpc_excp_t {
     POWERPC_EXCP_602,
     /* PowerPC 603 exception model      */
     POWERPC_EXCP_603,
-    /* PowerPC 603e exception model     */
-    POWERPC_EXCP_603E,
     /* PowerPC G2 exception model       */
     POWERPC_EXCP_G2,
     /* PowerPC 604 exception model      */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 55af48769a..8100b89033 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -4749,41 +4749,13 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
                  POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
 }
 
-static void init_proc_603E(CPUPPCState *env)
-{
-    register_ne_601_sprs(env);
-    register_sdr1_sprs(env);
-    register_603_sprs(env);
-    /* Time base */
-    register_tbl(env);
-    /* hardware implementation registers */
-    /* XXX : not implemented */
-    spr_register(env, SPR_HID0, "HID0",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_generic,
-                 0x00000000);
-    /* XXX : not implemented */
-    spr_register(env, SPR_HID1, "HID1",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_generic,
-                 0x00000000);
-    /* Memory management */
-    register_low_BATs(env);
-    register_6xx_7xx_soft_tlb(env, 64, 2);
-    init_excp_603(env);
-    env->dcache_line_size = 32;
-    env->icache_line_size = 32;
-    /* Allocate hardware IRQ controller */
-    ppc6xx_irq_init(env_archcpu(env));
-}
-
 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
 
     dc->desc = "PowerPC 603e";
-    pcc->init_proc = init_proc_603E;
+    pcc->init_proc = init_proc_603;
     pcc->check_pow = check_pow_hid0;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
@@ -4809,7 +4781,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
                     (1ull << MSR_RI) |
                     (1ull << MSR_LE);
     pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
-    pcc->excp_model = POWERPC_EXCP_603E;
+    pcc->excp_model = POWERPC_EXCP_603;
     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
     pcc->bfd_mach = bfd_mach_ppc_ec603e;
     pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 17607adbe4..f15a859fe4 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -672,7 +672,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
         switch (excp_model) {
         case POWERPC_EXCP_602:
         case POWERPC_EXCP_603:
-        case POWERPC_EXCP_603E:
         case POWERPC_EXCP_G2:
             /* Swap temporary saved registers with GPRs */
             if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
-- 
2.33.1



^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH 3/3] target/ppc: Set 601v exception model id
  2021-12-08 12:30 [PATCH 0/3] target/ppc: Minor fixes to exception code Fabiano Rosas
  2021-12-08 12:30 ` [PATCH 1/3] target/ppc: Fix MPCxxx FPU interrupt address Fabiano Rosas
  2021-12-08 12:30 ` [PATCH 2/3] target/ppc: Remove 603e exception model Fabiano Rosas
@ 2021-12-08 12:30 ` Fabiano Rosas
  2021-12-09  7:58   ` Cédric Le Goater
  2021-12-08 17:35 ` [PATCH 0/3] target/ppc: Minor fixes to exception code Richard Henderson
  2021-12-15 16:44 ` Cédric Le Goater
  4 siblings, 1 reply; 10+ messages in thread
From: Fabiano Rosas @ 2021-12-08 12:30 UTC (permalink / raw)
  To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david

The exception model id for 601v has been removed without mention
why. I assume it was inadvertent and restore it here.

Fixes: b632a148b6 ("target-ppc: Use QOM method dispatch for MMU fault handling")
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/cpu_init.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 8100b89033..0e1682ddd9 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -4607,6 +4607,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
                     (1ull << MSR_IR) |
                     (1ull << MSR_DR);
     pcc->mmu_model = POWERPC_MMU_601;
+    pcc->excp_model = POWERPC_EXCP_601;
     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
     pcc->bfd_mach = bfd_mach_ppc_601;
     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
-- 
2.33.1



^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [PATCH 0/3] target/ppc: Minor fixes to exception code
  2021-12-08 12:30 [PATCH 0/3] target/ppc: Minor fixes to exception code Fabiano Rosas
                   ` (2 preceding siblings ...)
  2021-12-08 12:30 ` [PATCH 3/3] target/ppc: Set 601v exception model id Fabiano Rosas
@ 2021-12-08 17:35 ` Richard Henderson
  2021-12-15 16:44 ` Cédric Le Goater
  4 siblings, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2021-12-08 17:35 UTC (permalink / raw)
  To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david

On 12/8/21 4:30 AM, Fabiano Rosas wrote:
> These are just some minor fixes to the exception code that I collected
> over the past few months.
> 
> Fabiano Rosas (3):
>    target/ppc: Fix MPCxxx FPU interrupt address
>    target/ppc: Remove 603e exception model
>    target/ppc: Set 601v exception model id
> 
>   target/ppc/cpu-qom.h     |  2 --
>   target/ppc/cpu_init.c    | 37 +++++--------------------------------
>   target/ppc/excp_helper.c |  1 -
>   3 files changed, 5 insertions(+), 35 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~



^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] target/ppc: Fix MPCxxx FPU interrupt address
  2021-12-08 12:30 ` [PATCH 1/3] target/ppc: Fix MPCxxx FPU interrupt address Fabiano Rosas
@ 2021-12-09  7:57   ` Cédric Le Goater
  2021-12-15 16:47   ` Cédric Le Goater
  1 sibling, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2021-12-09  7:57 UTC (permalink / raw)
  To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david

On 12/8/21 13:30, Fabiano Rosas wrote:
> The Floating-point Unavailable and Decrementer interrupts are being
> registered at the same 0x900 address. The FPU should be at 0x800
> instead.
> 
> Verified on MPC555, MPC860 and MPC885 user manuals.
> 
> Reported-by: BALATON Zoltan <balaton@eik.bme.hu>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.

> ---
>   target/ppc/cpu_init.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 6695985e9b..55af48769a 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2180,7 +2180,7 @@ static void init_excp_MPC5xx(CPUPPCState *env)
>       env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
>       env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
>       env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
> -    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
> +    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
>       env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
>       env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
>       env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
> @@ -2207,7 +2207,7 @@ static void init_excp_MPC8xx(CPUPPCState *env)
>       env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
>       env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
>       env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
> -    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
> +    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
>       env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
>       env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
>       env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
> 



^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] target/ppc: Remove 603e exception model
  2021-12-08 12:30 ` [PATCH 2/3] target/ppc: Remove 603e exception model Fabiano Rosas
@ 2021-12-09  7:58   ` Cédric Le Goater
  0 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2021-12-09  7:58 UTC (permalink / raw)
  To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david

On 12/8/21 13:30, Fabiano Rosas wrote:
> The 603e uses the same exception code as 603 so we don't need a
> dedicated entry for it.
> 
> This is only a removal of redundant code, no functional change.
> 
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>

QEMU really only supports the 604. I think we could drop the
previous 60x CPUs also.

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.


> ---
>   target/ppc/cpu-qom.h     |  2 --
>   target/ppc/cpu_init.c    | 32 ++------------------------------
>   target/ppc/excp_helper.c |  1 -
>   3 files changed, 2 insertions(+), 33 deletions(-)
> 
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index 5800fa324e..e585912571 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -94,8 +94,6 @@ enum powerpc_excp_t {
>       POWERPC_EXCP_602,
>       /* PowerPC 603 exception model      */
>       POWERPC_EXCP_603,
> -    /* PowerPC 603e exception model     */
> -    POWERPC_EXCP_603E,
>       /* PowerPC G2 exception model       */
>       POWERPC_EXCP_G2,
>       /* PowerPC 604 exception model      */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 55af48769a..8100b89033 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -4749,41 +4749,13 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
>                    POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
>   }
>   
> -static void init_proc_603E(CPUPPCState *env)
> -{
> -    register_ne_601_sprs(env);
> -    register_sdr1_sprs(env);
> -    register_603_sprs(env);
> -    /* Time base */
> -    register_tbl(env);
> -    /* hardware implementation registers */
> -    /* XXX : not implemented */
> -    spr_register(env, SPR_HID0, "HID0",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_generic,
> -                 0x00000000);
> -    /* XXX : not implemented */
> -    spr_register(env, SPR_HID1, "HID1",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_generic,
> -                 0x00000000);
> -    /* Memory management */
> -    register_low_BATs(env);
> -    register_6xx_7xx_soft_tlb(env, 64, 2);
> -    init_excp_603(env);
> -    env->dcache_line_size = 32;
> -    env->icache_line_size = 32;
> -    /* Allocate hardware IRQ controller */
> -    ppc6xx_irq_init(env_archcpu(env));
> -}
> -
>   POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
>   {
>       DeviceClass *dc = DEVICE_CLASS(oc);
>       PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
>   
>       dc->desc = "PowerPC 603e";
> -    pcc->init_proc = init_proc_603E;
> +    pcc->init_proc = init_proc_603;
>       pcc->check_pow = check_pow_hid0;
>       pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
>                          PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> @@ -4809,7 +4781,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
>                       (1ull << MSR_RI) |
>                       (1ull << MSR_LE);
>       pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
> -    pcc->excp_model = POWERPC_EXCP_603E;
> +    pcc->excp_model = POWERPC_EXCP_603;
>       pcc->bus_model = PPC_FLAGS_INPUT_6xx;
>       pcc->bfd_mach = bfd_mach_ppc_ec603e;
>       pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 17607adbe4..f15a859fe4 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -672,7 +672,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
>           switch (excp_model) {
>           case POWERPC_EXCP_602:
>           case POWERPC_EXCP_603:
> -        case POWERPC_EXCP_603E:
>           case POWERPC_EXCP_G2:
>               /* Swap temporary saved registers with GPRs */
>               if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
> 



^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] target/ppc: Set 601v exception model id
  2021-12-08 12:30 ` [PATCH 3/3] target/ppc: Set 601v exception model id Fabiano Rosas
@ 2021-12-09  7:58   ` Cédric Le Goater
  0 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2021-12-09  7:58 UTC (permalink / raw)
  To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david

On 12/8/21 13:30, Fabiano Rosas wrote:
> The exception model id for 601v has been removed without mention
> why. I assume it was inadvertent and restore it here.
> 
> Fixes: b632a148b6 ("target-ppc: Use QOM method dispatch for MMU fault handling")
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.


> ---
>   target/ppc/cpu_init.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 8100b89033..0e1682ddd9 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -4607,6 +4607,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
>                       (1ull << MSR_IR) |
>                       (1ull << MSR_DR);
>       pcc->mmu_model = POWERPC_MMU_601;
> +    pcc->excp_model = POWERPC_EXCP_601;
>       pcc->bus_model = PPC_FLAGS_INPUT_6xx;
>       pcc->bfd_mach = bfd_mach_ppc_601;
>       pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
> 



^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 0/3] target/ppc: Minor fixes to exception code
  2021-12-08 12:30 [PATCH 0/3] target/ppc: Minor fixes to exception code Fabiano Rosas
                   ` (3 preceding siblings ...)
  2021-12-08 17:35 ` [PATCH 0/3] target/ppc: Minor fixes to exception code Richard Henderson
@ 2021-12-15 16:44 ` Cédric Le Goater
  4 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2021-12-15 16:44 UTC (permalink / raw)
  To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david

On 12/8/21 13:30, Fabiano Rosas wrote:
> These are just some minor fixes to the exception code that I collected
> over the past few months.

Applied to ppc-next.

Thanks,

C.


^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] target/ppc: Fix MPCxxx FPU interrupt address
  2021-12-08 12:30 ` [PATCH 1/3] target/ppc: Fix MPCxxx FPU interrupt address Fabiano Rosas
  2021-12-09  7:57   ` Cédric Le Goater
@ 2021-12-15 16:47   ` Cédric Le Goater
  1 sibling, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2021-12-15 16:47 UTC (permalink / raw)
  To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david

On 12/8/21 13:30, Fabiano Rosas wrote:
> The Floating-point Unavailable and Decrementer interrupts are being
> registered at the same 0x900 address. The FPU should be at 0x800
> instead.
> 
> Verified on MPC555, MPC860 and MPC885 user manuals.
> 
> Reported-by: BALATON Zoltan <balaton@eik.bme.hu>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>



Applied to ppc-next.

Thanks,

C.


^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-12-15 16:59 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-08 12:30 [PATCH 0/3] target/ppc: Minor fixes to exception code Fabiano Rosas
2021-12-08 12:30 ` [PATCH 1/3] target/ppc: Fix MPCxxx FPU interrupt address Fabiano Rosas
2021-12-09  7:57   ` Cédric Le Goater
2021-12-15 16:47   ` Cédric Le Goater
2021-12-08 12:30 ` [PATCH 2/3] target/ppc: Remove 603e exception model Fabiano Rosas
2021-12-09  7:58   ` Cédric Le Goater
2021-12-08 12:30 ` [PATCH 3/3] target/ppc: Set 601v exception model id Fabiano Rosas
2021-12-09  7:58   ` Cédric Le Goater
2021-12-08 17:35 ` [PATCH 0/3] target/ppc: Minor fixes to exception code Richard Henderson
2021-12-15 16:44 ` Cédric Le Goater

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