* [PATCH 0/6] Add MT8195 APU Power Domain @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add MT8195 APU power domain. This series is based on drivers implemented in MT8192 apu power domain[1] and apu SMC[2]. [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=593809 [2] https://patchwork.kernel.org/patch/12670253 The device tree depends on MT8195 dts[3] which is under reviewing. [3] https://patchwork.kernel.org/patch/12616141 Flora Fu (6): dt-bindings: soc: mediatek: apu: Add MT8195 APU power domain dt-bindings: arm: mediatek: Add MT8195 APU bindings soc: mediatek: apu: Add MT8195 apu power domain arm64: dts: mt8195: Add APU nodes arm64: dts: mt8195: Add APU power domain node arm64: dts: mt8195: Set up apu power domain regulators .../arm/mediatek/mediatek,apusys.yaml | 3 + .../soc/mediatek/mediatek,apu-pm.yaml | 1 + arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 8 ++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 31 +++++ drivers/soc/mediatek/apusys/mtk-apu-pm.c | 124 ++++++++++++++++++ 5 files changed, 167 insertions(+) -- 2.18.0 ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 0/6] Add MT8195 APU Power Domain @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add MT8195 APU power domain. This series is based on drivers implemented in MT8192 apu power domain[1] and apu SMC[2]. [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=593809 [2] https://patchwork.kernel.org/patch/12670253 The device tree depends on MT8195 dts[3] which is under reviewing. [3] https://patchwork.kernel.org/patch/12616141 Flora Fu (6): dt-bindings: soc: mediatek: apu: Add MT8195 APU power domain dt-bindings: arm: mediatek: Add MT8195 APU bindings soc: mediatek: apu: Add MT8195 apu power domain arm64: dts: mt8195: Add APU nodes arm64: dts: mt8195: Add APU power domain node arm64: dts: mt8195: Set up apu power domain regulators .../arm/mediatek/mediatek,apusys.yaml | 3 + .../soc/mediatek/mediatek,apu-pm.yaml | 1 + arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 8 ++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 31 +++++ drivers/soc/mediatek/apusys/mtk-apu-pm.c | 124 ++++++++++++++++++ 5 files changed, 167 insertions(+) -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 0/6] Add MT8195 APU Power Domain @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add MT8195 APU power domain. This series is based on drivers implemented in MT8192 apu power domain[1] and apu SMC[2]. [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=593809 [2] https://patchwork.kernel.org/patch/12670253 The device tree depends on MT8195 dts[3] which is under reviewing. [3] https://patchwork.kernel.org/patch/12616141 Flora Fu (6): dt-bindings: soc: mediatek: apu: Add MT8195 APU power domain dt-bindings: arm: mediatek: Add MT8195 APU bindings soc: mediatek: apu: Add MT8195 apu power domain arm64: dts: mt8195: Add APU nodes arm64: dts: mt8195: Add APU power domain node arm64: dts: mt8195: Set up apu power domain regulators .../arm/mediatek/mediatek,apusys.yaml | 3 + .../soc/mediatek/mediatek,apu-pm.yaml | 1 + arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 8 ++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 31 +++++ drivers/soc/mediatek/apusys/mtk-apu-pm.c | 124 ++++++++++++++++++ 5 files changed, 167 insertions(+) -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 1/6] dt-bindings: soc: mediatek: apu: Add MT8195 APU power domain 2021-12-10 17:37 ` Flora Fu (?) @ 2021-12-10 17:37 ` Flora Fu -1 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Document the MT8195 APU power domain bindings. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- .../devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml index e1b7d4030dc9..66547f899014 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml @@ -21,6 +21,7 @@ properties: items: - enum: - mediatek,mt8192-apu-pm + - mediatek,mt8195-apu-pm - const: syscon reg: -- 2.18.0 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 1/6] dt-bindings: soc: mediatek: apu: Add MT8195 APU power domain @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Document the MT8195 APU power domain bindings. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- .../devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml index e1b7d4030dc9..66547f899014 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml @@ -21,6 +21,7 @@ properties: items: - enum: - mediatek,mt8192-apu-pm + - mediatek,mt8195-apu-pm - const: syscon reg: -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 1/6] dt-bindings: soc: mediatek: apu: Add MT8195 APU power domain @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Document the MT8195 APU power domain bindings. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- .../devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml index e1b7d4030dc9..66547f899014 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml @@ -21,6 +21,7 @@ properties: items: - enum: - mediatek,mt8192-apu-pm + - mediatek,mt8195-apu-pm - const: syscon reg: -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 2/6] dt-bindings: arm: mediatek: Add MT8195 APU bindings 2021-12-10 17:37 ` Flora Fu (?) @ 2021-12-10 17:37 ` Flora Fu -1 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Document the MT8195 APU bindings. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- .../devicetree/bindings/arm/mediatek/mediatek,apusys.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml index 7643c66dfaa2..fe96618ecb71 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml @@ -20,6 +20,9 @@ properties: - enum: - mediatek,mt8192-apu-conn - mediatek,mt8192-apu-vcore + - mediatek,mt8195-apu-conn + - mediatek,mt8195-apu-conn1 + - mediatek,mt8195-apu-vcore - const: syscon reg: -- 2.18.0 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 2/6] dt-bindings: arm: mediatek: Add MT8195 APU bindings @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Document the MT8195 APU bindings. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- .../devicetree/bindings/arm/mediatek/mediatek,apusys.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml index 7643c66dfaa2..fe96618ecb71 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml @@ -20,6 +20,9 @@ properties: - enum: - mediatek,mt8192-apu-conn - mediatek,mt8192-apu-vcore + - mediatek,mt8195-apu-conn + - mediatek,mt8195-apu-conn1 + - mediatek,mt8195-apu-vcore - const: syscon reg: -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 2/6] dt-bindings: arm: mediatek: Add MT8195 APU bindings @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Document the MT8195 APU bindings. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- .../devicetree/bindings/arm/mediatek/mediatek,apusys.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml index 7643c66dfaa2..fe96618ecb71 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml @@ -20,6 +20,9 @@ properties: - enum: - mediatek,mt8192-apu-conn - mediatek,mt8192-apu-vcore + - mediatek,mt8195-apu-conn + - mediatek,mt8195-apu-conn1 + - mediatek,mt8195-apu-vcore - const: syscon reg: -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 3/6] soc: mediatek: apu: Add MT8195 apu power domain 2021-12-10 17:37 ` Flora Fu (?) @ 2021-12-10 17:37 ` Flora Fu -1 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add MT8195 apu power domain settings. The clock and pll controller shall be accessed through SMC call and the power domain shall be enable before access MT8195 APU. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- drivers/soc/mediatek/apusys/mtk-apu-pm.c | 124 +++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/drivers/soc/mediatek/apusys/mtk-apu-pm.c b/drivers/soc/mediatek/apusys/mtk-apu-pm.c index 10dd30052c46..7be5acb75d78 100644 --- a/drivers/soc/mediatek/apusys/mtk-apu-pm.c +++ b/drivers/soc/mediatek/apusys/mtk-apu-pm.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ +#include <linux/arm-smccc.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/init.h> @@ -18,9 +19,12 @@ #include <linux/pm_domain.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> +#include <linux/soc/mediatek/mtk_sip_svc.h> #define APU_PD_IPUIF_HW_CG BIT(0) #define APU_PD_RPC_AUTO_BUCK BIT(1) +#define APU_PD_ACC BIT(2) +#define APU_PD_SEC_PWR BIT(3) #define APU_PD_CAPS(_pd, _x) ((_pd)->data->caps & (_x)) #define MTK_POLL_DELAY_US 10 @@ -44,6 +48,11 @@ static const struct reg_sequence mt8192_rpc_sw_type[] = { { MT8192_RPC_SW_TYPE(6), 0x3 }, }; +#define MTK_SIP_APUPWR_BUS_PROT_CG_ON 0x02U +#define MTK_SIP_APUPWR_BULK_PLL 0x03U +#define MTK_SIP_APUPWR_ACC_INIT_ALL 0x04U +#define MTK_SIP_APUPWR_ACC_TOP 0x05U + struct apu_top_domain { u32 spm_ext_buck_iso; u32 spm_ext_buck_iso_mask; @@ -81,6 +90,23 @@ static struct apu_top_domain mt8192_top_reg = { .num_rpc_sw = ARRAY_SIZE(mt8192_rpc_sw_type), }; +static struct apu_top_domain mt8195_top_reg = { + .spm_ext_buck_iso = 0x3EC, + .spm_ext_buck_iso_mask = 0x21, + .spm_cross_wake_m01 = 0x670, + .wake_apu = BIT(0), + .spm_other_pwr = 0x198, + .pwr_status = BIT(4), + .conn_clr = 0x8, + .conn1_clr = 0x8, + .vcore_clr = 0x8, + .rpc_top_con = 0x0, + .rpc_top_con_init_mask = 0x9E, + .rpc_top_sel = 0x4, + .rpc_top_intf_pwr_rdy = 0x44, + .pwr_rdy = BIT(0), +}; + struct apusys { struct device *dev; struct regmap *scpsys; @@ -125,6 +151,7 @@ static int apu_top_init_hw(struct apu_domain *pd) { struct apusys *apusys = pd->apusys; int ret; + struct arm_smccc_res res; if (APU_PD_CAPS(pd, APU_PD_IPUIF_HW_CG)) { ret = clk_prepare_enable(pd->clk_top_conn); @@ -148,6 +175,15 @@ static int apu_top_init_hw(struct apu_domain *pd) } } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + goto err_clk; + } + } ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_clk; @@ -181,6 +217,18 @@ static int apu_top_init_hw(struct apu_domain *pd) goto err_clk; } + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_INIT_ALL, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc init all fail: %lu\n", res.a0); + goto err_clk; + } + } + } + if (APU_PD_CAPS(pd, APU_PD_IPUIF_HW_CG)) { clk_disable_unprepare(pd->clk_top_conn); ret = clk_set_parent(pd->clk_top_ipu_if, pd->clk_off); @@ -189,6 +237,9 @@ static int apu_top_init_hw(struct apu_domain *pd) goto err_clk; } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -199,6 +250,9 @@ static int apu_top_init_hw(struct apu_domain *pd) clk_disable_unprepare(pd->clk_top_conn); clk_disable_unprepare(pd->clk_top_ipu_if); } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -214,16 +268,31 @@ static const struct apu_domain_data apu_domain_data_mt8192[] = { } }; +static const struct apu_domain_data apu_domain_data_mt8195[] = { + { + .domain_idx = 0, + .name = "apu-top", + .caps = APU_PD_RPC_AUTO_BUCK | APU_PD_ACC | APU_PD_SEC_PWR, + .topd = &mt8195_top_reg, + } +}; + static const struct apu_pm_data mt8192_apu_pm_data = { .domains_data = apu_domain_data_mt8192, .num_domains = ARRAY_SIZE(apu_domain_data_mt8192), }; +static const struct apu_pm_data mt8195_apu_pm_data = { + .domains_data = apu_domain_data_mt8195, + .num_domains = ARRAY_SIZE(apu_domain_data_mt8195), +}; + static int apu_top_power_on(struct generic_pm_domain *genpd) { struct apu_domain *pd = to_apu_domain(genpd); struct apusys *apusys = pd->apusys; int ret, tmp; + struct arm_smccc_res res; if (apusys->vsram_supply) { ret = regulator_enable(apusys->vsram_supply); @@ -269,6 +338,25 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) } } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + goto err_clk; + } + + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_TOP, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc top smc fail: %lu\n", res.a0); + goto err_clk; + } + } + } ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_clk; @@ -301,6 +389,15 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) goto err_clk; } + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BUS_PROT_CG_ON, + 0, 0, 0, 0, 0, 0, &res); + if (res.a0) { + dev_err(apusys->dev, "apu bus_prot smc fail: %lu\n", res.a0); + goto err_clk; + } + } + if (apusys->vcore) { ret = regmap_write(apusys->vcore, pd->data->topd->vcore_clr, CG_CLR); @@ -329,6 +426,9 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) clk_disable_unprepare(pd->clk_top_conn); clk_disable_unprepare(pd->clk_top_ipu_if); } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } if (pd->domain_supply) @@ -345,6 +445,7 @@ static int apu_top_power_off(struct generic_pm_domain *genpd) struct apu_domain *pd = to_apu_domain(genpd); struct apusys *apusys = pd->apusys; int ret, tmp; + struct arm_smccc_res res; if (apusys->vcore) { ret = regmap_write(apusys->vcore, @@ -405,6 +506,25 @@ static int apu_top_power_off(struct generic_pm_domain *genpd) return ret; } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_TOP, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc top smc fail: %lu\n", res.a0); + return ret; + } + } + + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + return ret; + } + } clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -610,6 +730,10 @@ static const struct of_device_id apu_pm_of_match[] = { .compatible = "mediatek,mt8192-apu-pm", .data = &mt8192_apu_pm_data, }, + { + .compatible = "mediatek,mt8195-apu-pm", + .data = &mt8195_apu_pm_data, + }, { } }; -- 2.18.0 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 3/6] soc: mediatek: apu: Add MT8195 apu power domain @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add MT8195 apu power domain settings. The clock and pll controller shall be accessed through SMC call and the power domain shall be enable before access MT8195 APU. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- drivers/soc/mediatek/apusys/mtk-apu-pm.c | 124 +++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/drivers/soc/mediatek/apusys/mtk-apu-pm.c b/drivers/soc/mediatek/apusys/mtk-apu-pm.c index 10dd30052c46..7be5acb75d78 100644 --- a/drivers/soc/mediatek/apusys/mtk-apu-pm.c +++ b/drivers/soc/mediatek/apusys/mtk-apu-pm.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ +#include <linux/arm-smccc.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/init.h> @@ -18,9 +19,12 @@ #include <linux/pm_domain.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> +#include <linux/soc/mediatek/mtk_sip_svc.h> #define APU_PD_IPUIF_HW_CG BIT(0) #define APU_PD_RPC_AUTO_BUCK BIT(1) +#define APU_PD_ACC BIT(2) +#define APU_PD_SEC_PWR BIT(3) #define APU_PD_CAPS(_pd, _x) ((_pd)->data->caps & (_x)) #define MTK_POLL_DELAY_US 10 @@ -44,6 +48,11 @@ static const struct reg_sequence mt8192_rpc_sw_type[] = { { MT8192_RPC_SW_TYPE(6), 0x3 }, }; +#define MTK_SIP_APUPWR_BUS_PROT_CG_ON 0x02U +#define MTK_SIP_APUPWR_BULK_PLL 0x03U +#define MTK_SIP_APUPWR_ACC_INIT_ALL 0x04U +#define MTK_SIP_APUPWR_ACC_TOP 0x05U + struct apu_top_domain { u32 spm_ext_buck_iso; u32 spm_ext_buck_iso_mask; @@ -81,6 +90,23 @@ static struct apu_top_domain mt8192_top_reg = { .num_rpc_sw = ARRAY_SIZE(mt8192_rpc_sw_type), }; +static struct apu_top_domain mt8195_top_reg = { + .spm_ext_buck_iso = 0x3EC, + .spm_ext_buck_iso_mask = 0x21, + .spm_cross_wake_m01 = 0x670, + .wake_apu = BIT(0), + .spm_other_pwr = 0x198, + .pwr_status = BIT(4), + .conn_clr = 0x8, + .conn1_clr = 0x8, + .vcore_clr = 0x8, + .rpc_top_con = 0x0, + .rpc_top_con_init_mask = 0x9E, + .rpc_top_sel = 0x4, + .rpc_top_intf_pwr_rdy = 0x44, + .pwr_rdy = BIT(0), +}; + struct apusys { struct device *dev; struct regmap *scpsys; @@ -125,6 +151,7 @@ static int apu_top_init_hw(struct apu_domain *pd) { struct apusys *apusys = pd->apusys; int ret; + struct arm_smccc_res res; if (APU_PD_CAPS(pd, APU_PD_IPUIF_HW_CG)) { ret = clk_prepare_enable(pd->clk_top_conn); @@ -148,6 +175,15 @@ static int apu_top_init_hw(struct apu_domain *pd) } } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + goto err_clk; + } + } ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_clk; @@ -181,6 +217,18 @@ static int apu_top_init_hw(struct apu_domain *pd) goto err_clk; } + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_INIT_ALL, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc init all fail: %lu\n", res.a0); + goto err_clk; + } + } + } + if (APU_PD_CAPS(pd, APU_PD_IPUIF_HW_CG)) { clk_disable_unprepare(pd->clk_top_conn); ret = clk_set_parent(pd->clk_top_ipu_if, pd->clk_off); @@ -189,6 +237,9 @@ static int apu_top_init_hw(struct apu_domain *pd) goto err_clk; } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -199,6 +250,9 @@ static int apu_top_init_hw(struct apu_domain *pd) clk_disable_unprepare(pd->clk_top_conn); clk_disable_unprepare(pd->clk_top_ipu_if); } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -214,16 +268,31 @@ static const struct apu_domain_data apu_domain_data_mt8192[] = { } }; +static const struct apu_domain_data apu_domain_data_mt8195[] = { + { + .domain_idx = 0, + .name = "apu-top", + .caps = APU_PD_RPC_AUTO_BUCK | APU_PD_ACC | APU_PD_SEC_PWR, + .topd = &mt8195_top_reg, + } +}; + static const struct apu_pm_data mt8192_apu_pm_data = { .domains_data = apu_domain_data_mt8192, .num_domains = ARRAY_SIZE(apu_domain_data_mt8192), }; +static const struct apu_pm_data mt8195_apu_pm_data = { + .domains_data = apu_domain_data_mt8195, + .num_domains = ARRAY_SIZE(apu_domain_data_mt8195), +}; + static int apu_top_power_on(struct generic_pm_domain *genpd) { struct apu_domain *pd = to_apu_domain(genpd); struct apusys *apusys = pd->apusys; int ret, tmp; + struct arm_smccc_res res; if (apusys->vsram_supply) { ret = regulator_enable(apusys->vsram_supply); @@ -269,6 +338,25 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) } } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + goto err_clk; + } + + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_TOP, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc top smc fail: %lu\n", res.a0); + goto err_clk; + } + } + } ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_clk; @@ -301,6 +389,15 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) goto err_clk; } + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BUS_PROT_CG_ON, + 0, 0, 0, 0, 0, 0, &res); + if (res.a0) { + dev_err(apusys->dev, "apu bus_prot smc fail: %lu\n", res.a0); + goto err_clk; + } + } + if (apusys->vcore) { ret = regmap_write(apusys->vcore, pd->data->topd->vcore_clr, CG_CLR); @@ -329,6 +426,9 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) clk_disable_unprepare(pd->clk_top_conn); clk_disable_unprepare(pd->clk_top_ipu_if); } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } if (pd->domain_supply) @@ -345,6 +445,7 @@ static int apu_top_power_off(struct generic_pm_domain *genpd) struct apu_domain *pd = to_apu_domain(genpd); struct apusys *apusys = pd->apusys; int ret, tmp; + struct arm_smccc_res res; if (apusys->vcore) { ret = regmap_write(apusys->vcore, @@ -405,6 +506,25 @@ static int apu_top_power_off(struct generic_pm_domain *genpd) return ret; } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_TOP, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc top smc fail: %lu\n", res.a0); + return ret; + } + } + + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + return ret; + } + } clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -610,6 +730,10 @@ static const struct of_device_id apu_pm_of_match[] = { .compatible = "mediatek,mt8192-apu-pm", .data = &mt8192_apu_pm_data, }, + { + .compatible = "mediatek,mt8195-apu-pm", + .data = &mt8195_apu_pm_data, + }, { } }; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 3/6] soc: mediatek: apu: Add MT8195 apu power domain @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add MT8195 apu power domain settings. The clock and pll controller shall be accessed through SMC call and the power domain shall be enable before access MT8195 APU. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- drivers/soc/mediatek/apusys/mtk-apu-pm.c | 124 +++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/drivers/soc/mediatek/apusys/mtk-apu-pm.c b/drivers/soc/mediatek/apusys/mtk-apu-pm.c index 10dd30052c46..7be5acb75d78 100644 --- a/drivers/soc/mediatek/apusys/mtk-apu-pm.c +++ b/drivers/soc/mediatek/apusys/mtk-apu-pm.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ +#include <linux/arm-smccc.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/init.h> @@ -18,9 +19,12 @@ #include <linux/pm_domain.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> +#include <linux/soc/mediatek/mtk_sip_svc.h> #define APU_PD_IPUIF_HW_CG BIT(0) #define APU_PD_RPC_AUTO_BUCK BIT(1) +#define APU_PD_ACC BIT(2) +#define APU_PD_SEC_PWR BIT(3) #define APU_PD_CAPS(_pd, _x) ((_pd)->data->caps & (_x)) #define MTK_POLL_DELAY_US 10 @@ -44,6 +48,11 @@ static const struct reg_sequence mt8192_rpc_sw_type[] = { { MT8192_RPC_SW_TYPE(6), 0x3 }, }; +#define MTK_SIP_APUPWR_BUS_PROT_CG_ON 0x02U +#define MTK_SIP_APUPWR_BULK_PLL 0x03U +#define MTK_SIP_APUPWR_ACC_INIT_ALL 0x04U +#define MTK_SIP_APUPWR_ACC_TOP 0x05U + struct apu_top_domain { u32 spm_ext_buck_iso; u32 spm_ext_buck_iso_mask; @@ -81,6 +90,23 @@ static struct apu_top_domain mt8192_top_reg = { .num_rpc_sw = ARRAY_SIZE(mt8192_rpc_sw_type), }; +static struct apu_top_domain mt8195_top_reg = { + .spm_ext_buck_iso = 0x3EC, + .spm_ext_buck_iso_mask = 0x21, + .spm_cross_wake_m01 = 0x670, + .wake_apu = BIT(0), + .spm_other_pwr = 0x198, + .pwr_status = BIT(4), + .conn_clr = 0x8, + .conn1_clr = 0x8, + .vcore_clr = 0x8, + .rpc_top_con = 0x0, + .rpc_top_con_init_mask = 0x9E, + .rpc_top_sel = 0x4, + .rpc_top_intf_pwr_rdy = 0x44, + .pwr_rdy = BIT(0), +}; + struct apusys { struct device *dev; struct regmap *scpsys; @@ -125,6 +151,7 @@ static int apu_top_init_hw(struct apu_domain *pd) { struct apusys *apusys = pd->apusys; int ret; + struct arm_smccc_res res; if (APU_PD_CAPS(pd, APU_PD_IPUIF_HW_CG)) { ret = clk_prepare_enable(pd->clk_top_conn); @@ -148,6 +175,15 @@ static int apu_top_init_hw(struct apu_domain *pd) } } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + goto err_clk; + } + } ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_clk; @@ -181,6 +217,18 @@ static int apu_top_init_hw(struct apu_domain *pd) goto err_clk; } + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_INIT_ALL, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc init all fail: %lu\n", res.a0); + goto err_clk; + } + } + } + if (APU_PD_CAPS(pd, APU_PD_IPUIF_HW_CG)) { clk_disable_unprepare(pd->clk_top_conn); ret = clk_set_parent(pd->clk_top_ipu_if, pd->clk_off); @@ -189,6 +237,9 @@ static int apu_top_init_hw(struct apu_domain *pd) goto err_clk; } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -199,6 +250,9 @@ static int apu_top_init_hw(struct apu_domain *pd) clk_disable_unprepare(pd->clk_top_conn); clk_disable_unprepare(pd->clk_top_ipu_if); } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -214,16 +268,31 @@ static const struct apu_domain_data apu_domain_data_mt8192[] = { } }; +static const struct apu_domain_data apu_domain_data_mt8195[] = { + { + .domain_idx = 0, + .name = "apu-top", + .caps = APU_PD_RPC_AUTO_BUCK | APU_PD_ACC | APU_PD_SEC_PWR, + .topd = &mt8195_top_reg, + } +}; + static const struct apu_pm_data mt8192_apu_pm_data = { .domains_data = apu_domain_data_mt8192, .num_domains = ARRAY_SIZE(apu_domain_data_mt8192), }; +static const struct apu_pm_data mt8195_apu_pm_data = { + .domains_data = apu_domain_data_mt8195, + .num_domains = ARRAY_SIZE(apu_domain_data_mt8195), +}; + static int apu_top_power_on(struct generic_pm_domain *genpd) { struct apu_domain *pd = to_apu_domain(genpd); struct apusys *apusys = pd->apusys; int ret, tmp; + struct arm_smccc_res res; if (apusys->vsram_supply) { ret = regulator_enable(apusys->vsram_supply); @@ -269,6 +338,25 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) } } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + goto err_clk; + } + + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_TOP, + 1, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc top smc fail: %lu\n", res.a0); + goto err_clk; + } + } + } ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_clk; @@ -301,6 +389,15 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) goto err_clk; } + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BUS_PROT_CG_ON, + 0, 0, 0, 0, 0, 0, &res); + if (res.a0) { + dev_err(apusys->dev, "apu bus_prot smc fail: %lu\n", res.a0); + goto err_clk; + } + } + if (apusys->vcore) { ret = regmap_write(apusys->vcore, pd->data->topd->vcore_clr, CG_CLR); @@ -329,6 +426,9 @@ static int apu_top_power_on(struct generic_pm_domain *genpd) clk_disable_unprepare(pd->clk_top_conn); clk_disable_unprepare(pd->clk_top_ipu_if); } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } if (pd->domain_supply) @@ -345,6 +445,7 @@ static int apu_top_power_off(struct generic_pm_domain *genpd) struct apu_domain *pd = to_apu_domain(genpd); struct apusys *apusys = pd->apusys; int ret, tmp; + struct arm_smccc_res res; if (apusys->vcore) { ret = regmap_write(apusys->vcore, @@ -405,6 +506,25 @@ static int apu_top_power_off(struct generic_pm_domain *genpd) return ret; } } else { + if (APU_PD_CAPS(pd, APU_PD_SEC_PWR)) { + if (APU_PD_CAPS(pd, APU_PD_ACC)) { + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_ACC_TOP, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu acc top smc fail: %lu\n", res.a0); + return ret; + } + } + + arm_smccc_smc(MTK_SIP_APUSYS_CONTROL, MTK_SIP_APUPWR_BULK_PLL, + 0, 0, 0, 0, 0, 0, &res); + ret = res.a0; + if (ret) { + dev_err(apusys->dev, "apu pll smc fail: %lu\n", res.a0); + return ret; + } + } clk_bulk_disable_unprepare(pd->num_clks, pd->clks); } @@ -610,6 +730,10 @@ static const struct of_device_id apu_pm_of_match[] = { .compatible = "mediatek,mt8192-apu-pm", .data = &mt8192_apu_pm_data, }, + { + .compatible = "mediatek,mt8195-apu-pm", + .data = &mt8195_apu_pm_data, + }, { } }; -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 4/6] arm64: dts: mt8195: Add APU nodes 2021-12-10 17:37 ` Flora Fu (?) @ 2021-12-10 17:37 ` Flora Fu -1 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add APU nodes to MT8195. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 4980b8329b54..828ac8a6b95f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1360,6 +1360,21 @@ #clock-cells = <1>; }; + apu_conn: syscon@19020000 { + compatible = "mediatek,mt8195-apu-conn", "syscon"; + reg = <0 0x19020000 0 0x1000>; + }; + + apu_conn1: syscon@19024000 { + compatible = "mediatek,mt8195-apu-conn1", "syscon"; + reg = <0 0x19024000 0 0x1000>; + }; + + apu_vcore: syscon@19029000 { + compatible = "mediatek,mt8195-apu-vcore", "syscon"; + reg = <0 0x19029000 0 0x1000>; + }; + apusys_pll: clock-controller@190f3000 { compatible = "mediatek,mt8195-apusys_pll"; reg = <0 0x190f3000 0 0x1000>; -- 2.18.0 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 4/6] arm64: dts: mt8195: Add APU nodes @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add APU nodes to MT8195. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 4980b8329b54..828ac8a6b95f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1360,6 +1360,21 @@ #clock-cells = <1>; }; + apu_conn: syscon@19020000 { + compatible = "mediatek,mt8195-apu-conn", "syscon"; + reg = <0 0x19020000 0 0x1000>; + }; + + apu_conn1: syscon@19024000 { + compatible = "mediatek,mt8195-apu-conn1", "syscon"; + reg = <0 0x19024000 0 0x1000>; + }; + + apu_vcore: syscon@19029000 { + compatible = "mediatek,mt8195-apu-vcore", "syscon"; + reg = <0 0x19029000 0 0x1000>; + }; + apusys_pll: clock-controller@190f3000 { compatible = "mediatek,mt8195-apusys_pll"; reg = <0 0x190f3000 0 0x1000>; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 4/6] arm64: dts: mt8195: Add APU nodes @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add APU nodes to MT8195. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 4980b8329b54..828ac8a6b95f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1360,6 +1360,21 @@ #clock-cells = <1>; }; + apu_conn: syscon@19020000 { + compatible = "mediatek,mt8195-apu-conn", "syscon"; + reg = <0 0x19020000 0 0x1000>; + }; + + apu_conn1: syscon@19024000 { + compatible = "mediatek,mt8195-apu-conn1", "syscon"; + reg = <0 0x19024000 0 0x1000>; + }; + + apu_vcore: syscon@19029000 { + compatible = "mediatek,mt8195-apu-vcore", "syscon"; + reg = <0 0x19029000 0 0x1000>; + }; + apusys_pll: clock-controller@190f3000 { compatible = "mediatek,mt8195-apusys_pll"; reg = <0 0x190f3000 0 0x1000>; -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 5/6] arm64: dts: mt8195: Add APU power domain node 2021-12-10 17:37 ` Flora Fu (?) @ 2021-12-10 17:37 ` Flora Fu -1 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add APU power domain node to MT8195. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 828ac8a6b95f..6e60c4a38495 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1375,6 +1375,22 @@ reg = <0 0x19029000 0 0x1000>; }; + apuspm: power-domain@190f0000 { + compatible = "mediatek,mt8195-apu-pm", "syscon"; + reg = <0 0x190f0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + mediatek,scpsys = <&scpsys>; + mediatek,apu-conn = <&apu_conn>; + mediatek,apu-conn1 = <&apu_conn1>; + mediatek,apu-vcore = <&apu_vcore>; + apu_top: power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + }; + apusys_pll: clock-controller@190f3000 { compatible = "mediatek,mt8195-apusys_pll"; reg = <0 0x190f3000 0 0x1000>; -- 2.18.0 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 5/6] arm64: dts: mt8195: Add APU power domain node @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add APU power domain node to MT8195. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 828ac8a6b95f..6e60c4a38495 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1375,6 +1375,22 @@ reg = <0 0x19029000 0 0x1000>; }; + apuspm: power-domain@190f0000 { + compatible = "mediatek,mt8195-apu-pm", "syscon"; + reg = <0 0x190f0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + mediatek,scpsys = <&scpsys>; + mediatek,apu-conn = <&apu_conn>; + mediatek,apu-conn1 = <&apu_conn1>; + mediatek,apu-vcore = <&apu_vcore>; + apu_top: power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + }; + apusys_pll: clock-controller@190f3000 { compatible = "mediatek,mt8195-apusys_pll"; reg = <0 0x190f3000 0 0x1000>; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 5/6] arm64: dts: mt8195: Add APU power domain node @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Add APU power domain node to MT8195. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 828ac8a6b95f..6e60c4a38495 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1375,6 +1375,22 @@ reg = <0 0x19029000 0 0x1000>; }; + apuspm: power-domain@190f0000 { + compatible = "mediatek,mt8195-apu-pm", "syscon"; + reg = <0 0x190f0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + mediatek,scpsys = <&scpsys>; + mediatek,apu-conn = <&apu_conn>; + mediatek,apu-conn1 = <&apu_conn1>; + mediatek,apu-vcore = <&apu_vcore>; + apu_top: power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + }; + apusys_pll: clock-controller@190f3000 { compatible = "mediatek,mt8195-apusys_pll"; reg = <0 0x190f3000 0 0x1000>; -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 6/6] arm64: dts: mt8195: Set up apu power domain regulators 2021-12-10 17:37 ` Flora Fu (?) @ 2021-12-10 17:37 ` Flora Fu -1 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Set up apu power domain related regulators. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index c9f23742cb6f..6333cab7929f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "mt8195.dtsi" +#include "mt6359.dtsi" / { model = "MediaTek MT8195 evaluation board"; @@ -36,6 +37,13 @@ status = "okay"; }; +&apuspm { + vsram-supply = <&mt6359_vsram_md_ldo_reg>; + apu_top: power-domain@0 { + domain-supply = <&mt6359_vproc1_buck_reg>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pin>; -- 2.18.0 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 6/6] arm64: dts: mt8195: Set up apu power domain regulators @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Set up apu power domain related regulators. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index c9f23742cb6f..6333cab7929f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "mt8195.dtsi" +#include "mt6359.dtsi" / { model = "MediaTek MT8195 evaluation board"; @@ -36,6 +37,13 @@ status = "okay"; }; +&apuspm { + vsram-supply = <&mt6359_vsram_md_ldo_reg>; + apu_top: power-domain@0 { + domain-supply = <&mt6359_vproc1_buck_reg>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pin>; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 6/6] arm64: dts: mt8195: Set up apu power domain regulators @ 2021-12-10 17:37 ` Flora Fu 0 siblings, 0 replies; 21+ messages in thread From: Flora Fu @ 2021-12-10 17:37 UTC (permalink / raw) To: Matthias Brugger, Pi-Cheng Chen Cc: linux-arm-kernel, linux-mediatek, linux-kernel, Flora Fu, Yong Wu, JB Tsai, Chun-Jie Chen Set up apu power domain related regulators. Signed-off-by: Flora Fu <flora.fu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index c9f23742cb6f..6333cab7929f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "mt8195.dtsi" +#include "mt6359.dtsi" / { model = "MediaTek MT8195 evaluation board"; @@ -36,6 +37,13 @@ status = "okay"; }; +&apuspm { + vsram-supply = <&mt6359_vsram_md_ldo_reg>; + apu_top: power-domain@0 { + domain-supply = <&mt6359_vproc1_buck_reg>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pin>; -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 21+ messages in thread
end of thread, other threads:[~2021-12-10 17:51 UTC | newest] Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-12-10 17:37 [PATCH 0/6] Add MT8195 APU Power Domain Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` [PATCH 1/6] dt-bindings: soc: mediatek: apu: Add MT8195 APU power domain Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` [PATCH 2/6] dt-bindings: arm: mediatek: Add MT8195 APU bindings Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` [PATCH 3/6] soc: mediatek: apu: Add MT8195 apu power domain Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` [PATCH 4/6] arm64: dts: mt8195: Add APU nodes Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` [PATCH 5/6] arm64: dts: mt8195: Add APU power domain node Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` [PATCH 6/6] arm64: dts: mt8195: Set up apu power domain regulators Flora Fu 2021-12-10 17:37 ` Flora Fu 2021-12-10 17:37 ` Flora Fu
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