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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>, Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-phy@lists.infradead.org,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v3 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450
Date: Sat, 11 Dec 2021 05:17:49 +0300	[thread overview]
Message-ID: <20211211021758.1712299-2-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20211211021758.1712299-1-dmitry.baryshkov@linaro.org>

Document the PCIe DT bindings for SM8450 SoC.The PCIe IP is similar
to the one used on SM8250. Add the compatible for SM8450.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 .../devicetree/bindings/pci/qcom,pcie.txt     | 21 ++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index a0ae024c2d0c..73bc763c5009 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -15,6 +15,7 @@
 			- "qcom,pcie-sc8180x" for sc8180x
 			- "qcom,pcie-sdm845" for sdm845
 			- "qcom,pcie-sm8250" for sm8250
+			- "qcom,pcie-sm8450" for sm8450
 			- "qcom,pcie-ipq6018" for ipq6018
 
 - reg:
@@ -169,6 +170,24 @@
 			- "ddrss_sf_tbu" PCIe SF TBU clock
 			- "pipe"	PIPE clock
 
+- clock-names:
+	Usage: required for sm8450
+	Value type: <stringlist>
+	Definition: Should contain the following entries
+			- "aux"         Auxiliary clock
+			- "cfg"         Configuration clock
+			- "bus_master"  Master AXI clock
+			- "bus_slave"   Slave AXI clock
+			- "slave_q2a"   Slave Q2A clock
+			- "tbu"         PCIe TBU clock
+			- "ddrss_sf_tbu" PCIe SF TBU clock
+			- "pipe"        PIPE clock
+			- "pipe_mux"    PIPE MUX
+			- "phy_pipe"    PIPE output clock
+			- "ref"         REFERENCE clock
+			- "aggre0"	Aggre NoC PCIe0 AXI clock
+			- "aggre1"	Aggre NoC PCIe1 AXI clock
+
 - resets:
 	Usage: required
 	Value type: <prop-encoded-array>
@@ -246,7 +265,7 @@
 			- "ahb"			AHB reset
 
 - reset-names:
-	Usage: required for sc8180x, sdm845 and sm8250
+	Usage: required for sc8180x, sdm845, sm8250 and sm8450
 	Value type: <stringlist>
 	Definition: Should contain the following entries
 			- "pci"			PCIe core reset
-- 
2.33.0


WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>, Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-phy@lists.infradead.org,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v3 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450
Date: Sat, 11 Dec 2021 05:17:49 +0300	[thread overview]
Message-ID: <20211211021758.1712299-2-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20211211021758.1712299-1-dmitry.baryshkov@linaro.org>

Document the PCIe DT bindings for SM8450 SoC.The PCIe IP is similar
to the one used on SM8250. Add the compatible for SM8450.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 .../devicetree/bindings/pci/qcom,pcie.txt     | 21 ++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index a0ae024c2d0c..73bc763c5009 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -15,6 +15,7 @@
 			- "qcom,pcie-sc8180x" for sc8180x
 			- "qcom,pcie-sdm845" for sdm845
 			- "qcom,pcie-sm8250" for sm8250
+			- "qcom,pcie-sm8450" for sm8450
 			- "qcom,pcie-ipq6018" for ipq6018
 
 - reg:
@@ -169,6 +170,24 @@
 			- "ddrss_sf_tbu" PCIe SF TBU clock
 			- "pipe"	PIPE clock
 
+- clock-names:
+	Usage: required for sm8450
+	Value type: <stringlist>
+	Definition: Should contain the following entries
+			- "aux"         Auxiliary clock
+			- "cfg"         Configuration clock
+			- "bus_master"  Master AXI clock
+			- "bus_slave"   Slave AXI clock
+			- "slave_q2a"   Slave Q2A clock
+			- "tbu"         PCIe TBU clock
+			- "ddrss_sf_tbu" PCIe SF TBU clock
+			- "pipe"        PIPE clock
+			- "pipe_mux"    PIPE MUX
+			- "phy_pipe"    PIPE output clock
+			- "ref"         REFERENCE clock
+			- "aggre0"	Aggre NoC PCIe0 AXI clock
+			- "aggre1"	Aggre NoC PCIe1 AXI clock
+
 - resets:
 	Usage: required
 	Value type: <prop-encoded-array>
@@ -246,7 +265,7 @@
 			- "ahb"			AHB reset
 
 - reset-names:
-	Usage: required for sc8180x, sdm845 and sm8250
+	Usage: required for sc8180x, sdm845, sm8250 and sm8450
 	Value type: <stringlist>
 	Definition: Should contain the following entries
 			- "pci"			PCIe core reset
-- 
2.33.0


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linux-phy@lists.infradead.org
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  reply	other threads:[~2021-12-11  2:18 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-11  2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
2021-12-11  2:17 ` Dmitry Baryshkov
2021-12-11  2:17 ` Dmitry Baryshkov [this message]
2021-12-11  2:17   ` [PATCH v3 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Dmitry Baryshkov
2021-12-11  2:17 ` [PATCH v3 02/10] dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings Dmitry Baryshkov
2021-12-11  2:17   ` [PATCH v3 02/10] dt-bindings: phy: qcom, qmp: " Dmitry Baryshkov
2021-12-11  2:17 ` [PATCH v3 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support Dmitry Baryshkov
2021-12-11  2:17   ` Dmitry Baryshkov
2021-12-15 22:36   ` Bjorn Andersson
2021-12-15 22:36     ` Bjorn Andersson
2021-12-16  1:28     ` Dmitry Baryshkov
2021-12-16  1:28       ` Dmitry Baryshkov
2021-12-18  5:17       ` Vinod Koul
2021-12-18  5:17         ` Vinod Koul
2021-12-11  2:17 ` [PATCH v3 04/10] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg Dmitry Baryshkov
2021-12-11  2:17   ` Dmitry Baryshkov
2021-12-13 23:24   ` Bjorn Helgaas
2021-12-13 23:24     ` Bjorn Helgaas
2021-12-11  2:17 ` [PATCH v3 05/10] PCI: qcom: Add ddrss_sf_tbu flag Dmitry Baryshkov
2021-12-11  2:17   ` Dmitry Baryshkov
2021-12-11  2:17 ` [PATCH v3 06/10] PCI: qcom: Add SM8450 PCIe support Dmitry Baryshkov
2021-12-11  2:17   ` Dmitry Baryshkov
2021-12-11  2:17 ` [PATCH v3 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node Dmitry Baryshkov
2021-12-11  2:17   ` Dmitry Baryshkov
2021-12-11  2:17 ` [PATCH v3 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device Dmitry Baryshkov
2021-12-11  2:17   ` Dmitry Baryshkov
2021-12-15 22:35   ` Bjorn Andersson
2021-12-15 22:35     ` Bjorn Andersson
2021-12-17  1:22     ` Dmitry Baryshkov
2021-12-17  1:22       ` Dmitry Baryshkov
2021-12-11  2:17 ` [PATCH v3 09/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device Dmitry Baryshkov
2021-12-11  2:17   ` Dmitry Baryshkov
2021-12-11  2:17 ` [PATCH v3 10/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 host Dmitry Baryshkov
2021-12-11  2:17   ` Dmitry Baryshkov

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