* [PATCH] arm64: dts: imx8m{m,n}_venice*: add gpio-line-names @ 2021-12-15 0:18 ` Tim Harvey 0 siblings, 0 replies; 8+ messages in thread From: Tim Harvey @ 2021-12-15 0:18 UTC (permalink / raw) To: Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel Cc: Tim Harvey Add gpio-line-names for the various GPIO's used on Gateworks Venice boards. Note that these GPIO's are typically 'configured' in Boot Firmware via gpio-hog therefore we only configure line names to keep the boot firmware configuration from changing on kernel init. Signed-off-by: Tim Harvey <tharvey@gateworks.com> --- .../dts/freescale/imx8mm-venice-gw71xx.dtsi | 14 +++++++ .../dts/freescale/imx8mm-venice-gw72xx.dtsi | 16 ++++++++ .../dts/freescale/imx8mm-venice-gw73xx.dtsi | 16 ++++++++ .../dts/freescale/imx8mm-venice-gw7901.dts | 23 +++++++++++ .../dts/freescale/imx8mm-venice-gw7902.dts | 39 ++++++++++++++++++- .../dts/freescale/imx8mn-venice-gw7902.dts | 39 ++++++++++++++++++- 6 files changed, 145 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 506335efc391..73addc0b8e57 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -68,6 +68,20 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 72a3a3aa8fcd..1e7badb2a82e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -88,6 +88,22 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "rs485_term", "mipi_gpio4", "", "", + "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", + "mipi_gpio1", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 7b00b6b5bb38..426483ec1f88 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -108,6 +108,22 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "rs485_term", "mipi_gpio4", "", "", + "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", + "mipi_gpio1", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 4bf2b97b3ef5..8710586a1d8f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -293,6 +293,29 @@ }; }; +&gpio1 { + gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", + "", "uart1_rs232#", "dig1_in", "dig1_out", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "uart3_rs232#", "uart3_rs422#", + "uart3_rs485#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", + "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &gpu_2d { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 1b2aaf299b24..edf0c7aaaef0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -260,6 +260,43 @@ }; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", + "uart2_en#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", + "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485", + "", "uart1_term", "uart1_half", "app_gpio2", + "mipi_gpio1", "", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "mipi_gpio4", + "mipi_gpio3", "mipi_gpio2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -691,7 +728,7 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 2d58005d20e4..3c0e63d2e82d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -255,6 +255,43 @@ }; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", + "uart2_en#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "app_gpio1", "", "uart1_rs485", + "", "uart1_term", "uart1_half", "app_gpio2", + "mipi_gpio1", "", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "mipi_gpio4", + "mipi_gpio3", "mipi_gpio2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &gpu { status = "disabled"; }; @@ -645,7 +682,7 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] arm64: dts: imx8m{m,n}_venice*: add gpio-line-names @ 2021-12-15 0:18 ` Tim Harvey 0 siblings, 0 replies; 8+ messages in thread From: Tim Harvey @ 2021-12-15 0:18 UTC (permalink / raw) To: Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel Cc: Tim Harvey Add gpio-line-names for the various GPIO's used on Gateworks Venice boards. Note that these GPIO's are typically 'configured' in Boot Firmware via gpio-hog therefore we only configure line names to keep the boot firmware configuration from changing on kernel init. Signed-off-by: Tim Harvey <tharvey@gateworks.com> --- .../dts/freescale/imx8mm-venice-gw71xx.dtsi | 14 +++++++ .../dts/freescale/imx8mm-venice-gw72xx.dtsi | 16 ++++++++ .../dts/freescale/imx8mm-venice-gw73xx.dtsi | 16 ++++++++ .../dts/freescale/imx8mm-venice-gw7901.dts | 23 +++++++++++ .../dts/freescale/imx8mm-venice-gw7902.dts | 39 ++++++++++++++++++- .../dts/freescale/imx8mn-venice-gw7902.dts | 39 ++++++++++++++++++- 6 files changed, 145 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 506335efc391..73addc0b8e57 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -68,6 +68,20 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 72a3a3aa8fcd..1e7badb2a82e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -88,6 +88,22 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "rs485_term", "mipi_gpio4", "", "", + "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", + "mipi_gpio1", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 7b00b6b5bb38..426483ec1f88 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -108,6 +108,22 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "rs485_term", "mipi_gpio4", "", "", + "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", + "mipi_gpio1", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 4bf2b97b3ef5..8710586a1d8f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -293,6 +293,29 @@ }; }; +&gpio1 { + gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", + "", "uart1_rs232#", "dig1_in", "dig1_out", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "uart3_rs232#", "uart3_rs422#", + "uart3_rs485#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", + "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &gpu_2d { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 1b2aaf299b24..edf0c7aaaef0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -260,6 +260,43 @@ }; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", + "uart2_en#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", + "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485", + "", "uart1_term", "uart1_half", "app_gpio2", + "mipi_gpio1", "", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "mipi_gpio4", + "mipi_gpio3", "mipi_gpio2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -691,7 +728,7 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 2d58005d20e4..3c0e63d2e82d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -255,6 +255,43 @@ }; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", + "uart2_en#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "app_gpio1", "", "uart1_rs485", + "", "uart1_term", "uart1_half", "app_gpio2", + "mipi_gpio1", "", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "mipi_gpio4", + "mipi_gpio3", "mipi_gpio2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &gpu { status = "disabled"; }; @@ -645,7 +682,7 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] arm64: dts: imx8m{m,n}_venice*: add gpio-line-names 2021-12-15 0:18 ` Tim Harvey @ 2022-01-26 9:07 ` Shawn Guo -1 siblings, 0 replies; 8+ messages in thread From: Shawn Guo @ 2022-01-26 9:07 UTC (permalink / raw) To: Tim Harvey Cc: Rob Herring, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel On Tue, Dec 14, 2021 at 04:18:12PM -0800, Tim Harvey wrote: > Add gpio-line-names for the various GPIO's used on Gateworks Venice > boards. Note that these GPIO's are typically 'configured' in Boot > Firmware via gpio-hog therefore we only configure line names to keep the > boot firmware configuration from changing on kernel init. > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> It doesn't apply to my imx/dt64 branch. Could you rebase? Shawn ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] arm64: dts: imx8m{m,n}_venice*: add gpio-line-names @ 2022-01-26 9:07 ` Shawn Guo 0 siblings, 0 replies; 8+ messages in thread From: Shawn Guo @ 2022-01-26 9:07 UTC (permalink / raw) To: Tim Harvey Cc: Rob Herring, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel On Tue, Dec 14, 2021 at 04:18:12PM -0800, Tim Harvey wrote: > Add gpio-line-names for the various GPIO's used on Gateworks Venice > boards. Note that these GPIO's are typically 'configured' in Boot > Firmware via gpio-hog therefore we only configure line names to keep the > boot firmware configuration from changing on kernel init. > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> It doesn't apply to my imx/dt64 branch. Could you rebase? Shawn _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] arm64: dts: imx8m{m,n}_venice*: add gpio-line-names 2022-01-26 9:07 ` Shawn Guo @ 2022-01-27 22:49 ` Tim Harvey -1 siblings, 0 replies; 8+ messages in thread From: Tim Harvey @ 2022-01-27 22:49 UTC (permalink / raw) To: Shawn Guo Cc: Rob Herring, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Device Tree Mailing List, open list, Linux ARM Mailing List On Wed, Jan 26, 2022 at 1:07 AM Shawn Guo <shawnguo@kernel.org> wrote: > > On Tue, Dec 14, 2021 at 04:18:12PM -0800, Tim Harvey wrote: > > Add gpio-line-names for the various GPIO's used on Gateworks Venice > > boards. Note that these GPIO's are typically 'configured' in Boot > > Firmware via gpio-hog therefore we only configure line names to keep the > > boot firmware configuration from changing on kernel init. > > > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> > > It doesn't apply to my imx/dt64 branch. Could you rebase? > Shawn, Sure, I'll try to submit another version within a couple of days. Did you happen to see 'arm64: dts: imx8mm-venice*: add PCIe support' [1]? It seems to have been archived for some reason and it may have to be rebased after I re-post this one unless you can take that now. Best Regards, Tim [1] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20211216164149.13333-1-tharvey@gateworks.com/ ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] arm64: dts: imx8m{m,n}_venice*: add gpio-line-names @ 2022-01-27 22:49 ` Tim Harvey 0 siblings, 0 replies; 8+ messages in thread From: Tim Harvey @ 2022-01-27 22:49 UTC (permalink / raw) To: Shawn Guo Cc: Rob Herring, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Device Tree Mailing List, open list, Linux ARM Mailing List On Wed, Jan 26, 2022 at 1:07 AM Shawn Guo <shawnguo@kernel.org> wrote: > > On Tue, Dec 14, 2021 at 04:18:12PM -0800, Tim Harvey wrote: > > Add gpio-line-names for the various GPIO's used on Gateworks Venice > > boards. Note that these GPIO's are typically 'configured' in Boot > > Firmware via gpio-hog therefore we only configure line names to keep the > > boot firmware configuration from changing on kernel init. > > > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> > > It doesn't apply to my imx/dt64 branch. Could you rebase? > Shawn, Sure, I'll try to submit another version within a couple of days. Did you happen to see 'arm64: dts: imx8mm-venice*: add PCIe support' [1]? It seems to have been archived for some reason and it may have to be rebased after I re-post this one unless you can take that now. Best Regards, Tim [1] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20211216164149.13333-1-tharvey@gateworks.com/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] arm64: dts: imx8m{m,n}_venice*: add gpio-line-names 2022-01-27 22:49 ` Tim Harvey @ 2022-01-28 3:54 ` Shawn Guo -1 siblings, 0 replies; 8+ messages in thread From: Shawn Guo @ 2022-01-28 3:54 UTC (permalink / raw) To: Tim Harvey Cc: Rob Herring, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Device Tree Mailing List, open list, Linux ARM Mailing List On Thu, Jan 27, 2022 at 02:49:41PM -0800, Tim Harvey wrote: > On Wed, Jan 26, 2022 at 1:07 AM Shawn Guo <shawnguo@kernel.org> wrote: > > > > On Tue, Dec 14, 2021 at 04:18:12PM -0800, Tim Harvey wrote: > > > Add gpio-line-names for the various GPIO's used on Gateworks Venice > > > boards. Note that these GPIO's are typically 'configured' in Boot > > > Firmware via gpio-hog therefore we only configure line names to keep the > > > boot firmware configuration from changing on kernel init. > > > > > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> > > > > It doesn't apply to my imx/dt64 branch. Could you rebase? > > > > Shawn, > > Sure, I'll try to submit another version within a couple of days. > > Did you happen to see 'arm64: dts: imx8mm-venice*: add PCIe support' > [1]? It seems to have been archived for some reason and it may have to > be rebased after I re-post this one unless you can take that now. I forgot to reply, but I had already pick that up. Shawn ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] arm64: dts: imx8m{m,n}_venice*: add gpio-line-names @ 2022-01-28 3:54 ` Shawn Guo 0 siblings, 0 replies; 8+ messages in thread From: Shawn Guo @ 2022-01-28 3:54 UTC (permalink / raw) To: Tim Harvey Cc: Rob Herring, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Device Tree Mailing List, open list, Linux ARM Mailing List On Thu, Jan 27, 2022 at 02:49:41PM -0800, Tim Harvey wrote: > On Wed, Jan 26, 2022 at 1:07 AM Shawn Guo <shawnguo@kernel.org> wrote: > > > > On Tue, Dec 14, 2021 at 04:18:12PM -0800, Tim Harvey wrote: > > > Add gpio-line-names for the various GPIO's used on Gateworks Venice > > > boards. Note that these GPIO's are typically 'configured' in Boot > > > Firmware via gpio-hog therefore we only configure line names to keep the > > > boot firmware configuration from changing on kernel init. > > > > > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> > > > > It doesn't apply to my imx/dt64 branch. Could you rebase? > > > > Shawn, > > Sure, I'll try to submit another version within a couple of days. > > Did you happen to see 'arm64: dts: imx8mm-venice*: add PCIe support' > [1]? It seems to have been archived for some reason and it may have to > be rebased after I re-post this one unless you can take that now. I forgot to reply, but I had already pick that up. Shawn _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-01-28 3:56 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-12-15 0:18 [PATCH] arm64: dts: imx8m{m,n}_venice*: add gpio-line-names Tim Harvey 2021-12-15 0:18 ` Tim Harvey 2022-01-26 9:07 ` Shawn Guo 2022-01-26 9:07 ` Shawn Guo 2022-01-27 22:49 ` Tim Harvey 2022-01-27 22:49 ` Tim Harvey 2022-01-28 3:54 ` Shawn Guo 2022-01-28 3:54 ` Shawn Guo
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.