From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
To: heiko@sntech.de
Cc: robh+dt@kernel.org, jbx6244@gmail.com,
devicetree@vger.kernel.org, vkoul@kernel.org,
michael.riesch@wolfvision.net,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
kishon@ti.com, p.zabel@pengutronix.de, cl@rock-chips.com,
kever.yang@rock-chips.com,
Yifeng Zhao <yifeng.zhao@rock-chips.com>
Subject: [PATCH v5 0/4] Add Naneng combo PHY support for RK3568
Date: Wed, 15 Dec 2021 17:56:53 +0800 [thread overview]
Message-ID: <20211215095657.13183-1-yifeng.zhao@rock-chips.com> (raw)
This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.
Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset
- add rockchip_combphy_updatel()
- restyle
Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name
- rename node name
Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.
- Move pipe_phy_grf0 to rk3568.dtsi
Changes in v2:
- Fix dtschema/dtc warnings/errors
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.
- Move phy0 to rk3568.dtsi
Johan Jonker (1):
dt-bindings: mfd: syscon: add naneng combo phy register compatible
Yifeng Zhao (3):
dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
phy: rockchip: add naneng combo phy for RK3568
arm64: dts: rockchip: add naneng combo phy nodes for rk3568
.../devicetree/bindings/mfd/syscon.yaml | 2 +
.../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++
drivers/phy/rockchip/Kconfig | 8 +
drivers/phy/rockchip/Makefile | 1 +
.../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++
7 files changed, 823 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
To: heiko@sntech.de
Cc: robh+dt@kernel.org, jbx6244@gmail.com,
devicetree@vger.kernel.org, vkoul@kernel.org,
michael.riesch@wolfvision.net,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
kishon@ti.com, p.zabel@pengutronix.de, cl@rock-chips.com,
kever.yang@rock-chips.com,
Yifeng Zhao <yifeng.zhao@rock-chips.com>
Subject: [PATCH v5 0/4] Add Naneng combo PHY support for RK3568
Date: Wed, 15 Dec 2021 17:56:53 +0800 [thread overview]
Message-ID: <20211215095657.13183-1-yifeng.zhao@rock-chips.com> (raw)
This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.
Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset
- add rockchip_combphy_updatel()
- restyle
Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name
- rename node name
Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.
- Move pipe_phy_grf0 to rk3568.dtsi
Changes in v2:
- Fix dtschema/dtc warnings/errors
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.
- Move phy0 to rk3568.dtsi
Johan Jonker (1):
dt-bindings: mfd: syscon: add naneng combo phy register compatible
Yifeng Zhao (3):
dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
phy: rockchip: add naneng combo phy for RK3568
arm64: dts: rockchip: add naneng combo phy nodes for rk3568
.../devicetree/bindings/mfd/syscon.yaml | 2 +
.../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++
drivers/phy/rockchip/Kconfig | 8 +
drivers/phy/rockchip/Makefile | 1 +
.../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++
7 files changed, 823 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
To: heiko@sntech.de
Cc: robh+dt@kernel.org, jbx6244@gmail.com,
devicetree@vger.kernel.org, vkoul@kernel.org,
michael.riesch@wolfvision.net,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
kishon@ti.com, p.zabel@pengutronix.de, cl@rock-chips.com,
kever.yang@rock-chips.com,
Yifeng Zhao <yifeng.zhao@rock-chips.com>
Subject: [PATCH v5 0/4] Add Naneng combo PHY support for RK3568
Date: Wed, 15 Dec 2021 17:56:53 +0800 [thread overview]
Message-ID: <20211215095657.13183-1-yifeng.zhao@rock-chips.com> (raw)
This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.
Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset
- add rockchip_combphy_updatel()
- restyle
Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name
- rename node name
Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.
- Move pipe_phy_grf0 to rk3568.dtsi
Changes in v2:
- Fix dtschema/dtc warnings/errors
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.
- Move phy0 to rk3568.dtsi
Johan Jonker (1):
dt-bindings: mfd: syscon: add naneng combo phy register compatible
Yifeng Zhao (3):
dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
phy: rockchip: add naneng combo phy for RK3568
arm64: dts: rockchip: add naneng combo phy nodes for rk3568
.../devicetree/bindings/mfd/syscon.yaml | 2 +
.../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++
drivers/phy/rockchip/Kconfig | 8 +
drivers/phy/rockchip/Makefile | 1 +
.../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++
7 files changed, 823 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
--
2.17.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID (diff)
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
To: heiko@sntech.de
Cc: robh+dt@kernel.org, jbx6244@gmail.com,
devicetree@vger.kernel.org, vkoul@kernel.org,
michael.riesch@wolfvision.net,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
kishon@ti.com, p.zabel@pengutronix.de, cl@rock-chips.com,
kever.yang@rock-chips.com,
Yifeng Zhao <yifeng.zhao@rock-chips.com>
Subject: [PATCH v5 0/4] Add Naneng combo PHY support for RK3568
Date: Wed, 15 Dec 2021 17:56:53 +0800 [thread overview]
Message-ID: <20211215095657.13183-1-yifeng.zhao@rock-chips.com> (raw)
This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.
Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset
- add rockchip_combphy_updatel()
- restyle
Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name
- rename node name
Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.
- Move pipe_phy_grf0 to rk3568.dtsi
Changes in v2:
- Fix dtschema/dtc warnings/errors
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.
- Move phy0 to rk3568.dtsi
Johan Jonker (1):
dt-bindings: mfd: syscon: add naneng combo phy register compatible
Yifeng Zhao (3):
dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
phy: rockchip: add naneng combo phy for RK3568
arm64: dts: rockchip: add naneng combo phy nodes for rk3568
.../devicetree/bindings/mfd/syscon.yaml | 2 +
.../phy/phy-rockchip-naneng-combphy.yaml | 126 ++++
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++
drivers/phy/rockchip/Kconfig | 8 +
drivers/phy/rockchip/Makefile | 1 +
.../rockchip/phy-rockchip-naneng-combphy.c | 618 ++++++++++++++++++
7 files changed, 823 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
--
2.17.1
next reply other threads:[~2021-12-15 10:00 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-15 9:56 Yifeng Zhao [this message]
2021-12-15 9:56 ` [PATCH v5 0/4] Add Naneng combo PHY support for RK3568 Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` [PATCH v5 1/4] dt-bindings: mfd: syscon: add naneng combo phy register compatible Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` [PATCH v5 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` [PATCH v5 3/4] phy: rockchip: add naneng combo phy for RK3568 Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 22:47 ` kernel test robot
2021-12-15 22:47 ` kernel test robot
2021-12-15 22:47 ` kernel test robot
2021-12-15 22:47 ` kernel test robot
2021-12-15 22:47 ` kernel test robot
2021-12-23 11:19 ` Vinod Koul
2021-12-23 11:19 ` Vinod Koul
2021-12-23 11:19 ` Vinod Koul
2021-12-23 11:19 ` Vinod Koul
2021-12-23 11:19 ` Vinod Koul
2021-12-15 9:56 ` [PATCH v5 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-15 9:56 ` Yifeng Zhao
2021-12-16 12:19 ` Johan Jonker
2021-12-16 12:19 ` Johan Jonker
2021-12-16 12:19 ` Johan Jonker
2021-12-16 12:19 ` Johan Jonker
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