From: Dinh Nguyen <dinguyen@kernel.org>
To: devicetree@vger.kernel.org
Cc: dinguyen@kernel.org, robh+dt@kernel.org, p.yadav@ti.com
Subject: [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi"
Date: Thu, 16 Dec 2021 16:49:01 -0600 [thread overview]
Message-ID: <20211216224902.374403-2-dinguyen@kernel.org> (raw)
In-Reply-To: <20211216224902.374403-1-dinguyen@kernel.org>
The QSPI controller on Intel's SoCFPGA platform does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash.
Introduce the dts compatible "intel,socfpga-qspi" to differentiate the
hardware.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v3: revert to "intel,socfpga-qspi"
v2: change binding to "cdns,qspi-nor-0010" to be more generic for other
platforms
---
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index ca155abbda7a..037f41f58503 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -29,6 +29,7 @@ properties:
- ti,am654-ospi
- intel,lgm-qspi
- xlnx,versal-ospi-1.0
+ - intel,socfpga-qspi
- const: cdns,qspi-nor
- const: cdns,qspi-nor
--
2.25.1
next prev parent reply other threads:[~2021-12-16 22:49 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 22:49 [PATCHv3 0/2] arm: dts: socfpga: introduce "intel,socfpga-qspi" Dinh Nguyen
2021-12-16 22:49 ` Dinh Nguyen [this message]
2021-12-17 3:47 ` [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" Rob Herring
2021-12-17 8:52 ` Pratyush Yadav
2021-12-21 17:05 ` Rob Herring
2021-12-16 22:49 ` [PATCHv3 2/2] ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" Dinh Nguyen
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