From: Pratyush Yadav <p.yadav@ti.com>
To: Dinh Nguyen <dinguyen@kernel.org>
Cc: <devicetree@vger.kernel.org>, <robh+dt@kernel.org>
Subject: Re: [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi"
Date: Fri, 17 Dec 2021 14:22:45 +0530 [thread overview]
Message-ID: <20211217085243.bmj45gc4awnmkmp3@ti.com> (raw)
In-Reply-To: <20211216224902.374403-2-dinguyen@kernel.org>
On 16/12/21 04:49PM, Dinh Nguyen wrote:
> The QSPI controller on Intel's SoCFPGA platform does not implement the
> CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
> results in a crash.
>
> Introduce the dts compatible "intel,socfpga-qspi" to differentiate the
> hardware.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
next prev parent reply other threads:[~2021-12-17 8:52 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 22:49 [PATCHv3 0/2] arm: dts: socfpga: introduce "intel,socfpga-qspi" Dinh Nguyen
2021-12-16 22:49 ` [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" Dinh Nguyen
2021-12-17 3:47 ` Rob Herring
2021-12-17 8:52 ` Pratyush Yadav [this message]
2021-12-21 17:05 ` Rob Herring
2021-12-16 22:49 ` [PATCHv3 2/2] ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" Dinh Nguyen
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