[igt-dev] [PATCH i-g-t,v5 0/5] Add testing for CCS

[igt-dev] [PATCH i-g-t,v5 0/5] Add testing for CCS

[apoorva1.singh]

From: Apoorva Singh <apoorva1.singh@intel.com>

- Add new library intel_mocs for mocs settings.

- Add new library i915_blt for various blt commands.

- Add a new platform flag, has_flat_ccs, for platforms
  supporting Flat CCS.

- Only use the main copy engines for XY_BLOCK_COPY.
  XY_BLOCK_COPY blt command is used to transfer the ccs data.
  So, we can only run the tests on those engines which have
  support for the "block_copy" capability.

- Add gem_ccs test for CCS testing.
  Commands are constructed with XY_BLOCK_COPY_BLT
  and XY_CTRL_SURF_COPY_BLT instructions.

Apoorva Singh (3):
  lib/i915: Introduce library intel_mocs
  lib/i915: Introduce library i915_blt
  lib/intel_chipset.h: Add has_flat_ccs flag

CQ Tang (1):
  i915/gem_ccs: Add testing for CCS

Chris Wilson (1):
  i915/gem_engine_topology: Only use the main copy engines for
    XY_BLOCK_COPY

 lib/i915/gem_engine_topology.c |  38 +++
 lib/i915/gem_engine_topology.h |   5 +
 lib/i915/i915_blt.c            | 393 +++++++++++++++++++++++++++++++
 lib/i915/i915_blt.h            |  72 ++++++
 lib/i915/intel_mocs.c          |  51 ++++
 lib/i915/intel_mocs.h          |  23 ++
 lib/intel_chipset.h            |   3 +
 lib/meson.build                |   2 +
 tests/i915/gem_ccs.c           | 413 +++++++++++++++++++++++++++++++++
 tests/meson.build              |   1 +
 10 files changed, 1001 insertions(+)
 create mode 100644 lib/i915/i915_blt.c
 create mode 100644 lib/i915/i915_blt.h
 create mode 100644 lib/i915/intel_mocs.c
 create mode 100644 lib/i915/intel_mocs.h
 create mode 100644 tests/i915/gem_ccs.c

-- 
2.25.1

[igt-dev] [PATCH i-g-t, v5 1/5] lib/i915: Introduce library intel_mocs

[apoorva1.singh]

From: Apoorva Singh <apoorva1.singh@intel.com>

Add new library intel_mocs for mocs settings.

Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
---
 lib/i915/intel_mocs.c | 51 +++++++++++++++++++++++++++++++++++++++++++
 lib/i915/intel_mocs.h | 23 +++++++++++++++++++
 lib/meson.build       |  1 +
 3 files changed, 75 insertions(+)
 create mode 100644 lib/i915/intel_mocs.c
 create mode 100644 lib/i915/intel_mocs.h

diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
new file mode 100644
index 00000000..021aef03
--- /dev/null
+++ b/lib/i915/intel_mocs.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "igt.h"
+#include "i915/gem.h"
+#include "intel_mocs.h"
+
+static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
+{
+	uint16_t devid = intel_get_drm_devid(fd);
+
+	/*
+	 * Gen >= 12 onwards don't have a setting for PTE,
+	 * so using I915_MOCS_PTE as mocs index may leads to
+	 * some undefined MOCS behavior.
+	 * This helper function is providing current UC as well
+	 * as WB MOCS index based on platform.
+	 */
+	if (IS_DG1(devid)) {
+		mocs->uc_index = DG1_MOCS_UC_IDX;
+		mocs->wb_index = DG1_MOCS_WB_IDX;
+	} else if (IS_GEN12(devid)) {
+		mocs->uc_index = GEN12_MOCS_UC_IDX;
+		mocs->wb_index = GEN12_MOCS_WB_IDX;
+	} else {
+		mocs->uc_index = I915_MOCS_PTE;
+		mocs->wb_index = I915_MOCS_CACHED;
+	}
+}
+
+/* BitField [6:1] represents index to MOCS Tables
+ * BitField [0] represents Encryption/Decryption
+ */
+
+uint8_t intel_get_wb_mocs(int fd)
+{
+	struct drm_i915_mocs_index mocs;
+
+	get_mocs_index(fd, &mocs);
+	return mocs.wb_index << 1;
+}
+
+uint8_t intel_get_uc_mocs(int fd)
+{
+	struct drm_i915_mocs_index mocs;
+
+	get_mocs_index(fd, &mocs);
+	return mocs.uc_index << 1;
+}
diff --git a/lib/i915/intel_mocs.h b/lib/i915/intel_mocs.h
new file mode 100644
index 00000000..92d0d920
--- /dev/null
+++ b/lib/i915/intel_mocs.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef _INTEL_MOCS_H
+#define _INTEL_MOCS_H
+
+#define DG1_MOCS_UC_IDX			1
+#define DG1_MOCS_WB_IDX			5
+#define GEN12_MOCS_UC_IDX			3
+#define GEN12_MOCS_WB_IDX			2
+#define XY_BLOCK_COPY_BLT_MOCS_SHIFT		21
+#define XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT	25
+
+struct drm_i915_mocs_index {
+	uint8_t uc_index;
+	uint8_t wb_index;
+};
+
+uint8_t intel_get_wb_mocs(int fd);
+uint8_t intel_get_uc_mocs(int fd);
+#endif /* _INTEL_MOCS_H */
diff --git a/lib/meson.build b/lib/meson.build
index b9568a71..f500f0f1 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -11,6 +11,7 @@ lib_sources = [
 	'i915/gem_mman.c',
 	'i915/gem_vm.c',
 	'i915/intel_memory_region.c',
+	'i915/intel_mocs.c',
 	'igt_collection.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t, v5 1/5] lib/i915: Introduce library intel_mocs

[Zbigniew Kempczyński]

On Sun, Dec 19, 2021 at 06:44:39PM +0530, apoorva1.singh@intel.com wrote:
> From: Apoorva Singh <apoorva1.singh@intel.com>
> 
> Add new library intel_mocs for mocs settings.
> 
> Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
> ---
>  lib/i915/intel_mocs.c | 51 +++++++++++++++++++++++++++++++++++++++++++
>  lib/i915/intel_mocs.h | 23 +++++++++++++++++++
>  lib/meson.build       |  1 +
>  3 files changed, 75 insertions(+)
>  create mode 100644 lib/i915/intel_mocs.c
>  create mode 100644 lib/i915/intel_mocs.h
> 
> diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
> new file mode 100644
> index 00000000..021aef03
> --- /dev/null
> +++ b/lib/i915/intel_mocs.c
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include "igt.h"
> +#include "i915/gem.h"
> +#include "intel_mocs.h"
> +
> +static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
> +{
> +	uint16_t devid = intel_get_drm_devid(fd);
> +
> +	/*
> +	 * Gen >= 12 onwards don't have a setting for PTE,
> +	 * so using I915_MOCS_PTE as mocs index may leads to
> +	 * some undefined MOCS behavior.
> +	 * This helper function is providing current UC as well
> +	 * as WB MOCS index based on platform.
> +	 */
> +	if (IS_DG1(devid)) {
> +		mocs->uc_index = DG1_MOCS_UC_IDX;
> +		mocs->wb_index = DG1_MOCS_WB_IDX;
> +	} else if (IS_GEN12(devid)) {
> +		mocs->uc_index = GEN12_MOCS_UC_IDX;
> +		mocs->wb_index = GEN12_MOCS_WB_IDX;
> +	} else {
> +		mocs->uc_index = I915_MOCS_PTE;
> +		mocs->wb_index = I915_MOCS_CACHED;
> +	}
> +}

Ok, this looks better for me right now.

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew


> +
> +/* BitField [6:1] represents index to MOCS Tables
> + * BitField [0] represents Encryption/Decryption
> + */
> +
> +uint8_t intel_get_wb_mocs(int fd)
> +{
> +	struct drm_i915_mocs_index mocs;
> +
> +	get_mocs_index(fd, &mocs);
> +	return mocs.wb_index << 1;
> +}
> +
> +uint8_t intel_get_uc_mocs(int fd)
> +{
> +	struct drm_i915_mocs_index mocs;
> +
> +	get_mocs_index(fd, &mocs);
> +	return mocs.uc_index << 1;
> +}
> diff --git a/lib/i915/intel_mocs.h b/lib/i915/intel_mocs.h
> new file mode 100644
> index 00000000..92d0d920
> --- /dev/null
> +++ b/lib/i915/intel_mocs.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#ifndef _INTEL_MOCS_H
> +#define _INTEL_MOCS_H
> +
> +#define DG1_MOCS_UC_IDX			1
> +#define DG1_MOCS_WB_IDX			5
> +#define GEN12_MOCS_UC_IDX			3
> +#define GEN12_MOCS_WB_IDX			2
> +#define XY_BLOCK_COPY_BLT_MOCS_SHIFT		21
> +#define XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT	25
> +
> +struct drm_i915_mocs_index {
> +	uint8_t uc_index;
> +	uint8_t wb_index;
> +};
> +
> +uint8_t intel_get_wb_mocs(int fd);
> +uint8_t intel_get_uc_mocs(int fd);
> +#endif /* _INTEL_MOCS_H */
> diff --git a/lib/meson.build b/lib/meson.build
> index b9568a71..f500f0f1 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -11,6 +11,7 @@ lib_sources = [
>  	'i915/gem_mman.c',
>  	'i915/gem_vm.c',
>  	'i915/intel_memory_region.c',
> +	'i915/intel_mocs.c',
>  	'igt_collection.c',
>  	'igt_color_encoding.c',
>  	'igt_debugfs.c',
> -- 
> 2.25.1
> 

[igt-dev] [PATCH i-g-t, v5 2/5] lib/i915: Introduce library i915_blt

[apoorva1.singh]

From: Apoorva Singh <apoorva1.singh@intel.com>

Add new library 'i915_blt' for various blt commands.

Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
---
 lib/i915/i915_blt.c | 393 ++++++++++++++++++++++++++++++++++++++++++++
 lib/i915/i915_blt.h |  72 ++++++++
 lib/meson.build     |   1 +
 3 files changed, 466 insertions(+)
 create mode 100644 lib/i915/i915_blt.c
 create mode 100644 lib/i915/i915_blt.h

diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
new file mode 100644
index 00000000..5d6d53e1
--- /dev/null
+++ b/lib/i915/i915_blt.c
@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+#include "i915_blt.h"
+#include "i915/intel_mocs.h"
+
+/*
+ * make_block_copy_batch:
+ * @fd: open i915 drm file descriptor
+ * @batch_buf: the batch buffer to populate with the command
+ * @src: handle of the source BO
+ * @dst: handle of the destination BO
+ * @length: size of the src and dest BOs
+ * @reloc: pointer to the relocation entry for this command
+ * @offset_src: source address offset
+ * @offset_dst: destination address offset
+ * @copy_mode: different modes of copy
+ * @enable_compression: flag to enable compression
+ * @return: length of batch buffer created
+ */
+static int make_block_copy_batch(int fd, uint32_t *batch_buf,
+				 uint32_t src, uint32_t dst, uint32_t length,
+				 struct drm_i915_gem_relocation_entry *reloc,
+				 uint64_t offset_src, uint64_t offset_dst,
+				 enum copy_mode mode, bool enable_compression)
+{
+	uint32_t *b = batch_buf;
+	uint32_t devid;
+	uint8_t src_mocs = intel_get_uc_mocs(fd);
+	uint8_t dst_mocs = src_mocs;
+	int src_mem_type, dst_mem_type;
+	int dst_compression, src_compression;
+	int resolve;
+
+	devid = intel_get_drm_devid(fd);
+
+	igt_assert(AT_LEAST_GEN(devid, 12));
+
+	switch (mode) {
+	case SYS_TO_SYS: /* copy from smem to smem */
+		src_mem_type = MEM_TYPE_SYS;
+		dst_mem_type = MEM_TYPE_SYS;
+		src_compression = 0;
+		dst_compression = 0;
+		resolve = NO_RESOLVE;
+		break;
+	case SYS_TO_LOCAL: /* copy from smem to lmem */
+		src_mem_type = MEM_TYPE_SYS;
+		dst_mem_type = MEM_TYPE_LOCAL;
+		src_compression = 0;
+		dst_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
+		resolve = NO_RESOLVE;
+		break;
+	case LOCAL_TO_SYS: /* copy from lmem to smem */
+		src_mem_type = MEM_TYPE_LOCAL;
+		dst_mem_type = MEM_TYPE_SYS;
+		src_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
+		dst_compression = 0;
+		resolve = NO_RESOLVE;
+		break;
+	case LOCAL_TO_LOCAL: /* copy from lmem to lmem */
+		src_mem_type = MEM_TYPE_LOCAL;
+		dst_mem_type = MEM_TYPE_LOCAL;
+		src_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
+		dst_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
+		resolve = (src == dst) ? FULL_RESOLVE : NO_RESOLVE;
+		break;
+	}
+
+	/* BG 0 */
+	b[0] = BLOCK_COPY_BLT_CMD | (resolve << 12);
+
+	/* BG 1
+	 *
+	 * Using Tile 4 dimensions.  Height = 32 rows
+	 * Width = 128 bytes
+	 */
+	b[1] = dst_compression | TILE_4_FORMAT | TILE_4_WIDTH_DWORD |
+		dst_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
+
+	/* BG 3
+	 *
+	 * X2 = TILE_4_WIDTH
+	 * Y2 = (length / TILE_4_WIDTH) << 16:
+	 */
+	b[3] = TILE_4_WIDTH | (length >> 7) << DEST_Y2_COORDINATE_SHIFT;
+
+	b[4] = offset_dst;
+	b[5] = offset_dst >> 32;
+
+	/* relocate address in b[4] and b[5] */
+	reloc->offset = 4 * (sizeof(uint32_t));
+	reloc->delta = 0;
+	reloc->target_handle = dst;
+	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc->write_domain = I915_GEM_DOMAIN_RENDER;
+	reloc->presumed_offset = 0;
+	reloc++;
+
+	/* BG 6 */
+	b[6] = dst_mem_type << DEST_MEM_TYPE_SHIFT;
+
+	/* BG 8 */
+	b[8] = src_compression | TILE_4_WIDTH_DWORD | TILE_4_FORMAT |
+		src_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
+
+	b[9] = offset_src;
+	b[10] = offset_src >> 32;
+
+	/* relocate address in b[9] and b[10] */
+	reloc->offset = 9 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle = src;
+	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+
+	/* BG 11 */
+	b[11] = src_mem_type << SRC_MEM_TYPE_SHIFT;
+
+	/* BG 16  */
+	b[16] = SURFACE_TYPE_2D |
+		((TILE_4_WIDTH - 1) << DEST_SURF_WIDTH_SHIFT) |
+		(TILE_4_HEIGHT - 1);
+
+	/* BG 19 */
+	b[19] = SURFACE_TYPE_2D |
+		((TILE_4_WIDTH - 1) << SRC_SURF_WIDTH_SHIFT) |
+		(TILE_4_HEIGHT - 1);
+
+	b += XY_BLOCK_COPY_BLT_LEN_DWORD;
+
+	b[0] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
+	reloc->offset = 23 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle = dst_compression > 0 ? dst : src;
+	reloc->read_domains = 0;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+	b[3] = 0;
+
+	b[4] = MI_FLUSH_DW | MI_FLUSH_CCS;
+	reloc->offset = 27 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle = dst_compression > 0 ? dst : src;
+	reloc->read_domains = 0;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+	b[7] = 0;
+
+	b[8] = MI_BATCH_BUFFER_END;
+	b[9] = 0;
+
+	b += 10;
+
+	return (b - batch_buf) * sizeof(uint32_t);
+}
+
+void xy_block_copy_blt(int fd, uint32_t bb_region, uint32_t src, uint32_t dst,
+		       uint64_t src_size, uint64_t dst_size, uint64_t ahnd,
+		       uint32_t length, enum copy_mode mode, bool enable_compression,
+		       uint32_t ctx, struct intel_execution_engine2 *e)
+{
+	struct drm_i915_gem_relocation_entry reloc[4];
+	struct drm_i915_gem_exec_object2 exec[3];
+	struct drm_i915_gem_execbuffer2 execbuf;
+	int len;
+	uint32_t cmd, batch_buf[BATCH_SIZE / sizeof(uint32_t)] = {};
+	uint64_t offset_src, offset_dst, offset_bb, bb_size, ret;
+
+	bb_size = BATCH_SIZE;
+	ret = __gem_create_in_memory_regions(fd, &cmd, &bb_size, bb_region);
+	igt_assert_eq(ret, 0);
+
+	offset_src = get_offset(ahnd, src, src_size, 0);
+	offset_dst = get_offset(ahnd, dst, dst_size, 0);
+	offset_bb = get_offset(ahnd, cmd, bb_size, 0);
+
+	/* construct the batch buffer */
+	memset(reloc, 0, sizeof(reloc));
+	len = make_block_copy_batch(fd, batch_buf, src, dst, length, reloc,
+				    offset_src, offset_dst, mode,
+				    enable_compression);
+
+	/* write batch buffer to 'cmd' BO */
+	gem_write(fd, cmd, 0, batch_buf, len);
+
+	/* Execute the batch buffer */
+	memset(exec, 0, sizeof(exec));
+	exec[0].handle = src;
+	exec[1].handle = dst;
+	exec[2].handle = cmd;
+	exec[2].relocation_count = !ahnd ? 4 : 0;
+	exec[2].relocs_ptr = to_user_pointer(reloc);
+	if (ahnd) {
+		exec[0].offset = offset_src;
+		exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		exec[1].offset = offset_dst;
+		exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+				 EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		exec[2].offset = offset_bb;
+		exec[2].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	}
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(exec);
+	execbuf.buffer_count = 3;
+	execbuf.batch_len = len;
+	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+	if (ctx)
+		execbuf.rsvd1 = ctx;
+
+	gem_execbuf(fd, &execbuf);
+	gem_close(fd, cmd);
+	put_offset(ahnd, src);
+	put_offset(ahnd, dst);
+	put_offset(ahnd, cmd);
+}
+
+/*
+ * make_ctrl_surf_batch:
+ * @fd: open i915 drm file descriptor
+ * @batch_buf: the batch buffer to populate with the command
+ * @src: handle of the source BO
+ * @dst: handle of the destination BO
+ * @length: size of the ctrl surf in bytes
+ * @reloc: pointer to the relocation entyr for this command
+ * @offset_src: source address offset
+ * @offset_dst: destination address offset
+ * @writetodev: flag to enable direct access of the address
+ * @return: length of batch buffer created
+ */
+static int make_ctrl_surf_batch(int fd, uint32_t *batch_buf,
+				uint32_t src, uint32_t dst, uint32_t length,
+				struct drm_i915_gem_relocation_entry *reloc,
+				uint64_t offset_src, uint64_t offset_dst,
+				bool writetodev)
+{
+	int num_ccs_blocks, src_mem_access, dst_mem_access;
+	uint32_t *b = batch_buf;
+	uint8_t src_mocs = intel_get_uc_mocs(fd);
+	uint8_t dst_mocs = src_mocs;
+
+	num_ccs_blocks = length / CCS_RATIO;
+	if (num_ccs_blocks < 1)
+		num_ccs_blocks = 1;
+	if (num_ccs_blocks > NUM_CCS_BLKS_PER_XFER)
+		return 0;
+
+	if (writetodev) {
+		src_mem_access = DIRECT_ACCESS;
+		dst_mem_access = INDIRECT_ACCESS;
+	} else {
+		src_mem_access = INDIRECT_ACCESS;
+		dst_mem_access = DIRECT_ACCESS;
+	}
+
+	/*
+	 * We use logical AND with 1023 since the size field
+	 * takes values which is in the range of 0 - 1023
+	 */
+	b[0] = ((XY_CTRL_SURF_COPY_BLT) |
+		(src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
+		(dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
+		(((num_ccs_blocks - 1) & 1023) << CCS_SIZE_SHIFT));
+
+	b[1] = offset_src;
+	b[2] = offset_src >> 32 | src_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
+
+	/* relocate address in b[1] and b[2] */
+	reloc->offset = 1 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle = src;
+	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+
+	b[3] = offset_dst;
+	b[4] = offset_dst >> 32 | dst_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
+
+	/* relocate address in b[3] and b[4] */
+	reloc->offset = 3 * (sizeof(uint32_t));
+	reloc->delta = 0;
+	reloc->target_handle = dst;
+	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
+	reloc->write_domain = I915_GEM_DOMAIN_RENDER;
+	reloc->presumed_offset = 0;
+	reloc++;
+
+	b[5] = 0;
+
+	b[6] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
+
+	reloc->offset = 7 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle =
+	dst_mem_access == INDIRECT_ACCESS ? dst : src;
+	reloc->read_domains = 0;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+	b[9] = 0;
+
+	b[10] = MI_FLUSH_DW | MI_FLUSH_CCS;
+	reloc->offset = 11 * sizeof(uint32_t);
+	reloc->delta = 0;
+	reloc->target_handle =
+	dst_mem_access == INDIRECT_ACCESS ? dst : src;
+	reloc->read_domains = 0;
+	reloc->write_domain = 0;
+	reloc->presumed_offset = 0;
+	reloc++;
+	b[13] = 0;
+
+	b[14] = MI_BATCH_BUFFER_END;
+	b[15] = 0;
+
+	b += 16;
+
+	return (b - batch_buf) * sizeof(uint32_t);
+}
+
+void xy_ctrl_surf_copy_blt(int fd, uint32_t bb_region, uint32_t src,
+			   uint32_t dst, uint64_t src_size, uint64_t dst_size,
+			   uint64_t ahnd, uint32_t length, bool writetodev,
+			   uint32_t ctx, struct intel_execution_engine2 *e)
+{
+	struct drm_i915_gem_relocation_entry reloc[4];
+	struct drm_i915_gem_exec_object2 exec[3];
+	struct drm_i915_gem_execbuffer2 execbuf;
+	int len;
+	uint32_t cmd, batch_buf[BATCH_SIZE / sizeof(uint32_t)] = {};
+	uint64_t offset_src, offset_dst, offset_bb, bb_size, ret;
+
+	bb_size = BATCH_SIZE;
+	ret = __gem_create_in_memory_regions(fd, &cmd, &bb_size, bb_region);
+	igt_assert_eq(ret, 0);
+
+	offset_src = get_offset(ahnd, src, src_size, 0);
+	offset_dst = get_offset(ahnd, dst, dst_size, 0);
+	offset_bb = get_offset(ahnd, cmd, bb_size, 0);
+
+	/* construct batch command buffer */
+	memset(reloc, 0, sizeof(reloc));
+	len = make_ctrl_surf_batch(fd, batch_buf, src, dst, length, reloc,
+				   offset_src, offset_dst, writetodev);
+
+	/* Copy the batch buff to BO cmd */
+	gem_write(fd, cmd, 0, batch_buf, len);
+
+	/* Execute the batch buffer */
+	memset(exec, 0, sizeof(exec));
+	exec[0].handle = src;
+	exec[1].handle = dst;
+	exec[2].handle = cmd;
+	exec[2].relocation_count = !ahnd ? 4 : 0;
+	exec[2].relocs_ptr = to_user_pointer(reloc);
+	if (ahnd) {
+		exec[0].offset = offset_src;
+		exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		exec[1].offset = offset_dst;
+		exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+				 EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+		exec[2].offset = offset_bb;
+		exec[2].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	}
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(exec);
+	execbuf.buffer_count = 3;
+	execbuf.batch_len = len;
+	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+	if (ctx)
+		execbuf.rsvd1 = ctx;
+
+	gem_execbuf(fd, &execbuf);
+	gem_close(fd, cmd);
+	put_offset(ahnd, src);
+	put_offset(ahnd, dst);
+	put_offset(ahnd, cmd);
+}
diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
new file mode 100644
index 00000000..ff3eee7f
--- /dev/null
+++ b/lib/i915/i915_blt.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+
+#define MI_FLUSH_DW_LEN_DWORD	4
+#define MI_FLUSH_DW		(0x26 << 23 | 1)
+#define MI_FLUSH_CCS		BIT(16)
+#define MI_FLUSH_LLC		BIT(9)
+#define MI_INVALIDATE_TLB	BIT(18)
+
+/* XY_BLOCK_COPY_BLT instruction has 22 bit groups 1 DWORD each */
+#define XY_BLOCK_COPY_BLT_LEN_DWORD	22
+#define BLOCK_COPY_BLT_CMD		(2 << 29 | 0x41 << 22 | 0x14)
+#define COMPRESSION_ENABLE		BIT(29)
+#define AUX_CCS_E			(5 << 18)
+#define NO_RESOLVE			0
+#define FULL_RESOLVE			1
+#define PARTIAL_RESOLVE			2
+#define TILE_4_FORMAT			(2 << 30)
+#define TILE_4_WIDTH			(128)
+#define TILE_4_WIDTH_DWORD		((128 >> 2) - 1)
+#define TILE_4_HEIGHT			(32)
+#define SURFACE_TYPE_2D			BIT(29)
+
+#define DEST_Y2_COORDINATE_SHIFT	(16)
+#define DEST_MEM_TYPE_SHIFT		(31)
+#define SRC_MEM_TYPE_SHIFT		(31)
+#define DEST_SURF_WIDTH_SHIFT		(14)
+#define SRC_SURF_WIDTH_SHIFT		(14)
+
+#define XY_CTRL_SURF_COPY_BLT		(2 << 29 | 0x48 << 22 | 3)
+#define SRC_ACCESS_TYPE_SHIFT		21
+#define DST_ACCESS_TYPE_SHIFT		20
+#define CCS_SIZE_SHIFT			8
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+#define MI_ARB_CHECK			MI_INSTR(0x05, 0)
+#define NUM_CCS_BLKS_PER_XFER		1024
+#define INDIRECT_ACCESS                 0
+#define DIRECT_ACCESS                   1
+
+#define BATCH_SIZE			4096
+#define BOSIZE_MIN			(4 * 1024)
+#define BOSIZE_MAX			(4 * 1024 * 1024)
+#define CCS_RATIO			256
+
+#define MEM_TYPE_SYS			1
+#define MEM_TYPE_LOCAL			0
+
+enum copy_mode {
+	SYS_TO_SYS = 0,
+	SYS_TO_LOCAL,
+	LOCAL_TO_SYS,
+	LOCAL_TO_LOCAL,
+};
+
+void xy_block_copy_blt(int fd, uint32_t bb_region, uint32_t src, uint32_t dst,
+		       uint64_t src_size, uint64_t dst_size, uint64_t ahnd,
+		       uint32_t length, enum copy_mode mode, bool enable_compression,
+		       uint32_t ctx, struct intel_execution_engine2 *e);
+
+void xy_ctrl_surf_copy_blt(int fd, uint32_t bb_region, uint32_t src, uint32_t dst,
+			   uint64_t src_size, uint64_t dst_size, uint64_t ahnd,
+			   uint32_t length, bool writetodev, uint32_t ctx,
+			   struct intel_execution_engine2 *e);
diff --git a/lib/meson.build b/lib/meson.build
index f500f0f1..f2924541 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -12,6 +12,7 @@ lib_sources = [
 	'i915/gem_vm.c',
 	'i915/intel_memory_region.c',
 	'i915/intel_mocs.c',
+	'i915/i915_blt.c',
 	'igt_collection.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
-- 
2.25.1

Re: [igt-dev] [PATCH i-g-t, v5 2/5] lib/i915: Introduce library i915_blt

[Zbigniew Kempczyński]

On Sun, Dec 19, 2021 at 06:44:40PM +0530, apoorva1.singh@intel.com wrote:
> From: Apoorva Singh <apoorva1.singh@intel.com>
> 
> Add new library 'i915_blt' for various blt commands.
> 
> Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
> ---
>  lib/i915/i915_blt.c | 393 ++++++++++++++++++++++++++++++++++++++++++++
>  lib/i915/i915_blt.h |  72 ++++++++
>  lib/meson.build     |   1 +
>  3 files changed, 466 insertions(+)
>  create mode 100644 lib/i915/i915_blt.c
>  create mode 100644 lib/i915/i915_blt.h
> 
> diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
> new file mode 100644
> index 00000000..5d6d53e1
> --- /dev/null
> +++ b/lib/i915/i915_blt.c
> @@ -0,0 +1,393 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include <errno.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include "drm.h"
> +#include "igt.h"
> +#include "i915_blt.h"
> +#include "i915/intel_mocs.h"
> +
> +/*
> + * make_block_copy_batch:
> + * @fd: open i915 drm file descriptor
> + * @batch_buf: the batch buffer to populate with the command
> + * @src: handle of the source BO
> + * @dst: handle of the destination BO
> + * @length: size of the src and dest BOs
> + * @reloc: pointer to the relocation entry for this command
> + * @offset_src: source address offset
> + * @offset_dst: destination address offset
> + * @copy_mode: different modes of copy
> + * @enable_compression: flag to enable compression
> + * @return: length of batch buffer created
> + */
> +static int make_block_copy_batch(int fd, uint32_t *batch_buf,
> +				 uint32_t src, uint32_t dst, uint32_t length,
> +				 struct drm_i915_gem_relocation_entry *reloc,
> +				 uint64_t offset_src, uint64_t offset_dst,
> +				 enum copy_mode mode, bool enable_compression)
> +{
> +	uint32_t *b = batch_buf;
> +	uint32_t devid;
> +	uint8_t src_mocs = intel_get_uc_mocs(fd);
> +	uint8_t dst_mocs = src_mocs;
> +	int src_mem_type, dst_mem_type;
> +	int dst_compression, src_compression;
> +	int resolve;
> +
> +	devid = intel_get_drm_devid(fd);
> +
> +	igt_assert(AT_LEAST_GEN(devid, 12));
> +
> +	switch (mode) {
> +	case SYS_TO_SYS: /* copy from smem to smem */
> +		src_mem_type = MEM_TYPE_SYS;
> +		dst_mem_type = MEM_TYPE_SYS;
> +		src_compression = 0;
> +		dst_compression = 0;
> +		resolve = NO_RESOLVE;
> +		break;
> +	case SYS_TO_LOCAL: /* copy from smem to lmem */
> +		src_mem_type = MEM_TYPE_SYS;
> +		dst_mem_type = MEM_TYPE_LOCAL;
> +		src_compression = 0;
> +		dst_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
> +		resolve = NO_RESOLVE;
> +		break;
> +	case LOCAL_TO_SYS: /* copy from lmem to smem */
> +		src_mem_type = MEM_TYPE_LOCAL;
> +		dst_mem_type = MEM_TYPE_SYS;
> +		src_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
> +		dst_compression = 0;
> +		resolve = NO_RESOLVE;
> +		break;
> +	case LOCAL_TO_LOCAL: /* copy from lmem to lmem */
> +		src_mem_type = MEM_TYPE_LOCAL;
> +		dst_mem_type = MEM_TYPE_LOCAL;
> +		src_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
> +		dst_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
> +		resolve = (src == dst) ? FULL_RESOLVE : NO_RESOLVE;
> +		break;
> +	}
> +
> +	/* BG 0 */
> +	b[0] = BLOCK_COPY_BLT_CMD | (resolve << 12);
> +
> +	/* BG 1
> +	 *
> +	 * Using Tile 4 dimensions.  Height = 32 rows
> +	 * Width = 128 bytes
> +	 */
> +	b[1] = dst_compression | TILE_4_FORMAT | TILE_4_WIDTH_DWORD |
> +		dst_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
> +
> +	/* BG 3
> +	 *
> +	 * X2 = TILE_4_WIDTH
> +	 * Y2 = (length / TILE_4_WIDTH) << 16:
> +	 */
> +	b[3] = TILE_4_WIDTH | (length >> 7) << DEST_Y2_COORDINATE_SHIFT;
> +
> +	b[4] = offset_dst;
> +	b[5] = offset_dst >> 32;
> +
> +	/* relocate address in b[4] and b[5] */
> +	reloc->offset = 4 * (sizeof(uint32_t));
> +	reloc->delta = 0;
> +	reloc->target_handle = dst;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = I915_GEM_DOMAIN_RENDER;
> +	reloc->presumed_offset = 0;

Set to -1 to enforce relocation could occur (TGL only).

> +	reloc++;
> +
> +	/* BG 6 */
> +	b[6] = dst_mem_type << DEST_MEM_TYPE_SHIFT;
> +
> +	/* BG 8 */
> +	b[8] = src_compression | TILE_4_WIDTH_DWORD | TILE_4_FORMAT |
> +		src_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
> +
> +	b[9] = offset_src;
> +	b[10] = offset_src >> 32;
> +
> +	/* relocate address in b[9] and b[10] */
> +	reloc->offset = 9 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = src;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;

Same.

> +	reloc++;
> +
> +	/* BG 11 */
> +	b[11] = src_mem_type << SRC_MEM_TYPE_SHIFT;
> +
> +	/* BG 16  */
> +	b[16] = SURFACE_TYPE_2D |
> +		((TILE_4_WIDTH - 1) << DEST_SURF_WIDTH_SHIFT) |
> +		(TILE_4_HEIGHT - 1);
> +
> +	/* BG 19 */
> +	b[19] = SURFACE_TYPE_2D |
> +		((TILE_4_WIDTH - 1) << SRC_SURF_WIDTH_SHIFT) |
> +		(TILE_4_HEIGHT - 1);
> +
> +	b += XY_BLOCK_COPY_BLT_LEN_DWORD;
> +
> +	b[0] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
> +	reloc->offset = 23 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = dst_compression > 0 ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;

Same.

> +	reloc++;
> +	b[3] = 0;
> +
> +	b[4] = MI_FLUSH_DW | MI_FLUSH_CCS;
> +	reloc->offset = 27 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = dst_compression > 0 ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;

Same.

> +	reloc++;
> +	b[7] = 0;
> +
> +	b[8] = MI_BATCH_BUFFER_END;
> +	b[9] = 0;
> +
> +	b += 10;
> +
> +	return (b - batch_buf) * sizeof(uint32_t);
> +}
> +
> +void xy_block_copy_blt(int fd, uint32_t bb_region, uint32_t src, uint32_t dst,
> +		       uint64_t src_size, uint64_t dst_size, uint64_t ahnd,
> +		       uint32_t length, enum copy_mode mode, bool enable_compression,
> +		       uint32_t ctx, struct intel_execution_engine2 *e)
> +{
> +	struct drm_i915_gem_relocation_entry reloc[4];
> +	struct drm_i915_gem_exec_object2 exec[3];
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	int len;
> +	uint32_t cmd, batch_buf[BATCH_SIZE / sizeof(uint32_t)] = {};
> +	uint64_t offset_src, offset_dst, offset_bb, bb_size, ret;
> +
> +	bb_size = BATCH_SIZE;
> +	ret = __gem_create_in_memory_regions(fd, &cmd, &bb_size, bb_region);
> +	igt_assert_eq(ret, 0);
> +
> +	offset_src = get_offset(ahnd, src, src_size, 0);
> +	offset_dst = get_offset(ahnd, dst, dst_size, 0);
> +	offset_bb = get_offset(ahnd, cmd, bb_size, 0);
> +
> +	/* construct the batch buffer */
> +	memset(reloc, 0, sizeof(reloc));
> +	len = make_block_copy_batch(fd, batch_buf, src, dst, length, reloc,
> +				    offset_src, offset_dst, mode,
> +				    enable_compression);
> +
> +	/* write batch buffer to 'cmd' BO */
> +	gem_write(fd, cmd, 0, batch_buf, len);
> +
> +	/* Execute the batch buffer */
> +	memset(exec, 0, sizeof(exec));
> +	exec[0].handle = src;
> +	exec[1].handle = dst;
> +	exec[2].handle = cmd;
> +	exec[2].relocation_count = !ahnd ? 4 : 0;
> +	exec[2].relocs_ptr = to_user_pointer(reloc);
> +	if (ahnd) {
> +		exec[0].offset = offset_src;
> +		exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		exec[1].offset = offset_dst;
> +		exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +				 EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		exec[2].offset = offset_bb;
> +		exec[2].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	}
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(exec);
> +	execbuf.buffer_count = 3;
> +	execbuf.batch_len = len;
> +	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +	if (ctx)
> +		execbuf.rsvd1 = ctx;

Conditional is not necessary, just:
	execbuf.rsvd1 = ctx;

is ok (you need to provide ctx anyway).

> +
> +	gem_execbuf(fd, &execbuf);
> +	gem_close(fd, cmd);
> +	put_offset(ahnd, src);
> +	put_offset(ahnd, dst);
> +	put_offset(ahnd, cmd);
> +}
> +
> +/*
> + * make_ctrl_surf_batch:
> + * @fd: open i915 drm file descriptor
> + * @batch_buf: the batch buffer to populate with the command
> + * @src: handle of the source BO
> + * @dst: handle of the destination BO
> + * @length: size of the ctrl surf in bytes
> + * @reloc: pointer to the relocation entyr for this command
> + * @offset_src: source address offset
> + * @offset_dst: destination address offset
> + * @writetodev: flag to enable direct access of the address
> + * @return: length of batch buffer created
> + */
> +static int make_ctrl_surf_batch(int fd, uint32_t *batch_buf,
> +				uint32_t src, uint32_t dst, uint32_t length,
> +				struct drm_i915_gem_relocation_entry *reloc,
> +				uint64_t offset_src, uint64_t offset_dst,
> +				bool writetodev)
> +{
> +	int num_ccs_blocks, src_mem_access, dst_mem_access;
> +	uint32_t *b = batch_buf;
> +	uint8_t src_mocs = intel_get_uc_mocs(fd);
> +	uint8_t dst_mocs = src_mocs;
> +
> +	num_ccs_blocks = length / CCS_RATIO;
> +	if (num_ccs_blocks < 1)
> +		num_ccs_blocks = 1;
> +	if (num_ccs_blocks > NUM_CCS_BLKS_PER_XFER)
> +		return 0;
> +
> +	if (writetodev) {
> +		src_mem_access = DIRECT_ACCESS;
> +		dst_mem_access = INDIRECT_ACCESS;
> +	} else {
> +		src_mem_access = INDIRECT_ACCESS;
> +		dst_mem_access = DIRECT_ACCESS;
> +	}
> +
> +	/*
> +	 * We use logical AND with 1023 since the size field
> +	 * takes values which is in the range of 0 - 1023
> +	 */
> +	b[0] = ((XY_CTRL_SURF_COPY_BLT) |
> +		(src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
> +		(dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
> +		(((num_ccs_blocks - 1) & 1023) << CCS_SIZE_SHIFT));
> +
> +	b[1] = offset_src;
> +	b[2] = offset_src >> 32 | src_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
> +
> +	/* relocate address in b[1] and b[2] */
> +	reloc->offset = 1 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = src;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;

Same as above, set to -1. Applies below too.

> +	reloc++;
> +
> +	b[3] = offset_dst;
> +	b[4] = offset_dst >> 32 | dst_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
> +
> +	/* relocate address in b[3] and b[4] */
> +	reloc->offset = 3 * (sizeof(uint32_t));
> +	reloc->delta = 0;
> +	reloc->target_handle = dst;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = I915_GEM_DOMAIN_RENDER;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +
> +	b[5] = 0;
> +
> +	b[6] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
> +
> +	reloc->offset = 7 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle =
> +	dst_mem_access == INDIRECT_ACCESS ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +	b[9] = 0;
> +
> +	b[10] = MI_FLUSH_DW | MI_FLUSH_CCS;
> +	reloc->offset = 11 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle =
> +	dst_mem_access == INDIRECT_ACCESS ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +	b[13] = 0;
> +
> +	b[14] = MI_BATCH_BUFFER_END;
> +	b[15] = 0;
> +
> +	b += 16;
> +
> +	return (b - batch_buf) * sizeof(uint32_t);
> +}
> +
> +void xy_ctrl_surf_copy_blt(int fd, uint32_t bb_region, uint32_t src,
> +			   uint32_t dst, uint64_t src_size, uint64_t dst_size,
> +			   uint64_t ahnd, uint32_t length, bool writetodev,
> +			   uint32_t ctx, struct intel_execution_engine2 *e)
> +{
> +	struct drm_i915_gem_relocation_entry reloc[4];
> +	struct drm_i915_gem_exec_object2 exec[3];
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	int len;
> +	uint32_t cmd, batch_buf[BATCH_SIZE / sizeof(uint32_t)] = {};
> +	uint64_t offset_src, offset_dst, offset_bb, bb_size, ret;
> +
> +	bb_size = BATCH_SIZE;
> +	ret = __gem_create_in_memory_regions(fd, &cmd, &bb_size, bb_region);
> +	igt_assert_eq(ret, 0);
> +
> +	offset_src = get_offset(ahnd, src, src_size, 0);
> +	offset_dst = get_offset(ahnd, dst, dst_size, 0);
> +	offset_bb = get_offset(ahnd, cmd, bb_size, 0);
> +
> +	/* construct batch command buffer */
> +	memset(reloc, 0, sizeof(reloc));
> +	len = make_ctrl_surf_batch(fd, batch_buf, src, dst, length, reloc,
> +				   offset_src, offset_dst, writetodev);
> +
> +	/* Copy the batch buff to BO cmd */
> +	gem_write(fd, cmd, 0, batch_buf, len);
> +
> +	/* Execute the batch buffer */
> +	memset(exec, 0, sizeof(exec));
> +	exec[0].handle = src;
> +	exec[1].handle = dst;
> +	exec[2].handle = cmd;
> +	exec[2].relocation_count = !ahnd ? 4 : 0;
> +	exec[2].relocs_ptr = to_user_pointer(reloc);
> +	if (ahnd) {
> +		exec[0].offset = offset_src;
> +		exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		exec[1].offset = offset_dst;
> +		exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +				 EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		exec[2].offset = offset_bb;
> +		exec[2].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	}
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(exec);
> +	execbuf.buffer_count = 3;
> +	execbuf.batch_len = len;
> +	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +	if (ctx)
> +		execbuf.rsvd1 = ctx;

Remove conditionals.

> +
> +	gem_execbuf(fd, &execbuf);
> +	gem_close(fd, cmd);
> +	put_offset(ahnd, src);
> +	put_offset(ahnd, dst);
> +	put_offset(ahnd, cmd);
> +}
> diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
> new file mode 100644
> index 00000000..ff3eee7f
> --- /dev/null
> +++ b/lib/i915/i915_blt.h
> @@ -0,0 +1,72 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include <errno.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include "drm.h"
> +#include "igt.h"
> +
> +#define MI_FLUSH_DW_LEN_DWORD	4
> +#define MI_FLUSH_DW		(0x26 << 23 | 1)
> +#define MI_FLUSH_CCS		BIT(16)
> +#define MI_FLUSH_LLC		BIT(9)
> +#define MI_INVALIDATE_TLB	BIT(18)
> +
> +/* XY_BLOCK_COPY_BLT instruction has 22 bit groups 1 DWORD each */
> +#define XY_BLOCK_COPY_BLT_LEN_DWORD	22
> +#define BLOCK_COPY_BLT_CMD		(2 << 29 | 0x41 << 22 | 0x14)
> +#define COMPRESSION_ENABLE		BIT(29)
> +#define AUX_CCS_E			(5 << 18)
> +#define NO_RESOLVE			0
> +#define FULL_RESOLVE			1
> +#define PARTIAL_RESOLVE			2
> +#define TILE_4_FORMAT			(2 << 30)
> +#define TILE_4_WIDTH			(128)
> +#define TILE_4_WIDTH_DWORD		((128 >> 2) - 1)
> +#define TILE_4_HEIGHT			(32)
> +#define SURFACE_TYPE_2D			BIT(29)
> +
> +#define DEST_Y2_COORDINATE_SHIFT	(16)
> +#define DEST_MEM_TYPE_SHIFT		(31)
> +#define SRC_MEM_TYPE_SHIFT		(31)
> +#define DEST_SURF_WIDTH_SHIFT		(14)
> +#define SRC_SURF_WIDTH_SHIFT		(14)
> +
> +#define XY_CTRL_SURF_COPY_BLT		(2 << 29 | 0x48 << 22 | 3)
> +#define SRC_ACCESS_TYPE_SHIFT		21
> +#define DST_ACCESS_TYPE_SHIFT		20
> +#define CCS_SIZE_SHIFT			8
> +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> +#define MI_ARB_CHECK			MI_INSTR(0x05, 0)
> +#define NUM_CCS_BLKS_PER_XFER		1024
> +#define INDIRECT_ACCESS                 0
> +#define DIRECT_ACCESS                   1
> +
> +#define BATCH_SIZE			4096
> +#define BOSIZE_MIN			(4 * 1024)
> +#define BOSIZE_MAX			(4 * 1024 * 1024)
> +#define CCS_RATIO			256
> +
> +#define MEM_TYPE_SYS			1
> +#define MEM_TYPE_LOCAL			0
> +
> +enum copy_mode {
> +	SYS_TO_SYS = 0,
> +	SYS_TO_LOCAL,
> +	LOCAL_TO_SYS,
> +	LOCAL_TO_LOCAL,
> +};
> +

Those functions should be documented as they are public. Don't
forget about adding this to xml for processing.

--
Zbigniew 

> +void xy_block_copy_blt(int fd, uint32_t bb_region, uint32_t src, uint32_t dst,
> +		       uint64_t src_size, uint64_t dst_size, uint64_t ahnd,
> +		       uint32_t length, enum copy_mode mode, bool enable_compression,
> +		       uint32_t ctx, struct intel_execution_engine2 *e);
> +
> +void xy_ctrl_surf_copy_blt(int fd, uint32_t bb_region, uint32_t src, uint32_t dst,
> +			   uint64_t src_size, uint64_t dst_size, uint64_t ahnd,
> +			   uint32_t length, bool writetodev, uint32_t ctx,
> +			   struct intel_execution_engine2 *e);
> diff --git a/lib/meson.build b/lib/meson.build
> index f500f0f1..f2924541 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -12,6 +12,7 @@ lib_sources = [
>  	'i915/gem_vm.c',
>  	'i915/intel_memory_region.c',
>  	'i915/intel_mocs.c',
> +	'i915/i915_blt.c',
>  	'igt_collection.c',
>  	'igt_color_encoding.c',
>  	'igt_debugfs.c',
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH i-g-t, v5 2/5] lib/i915: Introduce library i915_blt

[Petri Latvala]

On Sun, Dec 19, 2021 at 06:44:40PM +0530, apoorva1.singh@intel.com wrote:
> From: Apoorva Singh <apoorva1.singh@intel.com>
> 
> Add new library 'i915_blt' for various blt commands.
> 
> Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
> ---
>  lib/i915/i915_blt.c | 393 ++++++++++++++++++++++++++++++++++++++++++++
>  lib/i915/i915_blt.h |  72 ++++++++
>  lib/meson.build     |   1 +
>  3 files changed, 466 insertions(+)
>  create mode 100644 lib/i915/i915_blt.c
>  create mode 100644 lib/i915/i915_blt.h
> 
> diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
> new file mode 100644
> index 00000000..5d6d53e1
> --- /dev/null
> +++ b/lib/i915/i915_blt.c
> @@ -0,0 +1,393 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include <errno.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include "drm.h"
> +#include "igt.h"
> +#include "i915_blt.h"
> +#include "i915/intel_mocs.h"
> +
> +/*
> + * make_block_copy_batch:
> + * @fd: open i915 drm file descriptor
> + * @batch_buf: the batch buffer to populate with the command
> + * @src: handle of the source BO
> + * @dst: handle of the destination BO
> + * @length: size of the src and dest BOs
> + * @reloc: pointer to the relocation entry for this command
> + * @offset_src: source address offset
> + * @offset_dst: destination address offset
> + * @copy_mode: different modes of copy
> + * @enable_compression: flag to enable compression
> + * @return: length of batch buffer created
> + */
> +static int make_block_copy_batch(int fd, uint32_t *batch_buf,
> +				 uint32_t src, uint32_t dst, uint32_t length,
> +				 struct drm_i915_gem_relocation_entry *reloc,
> +				 uint64_t offset_src, uint64_t offset_dst,
> +				 enum copy_mode mode, bool enable_compression)
> +{
> +	uint32_t *b = batch_buf;
> +	uint32_t devid;
> +	uint8_t src_mocs = intel_get_uc_mocs(fd);
> +	uint8_t dst_mocs = src_mocs;
> +	int src_mem_type, dst_mem_type;
> +	int dst_compression, src_compression;
> +	int resolve;
> +
> +	devid = intel_get_drm_devid(fd);
> +
> +	igt_assert(AT_LEAST_GEN(devid, 12));
> +
> +	switch (mode) {
> +	case SYS_TO_SYS: /* copy from smem to smem */
> +		src_mem_type = MEM_TYPE_SYS;
> +		dst_mem_type = MEM_TYPE_SYS;
> +		src_compression = 0;
> +		dst_compression = 0;
> +		resolve = NO_RESOLVE;
> +		break;
> +	case SYS_TO_LOCAL: /* copy from smem to lmem */
> +		src_mem_type = MEM_TYPE_SYS;
> +		dst_mem_type = MEM_TYPE_LOCAL;
> +		src_compression = 0;
> +		dst_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
> +		resolve = NO_RESOLVE;
> +		break;
> +	case LOCAL_TO_SYS: /* copy from lmem to smem */
> +		src_mem_type = MEM_TYPE_LOCAL;
> +		dst_mem_type = MEM_TYPE_SYS;
> +		src_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
> +		dst_compression = 0;
> +		resolve = NO_RESOLVE;
> +		break;
> +	case LOCAL_TO_LOCAL: /* copy from lmem to lmem */
> +		src_mem_type = MEM_TYPE_LOCAL;
> +		dst_mem_type = MEM_TYPE_LOCAL;
> +		src_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
> +		dst_compression = enable_compression ? (COMPRESSION_ENABLE | AUX_CCS_E) : 0;
> +		resolve = (src == dst) ? FULL_RESOLVE : NO_RESOLVE;
> +		break;
> +	}
> +
> +	/* BG 0 */
> +	b[0] = BLOCK_COPY_BLT_CMD | (resolve << 12);
> +
> +	/* BG 1
> +	 *
> +	 * Using Tile 4 dimensions.  Height = 32 rows
> +	 * Width = 128 bytes
> +	 */
> +	b[1] = dst_compression | TILE_4_FORMAT | TILE_4_WIDTH_DWORD |
> +		dst_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
> +
> +	/* BG 3
> +	 *
> +	 * X2 = TILE_4_WIDTH
> +	 * Y2 = (length / TILE_4_WIDTH) << 16:
> +	 */
> +	b[3] = TILE_4_WIDTH | (length >> 7) << DEST_Y2_COORDINATE_SHIFT;
> +
> +	b[4] = offset_dst;
> +	b[5] = offset_dst >> 32;
> +
> +	/* relocate address in b[4] and b[5] */
> +	reloc->offset = 4 * (sizeof(uint32_t));
> +	reloc->delta = 0;
> +	reloc->target_handle = dst;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = I915_GEM_DOMAIN_RENDER;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +
> +	/* BG 6 */
> +	b[6] = dst_mem_type << DEST_MEM_TYPE_SHIFT;
> +
> +	/* BG 8 */
> +	b[8] = src_compression | TILE_4_WIDTH_DWORD | TILE_4_FORMAT |
> +		src_mocs << XY_BLOCK_COPY_BLT_MOCS_SHIFT;
> +
> +	b[9] = offset_src;
> +	b[10] = offset_src >> 32;
> +
> +	/* relocate address in b[9] and b[10] */
> +	reloc->offset = 9 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = src;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +
> +	/* BG 11 */
> +	b[11] = src_mem_type << SRC_MEM_TYPE_SHIFT;
> +
> +	/* BG 16  */
> +	b[16] = SURFACE_TYPE_2D |
> +		((TILE_4_WIDTH - 1) << DEST_SURF_WIDTH_SHIFT) |
> +		(TILE_4_HEIGHT - 1);
> +
> +	/* BG 19 */
> +	b[19] = SURFACE_TYPE_2D |
> +		((TILE_4_WIDTH - 1) << SRC_SURF_WIDTH_SHIFT) |
> +		(TILE_4_HEIGHT - 1);
> +
> +	b += XY_BLOCK_COPY_BLT_LEN_DWORD;
> +
> +	b[0] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
> +	reloc->offset = 23 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = dst_compression > 0 ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +	b[3] = 0;
> +
> +	b[4] = MI_FLUSH_DW | MI_FLUSH_CCS;
> +	reloc->offset = 27 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = dst_compression > 0 ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +	b[7] = 0;
> +
> +	b[8] = MI_BATCH_BUFFER_END;
> +	b[9] = 0;
> +
> +	b += 10;
> +
> +	return (b - batch_buf) * sizeof(uint32_t);
> +}
> +
> +void xy_block_copy_blt(int fd, uint32_t bb_region, uint32_t src, uint32_t dst,
> +		       uint64_t src_size, uint64_t dst_size, uint64_t ahnd,
> +		       uint32_t length, enum copy_mode mode, bool enable_compression,
> +		       uint32_t ctx, struct intel_execution_engine2 *e)


Why are only the static functions here documented, and not the
actually exported lib functions?

This one especially needs to document that the fd is expected to be
for a device of at least gen12, since it unconditionally calls
make_block_copy_batch.


-- 
Petri Latvala


> +{
> +	struct drm_i915_gem_relocation_entry reloc[4];
> +	struct drm_i915_gem_exec_object2 exec[3];
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	int len;
> +	uint32_t cmd, batch_buf[BATCH_SIZE / sizeof(uint32_t)] = {};
> +	uint64_t offset_src, offset_dst, offset_bb, bb_size, ret;
> +
> +	bb_size = BATCH_SIZE;
> +	ret = __gem_create_in_memory_regions(fd, &cmd, &bb_size, bb_region);
> +	igt_assert_eq(ret, 0);
> +
> +	offset_src = get_offset(ahnd, src, src_size, 0);
> +	offset_dst = get_offset(ahnd, dst, dst_size, 0);
> +	offset_bb = get_offset(ahnd, cmd, bb_size, 0);
> +
> +	/* construct the batch buffer */
> +	memset(reloc, 0, sizeof(reloc));
> +	len = make_block_copy_batch(fd, batch_buf, src, dst, length, reloc,
> +				    offset_src, offset_dst, mode,
> +				    enable_compression);
> +
> +	/* write batch buffer to 'cmd' BO */
> +	gem_write(fd, cmd, 0, batch_buf, len);
> +
> +	/* Execute the batch buffer */
> +	memset(exec, 0, sizeof(exec));
> +	exec[0].handle = src;
> +	exec[1].handle = dst;
> +	exec[2].handle = cmd;
> +	exec[2].relocation_count = !ahnd ? 4 : 0;
> +	exec[2].relocs_ptr = to_user_pointer(reloc);
> +	if (ahnd) {
> +		exec[0].offset = offset_src;
> +		exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		exec[1].offset = offset_dst;
> +		exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +				 EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		exec[2].offset = offset_bb;
> +		exec[2].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	}
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(exec);
> +	execbuf.buffer_count = 3;
> +	execbuf.batch_len = len;
> +	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +	if (ctx)
> +		execbuf.rsvd1 = ctx;
> +
> +	gem_execbuf(fd, &execbuf);
> +	gem_close(fd, cmd);
> +	put_offset(ahnd, src);
> +	put_offset(ahnd, dst);
> +	put_offset(ahnd, cmd);
> +}
> +
> +/*
> + * make_ctrl_surf_batch:
> + * @fd: open i915 drm file descriptor
> + * @batch_buf: the batch buffer to populate with the command
> + * @src: handle of the source BO
> + * @dst: handle of the destination BO
> + * @length: size of the ctrl surf in bytes
> + * @reloc: pointer to the relocation entyr for this command
> + * @offset_src: source address offset
> + * @offset_dst: destination address offset
> + * @writetodev: flag to enable direct access of the address
> + * @return: length of batch buffer created
> + */
> +static int make_ctrl_surf_batch(int fd, uint32_t *batch_buf,
> +				uint32_t src, uint32_t dst, uint32_t length,
> +				struct drm_i915_gem_relocation_entry *reloc,
> +				uint64_t offset_src, uint64_t offset_dst,
> +				bool writetodev)
> +{
> +	int num_ccs_blocks, src_mem_access, dst_mem_access;
> +	uint32_t *b = batch_buf;
> +	uint8_t src_mocs = intel_get_uc_mocs(fd);
> +	uint8_t dst_mocs = src_mocs;
> +
> +	num_ccs_blocks = length / CCS_RATIO;
> +	if (num_ccs_blocks < 1)
> +		num_ccs_blocks = 1;
> +	if (num_ccs_blocks > NUM_CCS_BLKS_PER_XFER)
> +		return 0;
> +
> +	if (writetodev) {
> +		src_mem_access = DIRECT_ACCESS;
> +		dst_mem_access = INDIRECT_ACCESS;
> +	} else {
> +		src_mem_access = INDIRECT_ACCESS;
> +		dst_mem_access = DIRECT_ACCESS;
> +	}
> +
> +	/*
> +	 * We use logical AND with 1023 since the size field
> +	 * takes values which is in the range of 0 - 1023
> +	 */
> +	b[0] = ((XY_CTRL_SURF_COPY_BLT) |
> +		(src_mem_access << SRC_ACCESS_TYPE_SHIFT) |
> +		(dst_mem_access << DST_ACCESS_TYPE_SHIFT) |
> +		(((num_ccs_blocks - 1) & 1023) << CCS_SIZE_SHIFT));
> +
> +	b[1] = offset_src;
> +	b[2] = offset_src >> 32 | src_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
> +
> +	/* relocate address in b[1] and b[2] */
> +	reloc->offset = 1 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle = src;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +
> +	b[3] = offset_dst;
> +	b[4] = offset_dst >> 32 | dst_mocs << XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT;
> +
> +	/* relocate address in b[3] and b[4] */
> +	reloc->offset = 3 * (sizeof(uint32_t));
> +	reloc->delta = 0;
> +	reloc->target_handle = dst;
> +	reloc->read_domains = I915_GEM_DOMAIN_RENDER;
> +	reloc->write_domain = I915_GEM_DOMAIN_RENDER;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +
> +	b[5] = 0;
> +
> +	b[6] = MI_FLUSH_DW | MI_FLUSH_LLC | MI_INVALIDATE_TLB;
> +
> +	reloc->offset = 7 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle =
> +	dst_mem_access == INDIRECT_ACCESS ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +	b[9] = 0;
> +
> +	b[10] = MI_FLUSH_DW | MI_FLUSH_CCS;
> +	reloc->offset = 11 * sizeof(uint32_t);
> +	reloc->delta = 0;
> +	reloc->target_handle =
> +	dst_mem_access == INDIRECT_ACCESS ? dst : src;
> +	reloc->read_domains = 0;
> +	reloc->write_domain = 0;
> +	reloc->presumed_offset = 0;
> +	reloc++;
> +	b[13] = 0;
> +
> +	b[14] = MI_BATCH_BUFFER_END;
> +	b[15] = 0;
> +
> +	b += 16;
> +
> +	return (b - batch_buf) * sizeof(uint32_t);
> +}
> +
> +void xy_ctrl_surf_copy_blt(int fd, uint32_t bb_region, uint32_t src,
> +			   uint32_t dst, uint64_t src_size, uint64_t dst_size,
> +			   uint64_t ahnd, uint32_t length, bool writetodev,
> +			   uint32_t ctx, struct intel_execution_engine2 *e)
> +{
> +	struct drm_i915_gem_relocation_entry reloc[4];
> +	struct drm_i915_gem_exec_object2 exec[3];
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	int len;
> +	uint32_t cmd, batch_buf[BATCH_SIZE / sizeof(uint32_t)] = {};
> +	uint64_t offset_src, offset_dst, offset_bb, bb_size, ret;
> +
> +	bb_size = BATCH_SIZE;
> +	ret = __gem_create_in_memory_regions(fd, &cmd, &bb_size, bb_region);
> +	igt_assert_eq(ret, 0);
> +
> +	offset_src = get_offset(ahnd, src, src_size, 0);
> +	offset_dst = get_offset(ahnd, dst, dst_size, 0);
> +	offset_bb = get_offset(ahnd, cmd, bb_size, 0);
> +
> +	/* construct batch command buffer */
> +	memset(reloc, 0, sizeof(reloc));
> +	len = make_ctrl_surf_batch(fd, batch_buf, src, dst, length, reloc,
> +				   offset_src, offset_dst, writetodev);
> +
> +	/* Copy the batch buff to BO cmd */
> +	gem_write(fd, cmd, 0, batch_buf, len);
> +
> +	/* Execute the batch buffer */
> +	memset(exec, 0, sizeof(exec));
> +	exec[0].handle = src;
> +	exec[1].handle = dst;
> +	exec[2].handle = cmd;
> +	exec[2].relocation_count = !ahnd ? 4 : 0;
> +	exec[2].relocs_ptr = to_user_pointer(reloc);
> +	if (ahnd) {
> +		exec[0].offset = offset_src;
> +		exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		exec[1].offset = offset_dst;
> +		exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +				 EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +		exec[2].offset = offset_bb;
> +		exec[2].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	}
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(exec);
> +	execbuf.buffer_count = 3;
> +	execbuf.batch_len = len;
> +	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +	if (ctx)
> +		execbuf.rsvd1 = ctx;
> +
> +	gem_execbuf(fd, &execbuf);
> +	gem_close(fd, cmd);
> +	put_offset(ahnd, src);
> +	put_offset(ahnd, dst);
> +	put_offset(ahnd, cmd);
> +}
> diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
> new file mode 100644
> index 00000000..ff3eee7f
> --- /dev/null
> +++ b/lib/i915/i915_blt.h
> @@ -0,0 +1,72 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include <errno.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include "drm.h"
> +#include "igt.h"
> +
> +#define MI_FLUSH_DW_LEN_DWORD	4
> +#define MI_FLUSH_DW		(0x26 << 23 | 1)
> +#define MI_FLUSH_CCS		BIT(16)
> +#define MI_FLUSH_LLC		BIT(9)
> +#define MI_INVALIDATE_TLB	BIT(18)
> +
> +/* XY_BLOCK_COPY_BLT instruction has 22 bit groups 1 DWORD each */
> +#define XY_BLOCK_COPY_BLT_LEN_DWORD	22
> +#define BLOCK_COPY_BLT_CMD		(2 << 29 | 0x41 << 22 | 0x14)
> +#define COMPRESSION_ENABLE		BIT(29)
> +#define AUX_CCS_E			(5 << 18)
> +#define NO_RESOLVE			0
> +#define FULL_RESOLVE			1
> +#define PARTIAL_RESOLVE			2
> +#define TILE_4_FORMAT			(2 << 30)
> +#define TILE_4_WIDTH			(128)
> +#define TILE_4_WIDTH_DWORD		((128 >> 2) - 1)
> +#define TILE_4_HEIGHT			(32)
> +#define SURFACE_TYPE_2D			BIT(29)
> +
> +#define DEST_Y2_COORDINATE_SHIFT	(16)
> +#define DEST_MEM_TYPE_SHIFT		(31)
> +#define SRC_MEM_TYPE_SHIFT		(31)
> +#define DEST_SURF_WIDTH_SHIFT		(14)
> +#define SRC_SURF_WIDTH_SHIFT		(14)
> +
> +#define XY_CTRL_SURF_COPY_BLT		(2 << 29 | 0x48 << 22 | 3)
> +#define SRC_ACCESS_TYPE_SHIFT		21
> +#define DST_ACCESS_TYPE_SHIFT		20
> +#define CCS_SIZE_SHIFT			8
> +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> +#define MI_ARB_CHECK			MI_INSTR(0x05, 0)
> +#define NUM_CCS_BLKS_PER_XFER		1024
> +#define INDIRECT_ACCESS                 0
> +#define DIRECT_ACCESS                   1
> +
> +#define BATCH_SIZE			4096
> +#define BOSIZE_MIN			(4 * 1024)
> +#define BOSIZE_MAX			(4 * 1024 * 1024)
> +#define CCS_RATIO			256
> +
> +#define MEM_TYPE_SYS			1
> +#define MEM_TYPE_LOCAL			0
> +
> +enum copy_mode {
> +	SYS_TO_SYS = 0,
> +	SYS_TO_LOCAL,
> +	LOCAL_TO_SYS,
> +	LOCAL_TO_LOCAL,
> +};
> +
> +void xy_block_copy_blt(int fd, uint32_t bb_region, uint32_t src, uint32_t dst,
> +		       uint64_t src_size, uint64_t dst_size, uint64_t ahnd,
> +		       uint32_t length, enum copy_mode mode, bool enable_compression,
> +		       uint32_t ctx, struct intel_execution_engine2 *e);
> +
> +void xy_ctrl_surf_copy_blt(int fd, uint32_t bb_region, uint32_t src, uint32_t dst,
> +			   uint64_t src_size, uint64_t dst_size, uint64_t ahnd,
> +			   uint32_t length, bool writetodev, uint32_t ctx,
> +			   struct intel_execution_engine2 *e);
> diff --git a/lib/meson.build b/lib/meson.build
> index f500f0f1..f2924541 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -12,6 +12,7 @@ lib_sources = [
>  	'i915/gem_vm.c',
>  	'i915/intel_memory_region.c',
>  	'i915/intel_mocs.c',
> +	'i915/i915_blt.c',
>  	'igt_collection.c',
>  	'igt_color_encoding.c',
>  	'igt_debugfs.c',
> -- 
> 2.25.1
> 

[igt-dev] [PATCH i-g-t, v5 3/5] lib/intel_chipset.h: Add has_flat_ccs flag

[apoorva1.singh]

From: Apoorva Singh <apoorva1.singh@intel.com>

Add a new platform flag, has_flat_ccs, for platforms
supporting Flat CCS.

Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
Acked-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_chipset.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 2b795527..d2719932 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -40,6 +40,7 @@ struct intel_device_info {
 	unsigned graphics_ver;
 	unsigned display_ver;
 	unsigned gt; /* 0 if unknown */
+	bool has_flat_ccs : 1;
 	bool is_mobile : 1;
 	bool is_whitney : 1;
 	bool is_almador : 1;
@@ -209,4 +210,6 @@ void intel_check_pch(void);
 				   IS_CHERRYVIEW(devid) || \
 				   IS_BROXTON(devid)))
 
+#define HAS_FLAT_CCS(devid)	(intel_get_device_info(devid)->has_flat_ccs)
+
 #endif /* _INTEL_CHIPSET_H */
-- 
2.25.1

[igt-dev] [PATCH i-g-t, v5 4/5] i915/gem_engine_topology: Only use the main copy engines for XY_BLOCK_COPY

[apoorva1.singh]

From: Chris Wilson <chris.p.wilson@intel.com>

XY_BLOCK_COPY blt command is used to transfer the ccs data.
So, we can only run the tests on those engines which have
support for the "block_copy" capability.

Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
---
 lib/i915/gem_engine_topology.c | 38 ++++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  5 +++++
 2 files changed, 43 insertions(+)

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 729f42b0..37b5875e 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -488,6 +488,44 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
 	return ret;
 }
 
+static bool
+__gem_engine_has_capability(int i915, const char *engine,
+			    const char *attr, const char *cap)
+{
+	char buf[4096] = {};
+	FILE *file;
+
+	file = __open_attr(igt_sysfs_open(i915), "r",
+			   "engine", engine, attr, NULL);
+	if (file) {
+		fread(buf, 1, sizeof(buf) - 1, file);
+		fclose(file);
+	}
+
+	return strstr(buf, cap);
+}
+
+bool gem_engine_has_capability(int i915, const char *engine, const char *cap)
+{
+	return __gem_engine_has_capability(i915, engine, "capabilities", cap);
+}
+
+bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap)
+{
+	return __gem_engine_has_capability(i915, engine, "known_capabilities", cap);
+}
+
+bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine)
+{
+	if (engine->class != I915_ENGINE_CLASS_COPY)
+		return false;
+
+	if (!gem_engine_has_known_capability(i915, engine->name, "block_copy"))
+		return intel_gen(intel_get_drm_devid(i915)) >= 12;
+
+	return gem_engine_has_capability(i915, engine->name, "block_copy");
+}
+
 uint32_t gem_engine_mmio_base(int i915, const char *engine)
 {
 	unsigned int mmio = 0;
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index 4cfab560..d24bc9e8 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -124,6 +124,11 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
 
 uint32_t gem_engine_mmio_base(int i915, const char *engine);
 
+bool gem_engine_has_capability(int i915, const char *engine, const char *cap);
+bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap);
+
+bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine);
+
 void dyn_sysfs_engines(int i915, int engines, const char *file,
 		       void (*test)(int i915, int engine));
 
-- 
2.25.1

[igt-dev] [PATCH i-g-t,v5 5/5] i915/gem_ccs: Add testing for CCS

[apoorva1.singh]

From: CQ Tang <cq.tang@intel.com>

Add gem_ccs test for CCS testing.
Commands are constructed with XY_BLOCK_COPY_BLT
and XY_CTRL_SURF_COPY_BLT instructions.

Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
---
 tests/i915/gem_ccs.c | 413 +++++++++++++++++++++++++++++++++++++++++++
 tests/meson.build    |   1 +
 2 files changed, 414 insertions(+)
 create mode 100644 tests/i915/gem_ccs.c

diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
new file mode 100644
index 00000000..2e2b6e3b
--- /dev/null
+++ b/tests/i915/gem_ccs.c
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+#include "i915/gem.h"
+#include "i915/gem_create.h"
+#include "lib/intel_chipset.h"
+#include "i915/i915_blt.h"
+
+IGT_TEST_DESCRIPTION("Exercise the memory bandwidth compression and "
+		     "decompression when copying data between "
+		     "system and local memory");
+
+static void igt_wr_xy_ctrl_surf_copy_blt(int fd, uint32_t region, uint32_t src, uint32_t dst,
+					 uint32_t out, uint64_t src_size, uint64_t dst_size,
+					 uint64_t out_size, uint64_t ahnd, int ccssize,
+					 uint8_t *pattern_buf, uint8_t *read_buf, int bosize,
+					 struct intel_execution_engine2 *e)
+{
+	gem_write(fd, src, 0, pattern_buf, bosize);
+
+	/*
+	 * 'dst' is lmem BO with ccs, directly
+	 * copy content in 'src' BO to 'dst' BO's ccs
+	 */
+	xy_ctrl_surf_copy_blt(fd, region, src, dst, src_size, dst_size,
+			      ahnd, ccssize, true, 0, e);
+
+	memset(read_buf, 0, ccssize);
+	gem_write(fd, out, 0, read_buf, ccssize);
+
+	/* copy 'dst' BO's ccs into 'out' BO */
+	xy_ctrl_surf_copy_blt(fd, region, dst, out, dst_size, out_size,
+			      ahnd, ccssize, false, 0, e);
+
+	gem_read(fd, out, 0, read_buf, ccssize);
+
+	igt_assert_eq(memcmp(read_buf, pattern_buf, ccssize), 0);
+}
+
+static void igt_overwritten_xy_block_copy_blt(int fd, uint32_t region, uint32_t src, uint32_t dst,
+					      uint32_t out, uint64_t src_size, uint64_t dst_size,
+					      uint64_t out_size, uint64_t ahnd, int ccssize,
+					      uint8_t *pattern_buf, uint8_t *read_buf, int bosize,
+					      struct intel_execution_engine2 *e)
+{
+	bool enable_compression = true;
+
+	igt_info("copy random pattern to lmem BO with compression\n");
+
+	gem_write(fd, src, 0, pattern_buf, bosize);
+	gem_write(fd, dst, 0, pattern_buf, bosize);
+
+	/*
+	 * 'dst' is lmem BO with ccs,
+	 * copy content in 'src' BO to 'dst' BO
+	 */
+	xy_block_copy_blt(fd, region, src, dst, src_size, dst_size, ahnd,
+			  bosize, SYS_TO_LOCAL, enable_compression, 0, e);
+
+	memset(read_buf, 0, ccssize);
+	gem_write(fd, out, 0, read_buf, ccssize);
+
+	/* copy 'dst' BO's ccs into 'out' BO */
+	xy_ctrl_surf_copy_blt(fd, region, dst, out, dst_size, out_size,
+			      ahnd, ccssize, false, 0, e);
+
+	gem_read(fd, out, 0, read_buf, ccssize);
+
+	igt_assert_neq(memcmp(read_buf, pattern_buf, ccssize), 0);
+
+	memset(read_buf, 0, bosize);
+	gem_read(fd, dst, 0, read_buf, bosize);
+
+	igt_assert_neq(memcmp(read_buf, pattern_buf, bosize), 0);
+
+	memset(read_buf, 0, bosize);
+	gem_write(fd, out, 0, read_buf, bosize);
+
+	/* copy 'dst' BO into 'out' BO */
+	xy_block_copy_blt(fd, region, dst, out, dst_size, out_size, ahnd,
+			  bosize, LOCAL_TO_SYS, enable_compression, 0, e);
+
+	gem_read(fd, out, 0, read_buf, bosize);
+
+	igt_assert_eq(memcmp(read_buf, pattern_buf, bosize), 0);
+
+	/* decompress 'dst' in place */
+	xy_block_copy_blt(fd, region, dst, dst, dst_size, dst_size, ahnd,
+			  bosize, LOCAL_TO_LOCAL, enable_compression, 0, e);
+
+	memset(read_buf, 0, bosize);
+	gem_read(fd, dst, 0, read_buf, bosize);
+
+	igt_assert_eq(memcmp(read_buf, pattern_buf, bosize), 0);
+
+	memset(read_buf, 0, bosize);
+	gem_write(fd, out, 0, read_buf, bosize);
+
+	/* copy decompressed 'dst' to 'out' */
+	xy_block_copy_blt(fd, region, dst, out, dst_size, out_size, ahnd,
+			  bosize, LOCAL_TO_SYS, enable_compression, 0, e);
+
+	gem_read(fd, out, 0, read_buf, bosize);
+
+	igt_assert_eq(memcmp(read_buf, pattern_buf, bosize), 0);
+}
+
+static void igt_corrupted_xy_ctrl_surf_copy_blt(int fd, uint32_t region, uint32_t src, uint32_t dst,
+						uint32_t out, uint64_t src_size, uint64_t dst_size,
+						uint64_t out_size, uint64_t ahnd, int ccssize,
+						uint8_t *pattern_buf, uint8_t *read_buf, int bosize,
+						struct intel_execution_engine2 *e)
+{
+	bool enable_compression = true;
+
+	gem_write(fd, src, 0, pattern_buf, bosize);
+
+	igt_info("corrupt CCS via XY_CTRL_SURF_COPY_BLT\n");
+
+	/* corrupt 'dst' BO's ccs by writing directly */
+	xy_ctrl_surf_copy_blt(fd, region, src, dst, src_size, dst_size,
+			      ahnd, ccssize, true, 0, e);
+
+	memset(read_buf, 0, bosize);
+	gem_write(fd, out, 0, read_buf, bosize);
+
+	/* copy 'dst' BO into 'out' BO */
+	xy_block_copy_blt(fd, region, dst, out, dst_size, out_size, ahnd,
+			  bosize, LOCAL_TO_SYS, enable_compression, 0, e);
+
+	gem_read(fd, out, 0, read_buf, bosize);
+
+	igt_assert_neq(memcmp(read_buf, pattern_buf, bosize), 0);
+
+	memset(read_buf, 0, ccssize);
+	gem_write(fd, out, 0, read_buf, ccssize);
+
+	/* copy 'dst' BO's ccs into 'out' BO */
+	xy_ctrl_surf_copy_blt(fd, region, dst, out, dst_size, out_size,
+			      ahnd, ccssize, false, 0, e);
+
+	gem_read(fd, out, 0, read_buf, ccssize);
+
+	igt_assert_eq(memcmp(read_buf, pattern_buf, ccssize), 0);
+}
+
+static void igt_copy_zero_pattern_xy_block_copy_blt(int fd, uint32_t region, uint32_t src,
+						    uint32_t dst, uint32_t out, uint64_t src_size,
+						    uint64_t dst_size, uint64_t out_size,
+						    uint64_t ahnd, int ccssize,
+						    uint8_t *pattern_buf, uint8_t *read_buf,
+						    uint8_t *input_buf, int bosize,
+						    struct intel_execution_engine2 *e)
+{
+	bool enable_compression = true;
+
+	igt_info("copy zeros pattern to lmem BO with compression\n");
+
+	gem_write(fd, src, 0, pattern_buf, bosize);
+	gem_write(fd, dst, 0, pattern_buf, bosize);
+	/* set ccs to random pattern */
+	xy_ctrl_surf_copy_blt(fd, region, src, dst, src_size, dst_size,
+			      ahnd, ccssize, true, 0, e);
+
+	memset(input_buf, 0, bosize);
+	gem_write(fd, src, 0, input_buf, bosize);
+
+	/* copy 'src' to 'dst' with compression */
+	xy_block_copy_blt(fd, region, src, dst, src_size, dst_size, ahnd,
+			  bosize, SYS_TO_LOCAL, enable_compression, 0, e);
+
+	gem_write(fd, out, 0, pattern_buf, bosize);
+
+	/* copy 'dst' BO back into 'out' BO */
+	xy_block_copy_blt(fd, region, dst, out, dst_size, out_size, ahnd,
+			  bosize, LOCAL_TO_SYS, enable_compression, 0, e);
+
+	gem_read(fd, out, 0, read_buf, bosize);
+
+	igt_assert_eq(memcmp(read_buf, input_buf, bosize), 0);
+
+	memset(read_buf, 0, bosize);
+	gem_read(fd, dst, 0, read_buf, bosize);
+
+	igt_assert_eq(memcmp(read_buf, pattern_buf, bosize), 0);
+
+	memset(read_buf, 0, ccssize);
+	gem_write(fd, out, 0, read_buf, ccssize);
+
+	/* copy 'dst' BO's ccs into 'out' BO */
+	xy_ctrl_surf_copy_blt(fd, region, dst, out, dst_size, out_size,
+			      ahnd, ccssize, false, 0, e);
+
+	gem_read(fd, out, 0, read_buf, ccssize);
+
+	igt_assert_neq(memcmp(read_buf, pattern_buf, ccssize), 0);
+}
+
+static void igt_copy_repeat_pattern_xy_block_copy_blt(int fd, uint32_t region, uint32_t src,
+						      uint32_t dst, uint32_t out, uint64_t src_size,
+						      uint64_t dst_size, uint64_t out_size,
+						      uint64_t ahnd, int ccssize,
+						      uint8_t *pattern_buf, uint8_t *read_buf,
+						      uint8_t *input_buf, int bosize,
+						      struct intel_execution_engine2 *e)
+{
+	int i;
+	bool enable_compression = true;
+
+	igt_info("copy repeat pattern to lmem BO with compression\n");
+
+	gem_write(fd, src, 0, pattern_buf, bosize);
+	gem_write(fd, src, 0, pattern_buf, ccssize);
+
+	xy_ctrl_surf_copy_blt(fd, region, src, dst, src_size, dst_size,
+			      ahnd, ccssize, true, 0, e);
+	gem_write(fd, dst, 0, pattern_buf, bosize);
+
+	/* generate repeating pattern */
+	input_buf[0] = (uint8_t)rand();
+	input_buf[1] = (uint8_t)rand();
+	input_buf[2] = (uint8_t)rand();
+	input_buf[3] = (uint8_t)rand();
+	for (i = 4; i < bosize; i++)
+		input_buf[i] = input_buf[i - 4];
+	gem_write(fd, src, 0, input_buf, bosize);
+
+	xy_block_copy_blt(fd, region, src, dst, src_size, dst_size, ahnd,
+			  bosize, SYS_TO_LOCAL, enable_compression, 0, e);
+
+	memset(read_buf, 0, bosize);
+	gem_write(fd, out, 0, read_buf, bosize);
+
+	/* copy 'dst' BO back into 'out' BO */
+	xy_block_copy_blt(fd, region, dst, out, dst_size, out_size, ahnd,
+			  bosize, LOCAL_TO_SYS, enable_compression, 0, e);
+
+	gem_read(fd, out, 0, read_buf, bosize);
+
+	igt_assert_eq(memcmp(read_buf, input_buf, bosize), 0);
+
+	memset(read_buf, 0, bosize);
+	gem_read(fd, dst, 0, read_buf, bosize);
+
+	igt_assert_neq(memcmp(read_buf, pattern_buf, bosize), 0);
+
+	memset(read_buf, 0, ccssize);
+	gem_write(fd, out, 0, read_buf, ccssize);
+
+	/* copy 'dst' BO's ccs into 'out' BO */
+	xy_ctrl_surf_copy_blt(fd, region, dst, out, dst_size, out_size,
+			      ahnd, ccssize, false, 0, e);
+
+	gem_read(fd, out, 0, read_buf, ccssize);
+
+	igt_assert_neq(memcmp(read_buf, pattern_buf, ccssize), 0);
+}
+
+/*
+ * Allocate a BO in SMEM.
+ * Fill a pattern
+ * Use XY_BLOCK_COPY_BLT to copy it to LMEM with compression enabled
+ * Clear the BO in SMEM, and the pattern_buf in which the pattern was
+ * stored
+ * Use XY_BLOCK_COPY_BLT to copy it back to the BO in SMEM with
+ * resolve
+ * Compare the value in the BO in SMEM matches the pattern
+ */
+static void test_ccs(int fd, int size, uint32_t region, char *sub_name,
+		     struct intel_execution_engine2 *e)
+{
+	int bosize, ccssize, ret, i;
+	int start, end;
+	uint32_t src, dst, out;
+	uint8_t *pattern_buf, *input_buf, *read_buf;
+	uint64_t ahnd, src_size, dst_size, out_size;
+	struct timeval tv;
+
+	ahnd = get_reloc_ahnd(fd, 0);
+
+	if (size > 0) {
+		start = size;
+		end = start + 1;
+	} else {
+		start = BOSIZE_MIN;
+		end = BOSIZE_MAX;
+	}
+
+	for (bosize = start; bosize < end; bosize *= 2) {
+		/* allocate working buffers */
+		pattern_buf = malloc(bosize);
+		igt_assert(pattern_buf);
+		input_buf = malloc(bosize);
+		igt_assert(input_buf);
+		read_buf = malloc(bosize);
+		igt_assert(read_buf);
+
+		ccssize = bosize / CCS_RATIO;
+		src_size = dst_size = out_size = bosize;
+
+		/* allocate working BOs in the right location */
+		ret = __gem_create_in_memory_regions(fd, &src, &src_size,
+						     INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
+		igt_assert_eq(ret, 0);
+
+		ret = __gem_create_in_memory_regions(fd, &dst, &dst_size, region);
+		igt_assert_eq(ret, 0);
+
+		ret = __gem_create_in_memory_regions(fd, &out, &out_size,
+						     INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
+		igt_assert_eq(ret, 0);
+
+		/* fill in random pattern */
+		ret = gettimeofday(&tv, NULL);
+		igt_assert(!ret);
+		srandom((int)tv.tv_usec);
+
+		for (i = 0; i < bosize; i++)
+			pattern_buf[i] = (uint8_t)rand();
+
+		igt_info("progress: bosize %d, ccssize %d\n", bosize, ccssize);
+
+		igt_dynamic_f("write_read_in_ccs_surface-%s-%s", sub_name, e->name)
+			igt_wr_xy_ctrl_surf_copy_blt(fd, region, src, dst, out, src_size, dst_size,
+						     out_size, ahnd, ccssize, pattern_buf, read_buf,
+						     bosize, e);
+		igt_dynamic_f("verify_compression_of_random_data-%s-%s", sub_name, e->name)
+			igt_overwritten_xy_block_copy_blt(fd, region, src, dst, out, src_size,
+							  dst_size, out_size, ahnd, ccssize,
+							  pattern_buf, read_buf, bosize, e);
+		igt_dynamic_f("verify_corrupted_pattern_in_ccs_surface-%s-%s", sub_name, e->name)
+			igt_corrupted_xy_ctrl_surf_copy_blt(fd, region, src, dst, out, src_size,
+							    dst_size, out_size, ahnd, ccssize,
+							    pattern_buf, read_buf, bosize, e);
+		igt_dynamic_f("copy_zero_pattern_with_compression-%s-%s", sub_name, e->name)
+			igt_copy_zero_pattern_xy_block_copy_blt(fd, region, src, dst, out, src_size,
+								dst_size, out_size, ahnd, ccssize,
+								pattern_buf, read_buf, input_buf,
+								bosize, e);
+		igt_dynamic_f("copy_repeat_pattern_with_compression-%s-%s", sub_name, e->name)
+			igt_copy_repeat_pattern_xy_block_copy_blt(fd, region, src, dst, out,
+								  src_size, dst_size, out_size,
+								  ahnd, ccssize, pattern_buf,
+								  read_buf, input_buf, bosize, e);
+
+		gem_close(fd, out);
+		gem_close(fd, dst);
+		gem_close(fd, src);
+		free(read_buf);
+		free(input_buf);
+		free(pattern_buf);
+	}
+
+	put_ahnd(ahnd);
+}
+
+static void subtest_ccs(int drm_fd, struct igt_collection *set, const char *subtest, int size)
+{
+	struct intel_execution_engine2 *e;
+	struct igt_collection *regions;
+	char *sub_name;
+	uint32_t region;
+
+	igt_subtest_with_dynamic(subtest) {
+		for_each_physical_engine(drm_fd, e) {
+			if (!gem_engine_can_block_copy(drm_fd, e))
+				continue;
+
+			for_each_combination(regions, 1, set) {
+				sub_name = memregion_dynamic_subtest_name(regions);
+				region = igt_collection_get_value(regions, 0);
+				test_ccs(drm_fd, size, region, sub_name, e);
+				free(sub_name);
+			}
+		}
+	}
+}
+
+igt_main
+{
+	struct drm_i915_query_memory_regions *query_info;
+	struct igt_collection *set;
+	int drm_fd;
+
+	igt_fixture {
+		drm_fd = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(drm_fd);
+		igt_require(AT_LEAST_GEN(intel_get_drm_devid(drm_fd), 12) > 0);
+		igt_require(HAS_FLAT_CCS(intel_get_drm_devid(drm_fd)));
+
+		query_info = gem_get_query_memory_regions(drm_fd);
+		igt_require(query_info);
+
+		set = get_memory_region_set(query_info, I915_DEVICE_MEMORY);
+	}
+
+	subtest_ccs(drm_fd, set, "basic-gem-ccs-4K", 4 * 1024);
+	subtest_ccs(drm_fd, set, "basic-gem-ccs-64K", 64 * 1024);
+	subtest_ccs(drm_fd, set, "basic-gem-ccs-1M", 1024 * 1024);
+	subtest_ccs(drm_fd, set, "basic-gem-ccs-all", 0);
+
+	igt_fixture {
+		close(drm_fd);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index c14acf99..e0b48d66 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -107,6 +107,7 @@ i915_progs = [
 	'gem_blits',
 	'gem_busy',
 	'gem_caching',
+	'gem_ccs',
 	'gem_close',
 	'gem_close_race',
 	'gem_concurrent_blit',
-- 
2.25.1

[igt-dev] ✓ Fi.CI.BAT: success for Add testing for CCS (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5692 bytes --]

== Series Details ==

Series: Add testing for CCS (rev5)
URL   : https://patchwork.freedesktop.org/series/96648/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11014 -> IGTPW_6505
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/index.html

Participating hosts (41 -> 36)
------------------------------

  Additional (2): fi-bxt-dsi fi-bdw-5557u 
  Missing    (7): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-jsl-2 fi-bsw-nick fi-bdw-samus 

Known issues
------------

  Here are the changes found in IGTPW_6505 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-skl-6600u:       [PASS][1] -> [INCOMPLETE][2] ([i915#4547])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-bxt-dsi/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-bxt-dsi/igt@gem_lmem_swapping@verify-random.html

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [PASS][5] -> [INCOMPLETE][6] ([i915#3921])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-bxt-dsi/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][8] ([fdo#109271]) +30 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-bxt-dsi/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-bxt-dsi/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
    - fi-skl-6600u:       NOTRUN -> [FAIL][10] ([i915#4312])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-skl-6600u/igt@runner@aborted.html
    - fi-bdw-5557u:       NOTRUN -> [FAIL][11] ([i915#2426] / [i915#4312])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-bdw-5557u/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gem_contexts:
    - {fi-tgl-dsi}:       [INCOMPLETE][12] ([i915#402]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@hugepages:
    - {fi-tgl-dsi}:       [INCOMPLETE][14] -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/fi-tgl-dsi/igt@i915_selftest@live@hugepages.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-tgl-dsi/igt@i915_selftest@live@hugepages.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cml-u2:          [DMESG-WARN][16] ([i915#4269]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6313 -> IGTPW_6505

  CI-20190529: 20190529
  CI_DRM_11014: c4f095f24fcdc6e85ae112052b3034328e24ae66 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6505: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/index.html
  IGT_6313: 1793ed798cc09966c27bf478781e0c1d6bb23bad @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@gem_ccs@basic-gem-ccs-1m
+igt@gem_ccs@basic-gem-ccs-4k
+igt@gem_ccs@basic-gem-ccs-64k
+igt@gem_ccs@basic-gem-ccs-all

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/index.html

[-- Attachment #2: Type: text/html, Size: 6814 bytes --]

[igt-dev] ✓ Fi.CI.IGT: success for Add testing for CCS (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30244 bytes --]

== Series Details ==

Series: Add testing for CCS (rev5)
URL   : https://patchwork.freedesktop.org/series/96648/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11014_full -> IGTPW_6505_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/index.html

Participating hosts (10 -> 7)
------------------------------

  Missing    (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6505_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@gem_ccs@basic-gem-ccs-4k} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][1] +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb3/igt@gem_ccs@basic-gem-ccs-4k.html

  * {igt@gem_ccs@basic-gem-ccs-all} (NEW):
    - shard-tglb:         NOTRUN -> [SKIP][2] +3 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb2/igt@gem_ccs@basic-gem-ccs-all.html

  
New tests
---------

  New tests have been introduced between CI_DRM_11014_full and IGTPW_6505_full:

### New IGT tests (4) ###

  * igt@gem_ccs@basic-gem-ccs-1m:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ccs@basic-gem-ccs-4k:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ccs@basic-gem-ccs-64k:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ccs@basic-gem-ccs-all:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_6505_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         NOTRUN -> [SKIP][3] ([i915#658])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb7/igt@feature_discovery@psr2.html

  * igt@gem_create@create-massive:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][4] ([i915#3002])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl7/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
    - shard-snb:          NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-snb6/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [PASS][6] -> [TIMEOUT][7] ([i915#3063] / [i915#3648])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-tglb2/igt@gem_eio@unwedge-stress.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb8/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         NOTRUN -> [FAIL][8] ([i915#2842]) +3 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
    - shard-glk:          NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
    - shard-tglb:         NOTRUN -> [FAIL][10] ([i915#2842]) +1 similar issue
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb6/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-apl:          [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [PASS][13] -> [FAIL][14] ([i915#2849])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-kbl3/igt@gem_exec_suspend@basic-s3.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl6/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_exec_whisper@basic-queues-forked:
    - shard-iclb:         NOTRUN -> [INCOMPLETE][17] ([i915#1895])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb7/igt@gem_exec_whisper@basic-queues-forked.html

  * igt@gem_huc_copy@huc-copy:
    - shard-apl:          NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl6/igt@gem_huc_copy@huc-copy.html
    - shard-kbl:          NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl7/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-kbl:          NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +1 similar issue
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl4/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-kbl:          NOTRUN -> [WARN][21] ([i915#2658])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl3/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@create-protected-buffer:
    - shard-tglb:         NOTRUN -> [SKIP][22] ([i915#4270])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb3/igt@gem_pxp@create-protected-buffer.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-iclb:         NOTRUN -> [SKIP][23] ([i915#4270]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb8/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
    - shard-kbl:          NOTRUN -> [SKIP][24] ([fdo#109271]) +306 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl6/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html

  * igt@gem_render_copy@y-tiled-to-vebox-linear:
    - shard-iclb:         NOTRUN -> [SKIP][25] ([i915#768]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb6/igt@gem_render_copy@y-tiled-to-vebox-linear.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-kbl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3323])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl6/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@readonly-pwrite-unsync:
    - shard-iclb:         NOTRUN -> [SKIP][27] ([i915#3297])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb4/igt@gem_userptr_blits@readonly-pwrite-unsync.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-tglb:         NOTRUN -> [SKIP][28] ([i915#2856])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb8/igt@gen9_exec_parse@shadow-peek.html
    - shard-iclb:         NOTRUN -> [SKIP][29] ([i915#2856])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb8/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [PASS][30] -> [SKIP][31] ([i915#4281])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-iclb7/igt@i915_pm_dc@dc9-dpms.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-tglb:         NOTRUN -> [SKIP][32] ([fdo#111644] / [i915#1397] / [i915#2411])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb2/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
    - shard-iclb:         NOTRUN -> [SKIP][33] ([fdo#110892])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb4/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([i915#4387])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb2/igt@i915_pm_sseu@full-enable.html
    - shard-iclb:         NOTRUN -> [SKIP][35] ([i915#4387])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb4/igt@i915_pm_sseu@full-enable.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [PASS][36] -> [DMESG-WARN][37] ([i915#180]) +4 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][38] ([fdo#110725] / [fdo#111614]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb1/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3777]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#111614])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb3/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-iclb:         NOTRUN -> [SKIP][41] ([fdo#110723])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb5/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-tglb:         NOTRUN -> [SKIP][42] ([fdo#111615])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-apl:          NOTRUN -> [SKIP][43] ([fdo#109271]) +122 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_joiner@2x-modeset:
    - shard-iclb:         NOTRUN -> [SKIP][44] ([i915#2705])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb5/igt@kms_big_joiner@2x-modeset.html
    - shard-tglb:         NOTRUN -> [SKIP][45] ([i915#2705])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb6/igt@kms_big_joiner@2x-modeset.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][46] ([fdo#109278] / [i915#3886]) +2 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb3/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk8/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
    - shard-tglb:         NOTRUN -> [SKIP][48] ([i915#3689] / [i915#3886]) +1 similar issue
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb6/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
    - shard-apl:          NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +3 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl8/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3886]) +14 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl4/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][51] ([i915#3689]) +3 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb5/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs:
    - shard-snb:          NOTRUN -> [SKIP][52] ([fdo#109271]) +98 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-snb7/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs.html

  * igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][53] ([fdo#111615] / [i915#3689])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb3/igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs.html

  * igt@kms_chamelium@dp-crc-multiple:
    - shard-apl:          NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl8/igt@kms_chamelium@dp-crc-multiple.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - shard-iclb:         NOTRUN -> [SKIP][55] ([fdo#109284] / [fdo#111827]) +8 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb1/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-crc-multiple:
    - shard-snb:          NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-snb7/igt@kms_chamelium@hdmi-crc-multiple.html

  * igt@kms_color@pipe-d-ctm-max:
    - shard-iclb:         NOTRUN -> [SKIP][57] ([fdo#109278] / [i915#1149])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb3/igt@kms_color@pipe-d-ctm-max.html

  * igt@kms_color_chamelium@pipe-a-degamma:
    - shard-kbl:          NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +30 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl7/igt@kms_color_chamelium@pipe-a-degamma.html

  * igt@kms_color_chamelium@pipe-d-ctm-max:
    - shard-tglb:         NOTRUN -> [SKIP][59] ([fdo#109284] / [fdo#111827]) +4 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb1/igt@kms_color_chamelium@pipe-d-ctm-max.html
    - shard-glk:          NOTRUN -> [SKIP][60] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk9/igt@kms_color_chamelium@pipe-d-ctm-max.html
    - shard-iclb:         NOTRUN -> [SKIP][61] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb5/igt@kms_color_chamelium@pipe-d-ctm-max.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-kbl:          NOTRUN -> [TIMEOUT][62] ([i915#1319])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl6/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-iclb:         NOTRUN -> [SKIP][63] ([i915#3116])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb6/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@srm:
    - shard-glk:          NOTRUN -> [SKIP][64] ([fdo#109271]) +49 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk3/igt@kms_content_protection@srm.html
    - shard-tglb:         NOTRUN -> [SKIP][65] ([fdo#111828])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb5/igt@kms_content_protection@srm.html
    - shard-iclb:         NOTRUN -> [SKIP][66] ([fdo#109300] / [fdo#111066])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb8/igt@kms_content_protection@srm.html
    - shard-apl:          NOTRUN -> [TIMEOUT][67] ([i915#1319])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl1/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@uevent:
    - shard-kbl:          NOTRUN -> [FAIL][68] ([i915#2105])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl4/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen:
    - shard-iclb:         NOTRUN -> [SKIP][69] ([fdo#109278] / [fdo#109279])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb4/igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][70] ([i915#3359]) +2 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb1/igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          NOTRUN -> [INCOMPLETE][71] ([i915#3614])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
    - shard-apl:          NOTRUN -> [DMESG-WARN][72] ([i915#180])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_edge_walk@pipe-d-256x256-left-edge:
    - shard-iclb:         NOTRUN -> [SKIP][73] ([fdo#109278]) +22 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb8/igt@kms_cursor_edge_walk@pipe-d-256x256-left-edge.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-iclb:         NOTRUN -> [SKIP][74] ([fdo#109274] / [fdo#109278]) +5 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb3/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_dsc@xrgb8888-dsc-compression:
    - shard-tglb:         NOTRUN -> [SKIP][75] ([i915#3828])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb6/igt@kms_dsc@xrgb8888-dsc-compression.html
    - shard-iclb:         NOTRUN -> [SKIP][76] ([i915#3828])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb7/igt@kms_dsc@xrgb8888-dsc-compression.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [PASS][77] -> [INCOMPLETE][78] ([i915#180] / [i915#1982])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-iclb:         NOTRUN -> [SKIP][79] ([fdo#109274]) +6 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-apl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2672])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
    - shard-iclb:         NOTRUN -> [SKIP][81] ([i915#2587])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
    - shard-iclb:         [PASS][82] -> [SKIP][83] ([i915#3701])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
    - shard-iclb:         NOTRUN -> [SKIP][84] ([fdo#109280]) +19 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-tglb:         NOTRUN -> [SKIP][85] ([fdo#111825]) +18 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#533])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl6/igt@kms_pipe_crc_basic@read-crc-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#533]) +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-apl:          NOTRUN -> [FAIL][88] ([fdo#108145] / [i915#265])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-glk:          NOTRUN -> [FAIL][89] ([fdo#108145] / [i915#265]) +1 similar issue
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-kbl:          NOTRUN -> [FAIL][90] ([fdo#108145] / [i915#265]) +3 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_plane_lowres@pipe-c-tiling-none:
    - shard-iclb:         NOTRUN -> [SKIP][91] ([i915#3536]) +2 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb1/igt@kms_plane_lowres@pipe-c-tiling-none.html

  * igt@kms_plane_lowres@pipe-c-tiling-x:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([i915#3536])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb5/igt@kms_plane_lowres@pipe-c-tiling-x.html

  * igt@kms_plane_multiple@atomic-pipe-d-tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][93] ([fdo#111615] / [fdo#112054]) +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb6/igt@kms_plane_multiple@atomic-pipe-d-tiling-yf.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area:
    - shard-iclb:         NOTRUN -> [SKIP][94] ([fdo#111068] / [i915#658]) +1 similar issue
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb6/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
    - shard-apl:          NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#658]) +1 similar issue
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl4/igt@kms_psr2_sf@plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-tglb:         NOTRUN -> [SKIP][96] ([i915#1911])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb3/igt@kms_psr2_su@page_flip-p010.html
    - shard-glk:          NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#658])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk3/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-kbl:          NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#658]) +2 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl4/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-tglb:         NOTRUN -> [FAIL][99] ([i915#132] / [i915#3467])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb3/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [PASS][100] -> [SKIP][101] ([fdo#109441]) +1 similar issue
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb5/igt@kms_psr@psr2_primary_mmap_gtt.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         NOTRUN -> [SKIP][102] ([fdo#109441]) +1 similar issue
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][103] -> [FAIL][104] ([i915#31])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl4/igt@kms_setmode@basic.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl2/igt@kms_setmode@basic.html
    - shard-glk:          [PASS][105] -> [FAIL][106] ([i915#31])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-glk7/igt@kms_setmode@basic.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk9/igt@kms_setmode@basic.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#2437]) +1 similar issue
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl8/igt@kms_writeback@writeback-check-output.html
    - shard-iclb:         NOTRUN -> [SKIP][108] ([i915#2437]) +1 similar issue
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb8/igt@kms_writeback@writeback-check-output.html
    - shard-tglb:         NOTRUN -> [SKIP][109] ([i915#2437])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb7/igt@kms_writeback@writeback-check-output.html
    - shard-glk:          NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#2437])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk1/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-kbl:          NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2437]) +1 similar issue
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl3/igt@kms_writeback@writeback-fb-id.html

  * igt@perf@gen12-mi-rpc:
    - shard-iclb:         NOTRUN -> [SKIP][112] ([fdo#109289])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb8/igt@perf@gen12-mi-rpc.html

  * igt@prime_nv_api@i915_nv_import_twice:
    - shard-iclb:         NOTRUN -> [SKIP][113] ([fdo#109291]) +1 similar issue
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb7/igt@prime_nv_api@i915_nv_import_twice.html

  * igt@prime_nv_pcopy@test2:
    - shard-tglb:         NOTRUN -> [SKIP][114] ([fdo#109291])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb2/igt@prime_nv_pcopy@test2.html

  * igt@prime_vgem@fence-read-hang:
    - shard-iclb:         NOTRUN -> [SKIP][115] ([fdo#109295])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb2/igt@prime_vgem@fence-read-hang.html

  * igt@sysfs_clients@fair-0:
    - shard-tglb:         NOTRUN -> [SKIP][116] ([i915#2994]) +1 similar issue
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-tglb7/igt@sysfs_clients@fair-0.html
    - shard-glk:          NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#2994]) +1 similar issue
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk5/igt@sysfs_clients@fair-0.html

  * igt@sysfs_clients@fair-7:
    - shard-apl:          NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#2994]) +1 similar issue
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl4/igt@sysfs_clients@fair-7.html
    - shard-iclb:         NOTRUN -> [SKIP][119] ([i915#2994]) +1 similar issue
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb5/igt@sysfs_clients@fair-7.html
    - shard-kbl:          NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#2994]) +3 similar issues
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl7/igt@sysfs_clients@fair-7.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-kbl:          [DMESG-WARN][121] ([i915#180]) -> [PASS][122] +8 similar issues
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          [FAIL][123] ([i915#2846]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-kbl4/igt@gem_exec_fair@basic-deadline.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][125] ([i915#454]) -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-iclb7/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-apl:          [SKIP][127] ([fdo#109271]) -> [PASS][128]
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-apl2/igt@i915_pm_dc@dc9-dpms.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-apl6/igt@i915_pm_dc@dc9-dpms.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
    - shard-glk:          [DMESG-WARN][129] ([i915#118]) -> [PASS][130]
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-glk7/igt@kms_big_fb@linear-32bpp-rotate-180.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk9/igt@kms_big_fb@linear-32bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
    - shard-glk:          [FAIL][131] ([i915#1888] / [i915#3653]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-glk2/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk2/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-180:
    - shard-glk:          [DMESG-FAIL][133] ([i915#118] / [i915#1888]) -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11014/shard-glk2/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/shard-glk5/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6505/index.html

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