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From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
	<libvir-list@redhat.com>, <anup.patel@wdc.com>,
	<palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
	<bin.meng@windriver.com>, <fanliang@huawei.com>,
	<wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>,
	<wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>,
	Mingwang Li <limingwang@huawei.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v3 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
Date: Mon, 20 Dec 2021 21:09:09 +0800	[thread overview]
Message-ID: <20211220130919.413-3-jiangyifei@huawei.com> (raw)
In-Reply-To: <20211220130919.413-1-jiangyifei@huawei.com>

Add target/riscv/kvm.c to place kvm_arch_* function needed by
kvm/kvm-all.c. Meanwhile, add kvm support in meson.build file.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
 meson.build              |   2 +
 target/riscv/kvm.c       | 133 +++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |   1 +
 3 files changed, 136 insertions(+)
 create mode 100644 target/riscv/kvm.c

diff --git a/meson.build b/meson.build
index 2495360fd0..e74633b42c 100644
--- a/meson.build
+++ b/meson.build
@@ -85,6 +85,8 @@ elif cpu in ['ppc', 'ppc64']
   kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
 elif cpu in ['mips', 'mips64']
   kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
+elif cpu in ['riscv']
+  kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
 else
   kvm_targets = []
 endif
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
new file mode 100644
index 0000000000..687dd4b621
--- /dev/null
+++ b/target/riscv/kvm.c
@@ -0,0 +1,133 @@
+/*
+ * RISC-V implementation of KVM hooks
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include <sys/ioctl.h>
+
+#include <linux/kvm.h>
+
+#include "qemu-common.h"
+#include "qemu/timer.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "sysemu/kvm_int.h"
+#include "cpu.h"
+#include "trace.h"
+#include "hw/pci/pci.h"
+#include "exec/memattrs.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "qemu/log.h"
+#include "hw/loader.h"
+
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+    KVM_CAP_LAST_INFO
+};
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+    return 0;
+}
+
+int kvm_arch_release_virq_post(int virq)
+{
+    return 0;
+}
+
+int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
+                             uint64_t address, uint32_t data, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_destroy_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+unsigned long kvm_arch_vcpu_id(CPUState *cpu)
+{
+    return cpu->cpu_index;
+}
+
+void kvm_arch_init_irq_routing(KVMState *s)
+{
+}
+
+int kvm_arch_init_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_msi_data_to_gsi(uint32_t data)
+{
+    abort();
+}
+
+int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
+                                int vector, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_init(MachineState *ms, KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_irqchip_create(KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+    return 0;
+}
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+}
+
+MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
+{
+    return MEMTXATTRS_UNSPECIFIED;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *cs)
+{
+    return true;
+}
+
+int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+{
+    return 0;
+}
+
+bool kvm_arch_cpu_check_are_resettable(void)
+{
+    return true;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index d5e0bc93ea..2faf08a941 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -19,6 +19,7 @@ riscv_ss.add(files(
   'bitmanip_helper.c',
   'translate.c',
 ))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
 riscv_softmmu_ss = ss.source_set()
 riscv_softmmu_ss.add(files(
-- 
2.19.1


WARNING: multiple messages have this Message-ID (diff)
From: Yifei Jiang via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
	<libvir-list@redhat.com>, <anup.patel@wdc.com>,
	<palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
	<bin.meng@windriver.com>, <fanliang@huawei.com>,
	<wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>,
	<wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>,
	Mingwang Li <limingwang@huawei.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v3 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
Date: Mon, 20 Dec 2021 21:09:09 +0800	[thread overview]
Message-ID: <20211220130919.413-3-jiangyifei@huawei.com> (raw)
In-Reply-To: <20211220130919.413-1-jiangyifei@huawei.com>

Add target/riscv/kvm.c to place kvm_arch_* function needed by
kvm/kvm-all.c. Meanwhile, add kvm support in meson.build file.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
 meson.build              |   2 +
 target/riscv/kvm.c       | 133 +++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |   1 +
 3 files changed, 136 insertions(+)
 create mode 100644 target/riscv/kvm.c

diff --git a/meson.build b/meson.build
index 2495360fd0..e74633b42c 100644
--- a/meson.build
+++ b/meson.build
@@ -85,6 +85,8 @@ elif cpu in ['ppc', 'ppc64']
   kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
 elif cpu in ['mips', 'mips64']
   kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
+elif cpu in ['riscv']
+  kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
 else
   kvm_targets = []
 endif
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
new file mode 100644
index 0000000000..687dd4b621
--- /dev/null
+++ b/target/riscv/kvm.c
@@ -0,0 +1,133 @@
+/*
+ * RISC-V implementation of KVM hooks
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include <sys/ioctl.h>
+
+#include <linux/kvm.h>
+
+#include "qemu-common.h"
+#include "qemu/timer.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "sysemu/kvm_int.h"
+#include "cpu.h"
+#include "trace.h"
+#include "hw/pci/pci.h"
+#include "exec/memattrs.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "qemu/log.h"
+#include "hw/loader.h"
+
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+    KVM_CAP_LAST_INFO
+};
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+    return 0;
+}
+
+int kvm_arch_release_virq_post(int virq)
+{
+    return 0;
+}
+
+int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
+                             uint64_t address, uint32_t data, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_destroy_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+unsigned long kvm_arch_vcpu_id(CPUState *cpu)
+{
+    return cpu->cpu_index;
+}
+
+void kvm_arch_init_irq_routing(KVMState *s)
+{
+}
+
+int kvm_arch_init_vcpu(CPUState *cs)
+{
+    return 0;
+}
+
+int kvm_arch_msi_data_to_gsi(uint32_t data)
+{
+    abort();
+}
+
+int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
+                                int vector, PCIDevice *dev)
+{
+    return 0;
+}
+
+int kvm_arch_init(MachineState *ms, KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_irqchip_create(KVMState *s)
+{
+    return 0;
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+    return 0;
+}
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+}
+
+MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
+{
+    return MEMTXATTRS_UNSPECIFIED;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *cs)
+{
+    return true;
+}
+
+int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+{
+    return 0;
+}
+
+bool kvm_arch_cpu_check_are_resettable(void)
+{
+    return true;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index d5e0bc93ea..2faf08a941 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -19,6 +19,7 @@ riscv_ss.add(files(
   'bitmanip_helper.c',
   'translate.c',
 ))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
 riscv_softmmu_ss = ss.source_set()
 riscv_softmmu_ss.add(files(
-- 
2.19.1



  parent reply	other threads:[~2021-12-20 13:09 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-20 13:09 [PATCH v3 00/12] Add riscv kvm accel support Yifei Jiang
2021-12-20 13:09 ` Yifei Jiang via
2021-12-20 13:09 ` [PATCH v3 01/12] update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang
2021-12-20 13:09   ` Yifei Jiang via
2021-12-20 13:09 ` Yifei Jiang [this message]
2021-12-20 13:09   ` [PATCH v3 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang via
2021-12-20 13:09 ` [PATCH v3 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2021-12-20 13:09   ` Yifei Jiang via
2021-12-20 13:09 ` [PATCH v3 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2021-12-20 13:09   ` Yifei Jiang via
2021-12-20 13:09 ` [PATCH v3 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2021-12-20 13:09   ` Yifei Jiang via
2021-12-20 13:09 ` [PATCH v3 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
2021-12-20 13:09   ` Yifei Jiang via
2021-12-23  6:03   ` Anup Patel
2021-12-23  6:03     ` Anup Patel
2021-12-23  6:04     ` Anup Patel
2021-12-23  6:04       ` Anup Patel
2022-01-10  1:28       ` Jiangyifei
2022-01-10  1:28         ` Jiangyifei via
2021-12-20 13:09 ` [PATCH v3 07/12] target/riscv: Support setting external interrupt " Yifei Jiang
2021-12-20 13:09   ` Yifei Jiang via
2021-12-23  6:05   ` Anup Patel
2021-12-23  6:05     ` Anup Patel
2021-12-20 13:09 ` [PATCH v3 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2021-12-20 13:09   ` Yifei Jiang via
2022-01-05 22:03   ` Alistair Francis
2022-01-05 22:03     ` Alistair Francis
2022-01-10  1:33     ` Jiangyifei
2022-01-10  1:33       ` Jiangyifei via
2021-12-20 13:09 ` [PATCH v3 09/12] target/riscv: Add host cpu type Yifei Jiang
2021-12-20 13:09   ` Yifei Jiang via
2021-12-20 13:09 ` [PATCH v3 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2021-12-20 13:09   ` Yifei Jiang via
2021-12-23  6:06   ` Anup Patel
2021-12-23  6:06     ` Anup Patel
2021-12-20 13:09 ` [PATCH v3 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2021-12-20 13:09   ` Yifei Jiang via
2022-01-05 22:04   ` Alistair Francis
2022-01-05 22:04     ` Alistair Francis
2021-12-20 13:09 ` [PATCH v3 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang
2021-12-20 13:09   ` Yifei Jiang via
2022-01-05 22:10   ` Alistair Francis
2022-01-05 22:10     ` Alistair Francis

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