From: Lukasz Maniak <lukasz.maniak@linux.intel.com>
To: qemu-devel@nongnu.org
Cc: "Klaus Jensen" <its@irrelevant.dk>,
"Keith Busch" <kbusch@kernel.org>,
"Lukasz Maniak" <lukasz.maniak@linux.intel.com>,
qemu-block@nongnu.org,
"Łukasz Gieryk" <lukasz.gieryk@linux.intel.com>
Subject: [PATCH v3 10/15] hw/nvme: Remove reg_size variable and update BAR0 size calculation
Date: Tue, 21 Dec 2021 15:32:41 +0100 [thread overview]
Message-ID: <20211221143246.2052050-11-lukasz.maniak@linux.intel.com> (raw)
In-Reply-To: <20211221143246.2052050-1-lukasz.maniak@linux.intel.com>
From: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
The n->reg_size parameter unnecessarily splits the BAR0 size calculation
in two phases; removed to simplify the code.
With all the calculations done in one place, it seems the pow2ceil,
applied originally to reg_size, is unnecessary. The rounding should
happen as the last step, when BAR size includes Nvme registers, queue
registers, and MSIX-related space.
Finally, the size of the mmio memory region is extended to cover the 1st
4KiB padding (see the map below). Access to this range is handled as
interaction with a non-existing queue and generates an error trace, so
actually nothing changes, while the reg_size variable is no longer needed.
--------------------
| BAR0 |
--------------------
[Nvme Registers ]
[Queues ]
[power-of-2 padding] - removed in this patch
[4KiB padding (1) ]
[MSIX TABLE ]
[4KiB padding (2) ]
[MSIX PBA ]
[power-of-2 padding]
Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
---
hw/nvme/ctrl.c | 10 +++++-----
hw/nvme/nvme.h | 1 -
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index de463450b6..a4b11b201a 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -6370,9 +6370,6 @@ static void nvme_init_state(NvmeCtrl *n)
n->conf_ioqpairs = n->params.max_ioqpairs;
n->conf_msix_qsize = n->params.msix_qsize;
- /* add one to max_ioqpairs to account for the admin queue pair */
- n->reg_size = pow2ceil(sizeof(NvmeBar) +
- 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE);
n->sq = g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1);
n->cq = g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1);
n->temperature = NVME_TEMPERATURE;
@@ -6496,7 +6493,10 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
pcie_ari_init(pci_dev, 0x100, 1);
}
- bar_size = QEMU_ALIGN_UP(n->reg_size, 4 * KiB);
+ /* add one to max_ioqpairs to account for the admin queue pair */
+ bar_size = sizeof(NvmeBar) +
+ 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE;
+ bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
msix_table_offset = bar_size;
msix_table_size = PCI_MSIX_ENTRY_SIZE * n->params.msix_qsize;
@@ -6510,7 +6510,7 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size);
memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
- n->reg_size);
+ msix_table_offset);
memory_region_add_subregion(&n->bar0, 0, &n->iomem);
if (pci_is_vf(pci_dev)) {
diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h
index 927890b490..1401ac3904 100644
--- a/hw/nvme/nvme.h
+++ b/hw/nvme/nvme.h
@@ -414,7 +414,6 @@ typedef struct NvmeCtrl {
uint16_t max_prp_ents;
uint16_t cqe_size;
uint16_t sqe_size;
- uint32_t reg_size;
uint32_t max_q_ents;
uint8_t outstanding_aers;
uint32_t irq_status;
--
2.25.1
next prev parent reply other threads:[~2021-12-21 14:47 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-21 14:32 [PATCH v3 00/15] hw/nvme: SR-IOV with Virtualization Enhancements Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 01/15] pcie: Add support for Single Root I/O Virtualization (SR/IOV) Lukasz Maniak
2022-01-06 10:16 ` Michael S. Tsirkin
2022-01-26 13:23 ` Łukasz Gieryk
2022-01-26 13:32 ` Knut Omang
2021-12-21 14:32 ` [PATCH v3 02/15] pcie: Add some SR/IOV API documentation in docs/pcie_sriov.txt Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 03/15] pcie: Add a helper to the SR/IOV API Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 04/15] pcie: Add 1.2 version token for the Power Management Capability Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 05/15] hw/nvme: Add support for SR-IOV Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 06/15] hw/nvme: Add support for Primary Controller Capabilities Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 07/15] hw/nvme: Add support for Secondary Controller List Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 08/15] hw/nvme: Implement the Function Level Reset Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 09/15] hw/nvme: Make max_ioqpairs and msix_qsize configurable in runtime Lukasz Maniak
2021-12-21 14:32 ` Lukasz Maniak [this message]
2021-12-21 14:32 ` [PATCH v3 11/15] hw/nvme: Calculate BAR attributes in a function Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 12/15] hw/nvme: Initialize capability structures for primary/secondary controllers Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 13/15] hw/nvme: Add support for the Virtualization Management command Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 14/15] docs: Add documentation for SR-IOV and Virtualization Enhancements Lukasz Maniak
2021-12-21 14:32 ` [PATCH v3 15/15] hw/nvme: Update the initalization place for the AER queue Lukasz Maniak
2022-01-26 8:58 ` [PATCH v3 00/15] hw/nvme: SR-IOV with Virtualization Enhancements Klaus Jensen
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