From: Pratyush Yadav <p.yadav@ti.com> To: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Rob Herring <robh+dt@kernel.org>, <devicetree@vger.kernel.org>, Michal Simek <monstr@monstr.eu>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Mark Brown <broonie@kernel.org>, <linux-spi@vger.kernel.org>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Tudor Ambarus <Tudor.Ambarus@microchip.com>, Michael Walle <michael@walle.cc>, <linux-mtd@lists.infradead.org>, Rob Herring <robh@kernel.org> Subject: Re: [PATCH v5 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device Date: Wed, 22 Dec 2021 00:17:27 +0530 [thread overview] Message-ID: <20211221184725.46lelrdfoxeom6uc@ti.com> (raw) In-Reply-To: <20211221170058.18333-2-miquel.raynal@bootlin.com> On 21/12/21 06:00PM, Miquel Raynal wrote: > The Xilinx QSPI controller has two advanced modes which allow the > controller to behave differently and consider two flashes as one single > storage. > > One of these two modes is quite complex to support from a binding point > of view and is the dual parallel memories. In this mode, each byte of > data is stored in both devices: the even bits in one, the odd bits in > the other. The split is automatically handled by the QSPI controller and > is transparent for the user. > > The other mode is simpler to support, it is called dual stacked > memories. The controller shares the same SPI bus but each of the devices > contain half of the data. Once in this mode, the controller does not > follow CS requests but instead internally wires the two CS levels with > the value of the most significant address bit. > > Supporting these two modes will involve core changes which include the > possibility of providing two CS for a single SPI device > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > Acked-by: Rob Herring <robh@kernel.org> > --- > Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > index 39421f7233e4..4abfb4cfc157 100644 > --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > @@ -47,7 +47,8 @@ properties: > identified by the JEDEC READ ID opcode (0x9F). > > reg: > - maxItems: 1 > + minItems: 1 > + maxItems: 2 You allow up to 4 items in stacked-memories but only allow up to 2 CS, which would make the other 2 memories unusable. Should also change this to 4. > > spi-max-frequency: true > spi-rx-bus-width: true > -- > 2.27.0 > -- Regards, Pratyush Yadav Texas Instruments Inc.
WARNING: multiple messages have this Message-ID (diff)
From: Pratyush Yadav <p.yadav@ti.com> To: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Rob Herring <robh+dt@kernel.org>, <devicetree@vger.kernel.org>, Michal Simek <monstr@monstr.eu>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Mark Brown <broonie@kernel.org>, <linux-spi@vger.kernel.org>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Tudor Ambarus <Tudor.Ambarus@microchip.com>, Michael Walle <michael@walle.cc>, <linux-mtd@lists.infradead.org>, Rob Herring <robh@kernel.org> Subject: Re: [PATCH v5 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device Date: Wed, 22 Dec 2021 00:17:27 +0530 [thread overview] Message-ID: <20211221184725.46lelrdfoxeom6uc@ti.com> (raw) In-Reply-To: <20211221170058.18333-2-miquel.raynal@bootlin.com> On 21/12/21 06:00PM, Miquel Raynal wrote: > The Xilinx QSPI controller has two advanced modes which allow the > controller to behave differently and consider two flashes as one single > storage. > > One of these two modes is quite complex to support from a binding point > of view and is the dual parallel memories. In this mode, each byte of > data is stored in both devices: the even bits in one, the odd bits in > the other. The split is automatically handled by the QSPI controller and > is transparent for the user. > > The other mode is simpler to support, it is called dual stacked > memories. The controller shares the same SPI bus but each of the devices > contain half of the data. Once in this mode, the controller does not > follow CS requests but instead internally wires the two CS levels with > the value of the most significant address bit. > > Supporting these two modes will involve core changes which include the > possibility of providing two CS for a single SPI device > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > Acked-by: Rob Herring <robh@kernel.org> > --- > Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > index 39421f7233e4..4abfb4cfc157 100644 > --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > @@ -47,7 +47,8 @@ properties: > identified by the JEDEC READ ID opcode (0x9F). > > reg: > - maxItems: 1 > + minItems: 1 > + maxItems: 2 You allow up to 4 items in stacked-memories but only allow up to 2 CS, which would make the other 2 memories unusable. Should also change this to 4. > > spi-max-frequency: true > spi-rx-bus-width: true > -- > 2.27.0 > -- Regards, Pratyush Yadav Texas Instruments Inc. ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2021-12-21 18:47 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-21 17:00 [PATCH v5 0/3] Stacked/parallel memories bindings Miquel Raynal 2021-12-21 17:00 ` Miquel Raynal 2021-12-21 17:00 ` [PATCH v5 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device Miquel Raynal 2021-12-21 17:00 ` Miquel Raynal 2021-12-21 18:47 ` Pratyush Yadav [this message] 2021-12-21 18:47 ` Pratyush Yadav 2021-12-22 8:23 ` Miquel Raynal 2021-12-22 8:23 ` Miquel Raynal 2021-12-22 8:33 ` Pratyush Yadav 2021-12-22 8:33 ` Pratyush Yadav 2021-12-22 8:41 ` Miquel Raynal 2021-12-22 8:41 ` Miquel Raynal 2021-12-21 17:00 ` [PATCH v5 2/3] spi: dt-bindings: Describe stacked/parallel memories modes Miquel Raynal 2021-12-21 17:00 ` Miquel Raynal 2021-12-21 18:45 ` Pratyush Yadav 2021-12-21 18:45 ` Pratyush Yadav 2021-12-22 7:52 ` Tudor.Ambarus 2021-12-22 7:52 ` Tudor.Ambarus 2021-12-22 8:05 ` Miquel Raynal 2021-12-22 8:05 ` Miquel Raynal 2021-12-22 8:22 ` Tudor.Ambarus 2021-12-22 8:22 ` Tudor.Ambarus 2021-12-22 8:35 ` Miquel Raynal 2021-12-22 8:35 ` Miquel Raynal 2021-12-22 8:44 ` Tudor.Ambarus 2021-12-22 8:44 ` Tudor.Ambarus 2021-12-22 8:53 ` Miquel Raynal 2021-12-22 8:53 ` Miquel Raynal 2021-12-22 19:30 ` Rob Herring 2021-12-22 19:30 ` Rob Herring 2021-12-22 19:08 ` Rob Herring 2021-12-22 19:08 ` Rob Herring 2021-12-22 19:28 ` Rob Herring 2021-12-22 19:28 ` Rob Herring 2021-12-21 17:00 ` [PATCH v5 3/3] spi: dt-bindings: Add an example with two stacked flashes Miquel Raynal 2021-12-21 17:00 ` Miquel Raynal
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