* [PATCH] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3
@ 2021-12-23 9:32 Lad Prabhakar
2022-01-10 15:20 ` Geert Uytterhoeven
0 siblings, 1 reply; 2+ messages in thread
From: Lad Prabhakar @ 2021-12-23 9:32 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: Biju Das, linux-renesas-soc, linux-clk, linux-kernel, Prabhakar
As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be 1600MHz,
but with current multiplier and divider values this resulted to 1596MHz.
This patch updates the multiplier and divider values for PLL2 and PLL3
so that we get the exact (1600MHz) values.
Fixes: 17f0ff3d49ff1 ("clk: renesas: Add support for R9A07G044 SoC")
Suggested-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Hi,
Below is the log for before and after this patch.
Clock output before the patch:
root@smarc-rzg2l:~# cat /sys/kernel/debug/clk/clk_summary | grep -E 'pll1|pll2|pll3'
.pll3 1 2 0 1596000000 0 0 50000 Y
.pll3_div2 1 1 0 798000000 0 0 50000 Y
.pll3_div2_4 3 3 0 199500000 0 0 50000 Y
.pll3_div2_4_2 2 2 0 99750000 0 0 50000 Y
.pll3_div2_2 0 0 0 399000000 0 0 50000 Y
.pll3_533 0 2 0 532000000 0 0 50000 Y
.sel_pll3_3 0 1 0 532000000 0 0 50000 Y
.pll3_400 0 0 0 399000000 0 0 50000 Y
.pll2 2 2 0 1596000000 0 0 50000 Y
.pll2_div2 1 2 0 798000000 0 0 50000 Y
.pll2_div2_10 0 1 0 79800000 0 0 50000 Y
.pll2_div2_8 1 1 0 99750000 0 0 50000 Y
.pll1 0 0 0 1200000000 0 0 50000 Y
root@smarc-rzg2l:~#
Clock output after the patch:
root@smarc-rzg2l:~# cat /sys/kernel/debug/clk/clk_summary | grep -E 'pll1|pll2|pll3'
.pll3 1 2 0 1600000000 0 0 50000 Y
.pll3_div2 1 1 0 800000000 0 0 50000 Y
.pll3_div2_4 3 3 0 200000000 0 0 50000 Y
.pll3_div2_4_2 2 2 0 100000000 0 0 50000 Y
.pll3_div2_2 0 0 0 400000000 0 0 50000 Y
.pll3_533 0 2 0 533333333 0 0 50000 Y
.sel_pll3_3 0 1 0 533333333 0 0 50000 Y
.pll3_400 0 0 0 400000000 0 0 50000 Y
.pll2 2 2 0 1600000000 0 0 50000 Y
.pll2_div2 1 2 0 800000000 0 0 50000 Y
.pll2_div2_10 0 1 0 80000000 0 0 50000 Y
.pll2_div2_8 1 1 0 100000000 0 0 50000 Y
.pll1 0 0 0 1200000000 0 0 50000 Y
root@smarc-rzg2l:~#
Cheers,
Prabhakar
---
drivers/clk/renesas/r9a07g044-cpg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index f4537345126d..22923f8949b1 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -89,8 +89,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
- DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
- DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
+ DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
+ DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3
2021-12-23 9:32 [PATCH] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 Lad Prabhakar
@ 2022-01-10 15:20 ` Geert Uytterhoeven
0 siblings, 0 replies; 2+ messages in thread
From: Geert Uytterhoeven @ 2022-01-10 15:20 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Linux Kernel Mailing List, Prabhakar
On Thu, Dec 23, 2021 at 10:32 AM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be 1600MHz,
> but with current multiplier and divider values this resulted to 1596MHz.
>
> This patch updates the multiplier and divider values for PLL2 and PLL3
> so that we get the exact (1600MHz) values.
>
> Fixes: 17f0ff3d49ff1 ("clk: renesas: Add support for R9A07G044 SoC")
> Suggested-by: Biju Das <biju.das.jz@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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2021-12-23 9:32 [PATCH] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 Lad Prabhakar
2022-01-10 15:20 ` Geert Uytterhoeven
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