* [PATCH v2 1/6] linux-user: Split out do_prctl and subroutines
2021-12-27 15:01 [PATCH v2 0/6] linux-user: prctl improvements Richard Henderson
@ 2021-12-27 15:01 ` Richard Henderson
2022-01-04 11:43 ` Laurent Vivier
2021-12-27 15:01 ` [PATCH v2 2/6] linux-user: Disable more prctl subcodes Richard Henderson
` (4 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Richard Henderson @ 2021-12-27 15:01 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent, Philippe Mathieu-Daudé
Since the prctl constants are supposed to be generic, supply
any that are not provided by the host.
Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE,
PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL,
PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do
not support these options rather than pass them on to the host.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/target_prctl.h | 160 ++++++++++
linux-user/aarch64/target_syscall.h | 23 --
linux-user/alpha/target_prctl.h | 1 +
linux-user/arm/target_prctl.h | 1 +
linux-user/cris/target_prctl.h | 1 +
linux-user/hexagon/target_prctl.h | 1 +
linux-user/hppa/target_prctl.h | 1 +
linux-user/i386/target_prctl.h | 1 +
linux-user/m68k/target_prctl.h | 1 +
linux-user/microblaze/target_prctl.h | 1 +
linux-user/mips/target_prctl.h | 88 ++++++
linux-user/mips/target_syscall.h | 6 -
linux-user/mips64/target_prctl.h | 1 +
linux-user/mips64/target_syscall.h | 6 -
linux-user/nios2/target_prctl.h | 1 +
linux-user/openrisc/target_prctl.h | 1 +
linux-user/ppc/target_prctl.h | 1 +
linux-user/riscv/target_prctl.h | 1 +
linux-user/s390x/target_prctl.h | 1 +
linux-user/sh4/target_prctl.h | 1 +
linux-user/sparc/target_prctl.h | 1 +
linux-user/x86_64/target_prctl.h | 1 +
linux-user/xtensa/target_prctl.h | 1 +
linux-user/syscall.c | 433 +++++++++------------------
24 files changed, 414 insertions(+), 320 deletions(-)
create mode 100644 linux-user/aarch64/target_prctl.h
create mode 100644 linux-user/alpha/target_prctl.h
create mode 100644 linux-user/arm/target_prctl.h
create mode 100644 linux-user/cris/target_prctl.h
create mode 100644 linux-user/hexagon/target_prctl.h
create mode 100644 linux-user/hppa/target_prctl.h
create mode 100644 linux-user/i386/target_prctl.h
create mode 100644 linux-user/m68k/target_prctl.h
create mode 100644 linux-user/microblaze/target_prctl.h
create mode 100644 linux-user/mips/target_prctl.h
create mode 100644 linux-user/mips64/target_prctl.h
create mode 100644 linux-user/nios2/target_prctl.h
create mode 100644 linux-user/openrisc/target_prctl.h
create mode 100644 linux-user/ppc/target_prctl.h
create mode 100644 linux-user/riscv/target_prctl.h
create mode 100644 linux-user/s390x/target_prctl.h
create mode 100644 linux-user/sh4/target_prctl.h
create mode 100644 linux-user/sparc/target_prctl.h
create mode 100644 linux-user/x86_64/target_prctl.h
create mode 100644 linux-user/xtensa/target_prctl.h
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
new file mode 100644
index 0000000000..3f5a5d3933
--- /dev/null
+++ b/linux-user/aarch64/target_prctl.h
@@ -0,0 +1,160 @@
+/*
+ * AArch64 specific prctl functions for linux-user
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef AARCH64_TARGET_PRCTL_H
+#define AARCH64_TARGET_PRCTL_H
+
+static abi_long do_prctl_get_vl(CPUArchState *env)
+{
+ ARMCPU *cpu = env_archcpu(env);
+ if (cpu_isar_feature(aa64_sve, cpu)) {
+ return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;
+ }
+ return -TARGET_EINVAL;
+}
+#define do_prctl_get_vl do_prctl_get_vl
+
+static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2)
+{
+ /*
+ * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT.
+ * Note the kernel definition of sve_vl_valid allows for VQ=512,
+ * i.e. VL=8192, even though the current architectural maximum is VQ=16.
+ */
+ if (cpu_isar_feature(aa64_sve, env_archcpu(env))
+ && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
+ ARMCPU *cpu = env_archcpu(env);
+ uint32_t vq, old_vq;
+
+ old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
+ vq = MAX(arg2 / 16, 1);
+ vq = MIN(vq, cpu->sve_max_vq);
+
+ if (vq < old_vq) {
+ aarch64_sve_narrow_vq(env, vq);
+ }
+ env->vfp.zcr_el[1] = vq - 1;
+ arm_rebuild_hflags(env);
+ return vq * 16;
+ }
+ return -TARGET_EINVAL;
+}
+#define do_prctl_set_vl do_prctl_set_vl
+
+static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2)
+{
+ ARMCPU *cpu = env_archcpu(env);
+
+ if (cpu_isar_feature(aa64_pauth, cpu)) {
+ int all = (PR_PAC_APIAKEY | PR_PAC_APIBKEY |
+ PR_PAC_APDAKEY | PR_PAC_APDBKEY | PR_PAC_APGAKEY);
+ int ret = 0;
+ Error *err = NULL;
+
+ if (arg2 == 0) {
+ arg2 = all;
+ } else if (arg2 & ~all) {
+ return -TARGET_EINVAL;
+ }
+ if (arg2 & PR_PAC_APIAKEY) {
+ ret |= qemu_guest_getrandom(&env->keys.apia,
+ sizeof(ARMPACKey), &err);
+ }
+ if (arg2 & PR_PAC_APIBKEY) {
+ ret |= qemu_guest_getrandom(&env->keys.apib,
+ sizeof(ARMPACKey), &err);
+ }
+ if (arg2 & PR_PAC_APDAKEY) {
+ ret |= qemu_guest_getrandom(&env->keys.apda,
+ sizeof(ARMPACKey), &err);
+ }
+ if (arg2 & PR_PAC_APDBKEY) {
+ ret |= qemu_guest_getrandom(&env->keys.apdb,
+ sizeof(ARMPACKey), &err);
+ }
+ if (arg2 & PR_PAC_APGAKEY) {
+ ret |= qemu_guest_getrandom(&env->keys.apga,
+ sizeof(ARMPACKey), &err);
+ }
+ if (ret != 0) {
+ /*
+ * Some unknown failure in the crypto. The best
+ * we can do is log it and fail the syscall.
+ * The real syscall cannot fail this way.
+ */
+ qemu_log_mask(LOG_UNIMP, "PR_PAC_RESET_KEYS: Crypto failure: %s",
+ error_get_pretty(err));
+ error_free(err);
+ return -TARGET_EIO;
+ }
+ return 0;
+ }
+ return -TARGET_EINVAL;
+}
+#define do_prctl_reset_keys do_prctl_reset_keys
+
+static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
+{
+ abi_ulong valid_mask = PR_TAGGED_ADDR_ENABLE;
+ ARMCPU *cpu = env_archcpu(env);
+
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ valid_mask |= PR_MTE_TCF_MASK;
+ valid_mask |= PR_MTE_TAG_MASK;
+ }
+
+ if (arg2 & ~valid_mask) {
+ return -TARGET_EINVAL;
+ }
+ env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
+
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ switch (arg2 & PR_MTE_TCF_MASK) {
+ case PR_MTE_TCF_NONE:
+ case PR_MTE_TCF_SYNC:
+ case PR_MTE_TCF_ASYNC:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /*
+ * Write PR_MTE_TCF to SCTLR_EL1[TCF0].
+ * Note that the syscall values are consistent with hw.
+ */
+ env->cp15.sctlr_el[1] =
+ deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
+
+ /*
+ * Write PR_MTE_TAG to GCR_EL1[Exclude].
+ * Note that the syscall uses an include mask,
+ * and hardware uses an exclude mask -- invert.
+ */
+ env->cp15.gcr_el1 =
+ deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT);
+ arm_rebuild_hflags(env);
+ }
+ return 0;
+}
+#define do_prctl_set_tagged_addr_ctrl do_prctl_set_tagged_addr_ctrl
+
+static abi_long do_prctl_get_tagged_addr_ctrl(CPUArchState *env)
+{
+ ARMCPU *cpu = env_archcpu(env);
+ abi_long ret = 0;
+
+ if (env->tagged_addr_enable) {
+ ret |= PR_TAGGED_ADDR_ENABLE;
+ }
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ /* See do_prctl_set_tagged_addr_ctrl. */
+ ret |= extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHIFT;
+ ret = deposit64(ret, PR_MTE_TAG_SHIFT, 16, ~env->cp15.gcr_el1);
+ }
+ return ret;
+}
+#define do_prctl_get_tagged_addr_ctrl do_prctl_get_tagged_addr_ctrl
+
+#endif /* AARCH64_TARGET_PRCTL_H */
diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h
index 76f6c3391d..819f112ab0 100644
--- a/linux-user/aarch64/target_syscall.h
+++ b/linux-user/aarch64/target_syscall.h
@@ -20,27 +20,4 @@ struct target_pt_regs {
#define TARGET_MCL_FUTURE 2
#define TARGET_MCL_ONFAULT 4
-#define TARGET_PR_SVE_SET_VL 50
-#define TARGET_PR_SVE_GET_VL 51
-
-#define TARGET_PR_PAC_RESET_KEYS 54
-# define TARGET_PR_PAC_APIAKEY (1 << 0)
-# define TARGET_PR_PAC_APIBKEY (1 << 1)
-# define TARGET_PR_PAC_APDAKEY (1 << 2)
-# define TARGET_PR_PAC_APDBKEY (1 << 3)
-# define TARGET_PR_PAC_APGAKEY (1 << 4)
-
-#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55
-#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56
-# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0)
-/* MTE tag check fault modes */
-# define TARGET_PR_MTE_TCF_SHIFT 1
-# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT)
-# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT)
-# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT)
-# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT)
-/* MTE tag inclusion mask */
-# define TARGET_PR_MTE_TAG_SHIFT 3
-# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT)
-
#endif /* AARCH64_TARGET_SYSCALL_H */
diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/alpha/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/arm/target_prctl.h b/linux-user/arm/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/arm/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/cris/target_prctl.h b/linux-user/cris/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/cris/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/hexagon/target_prctl.h b/linux-user/hexagon/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/hexagon/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/hppa/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/i386/target_prctl.h b/linux-user/i386/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/i386/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/m68k/target_prctl.h b/linux-user/m68k/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/m68k/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/microblaze/target_prctl.h b/linux-user/microblaze/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/microblaze/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/mips/target_prctl.h b/linux-user/mips/target_prctl.h
new file mode 100644
index 0000000000..e028333db9
--- /dev/null
+++ b/linux-user/mips/target_prctl.h
@@ -0,0 +1,88 @@
+/*
+ * MIPS specific prctl functions for linux-user
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef MIPS_TARGET_PRCTL_H
+#define MIPS_TARGET_PRCTL_H
+
+static abi_long do_prctl_get_fp_mode(CPUArchState *env)
+{
+ abi_long ret = 0;
+
+ if (env->CP0_Status & (1 << CP0St_FR)) {
+ ret |= PR_FP_MODE_FR;
+ }
+ if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
+ ret |= PR_FP_MODE_FRE;
+ }
+ return ret;
+}
+#define do_prctl_get_fp_mode do_prctl_get_fp_mode
+
+static abi_long do_prctl_set_fp_mode(CPUArchState *env, abi_long arg2)
+{
+ bool old_fr = env->CP0_Status & (1 << CP0St_FR);
+ bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE);
+ bool new_fr = arg2 & PR_FP_MODE_FR;
+ bool new_fre = arg2 & PR_FP_MODE_FRE;
+ const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
+
+ /* If nothing to change, return right away, successfully. */
+ if (old_fr == new_fr && old_fre == new_fre) {
+ return 0;
+ }
+ /* Check the value is valid */
+ if (arg2 & ~known_bits) {
+ return -TARGET_EOPNOTSUPP;
+ }
+ /* Setting FRE without FR is not supported. */
+ if (new_fre && !new_fr) {
+ return -TARGET_EOPNOTSUPP;
+ }
+ if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
+ /* FR1 is not supported */
+ return -TARGET_EOPNOTSUPP;
+ }
+ if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64))
+ && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
+ /* cannot set FR=0 */
+ return -TARGET_EOPNOTSUPP;
+ }
+ if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) {
+ /* Cannot set FRE=1 */
+ return -TARGET_EOPNOTSUPP;
+ }
+
+ int i;
+ fpr_t *fpr = env->active_fpu.fpr;
+ for (i = 0; i < 32 ; i += 2) {
+ if (!old_fr && new_fr) {
+ fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX];
+ } else if (old_fr && !new_fr) {
+ fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX];
+ }
+ }
+
+ if (new_fr) {
+ env->CP0_Status |= (1 << CP0St_FR);
+ env->hflags |= MIPS_HFLAG_F64;
+ } else {
+ env->CP0_Status &= ~(1 << CP0St_FR);
+ env->hflags &= ~MIPS_HFLAG_F64;
+ }
+ if (new_fre) {
+ env->CP0_Config5 |= (1 << CP0C5_FRE);
+ if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
+ env->hflags |= MIPS_HFLAG_FRE;
+ }
+ } else {
+ env->CP0_Config5 &= ~(1 << CP0C5_FRE);
+ env->hflags &= ~MIPS_HFLAG_FRE;
+ }
+
+ return 0;
+}
+#define do_prctl_set_fp_mode do_prctl_set_fp_mode
+
+#endif /* MIPS_TARGET_PRCTL_H */
diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h
index f59057493a..1ce0a5bbf4 100644
--- a/linux-user/mips/target_syscall.h
+++ b/linux-user/mips/target_syscall.h
@@ -36,10 +36,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env)
return 0x40000;
}
-/* MIPS-specific prctl() options */
-#define TARGET_PR_SET_FP_MODE 45
-#define TARGET_PR_GET_FP_MODE 46
-#define TARGET_PR_FP_MODE_FR (1 << 0)
-#define TARGET_PR_FP_MODE_FRE (1 << 1)
-
#endif /* MIPS_TARGET_SYSCALL_H */
diff --git a/linux-user/mips64/target_prctl.h b/linux-user/mips64/target_prctl.h
new file mode 100644
index 0000000000..18da9ae619
--- /dev/null
+++ b/linux-user/mips64/target_prctl.h
@@ -0,0 +1 @@
+#include "../mips/target_prctl.h"
diff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_syscall.h
index cd1e1b4969..74f12365bc 100644
--- a/linux-user/mips64/target_syscall.h
+++ b/linux-user/mips64/target_syscall.h
@@ -33,10 +33,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env)
return 0x40000;
}
-/* MIPS-specific prctl() options */
-#define TARGET_PR_SET_FP_MODE 45
-#define TARGET_PR_GET_FP_MODE 46
-#define TARGET_PR_FP_MODE_FR (1 << 0)
-#define TARGET_PR_FP_MODE_FRE (1 << 1)
-
#endif /* MIPS64_TARGET_SYSCALL_H */
diff --git a/linux-user/nios2/target_prctl.h b/linux-user/nios2/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/nios2/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/openrisc/target_prctl.h b/linux-user/openrisc/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/openrisc/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/ppc/target_prctl.h b/linux-user/ppc/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/ppc/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/riscv/target_prctl.h b/linux-user/riscv/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/riscv/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/s390x/target_prctl.h b/linux-user/s390x/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/s390x/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/sh4/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/sparc/target_prctl.h b/linux-user/sparc/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/sparc/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/x86_64/target_prctl.h b/linux-user/x86_64/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/x86_64/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/xtensa/target_prctl.h b/linux-user/xtensa/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/xtensa/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 56a3e17183..0f0f67d567 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6294,9 +6294,155 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
return ret;
}
#endif /* defined(TARGET_ABI32 */
-
#endif /* defined(TARGET_I386) */
+/*
+ * These constants are generic. Supply any that are missing from the host.
+ */
+#ifndef PR_SET_NAME
+# define PR_SET_NAME 15
+# define PR_GET_NAME 16
+#endif
+#ifndef PR_SET_FP_MODE
+# define PR_SET_FP_MODE 45
+# define PR_GET_FP_MODE 46
+# define PR_FP_MODE_FR (1 << 0)
+# define PR_FP_MODE_FRE (1 << 1)
+#endif
+#ifndef PR_SVE_SET_VL
+# define PR_SVE_SET_VL 50
+# define PR_SVE_GET_VL 51
+# define PR_SVE_VL_LEN_MASK 0xffff
+# define PR_SVE_VL_INHERIT (1 << 17)
+#endif
+#ifndef PR_PAC_RESET_KEYS
+# define PR_PAC_RESET_KEYS 54
+# define PR_PAC_APIAKEY (1 << 0)
+# define PR_PAC_APIBKEY (1 << 1)
+# define PR_PAC_APDAKEY (1 << 2)
+# define PR_PAC_APDBKEY (1 << 3)
+# define PR_PAC_APGAKEY (1 << 4)
+#endif
+#ifndef PR_SET_TAGGED_ADDR_CTRL
+# define PR_SET_TAGGED_ADDR_CTRL 55
+# define PR_GET_TAGGED_ADDR_CTRL 56
+# define PR_TAGGED_ADDR_ENABLE (1UL << 0)
+#endif
+#ifndef PR_MTE_TCF_SHIFT
+# define PR_MTE_TCF_SHIFT 1
+# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TAG_SHIFT 3
+# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
+#endif
+
+#include "target_prctl.h"
+
+static abi_long do_prctl_inval0(CPUArchState *env)
+{
+ return -TARGET_EINVAL;
+}
+
+static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
+{
+ return -TARGET_EINVAL;
+}
+
+#ifndef do_prctl_get_fp_mode
+#define do_prctl_get_fp_mode do_prctl_inval0
+#endif
+#ifndef do_prctl_set_fp_mode
+#define do_prctl_set_fp_mode do_prctl_inval1
+#endif
+#ifndef do_prctl_get_vl
+#define do_prctl_get_vl do_prctl_inval0
+#endif
+#ifndef do_prctl_set_vl
+#define do_prctl_set_vl do_prctl_inval1
+#endif
+#ifndef do_prctl_reset_keys
+#define do_prctl_reset_keys do_prctl_inval1
+#endif
+#ifndef do_prctl_set_tagged_addr_ctrl
+#define do_prctl_set_tagged_addr_ctrl do_prctl_inval1
+#endif
+#ifndef do_prctl_get_tagged_addr_ctrl
+#define do_prctl_get_tagged_addr_ctrl do_prctl_inval0
+#endif
+
+static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
+ abi_long arg3, abi_long arg4, abi_long arg5)
+{
+ abi_long ret;
+
+ switch (option) {
+ case PR_GET_PDEATHSIG:
+ {
+ int deathsig;
+ ret = get_errno(prctl(PR_GET_PDEATHSIG, &deathsig,
+ arg3, arg4, arg5));
+ if (!is_error(ret) && arg2 && put_user_s32(deathsig, arg2)) {
+ return -TARGET_EFAULT;
+ }
+ return ret;
+ }
+ case PR_GET_NAME:
+ {
+ void *name = lock_user(VERIFY_WRITE, arg2, 16, 1);
+ if (!name) {
+ return -TARGET_EFAULT;
+ }
+ ret = get_errno(prctl(PR_GET_NAME, (uintptr_t)name,
+ arg3, arg4, arg5));
+ unlock_user(name, arg2, 16);
+ return ret;
+ }
+ case PR_SET_NAME:
+ {
+ void *name = lock_user(VERIFY_READ, arg2, 16, 1);
+ if (!name) {
+ return -TARGET_EFAULT;
+ }
+ ret = get_errno(prctl(PR_SET_NAME, (uintptr_t)name,
+ arg3, arg4, arg5));
+ unlock_user(name, arg2, 0);
+ return ret;
+ }
+ case PR_GET_FP_MODE:
+ return do_prctl_get_fp_mode(env);
+ case PR_SET_FP_MODE:
+ return do_prctl_set_fp_mode(env, arg2);
+ case PR_SVE_GET_VL:
+ return do_prctl_get_vl(env);
+ case PR_SVE_SET_VL:
+ return do_prctl_set_vl(env, arg2);
+ case PR_PAC_RESET_KEYS:
+ if (arg3 || arg4 || arg5) {
+ return -TARGET_EINVAL;
+ }
+ return do_prctl_reset_keys(env, arg2);
+ case PR_SET_TAGGED_ADDR_CTRL:
+ if (arg3 || arg4 || arg5) {
+ return -TARGET_EINVAL;
+ }
+ return do_prctl_set_tagged_addr_ctrl(env, arg2);
+ case PR_GET_TAGGED_ADDR_CTRL:
+ if (arg2 || arg3 || arg4 || arg5) {
+ return -TARGET_EINVAL;
+ }
+ return do_prctl_get_tagged_addr_ctrl(env);
+ case PR_GET_SECCOMP:
+ case PR_SET_SECCOMP:
+ /* Disable seccomp to prevent the target disabling syscalls we need. */
+ return -TARGET_EINVAL;
+ default:
+ /* Most prctl options have no pointer arguments */
+ return get_errno(prctl(option, arg2, arg3, arg4, arg5));
+ }
+}
+
#define NEW_STACK_SIZE 0x40000
@@ -10635,290 +10781,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
return ret;
#endif
case TARGET_NR_prctl:
- switch (arg1) {
- case PR_GET_PDEATHSIG:
- {
- int deathsig;
- ret = get_errno(prctl(arg1, &deathsig, arg3, arg4, arg5));
- if (!is_error(ret) && arg2
- && put_user_s32(deathsig, arg2)) {
- return -TARGET_EFAULT;
- }
- return ret;
- }
-#ifdef PR_GET_NAME
- case PR_GET_NAME:
- {
- void *name = lock_user(VERIFY_WRITE, arg2, 16, 1);
- if (!name) {
- return -TARGET_EFAULT;
- }
- ret = get_errno(prctl(arg1, (unsigned long)name,
- arg3, arg4, arg5));
- unlock_user(name, arg2, 16);
- return ret;
- }
- case PR_SET_NAME:
- {
- void *name = lock_user(VERIFY_READ, arg2, 16, 1);
- if (!name) {
- return -TARGET_EFAULT;
- }
- ret = get_errno(prctl(arg1, (unsigned long)name,
- arg3, arg4, arg5));
- unlock_user(name, arg2, 0);
- return ret;
- }
-#endif
-#ifdef TARGET_MIPS
- case TARGET_PR_GET_FP_MODE:
- {
- CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
- ret = 0;
- if (env->CP0_Status & (1 << CP0St_FR)) {
- ret |= TARGET_PR_FP_MODE_FR;
- }
- if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
- ret |= TARGET_PR_FP_MODE_FRE;
- }
- return ret;
- }
- case TARGET_PR_SET_FP_MODE:
- {
- CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
- bool old_fr = env->CP0_Status & (1 << CP0St_FR);
- bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE);
- bool new_fr = arg2 & TARGET_PR_FP_MODE_FR;
- bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE;
-
- const unsigned int known_bits = TARGET_PR_FP_MODE_FR |
- TARGET_PR_FP_MODE_FRE;
-
- /* If nothing to change, return right away, successfully. */
- if (old_fr == new_fr && old_fre == new_fre) {
- return 0;
- }
- /* Check the value is valid */
- if (arg2 & ~known_bits) {
- return -TARGET_EOPNOTSUPP;
- }
- /* Setting FRE without FR is not supported. */
- if (new_fre && !new_fr) {
- return -TARGET_EOPNOTSUPP;
- }
- if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
- /* FR1 is not supported */
- return -TARGET_EOPNOTSUPP;
- }
- if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64))
- && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
- /* cannot set FR=0 */
- return -TARGET_EOPNOTSUPP;
- }
- if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) {
- /* Cannot set FRE=1 */
- return -TARGET_EOPNOTSUPP;
- }
-
- int i;
- fpr_t *fpr = env->active_fpu.fpr;
- for (i = 0; i < 32 ; i += 2) {
- if (!old_fr && new_fr) {
- fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX];
- } else if (old_fr && !new_fr) {
- fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX];
- }
- }
-
- if (new_fr) {
- env->CP0_Status |= (1 << CP0St_FR);
- env->hflags |= MIPS_HFLAG_F64;
- } else {
- env->CP0_Status &= ~(1 << CP0St_FR);
- env->hflags &= ~MIPS_HFLAG_F64;
- }
- if (new_fre) {
- env->CP0_Config5 |= (1 << CP0C5_FRE);
- if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
- env->hflags |= MIPS_HFLAG_FRE;
- }
- } else {
- env->CP0_Config5 &= ~(1 << CP0C5_FRE);
- env->hflags &= ~MIPS_HFLAG_FRE;
- }
-
- return 0;
- }
-#endif /* MIPS */
-#ifdef TARGET_AARCH64
- case TARGET_PR_SVE_SET_VL:
- /*
- * We cannot support either PR_SVE_SET_VL_ONEXEC or
- * PR_SVE_VL_INHERIT. Note the kernel definition
- * of sve_vl_valid allows for VQ=512, i.e. VL=8192,
- * even though the current architectural maximum is VQ=16.
- */
- ret = -TARGET_EINVAL;
- if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env))
- && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
- CPUARMState *env = cpu_env;
- ARMCPU *cpu = env_archcpu(env);
- uint32_t vq, old_vq;
-
- old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
- vq = MAX(arg2 / 16, 1);
- vq = MIN(vq, cpu->sve_max_vq);
-
- if (vq < old_vq) {
- aarch64_sve_narrow_vq(env, vq);
- }
- env->vfp.zcr_el[1] = vq - 1;
- arm_rebuild_hflags(env);
- ret = vq * 16;
- }
- return ret;
- case TARGET_PR_SVE_GET_VL:
- ret = -TARGET_EINVAL;
- {
- ARMCPU *cpu = env_archcpu(cpu_env);
- if (cpu_isar_feature(aa64_sve, cpu)) {
- ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;
- }
- }
- return ret;
- case TARGET_PR_PAC_RESET_KEYS:
- {
- CPUARMState *env = cpu_env;
- ARMCPU *cpu = env_archcpu(env);
-
- if (arg3 || arg4 || arg5) {
- return -TARGET_EINVAL;
- }
- if (cpu_isar_feature(aa64_pauth, cpu)) {
- int all = (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_APIBKEY |
- TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBKEY |
- TARGET_PR_PAC_APGAKEY);
- int ret = 0;
- Error *err = NULL;
-
- if (arg2 == 0) {
- arg2 = all;
- } else if (arg2 & ~all) {
- return -TARGET_EINVAL;
- }
- if (arg2 & TARGET_PR_PAC_APIAKEY) {
- ret |= qemu_guest_getrandom(&env->keys.apia,
- sizeof(ARMPACKey), &err);
- }
- if (arg2 & TARGET_PR_PAC_APIBKEY) {
- ret |= qemu_guest_getrandom(&env->keys.apib,
- sizeof(ARMPACKey), &err);
- }
- if (arg2 & TARGET_PR_PAC_APDAKEY) {
- ret |= qemu_guest_getrandom(&env->keys.apda,
- sizeof(ARMPACKey), &err);
- }
- if (arg2 & TARGET_PR_PAC_APDBKEY) {
- ret |= qemu_guest_getrandom(&env->keys.apdb,
- sizeof(ARMPACKey), &err);
- }
- if (arg2 & TARGET_PR_PAC_APGAKEY) {
- ret |= qemu_guest_getrandom(&env->keys.apga,
- sizeof(ARMPACKey), &err);
- }
- if (ret != 0) {
- /*
- * Some unknown failure in the crypto. The best
- * we can do is log it and fail the syscall.
- * The real syscall cannot fail this way.
- */
- qemu_log_mask(LOG_UNIMP,
- "PR_PAC_RESET_KEYS: Crypto failure: %s",
- error_get_pretty(err));
- error_free(err);
- return -TARGET_EIO;
- }
- return 0;
- }
- }
- return -TARGET_EINVAL;
- case TARGET_PR_SET_TAGGED_ADDR_CTRL:
- {
- abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE;
- CPUARMState *env = cpu_env;
- ARMCPU *cpu = env_archcpu(env);
-
- if (cpu_isar_feature(aa64_mte, cpu)) {
- valid_mask |= TARGET_PR_MTE_TCF_MASK;
- valid_mask |= TARGET_PR_MTE_TAG_MASK;
- }
-
- if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) {
- return -TARGET_EINVAL;
- }
- env->tagged_addr_enable = arg2 & TARGET_PR_TAGGED_ADDR_ENABLE;
-
- if (cpu_isar_feature(aa64_mte, cpu)) {
- switch (arg2 & TARGET_PR_MTE_TCF_MASK) {
- case TARGET_PR_MTE_TCF_NONE:
- case TARGET_PR_MTE_TCF_SYNC:
- case TARGET_PR_MTE_TCF_ASYNC:
- break;
- default:
- return -EINVAL;
- }
-
- /*
- * Write PR_MTE_TCF to SCTLR_EL1[TCF0].
- * Note that the syscall values are consistent with hw.
- */
- env->cp15.sctlr_el[1] =
- deposit64(env->cp15.sctlr_el[1], 38, 2,
- arg2 >> TARGET_PR_MTE_TCF_SHIFT);
-
- /*
- * Write PR_MTE_TAG to GCR_EL1[Exclude].
- * Note that the syscall uses an include mask,
- * and hardware uses an exclude mask -- invert.
- */
- env->cp15.gcr_el1 =
- deposit64(env->cp15.gcr_el1, 0, 16,
- ~arg2 >> TARGET_PR_MTE_TAG_SHIFT);
- arm_rebuild_hflags(env);
- }
- return 0;
- }
- case TARGET_PR_GET_TAGGED_ADDR_CTRL:
- {
- abi_long ret = 0;
- CPUARMState *env = cpu_env;
- ARMCPU *cpu = env_archcpu(env);
-
- if (arg2 || arg3 || arg4 || arg5) {
- return -TARGET_EINVAL;
- }
- if (env->tagged_addr_enable) {
- ret |= TARGET_PR_TAGGED_ADDR_ENABLE;
- }
- if (cpu_isar_feature(aa64_mte, cpu)) {
- /* See above. */
- ret |= (extract64(env->cp15.sctlr_el[1], 38, 2)
- << TARGET_PR_MTE_TCF_SHIFT);
- ret = deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16,
- ~env->cp15.gcr_el1);
- }
- return ret;
- }
-#endif /* AARCH64 */
- case PR_GET_SECCOMP:
- case PR_SET_SECCOMP:
- /* Disable seccomp to prevent the target disabling syscalls we
- * need. */
- return -TARGET_EINVAL;
- default:
- /* Most prctl options have no pointer arguments */
- return get_errno(prctl(arg1, arg2, arg3, arg4, arg5));
- }
+ return do_prctl(cpu_env, arg1, arg2, arg3, arg4, arg5);
break;
#ifdef TARGET_NR_arch_prctl
case TARGET_NR_arch_prctl:
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 1/6] linux-user: Split out do_prctl and subroutines
2021-12-27 15:01 ` [PATCH v2 1/6] linux-user: Split out do_prctl and subroutines Richard Henderson
@ 2022-01-04 11:43 ` Laurent Vivier
0 siblings, 0 replies; 15+ messages in thread
From: Laurent Vivier @ 2022-01-04 11:43 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Philippe Mathieu-Daudé
Le 27/12/2021 à 16:01, Richard Henderson a écrit :
> Since the prctl constants are supposed to be generic, supply
> any that are not provided by the host.
>
> Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE,
> PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL,
> PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do
> not support these options rather than pass them on to the host.
>
> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/aarch64/target_prctl.h | 160 ++++++++++
> linux-user/aarch64/target_syscall.h | 23 --
> linux-user/alpha/target_prctl.h | 1 +
> linux-user/arm/target_prctl.h | 1 +
> linux-user/cris/target_prctl.h | 1 +
> linux-user/hexagon/target_prctl.h | 1 +
> linux-user/hppa/target_prctl.h | 1 +
> linux-user/i386/target_prctl.h | 1 +
> linux-user/m68k/target_prctl.h | 1 +
> linux-user/microblaze/target_prctl.h | 1 +
> linux-user/mips/target_prctl.h | 88 ++++++
> linux-user/mips/target_syscall.h | 6 -
> linux-user/mips64/target_prctl.h | 1 +
> linux-user/mips64/target_syscall.h | 6 -
> linux-user/nios2/target_prctl.h | 1 +
> linux-user/openrisc/target_prctl.h | 1 +
> linux-user/ppc/target_prctl.h | 1 +
> linux-user/riscv/target_prctl.h | 1 +
> linux-user/s390x/target_prctl.h | 1 +
> linux-user/sh4/target_prctl.h | 1 +
> linux-user/sparc/target_prctl.h | 1 +
> linux-user/x86_64/target_prctl.h | 1 +
> linux-user/xtensa/target_prctl.h | 1 +
> linux-user/syscall.c | 433 +++++++++------------------
> 24 files changed, 414 insertions(+), 320 deletions(-)
> create mode 100644 linux-user/aarch64/target_prctl.h
> create mode 100644 linux-user/alpha/target_prctl.h
> create mode 100644 linux-user/arm/target_prctl.h
> create mode 100644 linux-user/cris/target_prctl.h
> create mode 100644 linux-user/hexagon/target_prctl.h
> create mode 100644 linux-user/hppa/target_prctl.h
> create mode 100644 linux-user/i386/target_prctl.h
> create mode 100644 linux-user/m68k/target_prctl.h
> create mode 100644 linux-user/microblaze/target_prctl.h
> create mode 100644 linux-user/mips/target_prctl.h
> create mode 100644 linux-user/mips64/target_prctl.h
> create mode 100644 linux-user/nios2/target_prctl.h
> create mode 100644 linux-user/openrisc/target_prctl.h
> create mode 100644 linux-user/ppc/target_prctl.h
> create mode 100644 linux-user/riscv/target_prctl.h
> create mode 100644 linux-user/s390x/target_prctl.h
> create mode 100644 linux-user/sh4/target_prctl.h
> create mode 100644 linux-user/sparc/target_prctl.h
> create mode 100644 linux-user/x86_64/target_prctl.h
> create mode 100644 linux-user/xtensa/target_prctl.h
>
> diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
> new file mode 100644
> index 0000000000..3f5a5d3933
> --- /dev/null
> +++ b/linux-user/aarch64/target_prctl.h
> @@ -0,0 +1,160 @@
> +/*
> + * AArch64 specific prctl functions for linux-user
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#ifndef AARCH64_TARGET_PRCTL_H
> +#define AARCH64_TARGET_PRCTL_H
> +
> +static abi_long do_prctl_get_vl(CPUArchState *env)
> +{
> + ARMCPU *cpu = env_archcpu(env);
> + if (cpu_isar_feature(aa64_sve, cpu)) {
> + return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;
> + }
> + return -TARGET_EINVAL;
> +}
> +#define do_prctl_get_vl do_prctl_get_vl
> +
> +static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2)
> +{
> + /*
> + * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT.
> + * Note the kernel definition of sve_vl_valid allows for VQ=512,
> + * i.e. VL=8192, even though the current architectural maximum is VQ=16.
> + */
> + if (cpu_isar_feature(aa64_sve, env_archcpu(env))
> + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
> + ARMCPU *cpu = env_archcpu(env);
> + uint32_t vq, old_vq;
> +
> + old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
> + vq = MAX(arg2 / 16, 1);
> + vq = MIN(vq, cpu->sve_max_vq);
> +
> + if (vq < old_vq) {
> + aarch64_sve_narrow_vq(env, vq);
> + }
> + env->vfp.zcr_el[1] = vq - 1;
> + arm_rebuild_hflags(env);
> + return vq * 16;
> + }
> + return -TARGET_EINVAL;
> +}
> +#define do_prctl_set_vl do_prctl_set_vl
> +
> +static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2)
> +{
> + ARMCPU *cpu = env_archcpu(env);
> +
> + if (cpu_isar_feature(aa64_pauth, cpu)) {
> + int all = (PR_PAC_APIAKEY | PR_PAC_APIBKEY |
> + PR_PAC_APDAKEY | PR_PAC_APDBKEY | PR_PAC_APGAKEY);
> + int ret = 0;
> + Error *err = NULL;
> +
> + if (arg2 == 0) {
> + arg2 = all;
> + } else if (arg2 & ~all) {
> + return -TARGET_EINVAL;
> + }
> + if (arg2 & PR_PAC_APIAKEY) {
> + ret |= qemu_guest_getrandom(&env->keys.apia,
> + sizeof(ARMPACKey), &err);
> + }
> + if (arg2 & PR_PAC_APIBKEY) {
> + ret |= qemu_guest_getrandom(&env->keys.apib,
> + sizeof(ARMPACKey), &err);
> + }
> + if (arg2 & PR_PAC_APDAKEY) {
> + ret |= qemu_guest_getrandom(&env->keys.apda,
> + sizeof(ARMPACKey), &err);
> + }
> + if (arg2 & PR_PAC_APDBKEY) {
> + ret |= qemu_guest_getrandom(&env->keys.apdb,
> + sizeof(ARMPACKey), &err);
> + }
> + if (arg2 & PR_PAC_APGAKEY) {
> + ret |= qemu_guest_getrandom(&env->keys.apga,
> + sizeof(ARMPACKey), &err);
> + }
> + if (ret != 0) {
> + /*
> + * Some unknown failure in the crypto. The best
> + * we can do is log it and fail the syscall.
> + * The real syscall cannot fail this way.
> + */
> + qemu_log_mask(LOG_UNIMP, "PR_PAC_RESET_KEYS: Crypto failure: %s",
> + error_get_pretty(err));
> + error_free(err);
> + return -TARGET_EIO;
> + }
> + return 0;
> + }
> + return -TARGET_EINVAL;
> +}
> +#define do_prctl_reset_keys do_prctl_reset_keys
> +
> +static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
> +{
> + abi_ulong valid_mask = PR_TAGGED_ADDR_ENABLE;
> + ARMCPU *cpu = env_archcpu(env);
> +
> + if (cpu_isar_feature(aa64_mte, cpu)) {
> + valid_mask |= PR_MTE_TCF_MASK;
> + valid_mask |= PR_MTE_TAG_MASK;
> + }
> +
> + if (arg2 & ~valid_mask) {
> + return -TARGET_EINVAL;
> + }
> + env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
> +
> + if (cpu_isar_feature(aa64_mte, cpu)) {
> + switch (arg2 & PR_MTE_TCF_MASK) {
> + case PR_MTE_TCF_NONE:
> + case PR_MTE_TCF_SYNC:
> + case PR_MTE_TCF_ASYNC:
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + /*
> + * Write PR_MTE_TCF to SCTLR_EL1[TCF0].
> + * Note that the syscall values are consistent with hw.
> + */
> + env->cp15.sctlr_el[1] =
> + deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
> +
> + /*
> + * Write PR_MTE_TAG to GCR_EL1[Exclude].
> + * Note that the syscall uses an include mask,
> + * and hardware uses an exclude mask -- invert.
> + */
> + env->cp15.gcr_el1 =
> + deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT);
> + arm_rebuild_hflags(env);
> + }
> + return 0;
> +}
> +#define do_prctl_set_tagged_addr_ctrl do_prctl_set_tagged_addr_ctrl
> +
> +static abi_long do_prctl_get_tagged_addr_ctrl(CPUArchState *env)
> +{
> + ARMCPU *cpu = env_archcpu(env);
> + abi_long ret = 0;
> +
> + if (env->tagged_addr_enable) {
> + ret |= PR_TAGGED_ADDR_ENABLE;
> + }
> + if (cpu_isar_feature(aa64_mte, cpu)) {
> + /* See do_prctl_set_tagged_addr_ctrl. */
> + ret |= extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHIFT;
> + ret = deposit64(ret, PR_MTE_TAG_SHIFT, 16, ~env->cp15.gcr_el1);
> + }
> + return ret;
> +}
> +#define do_prctl_get_tagged_addr_ctrl do_prctl_get_tagged_addr_ctrl
> +
> +#endif /* AARCH64_TARGET_PRCTL_H */
> diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h
> index 76f6c3391d..819f112ab0 100644
> --- a/linux-user/aarch64/target_syscall.h
> +++ b/linux-user/aarch64/target_syscall.h
> @@ -20,27 +20,4 @@ struct target_pt_regs {
> #define TARGET_MCL_FUTURE 2
> #define TARGET_MCL_ONFAULT 4
>
> -#define TARGET_PR_SVE_SET_VL 50
> -#define TARGET_PR_SVE_GET_VL 51
> -
> -#define TARGET_PR_PAC_RESET_KEYS 54
> -# define TARGET_PR_PAC_APIAKEY (1 << 0)
> -# define TARGET_PR_PAC_APIBKEY (1 << 1)
> -# define TARGET_PR_PAC_APDAKEY (1 << 2)
> -# define TARGET_PR_PAC_APDBKEY (1 << 3)
> -# define TARGET_PR_PAC_APGAKEY (1 << 4)
> -
> -#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55
> -#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56
> -# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0)
> -/* MTE tag check fault modes */
> -# define TARGET_PR_MTE_TCF_SHIFT 1
> -# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT)
> -# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT)
> -# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT)
> -# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT)
> -/* MTE tag inclusion mask */
> -# define TARGET_PR_MTE_TAG_SHIFT 3
> -# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT)
> -
> #endif /* AARCH64_TARGET_SYSCALL_H */
> diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/alpha/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/arm/target_prctl.h b/linux-user/arm/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/arm/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/cris/target_prctl.h b/linux-user/cris/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/cris/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/hexagon/target_prctl.h b/linux-user/hexagon/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/hexagon/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/hppa/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/i386/target_prctl.h b/linux-user/i386/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/i386/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/m68k/target_prctl.h b/linux-user/m68k/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/m68k/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/microblaze/target_prctl.h b/linux-user/microblaze/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/microblaze/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/mips/target_prctl.h b/linux-user/mips/target_prctl.h
> new file mode 100644
> index 0000000000..e028333db9
> --- /dev/null
> +++ b/linux-user/mips/target_prctl.h
> @@ -0,0 +1,88 @@
> +/*
> + * MIPS specific prctl functions for linux-user
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#ifndef MIPS_TARGET_PRCTL_H
> +#define MIPS_TARGET_PRCTL_H
> +
> +static abi_long do_prctl_get_fp_mode(CPUArchState *env)
> +{
> + abi_long ret = 0;
> +
> + if (env->CP0_Status & (1 << CP0St_FR)) {
> + ret |= PR_FP_MODE_FR;
> + }
> + if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
> + ret |= PR_FP_MODE_FRE;
> + }
> + return ret;
> +}
> +#define do_prctl_get_fp_mode do_prctl_get_fp_mode
> +
> +static abi_long do_prctl_set_fp_mode(CPUArchState *env, abi_long arg2)
> +{
> + bool old_fr = env->CP0_Status & (1 << CP0St_FR);
> + bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE);
> + bool new_fr = arg2 & PR_FP_MODE_FR;
> + bool new_fre = arg2 & PR_FP_MODE_FRE;
> + const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
> +
> + /* If nothing to change, return right away, successfully. */
> + if (old_fr == new_fr && old_fre == new_fre) {
> + return 0;
> + }
> + /* Check the value is valid */
> + if (arg2 & ~known_bits) {
> + return -TARGET_EOPNOTSUPP;
> + }
> + /* Setting FRE without FR is not supported. */
> + if (new_fre && !new_fr) {
> + return -TARGET_EOPNOTSUPP;
> + }
> + if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
> + /* FR1 is not supported */
> + return -TARGET_EOPNOTSUPP;
> + }
> + if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64))
> + && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
> + /* cannot set FR=0 */
> + return -TARGET_EOPNOTSUPP;
> + }
> + if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) {
> + /* Cannot set FRE=1 */
> + return -TARGET_EOPNOTSUPP;
> + }
> +
> + int i;
> + fpr_t *fpr = env->active_fpu.fpr;
> + for (i = 0; i < 32 ; i += 2) {
> + if (!old_fr && new_fr) {
> + fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX];
> + } else if (old_fr && !new_fr) {
> + fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX];
> + }
> + }
> +
> + if (new_fr) {
> + env->CP0_Status |= (1 << CP0St_FR);
> + env->hflags |= MIPS_HFLAG_F64;
> + } else {
> + env->CP0_Status &= ~(1 << CP0St_FR);
> + env->hflags &= ~MIPS_HFLAG_F64;
> + }
> + if (new_fre) {
> + env->CP0_Config5 |= (1 << CP0C5_FRE);
> + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
> + env->hflags |= MIPS_HFLAG_FRE;
> + }
> + } else {
> + env->CP0_Config5 &= ~(1 << CP0C5_FRE);
> + env->hflags &= ~MIPS_HFLAG_FRE;
> + }
> +
> + return 0;
> +}
> +#define do_prctl_set_fp_mode do_prctl_set_fp_mode
> +
> +#endif /* MIPS_TARGET_PRCTL_H */
> diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h
> index f59057493a..1ce0a5bbf4 100644
> --- a/linux-user/mips/target_syscall.h
> +++ b/linux-user/mips/target_syscall.h
> @@ -36,10 +36,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env)
> return 0x40000;
> }
>
> -/* MIPS-specific prctl() options */
> -#define TARGET_PR_SET_FP_MODE 45
> -#define TARGET_PR_GET_FP_MODE 46
> -#define TARGET_PR_FP_MODE_FR (1 << 0)
> -#define TARGET_PR_FP_MODE_FRE (1 << 1)
> -
> #endif /* MIPS_TARGET_SYSCALL_H */
> diff --git a/linux-user/mips64/target_prctl.h b/linux-user/mips64/target_prctl.h
> new file mode 100644
> index 0000000000..18da9ae619
> --- /dev/null
> +++ b/linux-user/mips64/target_prctl.h
> @@ -0,0 +1 @@
> +#include "../mips/target_prctl.h"
> diff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_syscall.h
> index cd1e1b4969..74f12365bc 100644
> --- a/linux-user/mips64/target_syscall.h
> +++ b/linux-user/mips64/target_syscall.h
> @@ -33,10 +33,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env)
> return 0x40000;
> }
>
> -/* MIPS-specific prctl() options */
> -#define TARGET_PR_SET_FP_MODE 45
> -#define TARGET_PR_GET_FP_MODE 46
> -#define TARGET_PR_FP_MODE_FR (1 << 0)
> -#define TARGET_PR_FP_MODE_FRE (1 << 1)
> -
> #endif /* MIPS64_TARGET_SYSCALL_H */
> diff --git a/linux-user/nios2/target_prctl.h b/linux-user/nios2/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/nios2/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/openrisc/target_prctl.h b/linux-user/openrisc/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/openrisc/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/ppc/target_prctl.h b/linux-user/ppc/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/ppc/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/riscv/target_prctl.h b/linux-user/riscv/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/riscv/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/s390x/target_prctl.h b/linux-user/s390x/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/s390x/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/sh4/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/sparc/target_prctl.h b/linux-user/sparc/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/sparc/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/x86_64/target_prctl.h b/linux-user/x86_64/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/x86_64/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/xtensa/target_prctl.h b/linux-user/xtensa/target_prctl.h
> new file mode 100644
> index 0000000000..eb53b31ad5
> --- /dev/null
> +++ b/linux-user/xtensa/target_prctl.h
> @@ -0,0 +1 @@
> +/* No special prctl support required. */
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 56a3e17183..0f0f67d567 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -6294,9 +6294,155 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
> return ret;
> }
> #endif /* defined(TARGET_ABI32 */
> -
> #endif /* defined(TARGET_I386) */
>
> +/*
> + * These constants are generic. Supply any that are missing from the host.
> + */
> +#ifndef PR_SET_NAME
> +# define PR_SET_NAME 15
> +# define PR_GET_NAME 16
> +#endif
> +#ifndef PR_SET_FP_MODE
> +# define PR_SET_FP_MODE 45
> +# define PR_GET_FP_MODE 46
> +# define PR_FP_MODE_FR (1 << 0)
> +# define PR_FP_MODE_FRE (1 << 1)
> +#endif
> +#ifndef PR_SVE_SET_VL
> +# define PR_SVE_SET_VL 50
> +# define PR_SVE_GET_VL 51
> +# define PR_SVE_VL_LEN_MASK 0xffff
> +# define PR_SVE_VL_INHERIT (1 << 17)
> +#endif
> +#ifndef PR_PAC_RESET_KEYS
> +# define PR_PAC_RESET_KEYS 54
> +# define PR_PAC_APIAKEY (1 << 0)
> +# define PR_PAC_APIBKEY (1 << 1)
> +# define PR_PAC_APDAKEY (1 << 2)
> +# define PR_PAC_APDBKEY (1 << 3)
> +# define PR_PAC_APGAKEY (1 << 4)
> +#endif
> +#ifndef PR_SET_TAGGED_ADDR_CTRL
> +# define PR_SET_TAGGED_ADDR_CTRL 55
> +# define PR_GET_TAGGED_ADDR_CTRL 56
> +# define PR_TAGGED_ADDR_ENABLE (1UL << 0)
> +#endif
> +#ifndef PR_MTE_TCF_SHIFT
> +# define PR_MTE_TCF_SHIFT 1
> +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
> +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
> +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
> +# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
> +# define PR_MTE_TAG_SHIFT 3
> +# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
> +#endif
> +
> +#include "target_prctl.h"
> +
> +static abi_long do_prctl_inval0(CPUArchState *env)
> +{
> + return -TARGET_EINVAL;
> +}
> +
> +static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
> +{
> + return -TARGET_EINVAL;
> +}
> +
> +#ifndef do_prctl_get_fp_mode
> +#define do_prctl_get_fp_mode do_prctl_inval0
> +#endif
> +#ifndef do_prctl_set_fp_mode
> +#define do_prctl_set_fp_mode do_prctl_inval1
> +#endif
> +#ifndef do_prctl_get_vl
> +#define do_prctl_get_vl do_prctl_inval0
> +#endif
> +#ifndef do_prctl_set_vl
> +#define do_prctl_set_vl do_prctl_inval1
> +#endif
> +#ifndef do_prctl_reset_keys
> +#define do_prctl_reset_keys do_prctl_inval1
> +#endif
> +#ifndef do_prctl_set_tagged_addr_ctrl
> +#define do_prctl_set_tagged_addr_ctrl do_prctl_inval1
> +#endif
> +#ifndef do_prctl_get_tagged_addr_ctrl
> +#define do_prctl_get_tagged_addr_ctrl do_prctl_inval0
> +#endif
> +
> +static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
> + abi_long arg3, abi_long arg4, abi_long arg5)
> +{
> + abi_long ret;
> +
> + switch (option) {
> + case PR_GET_PDEATHSIG:
> + {
> + int deathsig;
> + ret = get_errno(prctl(PR_GET_PDEATHSIG, &deathsig,
> + arg3, arg4, arg5));
> + if (!is_error(ret) && arg2 && put_user_s32(deathsig, arg2)) {
> + return -TARGET_EFAULT;
> + }
> + return ret;
> + }
> + case PR_GET_NAME:
> + {
> + void *name = lock_user(VERIFY_WRITE, arg2, 16, 1);
> + if (!name) {
> + return -TARGET_EFAULT;
> + }
> + ret = get_errno(prctl(PR_GET_NAME, (uintptr_t)name,
> + arg3, arg4, arg5));
> + unlock_user(name, arg2, 16);
> + return ret;
> + }
> + case PR_SET_NAME:
> + {
> + void *name = lock_user(VERIFY_READ, arg2, 16, 1);
> + if (!name) {
> + return -TARGET_EFAULT;
> + }
> + ret = get_errno(prctl(PR_SET_NAME, (uintptr_t)name,
> + arg3, arg4, arg5));
> + unlock_user(name, arg2, 0);
> + return ret;
> + }
> + case PR_GET_FP_MODE:
> + return do_prctl_get_fp_mode(env);
> + case PR_SET_FP_MODE:
> + return do_prctl_set_fp_mode(env, arg2);
> + case PR_SVE_GET_VL:
> + return do_prctl_get_vl(env);
> + case PR_SVE_SET_VL:
> + return do_prctl_set_vl(env, arg2);
> + case PR_PAC_RESET_KEYS:
> + if (arg3 || arg4 || arg5) {
> + return -TARGET_EINVAL;
> + }
> + return do_prctl_reset_keys(env, arg2);
> + case PR_SET_TAGGED_ADDR_CTRL:
> + if (arg3 || arg4 || arg5) {
> + return -TARGET_EINVAL;
> + }
> + return do_prctl_set_tagged_addr_ctrl(env, arg2);
> + case PR_GET_TAGGED_ADDR_CTRL:
> + if (arg2 || arg3 || arg4 || arg5) {
> + return -TARGET_EINVAL;
> + }
> + return do_prctl_get_tagged_addr_ctrl(env);
> + case PR_GET_SECCOMP:
> + case PR_SET_SECCOMP:
> + /* Disable seccomp to prevent the target disabling syscalls we need. */
> + return -TARGET_EINVAL;
> + default:
> + /* Most prctl options have no pointer arguments */
> + return get_errno(prctl(option, arg2, arg3, arg4, arg5));
> + }
> +}
> +
> #define NEW_STACK_SIZE 0x40000
>
>
> @@ -10635,290 +10781,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
> return ret;
> #endif
> case TARGET_NR_prctl:
> - switch (arg1) {
> - case PR_GET_PDEATHSIG:
> - {
> - int deathsig;
> - ret = get_errno(prctl(arg1, &deathsig, arg3, arg4, arg5));
> - if (!is_error(ret) && arg2
> - && put_user_s32(deathsig, arg2)) {
> - return -TARGET_EFAULT;
> - }
> - return ret;
> - }
> -#ifdef PR_GET_NAME
> - case PR_GET_NAME:
> - {
> - void *name = lock_user(VERIFY_WRITE, arg2, 16, 1);
> - if (!name) {
> - return -TARGET_EFAULT;
> - }
> - ret = get_errno(prctl(arg1, (unsigned long)name,
> - arg3, arg4, arg5));
> - unlock_user(name, arg2, 16);
> - return ret;
> - }
> - case PR_SET_NAME:
> - {
> - void *name = lock_user(VERIFY_READ, arg2, 16, 1);
> - if (!name) {
> - return -TARGET_EFAULT;
> - }
> - ret = get_errno(prctl(arg1, (unsigned long)name,
> - arg3, arg4, arg5));
> - unlock_user(name, arg2, 0);
> - return ret;
> - }
> -#endif
> -#ifdef TARGET_MIPS
> - case TARGET_PR_GET_FP_MODE:
> - {
> - CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
> - ret = 0;
> - if (env->CP0_Status & (1 << CP0St_FR)) {
> - ret |= TARGET_PR_FP_MODE_FR;
> - }
> - if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
> - ret |= TARGET_PR_FP_MODE_FRE;
> - }
> - return ret;
> - }
> - case TARGET_PR_SET_FP_MODE:
> - {
> - CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
> - bool old_fr = env->CP0_Status & (1 << CP0St_FR);
> - bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE);
> - bool new_fr = arg2 & TARGET_PR_FP_MODE_FR;
> - bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE;
> -
> - const unsigned int known_bits = TARGET_PR_FP_MODE_FR |
> - TARGET_PR_FP_MODE_FRE;
> -
> - /* If nothing to change, return right away, successfully. */
> - if (old_fr == new_fr && old_fre == new_fre) {
> - return 0;
> - }
> - /* Check the value is valid */
> - if (arg2 & ~known_bits) {
> - return -TARGET_EOPNOTSUPP;
> - }
> - /* Setting FRE without FR is not supported. */
> - if (new_fre && !new_fr) {
> - return -TARGET_EOPNOTSUPP;
> - }
> - if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
> - /* FR1 is not supported */
> - return -TARGET_EOPNOTSUPP;
> - }
> - if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64))
> - && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
> - /* cannot set FR=0 */
> - return -TARGET_EOPNOTSUPP;
> - }
> - if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) {
> - /* Cannot set FRE=1 */
> - return -TARGET_EOPNOTSUPP;
> - }
> -
> - int i;
> - fpr_t *fpr = env->active_fpu.fpr;
> - for (i = 0; i < 32 ; i += 2) {
> - if (!old_fr && new_fr) {
> - fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX];
> - } else if (old_fr && !new_fr) {
> - fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX];
> - }
> - }
> -
> - if (new_fr) {
> - env->CP0_Status |= (1 << CP0St_FR);
> - env->hflags |= MIPS_HFLAG_F64;
> - } else {
> - env->CP0_Status &= ~(1 << CP0St_FR);
> - env->hflags &= ~MIPS_HFLAG_F64;
> - }
> - if (new_fre) {
> - env->CP0_Config5 |= (1 << CP0C5_FRE);
> - if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
> - env->hflags |= MIPS_HFLAG_FRE;
> - }
> - } else {
> - env->CP0_Config5 &= ~(1 << CP0C5_FRE);
> - env->hflags &= ~MIPS_HFLAG_FRE;
> - }
> -
> - return 0;
> - }
> -#endif /* MIPS */
> -#ifdef TARGET_AARCH64
> - case TARGET_PR_SVE_SET_VL:
> - /*
> - * We cannot support either PR_SVE_SET_VL_ONEXEC or
> - * PR_SVE_VL_INHERIT. Note the kernel definition
> - * of sve_vl_valid allows for VQ=512, i.e. VL=8192,
> - * even though the current architectural maximum is VQ=16.
> - */
> - ret = -TARGET_EINVAL;
> - if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env))
> - && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
> - CPUARMState *env = cpu_env;
> - ARMCPU *cpu = env_archcpu(env);
> - uint32_t vq, old_vq;
> -
> - old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
> - vq = MAX(arg2 / 16, 1);
> - vq = MIN(vq, cpu->sve_max_vq);
> -
> - if (vq < old_vq) {
> - aarch64_sve_narrow_vq(env, vq);
> - }
> - env->vfp.zcr_el[1] = vq - 1;
> - arm_rebuild_hflags(env);
> - ret = vq * 16;
> - }
> - return ret;
> - case TARGET_PR_SVE_GET_VL:
> - ret = -TARGET_EINVAL;
> - {
> - ARMCPU *cpu = env_archcpu(cpu_env);
> - if (cpu_isar_feature(aa64_sve, cpu)) {
> - ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;
> - }
> - }
> - return ret;
> - case TARGET_PR_PAC_RESET_KEYS:
> - {
> - CPUARMState *env = cpu_env;
> - ARMCPU *cpu = env_archcpu(env);
> -
> - if (arg3 || arg4 || arg5) {
> - return -TARGET_EINVAL;
> - }
> - if (cpu_isar_feature(aa64_pauth, cpu)) {
> - int all = (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_APIBKEY |
> - TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBKEY |
> - TARGET_PR_PAC_APGAKEY);
> - int ret = 0;
> - Error *err = NULL;
> -
> - if (arg2 == 0) {
> - arg2 = all;
> - } else if (arg2 & ~all) {
> - return -TARGET_EINVAL;
> - }
> - if (arg2 & TARGET_PR_PAC_APIAKEY) {
> - ret |= qemu_guest_getrandom(&env->keys.apia,
> - sizeof(ARMPACKey), &err);
> - }
> - if (arg2 & TARGET_PR_PAC_APIBKEY) {
> - ret |= qemu_guest_getrandom(&env->keys.apib,
> - sizeof(ARMPACKey), &err);
> - }
> - if (arg2 & TARGET_PR_PAC_APDAKEY) {
> - ret |= qemu_guest_getrandom(&env->keys.apda,
> - sizeof(ARMPACKey), &err);
> - }
> - if (arg2 & TARGET_PR_PAC_APDBKEY) {
> - ret |= qemu_guest_getrandom(&env->keys.apdb,
> - sizeof(ARMPACKey), &err);
> - }
> - if (arg2 & TARGET_PR_PAC_APGAKEY) {
> - ret |= qemu_guest_getrandom(&env->keys.apga,
> - sizeof(ARMPACKey), &err);
> - }
> - if (ret != 0) {
> - /*
> - * Some unknown failure in the crypto. The best
> - * we can do is log it and fail the syscall.
> - * The real syscall cannot fail this way.
> - */
> - qemu_log_mask(LOG_UNIMP,
> - "PR_PAC_RESET_KEYS: Crypto failure: %s",
> - error_get_pretty(err));
> - error_free(err);
> - return -TARGET_EIO;
> - }
> - return 0;
> - }
> - }
> - return -TARGET_EINVAL;
> - case TARGET_PR_SET_TAGGED_ADDR_CTRL:
> - {
> - abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE;
> - CPUARMState *env = cpu_env;
> - ARMCPU *cpu = env_archcpu(env);
> -
> - if (cpu_isar_feature(aa64_mte, cpu)) {
> - valid_mask |= TARGET_PR_MTE_TCF_MASK;
> - valid_mask |= TARGET_PR_MTE_TAG_MASK;
> - }
> -
> - if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) {
> - return -TARGET_EINVAL;
> - }
> - env->tagged_addr_enable = arg2 & TARGET_PR_TAGGED_ADDR_ENABLE;
> -
> - if (cpu_isar_feature(aa64_mte, cpu)) {
> - switch (arg2 & TARGET_PR_MTE_TCF_MASK) {
> - case TARGET_PR_MTE_TCF_NONE:
> - case TARGET_PR_MTE_TCF_SYNC:
> - case TARGET_PR_MTE_TCF_ASYNC:
> - break;
> - default:
> - return -EINVAL;
> - }
> -
> - /*
> - * Write PR_MTE_TCF to SCTLR_EL1[TCF0].
> - * Note that the syscall values are consistent with hw.
> - */
> - env->cp15.sctlr_el[1] =
> - deposit64(env->cp15.sctlr_el[1], 38, 2,
> - arg2 >> TARGET_PR_MTE_TCF_SHIFT);
> -
> - /*
> - * Write PR_MTE_TAG to GCR_EL1[Exclude].
> - * Note that the syscall uses an include mask,
> - * and hardware uses an exclude mask -- invert.
> - */
> - env->cp15.gcr_el1 =
> - deposit64(env->cp15.gcr_el1, 0, 16,
> - ~arg2 >> TARGET_PR_MTE_TAG_SHIFT);
> - arm_rebuild_hflags(env);
> - }
> - return 0;
> - }
> - case TARGET_PR_GET_TAGGED_ADDR_CTRL:
> - {
> - abi_long ret = 0;
> - CPUARMState *env = cpu_env;
> - ARMCPU *cpu = env_archcpu(env);
> -
> - if (arg2 || arg3 || arg4 || arg5) {
> - return -TARGET_EINVAL;
> - }
> - if (env->tagged_addr_enable) {
> - ret |= TARGET_PR_TAGGED_ADDR_ENABLE;
> - }
> - if (cpu_isar_feature(aa64_mte, cpu)) {
> - /* See above. */
> - ret |= (extract64(env->cp15.sctlr_el[1], 38, 2)
> - << TARGET_PR_MTE_TCF_SHIFT);
> - ret = deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16,
> - ~env->cp15.gcr_el1);
> - }
> - return ret;
> - }
> -#endif /* AARCH64 */
> - case PR_GET_SECCOMP:
> - case PR_SET_SECCOMP:
> - /* Disable seccomp to prevent the target disabling syscalls we
> - * need. */
> - return -TARGET_EINVAL;
> - default:
> - /* Most prctl options have no pointer arguments */
> - return get_errno(prctl(arg1, arg2, arg3, arg4, arg5));
> - }
> + return do_prctl(cpu_env, arg1, arg2, arg3, arg4, arg5);
> break;
> #ifdef TARGET_NR_arch_prctl
> case TARGET_NR_arch_prctl:
Applied to my linux-user-for-7.0 branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 2/6] linux-user: Disable more prctl subcodes
2021-12-27 15:01 [PATCH v2 0/6] linux-user: prctl improvements Richard Henderson
2021-12-27 15:01 ` [PATCH v2 1/6] linux-user: Split out do_prctl and subroutines Richard Henderson
@ 2021-12-27 15:01 ` Richard Henderson
2022-01-04 11:44 ` Laurent Vivier
2021-12-27 15:01 ` [PATCH v2 3/6] linux-user: Add code for PR_GET/SET_UNALIGN Richard Henderson
` (3 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Richard Henderson @ 2021-12-27 15:01 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent, Philippe Mathieu-Daudé
Create a list of subcodes that we want to pass on, a list of
subcodes that should not be passed on because they would affect
the running qemu itself, and a list that probably could be
implemented but require extra work. Do not pass on unknown subcodes.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Log unknown prctl options.
---
linux-user/syscall.c | 58 +++++++++++++++++++++++++++++++++++++++++---
1 file changed, 55 insertions(+), 3 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 0f0f67d567..d868ef2910 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6337,6 +6337,13 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
# define PR_MTE_TAG_SHIFT 3
# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
#endif
+#ifndef PR_SET_IO_FLUSHER
+# define PR_SET_IO_FLUSHER 57
+# define PR_GET_IO_FLUSHER 58
+#endif
+#ifndef PR_SET_SYSCALL_USER_DISPATCH
+# define PR_SET_SYSCALL_USER_DISPATCH 59
+#endif
#include "target_prctl.h"
@@ -6433,13 +6440,58 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
return -TARGET_EINVAL;
}
return do_prctl_get_tagged_addr_ctrl(env);
+
+ case PR_GET_DUMPABLE:
+ case PR_SET_DUMPABLE:
+ case PR_GET_KEEPCAPS:
+ case PR_SET_KEEPCAPS:
+ case PR_GET_TIMING:
+ case PR_SET_TIMING:
+ case PR_GET_TIMERSLACK:
+ case PR_SET_TIMERSLACK:
+ case PR_MCE_KILL:
+ case PR_MCE_KILL_GET:
+ case PR_GET_NO_NEW_PRIVS:
+ case PR_SET_NO_NEW_PRIVS:
+ case PR_GET_IO_FLUSHER:
+ case PR_SET_IO_FLUSHER:
+ /* Some prctl options have no pointer arguments and we can pass on. */
+ return get_errno(prctl(option, arg2, arg3, arg4, arg5));
+
+ case PR_GET_CHILD_SUBREAPER:
+ case PR_SET_CHILD_SUBREAPER:
+ case PR_GET_SPECULATION_CTRL:
+ case PR_SET_SPECULATION_CTRL:
+ case PR_GET_TID_ADDRESS:
+ /* TODO */
+ return -TARGET_EINVAL;
+
+ case PR_GET_FPEXC:
+ case PR_SET_FPEXC:
+ /* Was used for SPE on PowerPC. */
+ return -TARGET_EINVAL;
+
+ case PR_GET_ENDIAN:
+ case PR_SET_ENDIAN:
+ case PR_GET_FPEMU:
+ case PR_SET_FPEMU:
+ case PR_SET_MM:
case PR_GET_SECCOMP:
case PR_SET_SECCOMP:
- /* Disable seccomp to prevent the target disabling syscalls we need. */
+ case PR_SET_SYSCALL_USER_DISPATCH:
+ case PR_GET_THP_DISABLE:
+ case PR_SET_THP_DISABLE:
+ case PR_GET_TSC:
+ case PR_SET_TSC:
+ case PR_GET_UNALIGN:
+ case PR_SET_UNALIGN:
+ /* Disable to prevent the target disabling stuff we need. */
return -TARGET_EINVAL;
+
default:
- /* Most prctl options have no pointer arguments */
- return get_errno(prctl(option, arg2, arg3, arg4, arg5));
+ qemu_log_mask(LOG_UNIMP, "Unsupported prctl: " TARGET_ABI_FMT_ld "\n",
+ option);
+ return -TARGET_EINVAL;
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 2/6] linux-user: Disable more prctl subcodes
2021-12-27 15:01 ` [PATCH v2 2/6] linux-user: Disable more prctl subcodes Richard Henderson
@ 2022-01-04 11:44 ` Laurent Vivier
0 siblings, 0 replies; 15+ messages in thread
From: Laurent Vivier @ 2022-01-04 11:44 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Philippe Mathieu-Daudé
Le 27/12/2021 à 16:01, Richard Henderson a écrit :
> Create a list of subcodes that we want to pass on, a list of
> subcodes that should not be passed on because they would affect
> the running qemu itself, and a list that probably could be
> implemented but require extra work. Do not pass on unknown subcodes.
>
> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v2: Log unknown prctl options.
> ---
> linux-user/syscall.c | 58 +++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 55 insertions(+), 3 deletions(-)
>
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 0f0f67d567..d868ef2910 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -6337,6 +6337,13 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
> # define PR_MTE_TAG_SHIFT 3
> # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
> #endif
> +#ifndef PR_SET_IO_FLUSHER
> +# define PR_SET_IO_FLUSHER 57
> +# define PR_GET_IO_FLUSHER 58
> +#endif
> +#ifndef PR_SET_SYSCALL_USER_DISPATCH
> +# define PR_SET_SYSCALL_USER_DISPATCH 59
> +#endif
>
> #include "target_prctl.h"
>
> @@ -6433,13 +6440,58 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
> return -TARGET_EINVAL;
> }
> return do_prctl_get_tagged_addr_ctrl(env);
> +
> + case PR_GET_DUMPABLE:
> + case PR_SET_DUMPABLE:
> + case PR_GET_KEEPCAPS:
> + case PR_SET_KEEPCAPS:
> + case PR_GET_TIMING:
> + case PR_SET_TIMING:
> + case PR_GET_TIMERSLACK:
> + case PR_SET_TIMERSLACK:
> + case PR_MCE_KILL:
> + case PR_MCE_KILL_GET:
> + case PR_GET_NO_NEW_PRIVS:
> + case PR_SET_NO_NEW_PRIVS:
> + case PR_GET_IO_FLUSHER:
> + case PR_SET_IO_FLUSHER:
> + /* Some prctl options have no pointer arguments and we can pass on. */
> + return get_errno(prctl(option, arg2, arg3, arg4, arg5));
> +
> + case PR_GET_CHILD_SUBREAPER:
> + case PR_SET_CHILD_SUBREAPER:
> + case PR_GET_SPECULATION_CTRL:
> + case PR_SET_SPECULATION_CTRL:
> + case PR_GET_TID_ADDRESS:
> + /* TODO */
> + return -TARGET_EINVAL;
> +
> + case PR_GET_FPEXC:
> + case PR_SET_FPEXC:
> + /* Was used for SPE on PowerPC. */
> + return -TARGET_EINVAL;
> +
> + case PR_GET_ENDIAN:
> + case PR_SET_ENDIAN:
> + case PR_GET_FPEMU:
> + case PR_SET_FPEMU:
> + case PR_SET_MM:
> case PR_GET_SECCOMP:
> case PR_SET_SECCOMP:
> - /* Disable seccomp to prevent the target disabling syscalls we need. */
> + case PR_SET_SYSCALL_USER_DISPATCH:
> + case PR_GET_THP_DISABLE:
> + case PR_SET_THP_DISABLE:
> + case PR_GET_TSC:
> + case PR_SET_TSC:
> + case PR_GET_UNALIGN:
> + case PR_SET_UNALIGN:
> + /* Disable to prevent the target disabling stuff we need. */
> return -TARGET_EINVAL;
> +
> default:
> - /* Most prctl options have no pointer arguments */
> - return get_errno(prctl(option, arg2, arg3, arg4, arg5));
> + qemu_log_mask(LOG_UNIMP, "Unsupported prctl: " TARGET_ABI_FMT_ld "\n",
> + option);
> + return -TARGET_EINVAL;
> }
> }
>
Applied to my linux-user-for-7.0 branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 3/6] linux-user: Add code for PR_GET/SET_UNALIGN
2021-12-27 15:01 [PATCH v2 0/6] linux-user: prctl improvements Richard Henderson
2021-12-27 15:01 ` [PATCH v2 1/6] linux-user: Split out do_prctl and subroutines Richard Henderson
2021-12-27 15:01 ` [PATCH v2 2/6] linux-user: Disable more prctl subcodes Richard Henderson
@ 2021-12-27 15:01 ` Richard Henderson
2021-12-27 15:01 ` [PATCH v2 4/6] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
` (2 subsequent siblings)
5 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2021-12-27 15:01 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent, Warner Losh, Philippe Mathieu-Daudé
This requires extra work for each target, but adds the
common syscall code, and the necessary flag in CPUState.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 3 +++
linux-user/generic/target_prctl_unalign.h | 27 +++++++++++++++++++++++
cpu.c | 20 ++++++++++++-----
linux-user/syscall.c | 13 +++++++++--
4 files changed, 56 insertions(+), 7 deletions(-)
create mode 100644 linux-user/generic/target_prctl_unalign.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e948e81f1a..76ab3b851c 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -413,6 +413,9 @@ struct CPUState {
bool ignore_memory_transaction_failures;
+ /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */
+ bool prctl_unalign_sigbus;
+
struct hax_vcpu_state *hax_vcpu;
struct hvf_vcpu_state *hvf;
diff --git a/linux-user/generic/target_prctl_unalign.h b/linux-user/generic/target_prctl_unalign.h
new file mode 100644
index 0000000000..bc3b83af2a
--- /dev/null
+++ b/linux-user/generic/target_prctl_unalign.h
@@ -0,0 +1,27 @@
+/*
+ * Generic prctl unalign functions for linux-user
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef GENERIC_TARGET_PRCTL_UNALIGN_H
+#define GENERIC_TARGET_PRCTL_UNALIGN_H
+
+static abi_long do_prctl_get_unalign(CPUArchState *env, target_long arg2)
+{
+ CPUState *cs = env_cpu(env);
+ uint32_t res = PR_UNALIGN_NOPRINT;
+ if (cs->prctl_unalign_sigbus) {
+ res |= PR_UNALIGN_SIGBUS;
+ }
+ return put_user_u32(res, arg2);
+}
+#define do_prctl_get_unalign do_prctl_get_unalign
+
+static abi_long do_prctl_set_unalign(CPUArchState *env, target_long arg2)
+{
+ env_cpu(env)->prctl_unalign_sigbus = arg2 & PR_UNALIGN_SIGBUS;
+ return 0;
+}
+#define do_prctl_set_unalign do_prctl_set_unalign
+
+#endif /* GENERIC_TARGET_PRCTL_UNALIGN_H */
diff --git a/cpu.c b/cpu.c
index 945dd3dded..016bf06a1a 100644
--- a/cpu.c
+++ b/cpu.c
@@ -174,13 +174,23 @@ void cpu_exec_unrealizefn(CPUState *cpu)
cpu_list_remove(cpu);
}
+/*
+ * This can't go in hw/core/cpu.c because that file is compiled only
+ * once for both user-mode and system builds.
+ */
static Property cpu_common_props[] = {
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
/*
- * Create a memory property for softmmu CPU object,
- * so users can wire up its memory. (This can't go in hw/core/cpu.c
- * because that file is compiled only once for both user-mode
- * and system builds.) The default if no link is set up is to use
+ * Create a property for the user-only object, so users can
+ * adjust prctl(PR_SET_UNALIGN) from the command-line.
+ * Has no effect if the target does not support the feature.
+ */
+ DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
+ prctl_unalign_sigbus, false),
+#else
+ /*
+ * Create a memory property for softmmu CPU object, so users can
+ * wire up its memory. The default if no link is set up is to use
* the system address space.
*/
DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index d868ef2910..b5112891b0 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6378,6 +6378,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
#ifndef do_prctl_get_tagged_addr_ctrl
#define do_prctl_get_tagged_addr_ctrl do_prctl_inval0
#endif
+#ifndef do_prctl_get_unalign
+#define do_prctl_get_unalign do_prctl_inval1
+#endif
+#ifndef do_prctl_set_unalign
+#define do_prctl_set_unalign do_prctl_inval1
+#endif
static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
abi_long arg3, abi_long arg4, abi_long arg5)
@@ -6441,6 +6447,11 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
}
return do_prctl_get_tagged_addr_ctrl(env);
+ case PR_GET_UNALIGN:
+ return do_prctl_get_unalign(env, arg2);
+ case PR_SET_UNALIGN:
+ return do_prctl_set_unalign(env, arg2);
+
case PR_GET_DUMPABLE:
case PR_SET_DUMPABLE:
case PR_GET_KEEPCAPS:
@@ -6483,8 +6494,6 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
case PR_SET_THP_DISABLE:
case PR_GET_TSC:
case PR_SET_TSC:
- case PR_GET_UNALIGN:
- case PR_SET_UNALIGN:
/* Disable to prevent the target disabling stuff we need. */
return -TARGET_EINVAL;
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 4/6] target/alpha: Implement prctl_unalign_sigbus
2021-12-27 15:01 [PATCH v2 0/6] linux-user: prctl improvements Richard Henderson
` (2 preceding siblings ...)
2021-12-27 15:01 ` [PATCH v2 3/6] linux-user: Add code for PR_GET/SET_UNALIGN Richard Henderson
@ 2021-12-27 15:01 ` Richard Henderson
2021-12-27 15:39 ` Laurent Vivier
2022-01-04 11:46 ` Laurent Vivier
2021-12-27 15:01 ` [PATCH v2 5/6] target/hppa: " Richard Henderson
2021-12-27 15:01 ` [PATCH v2 6/6] target/sh4: " Richard Henderson
5 siblings, 2 replies; 15+ messages in thread
From: Richard Henderson @ 2021-12-27 15:01 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/alpha/target_prctl.h | 2 +-
target/alpha/cpu.h | 5 +++++
target/alpha/translate.c | 31 ++++++++++++++++++++++---------
3 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h
index eb53b31ad5..5629ddbf39 100644
--- a/linux-user/alpha/target_prctl.h
+++ b/linux-user/alpha/target_prctl.h
@@ -1 +1 @@
-/* No special prctl support required. */
+#include "../generic/target_prctl_unalign.h"
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index afd975c878..e819211503 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -383,6 +383,8 @@ enum {
#define ENV_FLAG_TB_MASK \
(ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN)
+#define TB_FLAG_UNALIGN (1u << 1)
+
static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
{
int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
@@ -470,6 +472,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
*pc = env->pc;
*cs_base = 0;
*pflags = env->flags & ENV_FLAG_TB_MASK;
+#ifdef CONFIG_USER_ONLY
+ *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
}
#ifdef CONFIG_USER_ONLY
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index a4c3f43e72..208ae5fbd5 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext;
struct DisasContext {
DisasContextBase base;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ MemOp unalign;
+#else
uint64_t palbr;
#endif
uint32_t tbflags;
@@ -68,6 +70,12 @@ struct DisasContext {
TCGv sink;
};
+#ifdef CONFIG_USER_ONLY
+#define UNALIGN(C) (C)->unalign
+#else
+#define UNALIGN(C) 0
+#endif
+
/* Target-specific return values from translate_one, indicating the
state of the TB. Note that DISAS_NEXT indicates that we are not
exiting the TB. */
@@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx)
static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
gen_helper_memory_to_f(dest, tmp32);
tcg_temp_free_i32(tmp32);
}
@@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr)
static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv tmp = tcg_temp_new();
- tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
+ tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
gen_helper_memory_to_g(dest, tmp);
tcg_temp_free(tmp);
}
@@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr)
static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
gen_helper_memory_to_s(dest, tmp32);
tcg_temp_free_i32(tmp32);
}
static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr)
{
- tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ);
+ tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
}
static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
@@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
if (clear) {
tcg_gen_andi_i64(addr, addr, ~0x7);
+ } else if (!locked) {
+ op |= UNALIGN(ctx);
}
dest = ctx->ir[ra];
@@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
gen_helper_f_to_memory(tmp32, addr);
- tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
tcg_temp_free_i32(tmp32);
}
@@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv tmp = tcg_temp_new();
gen_helper_g_to_memory(tmp, src);
- tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
+ tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
tcg_temp_free(tmp);
}
@@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
gen_helper_s_to_memory(tmp32, src);
- tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
tcg_temp_free_i32(tmp32);
}
static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr)
{
- tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ);
+ tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
}
static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
@@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
if (clear) {
tcg_gen_andi_i64(addr, addr, ~0x7);
+ } else {
+ op |= UNALIGN(ctx);
}
src = load_gpr(ctx, ra);
@@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
#ifdef CONFIG_USER_ONLY
ctx->ir = cpu_std_ir;
+ ctx->unalign = (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN);
#else
ctx->palbr = env->palbr;
ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir);
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 4/6] target/alpha: Implement prctl_unalign_sigbus
2021-12-27 15:01 ` [PATCH v2 4/6] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
@ 2021-12-27 15:39 ` Laurent Vivier
2022-01-04 11:46 ` Laurent Vivier
1 sibling, 0 replies; 15+ messages in thread
From: Laurent Vivier @ 2021-12-27 15:39 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Le 27/12/2021 à 16:01, Richard Henderson a écrit :
> Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
> flag to set MO_UNALN for the instructions that the kernel
> handles in the unaligned trap.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/alpha/target_prctl.h | 2 +-
> target/alpha/cpu.h | 5 +++++
> target/alpha/translate.c | 31 ++++++++++++++++++++++---------
> 3 files changed, 28 insertions(+), 10 deletions(-)
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 4/6] target/alpha: Implement prctl_unalign_sigbus
2021-12-27 15:01 ` [PATCH v2 4/6] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
2021-12-27 15:39 ` Laurent Vivier
@ 2022-01-04 11:46 ` Laurent Vivier
1 sibling, 0 replies; 15+ messages in thread
From: Laurent Vivier @ 2022-01-04 11:46 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Le 27/12/2021 à 16:01, Richard Henderson a écrit :
> Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
> flag to set MO_UNALN for the instructions that the kernel
> handles in the unaligned trap.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/alpha/target_prctl.h | 2 +-
> target/alpha/cpu.h | 5 +++++
> target/alpha/translate.c | 31 ++++++++++++++++++++++---------
> 3 files changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h
> index eb53b31ad5..5629ddbf39 100644
> --- a/linux-user/alpha/target_prctl.h
> +++ b/linux-user/alpha/target_prctl.h
> @@ -1 +1 @@
> -/* No special prctl support required. */
> +#include "../generic/target_prctl_unalign.h"
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index afd975c878..e819211503 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -383,6 +383,8 @@ enum {
> #define ENV_FLAG_TB_MASK \
> (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN)
>
> +#define TB_FLAG_UNALIGN (1u << 1)
> +
> static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
> {
> int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
> @@ -470,6 +472,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
> *pc = env->pc;
> *cs_base = 0;
> *pflags = env->flags & ENV_FLAG_TB_MASK;
> +#ifdef CONFIG_USER_ONLY
> + *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
> +#endif
> }
>
> #ifdef CONFIG_USER_ONLY
> diff --git a/target/alpha/translate.c b/target/alpha/translate.c
> index a4c3f43e72..208ae5fbd5 100644
> --- a/target/alpha/translate.c
> +++ b/target/alpha/translate.c
> @@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext;
> struct DisasContext {
> DisasContextBase base;
>
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + MemOp unalign;
> +#else
> uint64_t palbr;
> #endif
> uint32_t tbflags;
> @@ -68,6 +70,12 @@ struct DisasContext {
> TCGv sink;
> };
>
> +#ifdef CONFIG_USER_ONLY
> +#define UNALIGN(C) (C)->unalign
> +#else
> +#define UNALIGN(C) 0
> +#endif
> +
> /* Target-specific return values from translate_one, indicating the
> state of the TB. Note that DISAS_NEXT indicates that we are not
> exiting the TB. */
> @@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx)
> static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr)
> {
> TCGv_i32 tmp32 = tcg_temp_new_i32();
> - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
> + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
> gen_helper_memory_to_f(dest, tmp32);
> tcg_temp_free_i32(tmp32);
> }
> @@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr)
> static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr)
> {
> TCGv tmp = tcg_temp_new();
> - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
> + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
> gen_helper_memory_to_g(dest, tmp);
> tcg_temp_free(tmp);
> }
> @@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr)
> static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr)
> {
> TCGv_i32 tmp32 = tcg_temp_new_i32();
> - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
> + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
> gen_helper_memory_to_s(dest, tmp32);
> tcg_temp_free_i32(tmp32);
> }
>
> static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr)
> {
> - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ);
> + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
> }
>
> static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
> @@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
> tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
> if (clear) {
> tcg_gen_andi_i64(addr, addr, ~0x7);
> + } else if (!locked) {
> + op |= UNALIGN(ctx);
> }
>
> dest = ctx->ir[ra];
> @@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr)
> {
> TCGv_i32 tmp32 = tcg_temp_new_i32();
> gen_helper_f_to_memory(tmp32, addr);
> - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
> + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
> tcg_temp_free_i32(tmp32);
> }
>
> @@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr)
> {
> TCGv tmp = tcg_temp_new();
> gen_helper_g_to_memory(tmp, src);
> - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
> + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
> tcg_temp_free(tmp);
> }
>
> @@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr)
> {
> TCGv_i32 tmp32 = tcg_temp_new_i32();
> gen_helper_s_to_memory(tmp32, src);
> - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
> + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
> tcg_temp_free_i32(tmp32);
> }
>
> static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr)
> {
> - tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ);
> + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
> }
>
> static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
> @@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
> tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
> if (clear) {
> tcg_gen_andi_i64(addr, addr, ~0x7);
> + } else {
> + op |= UNALIGN(ctx);
> }
>
> src = load_gpr(ctx, ra);
> @@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
>
> #ifdef CONFIG_USER_ONLY
> ctx->ir = cpu_std_ir;
> + ctx->unalign = (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN);
> #else
> ctx->palbr = env->palbr;
> ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir);
Applied to my linux-user-for-7.0 branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 5/6] target/hppa: Implement prctl_unalign_sigbus
2021-12-27 15:01 [PATCH v2 0/6] linux-user: prctl improvements Richard Henderson
` (3 preceding siblings ...)
2021-12-27 15:01 ` [PATCH v2 4/6] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
@ 2021-12-27 15:01 ` Richard Henderson
2021-12-27 15:39 ` Laurent Vivier
2022-01-04 11:47 ` Laurent Vivier
2021-12-27 15:01 ` [PATCH v2 6/6] target/sh4: " Richard Henderson
5 siblings, 2 replies; 15+ messages in thread
From: Richard Henderson @ 2021-12-27 15:01 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/hppa/target_prctl.h | 2 +-
target/hppa/cpu.h | 5 ++++-
target/hppa/translate.c | 19 +++++++++++++++----
3 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h
index eb53b31ad5..5629ddbf39 100644
--- a/linux-user/hppa/target_prctl.h
+++ b/linux-user/hppa/target_prctl.h
@@ -1 +1 @@
-/* No special prctl support required. */
+#include "../generic/target_prctl_unalign.h"
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 294fd7297f..45fd338b02 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
return hppa_form_gva_psw(env->psw, spc, off);
}
-/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
+/*
+ * Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
* TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
* same value.
*/
#define TB_FLAG_SR_SAME PSW_I
#define TB_FLAG_PRIV_SHIFT 8
+#define TB_FLAG_UNALIGN 0x400
static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
target_ulong *cs_base,
@@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
#ifdef CONFIG_USER_ONLY
*pc = env->iaoq_f & -4;
*cs_base = env->iaoq_b & -4;
+ flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
#else
/* ??? E, T, H, L, B, P bits need to be here, when implemented. */
flags |= env->psw & (PSW_W | PSW_C | PSW_D);
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 952027a28e..a2392a1b64 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -274,8 +274,18 @@ typedef struct DisasContext {
int mmu_idx;
int privilege;
bool psw_n_nonzero;
+
+#ifdef CONFIG_USER_ONLY
+ MemOp unalign;
+#endif
} DisasContext;
+#ifdef CONFIG_USER_ONLY
+#define UNALIGN(C) (C)->unalign
+#else
+#define UNALIGN(C) 0
+#endif
+
/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
static int expand_sm_imm(DisasContext *ctx, int val)
{
@@ -1475,7 +1485,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
- tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop);
+ tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
}
@@ -1493,7 +1503,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
- tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop);
+ tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
}
@@ -1511,7 +1521,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
- tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop);
+ tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
}
@@ -1529,7 +1539,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
- tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop);
+ tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
}
@@ -4107,6 +4117,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->mmu_idx = MMU_USER_IDX;
ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX;
ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX;
+ ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN);
#else
ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3;
ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX);
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 5/6] target/hppa: Implement prctl_unalign_sigbus
2021-12-27 15:01 ` [PATCH v2 5/6] target/hppa: " Richard Henderson
@ 2021-12-27 15:39 ` Laurent Vivier
2022-01-04 11:47 ` Laurent Vivier
1 sibling, 0 replies; 15+ messages in thread
From: Laurent Vivier @ 2021-12-27 15:39 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Le 27/12/2021 à 16:01, Richard Henderson a écrit :
> Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
> flag to set MO_UNALN for the instructions that the kernel
> handles in the unaligned trap.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/hppa/target_prctl.h | 2 +-
> target/hppa/cpu.h | 5 ++++-
> target/hppa/translate.c | 19 +++++++++++++++----
> 3 files changed, 20 insertions(+), 6 deletions(-)
>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 5/6] target/hppa: Implement prctl_unalign_sigbus
2021-12-27 15:01 ` [PATCH v2 5/6] target/hppa: " Richard Henderson
2021-12-27 15:39 ` Laurent Vivier
@ 2022-01-04 11:47 ` Laurent Vivier
1 sibling, 0 replies; 15+ messages in thread
From: Laurent Vivier @ 2022-01-04 11:47 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Le 27/12/2021 à 16:01, Richard Henderson a écrit :
> Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
> flag to set MO_UNALN for the instructions that the kernel
> handles in the unaligned trap.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/hppa/target_prctl.h | 2 +-
> target/hppa/cpu.h | 5 ++++-
> target/hppa/translate.c | 19 +++++++++++++++----
> 3 files changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h
> index eb53b31ad5..5629ddbf39 100644
> --- a/linux-user/hppa/target_prctl.h
> +++ b/linux-user/hppa/target_prctl.h
> @@ -1 +1 @@
> -/* No special prctl support required. */
> +#include "../generic/target_prctl_unalign.h"
> diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
> index 294fd7297f..45fd338b02 100644
> --- a/target/hppa/cpu.h
> +++ b/target/hppa/cpu.h
> @@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
> return hppa_form_gva_psw(env->psw, spc, off);
> }
>
> -/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
> +/*
> + * Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
> * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
> * same value.
> */
> #define TB_FLAG_SR_SAME PSW_I
> #define TB_FLAG_PRIV_SHIFT 8
> +#define TB_FLAG_UNALIGN 0x400
>
> static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
> target_ulong *cs_base,
> @@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
> #ifdef CONFIG_USER_ONLY
> *pc = env->iaoq_f & -4;
> *cs_base = env->iaoq_b & -4;
> + flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
> #else
> /* ??? E, T, H, L, B, P bits need to be here, when implemented. */
> flags |= env->psw & (PSW_W | PSW_C | PSW_D);
> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
> index 952027a28e..a2392a1b64 100644
> --- a/target/hppa/translate.c
> +++ b/target/hppa/translate.c
> @@ -274,8 +274,18 @@ typedef struct DisasContext {
> int mmu_idx;
> int privilege;
> bool psw_n_nonzero;
> +
> +#ifdef CONFIG_USER_ONLY
> + MemOp unalign;
> +#endif
> } DisasContext;
>
> +#ifdef CONFIG_USER_ONLY
> +#define UNALIGN(C) (C)->unalign
> +#else
> +#define UNALIGN(C) 0
> +#endif
> +
> /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
> static int expand_sm_imm(DisasContext *ctx, int val)
> {
> @@ -1475,7 +1485,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
>
> form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
> ctx->mmu_idx == MMU_PHYS_IDX);
> - tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop);
> + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
> if (modify) {
> save_gpr(ctx, rb, ofs);
> }
> @@ -1493,7 +1503,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
>
> form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
> ctx->mmu_idx == MMU_PHYS_IDX);
> - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop);
> + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
> if (modify) {
> save_gpr(ctx, rb, ofs);
> }
> @@ -1511,7 +1521,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
>
> form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
> ctx->mmu_idx == MMU_PHYS_IDX);
> - tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop);
> + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
> if (modify) {
> save_gpr(ctx, rb, ofs);
> }
> @@ -1529,7 +1539,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
>
> form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
> ctx->mmu_idx == MMU_PHYS_IDX);
> - tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop);
> + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
> if (modify) {
> save_gpr(ctx, rb, ofs);
> }
> @@ -4107,6 +4117,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->mmu_idx = MMU_USER_IDX;
> ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX;
> ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX;
> + ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN);
> #else
> ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3;
> ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX);
Applied to my linux-user-for-7.0 branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 6/6] target/sh4: Implement prctl_unalign_sigbus
2021-12-27 15:01 [PATCH v2 0/6] linux-user: prctl improvements Richard Henderson
` (4 preceding siblings ...)
2021-12-27 15:01 ` [PATCH v2 5/6] target/hppa: " Richard Henderson
@ 2021-12-27 15:01 ` Richard Henderson
2021-12-27 15:40 ` Laurent Vivier
2022-01-04 11:47 ` Laurent Vivier
5 siblings, 2 replies; 15+ messages in thread
From: Richard Henderson @ 2021-12-27 15:01 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
The Linux kernel does not handle all memory operations: no
floating-point and no MAC.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/sh4/target_prctl.h | 2 +-
target/sh4/cpu.h | 4 +++
target/sh4/translate.c | 50 ++++++++++++++++++++++++-----------
3 files changed, 39 insertions(+), 17 deletions(-)
diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h
index eb53b31ad5..5629ddbf39 100644
--- a/linux-user/sh4/target_prctl.h
+++ b/linux-user/sh4/target_prctl.h
@@ -1 +1 @@
-/* No special prctl support required. */
+#include "../generic/target_prctl_unalign.h"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 4cfb109f56..fb9dd9db2f 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -83,6 +83,7 @@
#define DELAY_SLOT_RTE (1 << 2)
#define TB_FLAG_PENDING_MOVCA (1 << 3)
+#define TB_FLAG_UNALIGN (1 << 4)
#define GUSA_SHIFT 4
#ifdef CONFIG_USER_ONLY
@@ -373,6 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
| (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
| (env->sr & (1u << SR_FD)) /* Bit 15 */
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
+#ifdef CONFIG_USER_ONLY
+ *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
}
#endif /* SH4_CPU_H */
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index ce5d674a52..50493c61ea 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -50,8 +50,10 @@ typedef struct DisasContext {
#if defined(CONFIG_USER_ONLY)
#define IS_USER(ctx) 1
+#define UNALIGN(C) (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN)
#else
#define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))
+#define UNALIGN(C) 0
#endif
/* Target-specific values for ctx->base.is_jmp. */
@@ -495,7 +497,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -503,7 +506,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
- tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -558,19 +562,23 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB);
return;
case 0x2001: /* mov.w Rm,@Rn */
- tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
return;
case 0x2002: /* mov.l Rm,@Rn */
- tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
return;
case 0x6000: /* mov.b @Rm,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
return;
case 0x6001: /* mov.w @Rm,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
return;
case 0x6002: /* mov.l @Rm,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
return;
case 0x2004: /* mov.b Rm,@-Rn */
{
@@ -586,7 +594,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 2);
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
}
@@ -595,7 +604,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
}
@@ -606,12 +616,14 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
return;
case 0x6005: /* mov.w @Rm+,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
return;
case 0x6006: /* mov.l @Rm+,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
return;
@@ -627,7 +639,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -635,7 +648,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -651,7 +665,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
- tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -659,7 +674,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
- tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -1253,7 +1269,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
- tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -1269,7 +1286,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
- tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 6/6] target/sh4: Implement prctl_unalign_sigbus
2021-12-27 15:01 ` [PATCH v2 6/6] target/sh4: " Richard Henderson
@ 2021-12-27 15:40 ` Laurent Vivier
2022-01-04 11:47 ` Laurent Vivier
1 sibling, 0 replies; 15+ messages in thread
From: Laurent Vivier @ 2021-12-27 15:40 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Le 27/12/2021 à 16:01, Richard Henderson a écrit :
> Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
> flag to set MO_UNALN for the instructions that the kernel
> handles in the unaligned trap.
>
> The Linux kernel does not handle all memory operations: no
> floating-point and no MAC.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/sh4/target_prctl.h | 2 +-
> target/sh4/cpu.h | 4 +++
> target/sh4/translate.c | 50 ++++++++++++++++++++++++-----------
> 3 files changed, 39 insertions(+), 17 deletions(-)
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 6/6] target/sh4: Implement prctl_unalign_sigbus
2021-12-27 15:01 ` [PATCH v2 6/6] target/sh4: " Richard Henderson
2021-12-27 15:40 ` Laurent Vivier
@ 2022-01-04 11:47 ` Laurent Vivier
1 sibling, 0 replies; 15+ messages in thread
From: Laurent Vivier @ 2022-01-04 11:47 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Le 27/12/2021 à 16:01, Richard Henderson a écrit :
> Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
> flag to set MO_UNALN for the instructions that the kernel
> handles in the unaligned trap.
>
> The Linux kernel does not handle all memory operations: no
> floating-point and no MAC.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/sh4/target_prctl.h | 2 +-
> target/sh4/cpu.h | 4 +++
> target/sh4/translate.c | 50 ++++++++++++++++++++++++-----------
> 3 files changed, 39 insertions(+), 17 deletions(-)
>
> diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h
> index eb53b31ad5..5629ddbf39 100644
> --- a/linux-user/sh4/target_prctl.h
> +++ b/linux-user/sh4/target_prctl.h
> @@ -1 +1 @@
> -/* No special prctl support required. */
> +#include "../generic/target_prctl_unalign.h"
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index 4cfb109f56..fb9dd9db2f 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -83,6 +83,7 @@
> #define DELAY_SLOT_RTE (1 << 2)
>
> #define TB_FLAG_PENDING_MOVCA (1 << 3)
> +#define TB_FLAG_UNALIGN (1 << 4)
>
> #define GUSA_SHIFT 4
> #ifdef CONFIG_USER_ONLY
> @@ -373,6 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
> | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
> | (env->sr & (1u << SR_FD)) /* Bit 15 */
> | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
> +#ifdef CONFIG_USER_ONLY
> + *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
> +#endif
> }
>
> #endif /* SH4_CPU_H */
> diff --git a/target/sh4/translate.c b/target/sh4/translate.c
> index ce5d674a52..50493c61ea 100644
> --- a/target/sh4/translate.c
> +++ b/target/sh4/translate.c
> @@ -50,8 +50,10 @@ typedef struct DisasContext {
>
> #if defined(CONFIG_USER_ONLY)
> #define IS_USER(ctx) 1
> +#define UNALIGN(C) (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN)
> #else
> #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))
> +#define UNALIGN(C) 0
> #endif
>
> /* Target-specific values for ctx->base.is_jmp. */
> @@ -495,7 +497,8 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
> - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
> + MO_TEUL | UNALIGN(ctx));
> tcg_temp_free(addr);
> }
> return;
> @@ -503,7 +506,8 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
> - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
> + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
> + MO_TESL | UNALIGN(ctx));
> tcg_temp_free(addr);
> }
> return;
> @@ -558,19 +562,23 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB);
> return;
> case 0x2001: /* mov.w Rm,@Rn */
> - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW);
> + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
> + MO_TEUW | UNALIGN(ctx));
> return;
> case 0x2002: /* mov.l Rm,@Rn */
> - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
> + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
> + MO_TEUL | UNALIGN(ctx));
> return;
> case 0x6000: /* mov.b @Rm,Rn */
> tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
> return;
> case 0x6001: /* mov.w @Rm,Rn */
> - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
> + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
> + MO_TESW | UNALIGN(ctx));
> return;
> case 0x6002: /* mov.l @Rm,Rn */
> - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
> + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
> + MO_TESL | UNALIGN(ctx));
> return;
> case 0x2004: /* mov.b Rm,@-Rn */
> {
> @@ -586,7 +594,8 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_subi_i32(addr, REG(B11_8), 2);
> - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
> + MO_TEUW | UNALIGN(ctx));
> tcg_gen_mov_i32(REG(B11_8), addr);
> tcg_temp_free(addr);
> }
> @@ -595,7 +604,8 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_subi_i32(addr, REG(B11_8), 4);
> - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
> + MO_TEUL | UNALIGN(ctx));
> tcg_gen_mov_i32(REG(B11_8), addr);
> tcg_temp_free(addr);
> }
> @@ -606,12 +616,14 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
> return;
> case 0x6005: /* mov.w @Rm+,Rn */
> - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
> + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
> + MO_TESW | UNALIGN(ctx));
> if ( B11_8 != B7_4 )
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
> return;
> case 0x6006: /* mov.l @Rm+,Rn */
> - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
> + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
> + MO_TESL | UNALIGN(ctx));
> if ( B11_8 != B7_4 )
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> return;
> @@ -627,7 +639,8 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B11_8), REG(0));
> - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
> + MO_TEUW | UNALIGN(ctx));
> tcg_temp_free(addr);
> }
> return;
> @@ -635,7 +648,8 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B11_8), REG(0));
> - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
> + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
> + MO_TEUL | UNALIGN(ctx));
> tcg_temp_free(addr);
> }
> return;
> @@ -651,7 +665,8 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B7_4), REG(0));
> - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
> + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
> + MO_TESW | UNALIGN(ctx));
> tcg_temp_free(addr);
> }
> return;
> @@ -659,7 +674,8 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B7_4), REG(0));
> - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
> + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
> + MO_TESL | UNALIGN(ctx));
> tcg_temp_free(addr);
> }
> return;
> @@ -1253,7 +1269,8 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
> - tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW);
> + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx,
> + MO_TEUW | UNALIGN(ctx));
> tcg_temp_free(addr);
> }
> return;
> @@ -1269,7 +1286,8 @@ static void _decode_opc(DisasContext * ctx)
> {
> TCGv addr = tcg_temp_new();
> tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
> - tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW);
> + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx,
> + MO_TESW | UNALIGN(ctx));
> tcg_temp_free(addr);
> }
> return;
Applied to my linux-user-for-7.0 branch.
Thanks,
Laurent
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