From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
Date: Wed, 5 Jan 2022 11:01:19 +0800 [thread overview]
Message-ID: <20220105030126.778503-1-bin.meng@windriver.com> (raw)
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented is 2, which is the number that we can
find in the SiFive U54/U74 cores.
[1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
Changes in v3:
- drop riscv_trigger_init(), which will be moved to patch #5
- add riscv_trigger_init(), moved from patch #1 to this patch
- enable debug feature by default for all CPUs
Changes in v2:
- new patch: add debug state description
- use 0 instead of GETPC()
- change the config option to 'disabled' by default
Bin Meng (7):
target/riscv: Add initial support for native debug
target/riscv: machine: Add debug state description
target/riscv: debug: Implement debug related TCGCPUOps
target/riscv: cpu: Add a config option for native debug
target/riscv: csr: Hook debug CSR read/write
target/riscv: cpu: Enable native debug feature
hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
include/hw/core/tcg-cpu-ops.h | 1 +
target/riscv/cpu.h | 7 +
target/riscv/debug.h | 114 +++++++++
target/riscv/cpu.c | 14 ++
target/riscv/csr.c | 57 +++++
target/riscv/debug.c | 441 ++++++++++++++++++++++++++++++++++
target/riscv/machine.c | 33 +++
target/riscv/meson.build | 1 +
8 files changed, 668 insertions(+)
create mode 100644 target/riscv/debug.h
create mode 100644 target/riscv/debug.c
--
2.25.1
next reply other threads:[~2022-01-05 3:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-05 3:01 Bin Meng [this message]
2022-01-05 3:01 ` [PATCH v3 1/7] target/riscv: Add initial support for native debug Bin Meng
2022-01-05 3:01 ` [PATCH v3 2/7] target/riscv: machine: Add debug state description Bin Meng
2022-01-05 3:01 ` [PATCH v3 3/7] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2022-01-05 3:01 ` [PATCH v3 4/7] target/riscv: cpu: Add a config option for native debug Bin Meng
2022-01-05 3:01 ` [PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write Bin Meng
2022-01-05 3:01 ` [PATCH v3 6/7] target/riscv: cpu: Enable native debug feature Bin Meng
2022-01-05 3:01 ` [PATCH v3 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng
2022-01-05 3:01 ` Bin Meng
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