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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v3 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
Date: Wed,  5 Jan 2022 11:01:26 +0800	[thread overview]
Message-ID: <20220105030126.778503-8-bin.meng@windriver.com> (raw)
In-Reply-To: <20220105030126.778503-1-bin.meng@windriver.com>

This is now used by RISC-V as well. Update the comments.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

---

(no changes since v1)

 include/hw/core/tcg-cpu-ops.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index e13898553a..f98671ff32 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -90,6 +90,7 @@ struct TCGCPUOps {
     /**
      * @debug_check_watchpoint: return true if the architectural
      * watchpoint whose address has matched should really fire, used by ARM
+     * and RISC-V
      */
     bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
 
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v3 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
Date: Wed,  5 Jan 2022 11:01:26 +0800	[thread overview]
Message-ID: <20220105030126.778503-8-bin.meng@windriver.com> (raw)
In-Reply-To: <20220105030126.778503-1-bin.meng@windriver.com>

This is now used by RISC-V as well. Update the comments.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

---

(no changes since v1)

 include/hw/core/tcg-cpu-ops.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index e13898553a..f98671ff32 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -90,6 +90,7 @@ struct TCGCPUOps {
     /**
      * @debug_check_watchpoint: return true if the architectural
      * watchpoint whose address has matched should really fire, used by ARM
+     * and RISC-V
      */
     bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
 
-- 
2.25.1



  parent reply	other threads:[~2022-01-05  3:16 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-05  3:01 [PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs Bin Meng
2022-01-05  3:01 ` [PATCH v3 1/7] target/riscv: Add initial support for native debug Bin Meng
2022-01-05  3:01 ` [PATCH v3 2/7] target/riscv: machine: Add debug state description Bin Meng
2022-01-05  3:01 ` [PATCH v3 3/7] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2022-01-05  3:01 ` [PATCH v3 4/7] target/riscv: cpu: Add a config option for native debug Bin Meng
2022-01-05  3:01 ` [PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write Bin Meng
2022-01-05  3:01 ` [PATCH v3 6/7] target/riscv: cpu: Enable native debug feature Bin Meng
2022-01-05  3:01 ` Bin Meng [this message]
2022-01-05  3:01   ` [PATCH v3 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng

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