* [RESEND PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
@ 2022-01-05 3:06 Bin Meng
0 siblings, 0 replies; 2+ messages in thread
From: Bin Meng @ 2022-01-05 3:06 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented is 2, which is the number that we can
find in the SiFive U54/U74 cores.
[1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
- RESEND to correct the email address
Changes in v3:
- drop riscv_trigger_init(), which will be moved to patch #5
- add riscv_trigger_init(), moved from patch #1 to this patch
- enable debug feature by default for all CPUs
Changes in v2:
- new patch: add debug state description
- use 0 instead of GETPC()
- change the config option to 'disabled' by default
Bin Meng (7):
target/riscv: Add initial support for native debug
target/riscv: machine: Add debug state description
target/riscv: debug: Implement debug related TCGCPUOps
target/riscv: cpu: Add a config option for native debug
target/riscv: csr: Hook debug CSR read/write
target/riscv: cpu: Enable native debug feature
hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
include/hw/core/tcg-cpu-ops.h | 1 +
target/riscv/cpu.h | 7 +
target/riscv/debug.h | 114 +++++++++
target/riscv/cpu.c | 14 ++
target/riscv/csr.c | 57 +++++
target/riscv/debug.c | 441 ++++++++++++++++++++++++++++++++++
target/riscv/machine.c | 33 +++
target/riscv/meson.build | 1 +
8 files changed, 668 insertions(+)
create mode 100644 target/riscv/debug.h
create mode 100644 target/riscv/debug.c
--
2.25.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* [RESEND PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
@ 2022-01-05 3:08 Bin Meng
0 siblings, 0 replies; 2+ messages in thread
From: Bin Meng @ 2022-01-05 3:08 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
This adds initial support for the native debug via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented is 2, which is the number that we can
find in the SiFive U54/U74 cores.
[1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
- RESEND to correct the email address
Changes in v3:
- drop riscv_trigger_init(), which will be moved to patch #5
- add riscv_trigger_init(), moved from patch #1 to this patch
- enable debug feature by default for all CPUs
Changes in v2:
- new patch: add debug state description
- use 0 instead of GETPC()
- change the config option to 'disabled' by default
Bin Meng (7):
target/riscv: Add initial support for native debug
target/riscv: machine: Add debug state description
target/riscv: debug: Implement debug related TCGCPUOps
target/riscv: cpu: Add a config option for native debug
target/riscv: csr: Hook debug CSR read/write
target/riscv: cpu: Enable native debug feature
hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
include/hw/core/tcg-cpu-ops.h | 1 +
target/riscv/cpu.h | 7 +
target/riscv/debug.h | 114 +++++++++
target/riscv/cpu.c | 14 ++
target/riscv/csr.c | 57 +++++
target/riscv/debug.c | 441 ++++++++++++++++++++++++++++++++++
target/riscv/machine.c | 33 +++
target/riscv/meson.build | 1 +
8 files changed, 668 insertions(+)
create mode 100644 target/riscv/debug.h
create mode 100644 target/riscv/debug.c
--
2.25.1
^ permalink raw reply [flat|nested] 2+ messages in thread
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2022-01-05 3:06 [RESEND PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs Bin Meng
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