* [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection @ 2022-01-05 6:49 Zbigniew Kempczyński 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_memory_region: " Zbigniew Kempczyński ` (4 more replies) 0 siblings, 5 replies; 16+ messages in thread From: Zbigniew Kempczyński @ 2022-01-05 6:49 UTC (permalink / raw) To: igt-dev Add some universal code which tries to detect kernel offset capabilities. v2: unify cache, fix start offset iteration run gem_softpin@safe-alignment also on integrated v3: move cache entry out of mutex v4: avoid assert and skip adding to cache if there's no memory rename to safe-start verify safe start offset on each engine v5: fix function doc (Ashutosh) Zbigniew Kempczyński (3): lib/intel_memory_region: Add start offset and alignment detection tests/i915/gem_softpin: Add safe-start test tests/fast-feedback.testlist: Add gem_softpin@safe-start subtest lib/i915/intel_memory_region.c | 371 ++++++++++++++++++++++++++ lib/i915/intel_memory_region.h | 5 + tests/i915/gem_softpin.c | 87 ++++++ tests/intel-ci/fast-feedback.testlist | 1 + 4 files changed, 464 insertions(+) -- 2.32.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 1/3] lib/intel_memory_region: Add start offset and alignment detection 2022-01-05 6:49 [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection Zbigniew Kempczyński @ 2022-01-05 6:49 ` Zbigniew Kempczyński 2022-01-06 2:23 ` Dixit, Ashutosh 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 2/3] tests/i915/gem_softpin: Add safe-start test Zbigniew Kempczyński ` (3 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Zbigniew Kempczyński @ 2022-01-05 6:49 UTC (permalink / raw) To: igt-dev; +Cc: Petri Latvala With era of new gens we're enforced to use no-reloc (softpin). This brings few problems like vm range limitations which were well solved by the kernel. This can be handled also in userspace code by adding gen related conditionals or by trying to detect the constraints. Lets try to do this dynamically and detect safe start offset and alignment for each memory region we got. This should be universal solution regardless hw limitations and bugs. As such detection is not lightweight technique add also some caching structures to handle consequtive calls about same data. v2: unify cache v3: move allocation of cache entry out of mutex v4: remove assert on allocation newentry, just skip adding to cache v5: fix function documentation (Ashutosh) Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Petri Latvala <petri.latvala@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> --- lib/i915/intel_memory_region.c | 371 +++++++++++++++++++++++++++++++++ lib/i915/intel_memory_region.h | 5 + 2 files changed, 376 insertions(+) diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c index dfbb8acf0..c54dc03b1 100644 --- a/lib/i915/intel_memory_region.c +++ b/lib/i915/intel_memory_region.c @@ -28,11 +28,13 @@ #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> +#include <pthread.h> #include "i915/gem_create.h" #include "intel_reg.h" #include "drmtest.h" #include "ioctl_wrappers.h" +#include "igt_aux.h" #include "igt_dummyload.h" #include "igt_gt.h" #include "igt_params.h" @@ -40,6 +42,7 @@ #include "intel_chipset.h" #include "igt_collection.h" #include "igt_device.h" +#include "gem_mman.h" #include "i915/intel_memory_region.h" @@ -480,3 +483,371 @@ uint64_t gpu_meminfo_region_available(const struct drm_i915_query_memory_regions return 0; } + +#define PAGE_SIZE 4096 + +enum cache_entry_type { + MIN_START_OFFSET, + MIN_ALIGNMENT, + SAFE_START_OFFSET, + SAFE_ALIGNMENT, +}; + +struct cache_entry { + uint16_t devid; + enum cache_entry_type type; + + union { + /* for MIN_START_OFFSET */ + struct { + uint64_t offset; + uint32_t region; + } start; + + /* for MIN_ALIGNMENT */ + struct { + uint64_t alignment; + uint64_t region1; + uint64_t region2; + } minalign; + + /* for SAFE_START_OFFSET */ + uint64_t safe_start_offset; + + /* for SAFE_ALIGNMENT */ + uint64_t safe_alignment; + }; + struct igt_list_head link; +}; + +static IGT_LIST_HEAD(cache); +static pthread_mutex_t cache_mutex = PTHREAD_MUTEX_INITIALIZER; + +static struct cache_entry *find_entry_unlocked(enum cache_entry_type type, + uint16_t devid, + uint32_t region1, + uint32_t region2) +{ + struct cache_entry *entry; + + igt_list_for_each_entry(entry, &cache, link) { + if (entry->type != type || entry->devid != devid) + continue; + + switch (entry->type) { + case MIN_START_OFFSET: + if (entry->start.region == region1) + return entry; + continue; + + case MIN_ALIGNMENT: + if (entry->minalign.region1 == region1 && + entry->minalign.region2 == region2) + return entry; + continue; + + case SAFE_START_OFFSET: + case SAFE_ALIGNMENT: + return entry; + } + } + + return NULL; +} + +/** + * gem_detect_min_start_offset_for_region: + * @i915: drm fd + * @region: memory region + * + * Returns: minimum start offset at which kernel allows placing objects + * for memory region. + */ +uint64_t gem_detect_min_start_offset_for_region(int i915, uint32_t region) +{ + struct drm_i915_gem_exec_object2 obj; + struct drm_i915_gem_execbuffer2 eb; + uint64_t start_offset = 0; + uint64_t bb_size = PAGE_SIZE; + uint32_t *batch; + uint16_t devid = intel_get_drm_devid(i915); + struct cache_entry *entry, *newentry; + + pthread_mutex_lock(&cache_mutex); + entry = find_entry_unlocked(MIN_START_OFFSET, devid, region, 0); + if (entry) + goto out; + pthread_mutex_unlock(&cache_mutex); + + memset(&obj, 0, sizeof(obj)); + memset(&eb, 0, sizeof(eb)); + + eb.buffers_ptr = to_user_pointer(&obj); + eb.buffer_count = 1; + eb.flags = I915_EXEC_DEFAULT; + igt_assert(__gem_create_in_memory_regions(i915, &obj.handle, &bb_size, region) == 0); + obj.flags = EXEC_OBJECT_PINNED; + + batch = gem_mmap__device_coherent(i915, obj.handle, 0, bb_size, PROT_WRITE); + *batch = MI_BATCH_BUFFER_END; + munmap(batch, bb_size); + + while (1) { + obj.offset = start_offset; + + if (__gem_execbuf(i915, &eb) == 0) + break; + + if (start_offset) + start_offset <<= 1; + else + start_offset = PAGE_SIZE; + + igt_assert(start_offset <= 1ull << 48); + } + gem_close(i915, obj.handle); + + newentry = malloc(sizeof(*newentry)); + if (!newentry) + return start_offset; + + /* Check does other thread did the job before */ + pthread_mutex_lock(&cache_mutex); + entry = find_entry_unlocked(MIN_START_OFFSET, devid, region, 0); + if (entry) + goto out; + + entry = newentry; + entry->devid = devid; + entry->type = MIN_START_OFFSET; + entry->start.offset = start_offset; + entry->start.region = region; + igt_list_add(&entry->link, &cache); + +out: + pthread_mutex_unlock(&cache_mutex); + + return entry->start.offset; +} + +/** + * gem_detect_safe_start_offset: + * @i915: drm fd + * + * Returns: finds start offset which can be used as first one regardless + * memory region. Useful if for some reason some regions don't allow + * starting from 0x0 offset. + */ +uint64_t gem_detect_safe_start_offset(int i915) +{ + struct drm_i915_query_memory_regions *query_info; + struct igt_collection *regions, *set; + uint32_t region; + uint64_t offset = 0; + uint16_t devid = intel_get_drm_devid(i915); + struct cache_entry *entry, *newentry; + + pthread_mutex_lock(&cache_mutex); + entry = find_entry_unlocked(SAFE_START_OFFSET, devid, 0, 0); + if (entry) + goto out; + pthread_mutex_unlock(&cache_mutex); + + query_info = gem_get_query_memory_regions(i915); + igt_assert(query_info); + + set = get_memory_region_set(query_info, + I915_SYSTEM_MEMORY, + I915_DEVICE_MEMORY); + + for_each_combination(regions, 1, set) { + region = igt_collection_get_value(regions, 0); + offset = max(offset, + gem_detect_min_start_offset_for_region(i915, region)); + } + free(query_info); + igt_collection_destroy(set); + + newentry = malloc(sizeof(*newentry)); + if (!newentry) + return offset; + + pthread_mutex_lock(&cache_mutex); + entry = find_entry_unlocked(SAFE_START_OFFSET, devid, 0, 0); + if (entry) + goto out; + + entry = newentry; + entry->devid = devid; + entry->type = SAFE_START_OFFSET; + entry->safe_start_offset = offset; + igt_list_add(&entry->link, &cache); + +out: + pthread_mutex_unlock(&cache_mutex); + + return entry->safe_start_offset; +} + +/** + * gem_detect_min_alignment_for_regions: + * @i915: drm fd + * @region1: first region + * @region2: second region + * + * Returns: minimum alignment which must be used when objects from @region1 and + * @region2 are going to interact. + */ +uint64_t gem_detect_min_alignment_for_regions(int i915, + uint32_t region1, + uint32_t region2) +{ + struct drm_i915_gem_exec_object2 obj[2]; + struct drm_i915_gem_execbuffer2 eb; + uint64_t min_alignment = PAGE_SIZE; + uint64_t bb_size = PAGE_SIZE, obj_size = PAGE_SIZE; + uint32_t *batch; + uint16_t devid = intel_get_drm_devid(i915); + struct cache_entry *entry, *newentry; + + pthread_mutex_lock(&cache_mutex); + entry = find_entry_unlocked(MIN_ALIGNMENT, devid, region1, region2); + if (entry) + goto out; + pthread_mutex_unlock(&cache_mutex); + + memset(obj, 0, sizeof(obj)); + memset(&eb, 0, sizeof(eb)); + + /* Establish bb offset first */ + eb.buffers_ptr = to_user_pointer(obj); + eb.buffer_count = 1; + eb.flags = I915_EXEC_BATCH_FIRST | I915_EXEC_DEFAULT; + igt_assert(__gem_create_in_memory_regions(i915, &obj[0].handle, + &bb_size, region1) == 0); + obj[0].flags = EXEC_OBJECT_PINNED; + + batch = gem_mmap__device_coherent(i915, obj[0].handle, 0, bb_size, + PROT_WRITE); + *batch = MI_BATCH_BUFFER_END; + munmap(batch, bb_size); + + obj[0].offset = gem_detect_min_start_offset_for_region(i915, region1); + + /* Find appropriate alignment of object */ + eb.buffer_count = ARRAY_SIZE(obj); + igt_assert(__gem_create_in_memory_regions(i915, &obj[1].handle, + &obj_size, region2) == 0); + obj[1].handle = gem_create_in_memory_regions(i915, PAGE_SIZE, region2); + obj[1].flags = EXEC_OBJECT_PINNED; + while (1) { + obj[1].offset = ALIGN(obj[0].offset + bb_size, min_alignment); + igt_assert(obj[1].offset <= 1ull << 32); + + if (__gem_execbuf(i915, &eb) == 0) + break; + + min_alignment <<= 1; + } + + gem_close(i915, obj[0].handle); + gem_close(i915, obj[1].handle); + + newentry = malloc(sizeof(*newentry)); + if (!newentry) + return min_alignment; + + pthread_mutex_lock(&cache_mutex); + entry = find_entry_unlocked(MIN_ALIGNMENT, devid, region1, region2); + if (entry) + goto out; + + entry = newentry; + entry->devid = devid; + entry->type = MIN_ALIGNMENT; + entry->minalign.alignment = min_alignment; + entry->minalign.region1 = region1; + entry->minalign.region2 = region2; + igt_list_add(&entry->link, &cache); + +out: + pthread_mutex_unlock(&cache_mutex); + + return entry->minalign.alignment; +} + +/** + * gem_detect_safe_alignment: + * @i915: drm fd + * + * Returns: safe alignment for all memory regions on @i915 device. + * Safe in this case means max() from all minimum alignments for each + * region. + */ +uint64_t gem_detect_safe_alignment(int i915) +{ + struct drm_i915_query_memory_regions *query_info; + struct igt_collection *regions, *set; + uint64_t default_alignment = 0; + uint32_t region_bb, region_obj; + uint16_t devid = intel_get_drm_devid(i915); + struct cache_entry *entry, *newentry; + + /* non-discrete uses 4K page size */ + if (!gem_has_lmem(i915)) + return PAGE_SIZE; + + pthread_mutex_lock(&cache_mutex); + entry = find_entry_unlocked(SAFE_ALIGNMENT, devid, 0, 0); + if (entry) + goto out; + pthread_mutex_unlock(&cache_mutex); + + query_info = gem_get_query_memory_regions(i915); + igt_assert(query_info); + + set = get_memory_region_set(query_info, + I915_SYSTEM_MEMORY, + I915_DEVICE_MEMORY); + + for_each_variation_r(regions, 2, set) { + uint64_t alignment; + + region_bb = igt_collection_get_value(regions, 0); + region_obj = igt_collection_get_value(regions, 1); + + /* We're interested in triangular matrix */ + if (region_bb > region_obj) + continue; + + alignment = gem_detect_min_alignment_for_regions(i915, + region_bb, + region_obj); + if (default_alignment < alignment) + default_alignment = alignment; + } + + free(query_info); + igt_collection_destroy(set); + + newentry = malloc(sizeof(*newentry)); + if (!newentry) + return default_alignment; + + /* Try again, check does we have cache updated in the meantime. */ + pthread_mutex_lock(&cache_mutex); + entry = find_entry_unlocked(SAFE_ALIGNMENT, devid, 0, 0); + if (entry) + goto out; + + entry = newentry; + entry->devid = devid; + entry->type = SAFE_ALIGNMENT; + entry->safe_alignment = default_alignment; + igt_list_add(&entry->link, &cache); + +out: + pthread_mutex_unlock(&cache_mutex); + + return entry->minalign.alignment; +} diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h index 8b427b7e7..936e7d1c8 100644 --- a/lib/i915/intel_memory_region.h +++ b/lib/i915/intel_memory_region.h @@ -129,4 +129,9 @@ uint64_t gpu_meminfo_region_available(const struct drm_i915_query_memory_regions uint16_t memory_class, uint16_t memory_instance); +uint64_t gem_detect_min_start_offset_for_region(int i915, uint32_t region); +uint64_t gem_detect_safe_start_offset(int i915); +uint64_t gem_detect_min_alignment_for_regions(int i915, uint32_t region1, uint32_t region2); +uint64_t gem_detect_safe_alignment(int i915); + #endif /* INTEL_MEMORY_REGION_H */ -- 2.32.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/3] lib/intel_memory_region: Add start offset and alignment detection 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_memory_region: " Zbigniew Kempczyński @ 2022-01-06 2:23 ` Dixit, Ashutosh 2022-01-06 9:45 ` Zbigniew Kempczyński 0 siblings, 1 reply; 16+ messages in thread From: Dixit, Ashutosh @ 2022-01-06 2:23 UTC (permalink / raw) To: Zbigniew Kempczyński; +Cc: igt-dev, Petri Latvala On Tue, 04 Jan 2022 22:49:43 -0800, Zbigniew Kempczyński wrote: > > With era of new gens we're enforced to use no-reloc (softpin). This > brings few problems like vm range limitations which were well solved > by the kernel. This can be handled also in userspace code by adding > gen related conditionals or by trying to detect the constraints. > > Lets try to do this dynamically and detect safe start offset and > alignment for each memory region we got. This should be universal solution > regardless hw limitations and bugs. As such detection is not lightweight > technique add also some caching structures to handle consequtive calls > about same data. I have a few more comments and suggestions below. However, since these are non-blocking this patch is: Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > +static IGT_LIST_HEAD(cache); > +static pthread_mutex_t cache_mutex = PTHREAD_MUTEX_INITIALIZER; The caching will help for multiple calls to the code within a single process, but in CI each process will still need to build up the cache. > +uint64_t gem_detect_min_start_offset_for_region(int i915, uint32_t region) > +{ > + struct drm_i915_gem_exec_object2 obj; > + struct drm_i915_gem_execbuffer2 eb; > + uint64_t start_offset = 0; > + uint64_t bb_size = PAGE_SIZE; > + uint32_t *batch; > + uint16_t devid = intel_get_drm_devid(i915); > + struct cache_entry *entry, *newentry; > + > + pthread_mutex_lock(&cache_mutex); > + entry = find_entry_unlocked(MIN_START_OFFSET, devid, region, 0); > + if (entry) > + goto out; > + pthread_mutex_unlock(&cache_mutex); I think it would be better to add the locking to find_entry_unlocked(). And also add a list_add_entry() kind of function with the locking. This will associate the mutex directly with the list and get it out of the callers. The check if the entry has been previously added would also need to move to list_add_entry(). Anyway if this is complicated leave as is. > + newentry = malloc(sizeof(*newentry)); > + if (!newentry) > + return start_offset; I'd suggest just do 'igt_assert(newentry)' in all these functions to keep things simple. > +/** > + * gem_detect_min_alignment_for_regions: > + * @i915: drm fd > + * @region1: first region > + * @region2: second region > + * > + * Returns: minimum alignment which must be used when objects from @region1 and > + * @region2 are going to interact. Here actually it is not obvious why the code below in this function is needed. Page sizes for different memory regions can be different. From discussions with people here, it seems what happens is that different page sizes cannot be included as part of the same page table structure level (in the multi-level page table structure hierarchy). That is why offsets for memory regions with different page sizes cannot be adjacent. Can we add some explanation of this sort here as a hint as to why the code below is needed? There is still the question in my mind whether the situation is "dynamic" when a memory region has multiple page sizes, say 64 K and 2 MiB. In this case when we run the detection we get one safe alignemnt value which is cached, but "later" because of memory use, this cached value proves insufficient (so when we detect say we get 64 K but actually later the 2 MiB value is needed). This could happen because of different code paths taken in the kernel. Any case, I think what we have is good enough for now and worth trying. Let's see if we hit this issue later. > + /* Establish bb offset first */ > + eb.buffers_ptr = to_user_pointer(obj); > + eb.buffer_count = 1; Looks like this line is not needed, eb.buffer_count is set again below. > + eb.flags = I915_EXEC_BATCH_FIRST | I915_EXEC_DEFAULT; > + igt_assert(__gem_create_in_memory_regions(i915, &obj[0].handle, > + &bb_size, region1) == 0); > + obj[0].flags = EXEC_OBJECT_PINNED; > + > + batch = gem_mmap__device_coherent(i915, obj[0].handle, 0, bb_size, > + PROT_WRITE); > + *batch = MI_BATCH_BUFFER_END; > + munmap(batch, bb_size); > + > + obj[0].offset = gem_detect_min_start_offset_for_region(i915, region1); > + > + /* Find appropriate alignment of object */ > + eb.buffer_count = ARRAY_SIZE(obj); ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/3] lib/intel_memory_region: Add start offset and alignment detection 2022-01-06 2:23 ` Dixit, Ashutosh @ 2022-01-06 9:45 ` Zbigniew Kempczyński 0 siblings, 0 replies; 16+ messages in thread From: Zbigniew Kempczyński @ 2022-01-06 9:45 UTC (permalink / raw) To: Dixit, Ashutosh; +Cc: igt-dev, Petri Latvala On Wed, Jan 05, 2022 at 06:23:21PM -0800, Dixit, Ashutosh wrote: > On Tue, 04 Jan 2022 22:49:43 -0800, Zbigniew Kempczyński wrote: > > > > With era of new gens we're enforced to use no-reloc (softpin). This > > brings few problems like vm range limitations which were well solved > > by the kernel. This can be handled also in userspace code by adding > > gen related conditionals or by trying to detect the constraints. > > > > Lets try to do this dynamically and detect safe start offset and > > alignment for each memory region we got. This should be universal solution > > regardless hw limitations and bugs. As such detection is not lightweight > > technique add also some caching structures to handle consequtive calls > > about same data. > > I have a few more comments and suggestions below. However, since these are > non-blocking this patch is: > > Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Thanks for the review. > > > +static IGT_LIST_HEAD(cache); > > +static pthread_mutex_t cache_mutex = PTHREAD_MUTEX_INITIALIZER; > > The caching will help for multiple calls to the code within a single > process, but in CI each process will still need to build up the cache. Each code which will be called during single execution will need to build the cache. That's the cost of softpinning and differences in hw / i915 paths. Some panacea would be to expose some queries from i915 but this adds new uAPI and requires to be handled forever. Detection generates few extra calls on the very beginning where only one bb really touches hardware. > > > +uint64_t gem_detect_min_start_offset_for_region(int i915, uint32_t region) > > +{ > > + struct drm_i915_gem_exec_object2 obj; > > + struct drm_i915_gem_execbuffer2 eb; > > + uint64_t start_offset = 0; > > + uint64_t bb_size = PAGE_SIZE; > > + uint32_t *batch; > > + uint16_t devid = intel_get_drm_devid(i915); > > + struct cache_entry *entry, *newentry; > > + > > + pthread_mutex_lock(&cache_mutex); > > + entry = find_entry_unlocked(MIN_START_OFFSET, devid, region, 0); > > + if (entry) > > + goto out; > > + pthread_mutex_unlock(&cache_mutex); > > I think it would be better to add the locking to find_entry_unlocked(). And > also add a list_add_entry() kind of function with the locking. This will > associate the mutex directly with the list and get it out of the > callers. The check if the entry has been previously added would also need > to move to list_add_entry(). > > Anyway if this is complicated leave as is. find_entry_unlocked() is used also in adding to cache path, where you need to do following ops within single mutex locked: 1. mutex_lock() 2. find_entry_unlocked() 3. if found skip adding to cache (goto out) 4. add_to_cache_unlocked() 5. mutex_unlock() That's why I couldn't add find()/add() functions to lock mutex themselves because if I would drop mutex after find noone prevents for adding same entry to cache twice (or more if there will be more threads). > > > + newentry = malloc(sizeof(*newentry)); > > + if (!newentry) > > + return start_offset; > > I'd suggest just do 'igt_assert(newentry)' in all these functions to keep > things simple. Primary code has assert here, but we don't need it. At least we won't expose memory problem here. I got heavy discussion about this on irc and I was convinced that if we got value already established we can return it (in hope some memory can be reclaimed in the meantime). > > > +/** > > + * gem_detect_min_alignment_for_regions: > > + * @i915: drm fd > > + * @region1: first region > > + * @region2: second region > > + * > > + * Returns: minimum alignment which must be used when objects from @region1 and > > + * @region2 are going to interact. > > Here actually it is not obvious why the code below in this function is > needed. Page sizes for different memory regions can be different. From > discussions with people here, it seems what happens is that different page > sizes cannot be included as part of the same page table structure level (in > the multi-level page table structure hierarchy). That is why offsets for > memory regions with different page sizes cannot be adjacent. > > Can we add some explanation of this sort here as a hint as to why the code > below is needed? I haven't found better idea how to properly align objects from different regions than use some detection on the very beginning. If you have better idea how to solve this I won't insist to merge my code. > > There is still the question in my mind whether the situation is "dynamic" > when a memory region has multiple page sizes, say 64 K and 2 MiB. In this > case when we run the detection we get one safe alignemnt value which is > cached, but "later" because of memory use, this cached value proves > insufficient (so when we detect say we get 64 K but actually later the 2 > MiB value is needed). This could happen because of different code paths > taken in the kernel. If kernel will change alignment during runtime detection and caching is wrong and almost all of that code should looks: uint64_t gem_get_safe_alignment() { return SIZE_2M; /* or SIZE_1G */ } Only start offset should be still detected as we've no idea what is first offset we can use. I wondered to add same for end offset but it can be tricky as if I good remember last page can be problematic but it is not easily detectable and can depend on engine (likely there're problems on rcs0 if my memory is not failing too much). > > Any case, I think what we have is good enough for now and worth > trying. Let's see if we hit this issue later. > > > + /* Establish bb offset first */ > > + eb.buffers_ptr = to_user_pointer(obj); > > + eb.buffer_count = 1; > > Looks like this line is not needed, eb.buffer_count is set again below. Good catch. This is remnant where I've detected min start offset here. If you think there's better way how to solve problems regarding alignment / start offset please propose. I focused on detecton but maybe there's different technique we can use for those problems. Thank you for the comments and debug session :) -- Zbigniew > > > + eb.flags = I915_EXEC_BATCH_FIRST | I915_EXEC_DEFAULT; > > + igt_assert(__gem_create_in_memory_regions(i915, &obj[0].handle, > > + &bb_size, region1) == 0); > > + obj[0].flags = EXEC_OBJECT_PINNED; > > + > > + batch = gem_mmap__device_coherent(i915, obj[0].handle, 0, bb_size, > > + PROT_WRITE); > > + *batch = MI_BATCH_BUFFER_END; > > + munmap(batch, bb_size); > > + > > + obj[0].offset = gem_detect_min_start_offset_for_region(i915, region1); > > + > > + /* Find appropriate alignment of object */ > > + eb.buffer_count = ARRAY_SIZE(obj); ^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 2/3] tests/i915/gem_softpin: Add safe-start test 2022-01-05 6:49 [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection Zbigniew Kempczyński 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_memory_region: " Zbigniew Kempczyński @ 2022-01-05 6:49 ` Zbigniew Kempczyński 2022-01-06 2:24 ` Dixit, Ashutosh 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 3/3] tests/fast-feedback.testlist: Add gem_softpin@safe-start subtest Zbigniew Kempczyński ` (2 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Zbigniew Kempczyński @ 2022-01-05 6:49 UTC (permalink / raw) To: igt-dev; +Cc: Petri Latvala Exercise start offset and alignment detection when we start mixing system and local memory. v2: support integrated and check smem <-> smem alignment v3: iterate over engines to verify safe start is correct everywhere Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Petri Latvala <petri.latvala@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> --- tests/i915/gem_softpin.c | 87 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c index d085dea34..7085605bc 100644 --- a/tests/i915/gem_softpin.c +++ b/tests/i915/gem_softpin.c @@ -1072,6 +1072,89 @@ static void test_allocator_evict(int fd, const intel_ctx_t *ctx, igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0); } +static void make_batch(int i915, uint32_t handle, uint64_t size) +{ + uint32_t *bb = gem_mmap__device_coherent(i915, handle, 0, size, PROT_WRITE); + *bb = MI_BATCH_BUFFER_END; + munmap(bb, size); +} + +static void safe_start(int i915) +{ + struct drm_i915_gem_execbuffer2 execbuf = {}; + struct drm_i915_gem_exec_object2 obj[2] = {}; + uint32_t handle1, handle2, region1, region2; + uint64_t alignment, offset1, offset2, size1 = 4096, size2 = 4096; + const struct intel_execution_engine2 *e; + const intel_ctx_t *ctx; + + region1 = REGION_SMEM; + region2 = gem_has_lmem(i915) ? REGION_LMEM(0) : REGION_SMEM; + igt_assert(__gem_create_in_memory_regions(i915, &handle1, &size1, region1) == 0); + igt_assert(handle1); + make_batch(i915, handle1, 4096); + igt_assert(__gem_create_in_memory_regions(i915, &handle2, &size2, region2) == 0); + igt_assert(handle2); + make_batch(i915, handle2, 4096); + + offset1 = gem_detect_min_start_offset_for_region(i915, region1); + offset2 = gem_detect_min_start_offset_for_region(i915, region2); + alignment = gem_detect_safe_alignment(i915); + igt_debug("safe alignment: %llx\n", (long long) alignment); + igt_debug("safe start offset: %llx\n", + (long long) gem_detect_safe_start_offset(i915)); + igt_debug("minimum object1 start offset: %llx\n", (long long) offset1); + igt_debug("minimum object2 start offset: %llx\n", (long long) offset2); + + execbuf.buffer_count = 2; + execbuf.buffers_ptr = to_user_pointer(obj); + + obj[0].offset = offset1; + obj[0].flags = EXEC_OBJECT_PINNED; + obj[0].handle = handle1; + obj[1].offset = max(ALIGN(offset1 + size1, alignment), offset2); + obj[1].flags = EXEC_OBJECT_PINNED; + obj[1].handle = handle2; + igt_debug("obj[0].offset: %llx, handle: %u\n", obj[0].offset, obj[0].handle); + igt_debug("obj[1].offset: %llx, handle: %u\n", obj[1].offset, obj[1].handle); + + gem_execbuf(i915, &execbuf); + execbuf.flags = I915_EXEC_BATCH_FIRST; + gem_execbuf(i915, &execbuf); + + obj[0].offset = offset2; + obj[0].flags = EXEC_OBJECT_PINNED; + obj[0].handle = handle2; + obj[1].offset = max(ALIGN(offset2 + size2, alignment), offset1); + obj[1].flags = EXEC_OBJECT_PINNED; + obj[1].handle = handle1; + igt_debug("obj[0].offset: %llx, handle: %u\n", obj[0].offset, obj[0].handle); + igt_debug("obj[1].offset: %llx, handle: %u\n", obj[1].offset, obj[1].handle); + + gem_execbuf(i915, &execbuf); + execbuf.flags = 0; + gem_execbuf(i915, &execbuf); + gem_sync(i915, handle1); + + /* Last check, verify safe start for each engine */ + ctx = intel_ctx_create_all_physical(i915); + execbuf.buffer_count = 1; + execbuf.rsvd1 = ctx->id; + obj[0].offset = gem_detect_safe_start_offset(i915); + for_each_ctx_engine(i915, ctx, e) { + execbuf.flags = e->flags; + obj[0].handle = handle1; + gem_execbuf(i915, &execbuf); + obj[0].handle = handle2; + gem_execbuf(i915, &execbuf); + } + + gem_sync(i915, handle1); + gem_close(i915, handle1); + gem_close(i915, handle2); + intel_ctx_destroy(i915, ctx); +} + #define test_each_engine(T, i915, ctx, e) \ igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \ igt_dynamic_f("%s", e->name) @@ -1133,6 +1216,10 @@ igt_main test_allocator_evict(fd, ctx, ALL_ENGINES, 20); } + igt_describe("Check start offset and alignment detection"); + igt_subtest("safe-start") + safe_start(fd); + igt_subtest("softpin") test_softpin(fd); igt_subtest("overlap") -- 2.32.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/3] tests/i915/gem_softpin: Add safe-start test 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 2/3] tests/i915/gem_softpin: Add safe-start test Zbigniew Kempczyński @ 2022-01-06 2:24 ` Dixit, Ashutosh 2022-01-06 9:55 ` Zbigniew Kempczyński 0 siblings, 1 reply; 16+ messages in thread From: Dixit, Ashutosh @ 2022-01-06 2:24 UTC (permalink / raw) To: Zbigniew Kempczyński; +Cc: igt-dev, Petri Latvala On Tue, 04 Jan 2022 22:49:44 -0800, Zbigniew Kempczyński wrote: > > + offset1 = gem_detect_min_start_offset_for_region(i915, region1); > + offset2 = gem_detect_min_start_offset_for_region(i915, region2); > + alignment = gem_detect_safe_alignment(i915); > + igt_debug("safe alignment: %llx\n", (long long) alignment); > + igt_debug("safe start offset: %llx\n", > + (long long) gem_detect_safe_start_offset(i915)); > + igt_debug("minimum object1 start offset: %llx\n", (long long) offset1); > + igt_debug("minimum object2 start offset: %llx\n", (long long) offset2); Maybe also add print for the min_alignment value here? > + igt_describe("Check start offset and alignment detection"); > + igt_subtest("safe-start") > + safe_start(fd); I think "safe-start" is a really ambiguous name so we should change the name to something like "safe-align" or 'safe-offset", no? Otherwise this is: Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/3] tests/i915/gem_softpin: Add safe-start test 2022-01-06 2:24 ` Dixit, Ashutosh @ 2022-01-06 9:55 ` Zbigniew Kempczyński 2022-01-06 13:20 ` Dixit, Ashutosh 0 siblings, 1 reply; 16+ messages in thread From: Zbigniew Kempczyński @ 2022-01-06 9:55 UTC (permalink / raw) To: Dixit, Ashutosh; +Cc: igt-dev, Petri Latvala On Wed, Jan 05, 2022 at 06:24:14PM -0800, Dixit, Ashutosh wrote: > On Tue, 04 Jan 2022 22:49:44 -0800, Zbigniew Kempczyński wrote: > > > > + offset1 = gem_detect_min_start_offset_for_region(i915, region1); > > + offset2 = gem_detect_min_start_offset_for_region(i915, region2); > > + alignment = gem_detect_safe_alignment(i915); > > + igt_debug("safe alignment: %llx\n", (long long) alignment); > > + igt_debug("safe start offset: %llx\n", > > + (long long) gem_detect_safe_start_offset(i915)); > > + igt_debug("minimum object1 start offset: %llx\n", (long long) offset1); > > + igt_debug("minimum object2 start offset: %llx\n", (long long) offset2); > > Maybe also add print for the min_alignment value here? You want to print minimum alignment for same region? > > > + igt_describe("Check start offset and alignment detection"); > > + igt_subtest("safe-start") > > + safe_start(fd); > > I think "safe-start" is a really ambiguous name so we should change the > name to something like "safe-align" or 'safe-offset", no? Already got that name to safe-alignment on first version of patch but I got suggestion to change to safe-start. Anyway we exercise start offset as well as alignment here. But my preference is also safe-align so there 2:1 voice. > > Otherwise this is: > > Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Thanks for the review, I'm going to wait for you comment regarding min alignment. -- Zbigniew ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/3] tests/i915/gem_softpin: Add safe-start test 2022-01-06 9:55 ` Zbigniew Kempczyński @ 2022-01-06 13:20 ` Dixit, Ashutosh 0 siblings, 0 replies; 16+ messages in thread From: Dixit, Ashutosh @ 2022-01-06 13:20 UTC (permalink / raw) To: Zbigniew Kempczyński; +Cc: igt-dev, Petri Latvala On Thu, 06 Jan 2022 01:55:50 -0800, Zbigniew Kempczyński wrote: > > On Wed, Jan 05, 2022 at 06:24:14PM -0800, Dixit, Ashutosh wrote: > > On Tue, 04 Jan 2022 22:49:44 -0800, Zbigniew Kempczyński wrote: > > > > > > + offset1 = gem_detect_min_start_offset_for_region(i915, region1); > > > + offset2 = gem_detect_min_start_offset_for_region(i915, region2); > > > + alignment = gem_detect_safe_alignment(i915); > > > + igt_debug("safe alignment: %llx\n", (long long) alignment); > > > + igt_debug("safe start offset: %llx\n", > > > + (long long) gem_detect_safe_start_offset(i915)); > > > + igt_debug("minimum object1 start offset: %llx\n", (long long) offset1); > > > + igt_debug("minimum object2 start offset: %llx\n", (long long) offset2); > > > > Maybe also add print for the min_alignment value here? > > You want to print minimum alignment for same region? Yes, just the min alignment for the pair or regions above. Otherwise please go ahead and merge. The series is: Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> ^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 3/3] tests/fast-feedback.testlist: Add gem_softpin@safe-start subtest 2022-01-05 6:49 [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection Zbigniew Kempczyński 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_memory_region: " Zbigniew Kempczyński 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 2/3] tests/i915/gem_softpin: Add safe-start test Zbigniew Kempczyński @ 2022-01-05 6:49 ` Zbigniew Kempczyński 2022-01-05 7:39 ` [igt-dev] ✓ Fi.CI.BAT: success for Add start offset and alignment detection (rev6) Patchwork 2022-01-05 8:47 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 16+ messages in thread From: Zbigniew Kempczyński @ 2022-01-05 6:49 UTC (permalink / raw) To: igt-dev; +Cc: Petri Latvala This test takes up to few hundred of milliseconds and exercises detecting of safe starting offset and alignment to use on discrete where memory regions constraints could differ on different gens. Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Petri Latvala <petri.latvala@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Acked-by: Petri Latvala <petri.latvala@intel.com> --- tests/intel-ci/fast-feedback.testlist | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist index de1c6cb46..38a90ceb6 100644 --- a/tests/intel-ci/fast-feedback.testlist +++ b/tests/intel-ci/fast-feedback.testlist @@ -45,6 +45,7 @@ igt@gem_render_tiled_blits@basic igt@gem_ringfill@basic-all igt@gem_softpin@allocator-basic igt@gem_softpin@allocator-basic-reserve +igt@gem_softpin@safe-start igt@gem_sync@basic-all igt@gem_sync@basic-each igt@gem_tiled_blits@basic -- 2.32.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Add start offset and alignment detection (rev6) 2022-01-05 6:49 [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection Zbigniew Kempczyński ` (2 preceding siblings ...) 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 3/3] tests/fast-feedback.testlist: Add gem_softpin@safe-start subtest Zbigniew Kempczyński @ 2022-01-05 7:39 ` Patchwork 2022-01-05 8:47 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-01-05 7:39 UTC (permalink / raw) To: Zbigniew Kempczyński; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 4106 bytes --] == Series Details == Series: Add start offset and alignment detection (rev6) URL : https://patchwork.freedesktop.org/series/98402/ State : success == Summary == CI Bug Log - changes from CI_DRM_11047 -> IGTPW_6537 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/index.html Participating hosts (48 -> 36) ------------------------------ Additional (1): fi-kbl-soraka Missing (13): fi-ilk-m540 fi-bdw-5557u bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 bat-rpls-1 fi-bdw-samus bat-jsl-2 bat-jsl-1 New tests --------- New tests have been introduced between CI_DRM_11047 and IGTPW_6537: ### New IGT tests (1) ### * igt@gem_softpin@safe-start: - Statuses : 34 pass(s) 1 skip(s) - Exec time: [0.0, 0.10] s Known issues ------------ Here are the changes found in IGTPW_6537 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_cs_nop@sync-fork-gfx0: - fi-skl-6600u: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/fi-skl-6600u/igt@amdgpu/amd_cs_nop@sync-fork-gfx0.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html * {igt@gem_softpin@safe-start} (NEW): - fi-bwr-2160: NOTRUN -> [SKIP][5] ([fdo#109271]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/fi-bwr-2160/igt@gem_softpin@safe-start.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][6] ([i915#1886] / [i915#2291]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_6323 -> IGTPW_6537 CI-20190529: 20190529 CI_DRM_11047: f50e5d7abd1873b3488081da88dc8412584280b9 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_6537: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/index.html IGT_6323: 9dbaa0d5be7a859cda9b7d54c20ba96a596f43bd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git == Testlist changes == +igt@gem_softpin@safe-start == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/index.html [-- Attachment #2: Type: text/html, Size: 5337 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Add start offset and alignment detection (rev6) 2022-01-05 6:49 [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection Zbigniew Kempczyński ` (3 preceding siblings ...) 2022-01-05 7:39 ` [igt-dev] ✓ Fi.CI.BAT: success for Add start offset and alignment detection (rev6) Patchwork @ 2022-01-05 8:47 ` Patchwork 4 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-01-05 8:47 UTC (permalink / raw) To: Zbigniew Kempczyński; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 30265 bytes --] == Series Details == Series: Add start offset and alignment detection (rev6) URL : https://patchwork.freedesktop.org/series/98402/ State : success == Summary == CI Bug Log - changes from CI_DRM_11047_full -> IGTPW_6537_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/index.html Participating hosts (13 -> 8) ------------------------------ Missing (5): pig-kbl-iris pig-glk-j5005 pig-skl-6260u shard-rkl shard-dg1 Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_6537_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@gem_eio@suspend: - {shard-tglu}: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglu-2/igt@gem_eio@suspend.html * igt@i915_pm_dc@dc6-psr: - {shard-tglu}: NOTRUN -> [SKIP][2] +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglu-7/igt@i915_pm_dc@dc6-psr.html * igt@prime_busy@hang-wait@vcs1: - {shard-tglu}: [INCOMPLETE][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-7/igt@prime_busy@hang-wait@vcs1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglu-7/igt@prime_busy@hang-wait@vcs1.html * igt@prime_busy@hang-wait@vecs0: - {shard-tglu}: NOTRUN -> [INCOMPLETE][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglu-7/igt@prime_busy@hang-wait@vecs0.html New tests --------- New tests have been introduced between CI_DRM_11047_full and IGTPW_6537_full: ### New IGT tests (1) ### * igt@gem_softpin@safe-start: - Statuses : 6 pass(s) - Exec time: [0.01, 0.03] s Known issues ------------ Here are the changes found in IGTPW_6537_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_create@create-massive: - shard-tglb: NOTRUN -> [DMESG-WARN][6] ([i915#3002]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb7/igt@gem_create@create-massive.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-apl: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl1/igt@gem_exec_fair@basic-none-share@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl2/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: NOTRUN -> [FAIL][13] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl3/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@parallel-random: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl3/igt@gem_lmem_swapping@parallel-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +4 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl7/igt@gem_lmem_swapping@parallel-random-verify.html - shard-iclb: NOTRUN -> [SKIP][19] ([i915#4613]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb4/igt@gem_lmem_swapping@parallel-random-verify.html - shard-tglb: NOTRUN -> [SKIP][20] ([i915#4613]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb5/igt@gem_lmem_swapping@parallel-random-verify.html * igt@gem_pread@exhaustion: - shard-kbl: NOTRUN -> [WARN][21] ([i915#2658]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl3/igt@gem_pread@exhaustion.html * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled: - shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271]) +222 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl3/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html * igt@gem_userptr_blits@coherency-unsync: - shard-tglb: NOTRUN -> [SKIP][23] ([i915#3297]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb7/igt@gem_userptr_blits@coherency-unsync.html * igt@gem_workarounds@suspend-resume: - shard-kbl: [PASS][24] -> [DMESG-WARN][25] ([i915#180]) +2 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl6/igt@gem_workarounds@suspend-resume.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl4/igt@gem_workarounds@suspend-resume.html * igt@i915_pm_dc@dc6-dpms: - shard-kbl: NOTRUN -> [FAIL][26] ([i915#454]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl3/igt@i915_pm_dc@dc6-dpms.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][27] -> [FAIL][28] ([i915#454]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb7/igt@i915_pm_dc@dc6-psr.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb3/igt@i915_pm_dc@dc6-psr.html * igt@i915_suspend@forcewake: - shard-apl: NOTRUN -> [DMESG-WARN][29] ([i915#180]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl2/igt@i915_suspend@forcewake.html * igt@kms_big_fb@linear-64bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][30] ([fdo#110725] / [fdo#111614]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb1/igt@kms_big_fb@linear-64bpp-rotate-90.html - shard-tglb: NOTRUN -> [SKIP][31] ([fdo#111614]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb6/igt@kms_big_fb@linear-64bpp-rotate-90.html * igt@kms_big_fb@x-tiled-32bpp-rotate-180: - shard-glk: [PASS][32] -> [DMESG-WARN][33] ([i915#118]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk3/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk3/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-glk: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3777]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html - shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3777]) +1 similar issue [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-tglb: NOTRUN -> [SKIP][37] ([fdo#111615]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3886]) +10 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][40] ([fdo#111615] / [i915#3689]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb6/igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs.html * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3886]) +5 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][42] ([i915#3689] / [i915#3886]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb7/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html - shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278] / [i915#3886]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb1/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html * igt@kms_chamelium@dp-hpd-storm-disable: - shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +8 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl1/igt@kms_chamelium@dp-hpd-storm-disable.html * igt@kms_chamelium@hdmi-edid-change-during-suspend: - shard-tglb: NOTRUN -> [SKIP][45] ([fdo#109284] / [fdo#111827]) +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb3/igt@kms_chamelium@hdmi-edid-change-during-suspend.html - shard-glk: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +1 similar issue [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk9/igt@kms_chamelium@hdmi-edid-change-during-suspend.html * igt@kms_color@pipe-d-ctm-0-25: - shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109278] / [i915#1149]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb3/igt@kms_color@pipe-d-ctm-0-25.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-kbl: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +17 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl3/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-c-ctm-limited-range: - shard-snb: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-snb5/igt@kms_color_chamelium@pipe-c-ctm-limited-range.html - shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109284] / [fdo#111827]) +1 similar issue [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb4/igt@kms_color_chamelium@pipe-c-ctm-limited-range.html * igt@kms_content_protection@atomic-dpms: - shard-apl: NOTRUN -> [TIMEOUT][51] ([i915#1319]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl4/igt@kms_content_protection@atomic-dpms.html - shard-kbl: NOTRUN -> [TIMEOUT][52] ([i915#1319]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl3/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@uevent: - shard-kbl: NOTRUN -> [FAIL][53] ([i915#2105]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl4/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding: - shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109278]) +3 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding.html - shard-tglb: NOTRUN -> [SKIP][55] ([i915#3359]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding.html * igt@kms_cursor_crc@pipe-d-cursor-32x32-sliding: - shard-tglb: NOTRUN -> [SKIP][56] ([i915#3319]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-32x32-sliding.html * igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding: - shard-tglb: NOTRUN -> [SKIP][57] ([fdo#109279] / [i915#3359]) +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb2/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: - shard-tglb: NOTRUN -> [SKIP][58] ([fdo#109274] / [fdo#111825]) +2 similar issues [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb8/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109274] / [fdo#109278]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb3/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2: - shard-glk: [PASS][60] -> [FAIL][61] ([i915#2122]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: NOTRUN -> [DMESG-WARN][62] ([i915#180]) +8 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html - shard-apl: [PASS][63] -> [DMESG-WARN][64] ([i915#180]) +2 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling: - shard-glk: [PASS][65] -> [FAIL][66] ([i915#4911]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling: - shard-iclb: [PASS][67] -> [SKIP][68] ([i915#3701]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-rte: - shard-glk: NOTRUN -> [SKIP][69] ([fdo#109271]) +17 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk9/igt@kms_frontbuffer_tracking@fbcpsr-2p-rte.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> [SKIP][70] ([fdo#109280]) +8 similar issues [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-cpu: - shard-tglb: NOTRUN -> [SKIP][71] ([fdo#109280] / [fdo#111825]) +12 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt: - shard-snb: NOTRUN -> [SKIP][72] ([fdo#109271]) +19 similar issues [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-snb7/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d: - shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#533]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl4/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html - shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#533]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl3/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-kbl: NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265]) +2 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb: - shard-glk: NOTRUN -> [FAIL][76] ([i915#265]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html - shard-apl: NOTRUN -> [FAIL][77] ([i915#265]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl7/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html - shard-kbl: NOTRUN -> [FAIL][78] ([i915#265]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html * igt@kms_plane_lowres@pipe-d-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][79] ([fdo#111615] / [fdo#112054]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb7/igt@kms_plane_lowres@pipe-d-tiling-yf.html * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: - shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl3/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area: - shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#658]) +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html * igt@kms_psr@psr2_sprite_render: - shard-tglb: NOTRUN -> [FAIL][82] ([i915#132] / [i915#3467]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb7/igt@kms_psr@psr2_sprite_render.html - shard-iclb: NOTRUN -> [SKIP][83] ([fdo#109441]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb1/igt@kms_psr@psr2_sprite_render.html * igt@kms_vblank@pipe-d-ts-continuation-idle: - shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271]) +129 similar issues [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl6/igt@kms_vblank@pipe-d-ts-continuation-idle.html * igt@kms_writeback@writeback-invalid-parameters: - shard-kbl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#2437]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl7/igt@kms_writeback@writeback-invalid-parameters.html - shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#2437]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl8/igt@kms_writeback@writeback-invalid-parameters.html * igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame: - shard-iclb: NOTRUN -> [SKIP][87] ([i915#2530]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb4/igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame.html * igt@nouveau_crc@pipe-b-ctx-flip-detection: - shard-tglb: NOTRUN -> [SKIP][88] ([i915#2530]) +1 similar issue [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb3/igt@nouveau_crc@pipe-b-ctx-flip-detection.html * igt@sysfs_clients@sema-10: - shard-tglb: NOTRUN -> [SKIP][89] ([i915#2994]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb1/igt@sysfs_clients@sema-10.html - shard-kbl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2994]) +1 similar issue [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl6/igt@sysfs_clients@sema-10.html - shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2994]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl8/igt@sysfs_clients@sema-10.html - shard-glk: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#2994]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk9/igt@sysfs_clients@sema-10.html #### Possible fixes #### * igt@gem_eio@kms: - shard-tglb: [FAIL][93] ([i915#232]) -> [PASS][94] [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb8/igt@gem_eio@kms.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb6/igt@gem_eio@kms.html * igt@gem_eio@unwedge-stress: - shard-iclb: [TIMEOUT][95] ([i915#2481] / [i915#3070]) -> [PASS][96] [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb2/igt@gem_eio@unwedge-stress.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb3/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@parallel-out-fence: - shard-iclb: [SKIP][97] ([i915#4525]) -> [PASS][98] +2 similar issues [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb8/igt@gem_exec_balancer@parallel-out-fence.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb4/igt@gem_exec_balancer@parallel-out-fence.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [FAIL][99] ([i915#2846]) -> [PASS][100] [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk3/igt@gem_exec_fair@basic-deadline.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk6/igt@gem_exec_fair@basic-deadline.html - shard-apl: [FAIL][101] ([i915#2846]) -> [PASS][102] [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl1/igt@gem_exec_fair@basic-deadline.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl6/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [FAIL][103] ([i915#2842]) -> [PASS][104] [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk8/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [FAIL][105] ([i915#2842]) -> [PASS][106] +2 similar issues [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [FAIL][107] ([i915#2842]) -> [PASS][108] +1 similar issue [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl4/igt@gem_exec_fair@basic-none@vecs0.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: [FAIL][109] ([i915#2842]) -> [PASS][110] [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb3/igt@gem_exec_fair@basic-pace-solo@rcs0.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_ppgtt@blt-vs-render-ctxn: - {shard-tglu}: [INCOMPLETE][111] ([i915#750]) -> [PASS][112] +1 similar issue [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-7/igt@gem_ppgtt@blt-vs-render-ctxn.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglu-2/igt@gem_ppgtt@blt-vs-render-ctxn.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][113] ([i915#180]) -> [PASS][114] +3 similar issues [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl3/igt@gem_workarounds@suspend-resume-context.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl1/igt@gem_workarounds@suspend-resume-context.html * igt@i915_pm_dc@dc9-dpms: - shard-apl: [SKIP][115] ([fdo#109271]) -> [PASS][116] [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl3/igt@i915_pm_dc@dc9-dpms.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl2/igt@i915_pm_dc@dc9-dpms.html - shard-iclb: [SKIP][117] ([i915#4281]) -> [PASS][118] [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-tglb: [WARN][119] ([i915#2681] / [i915#2684]) -> [PASS][120] [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb7/igt@i915_pm_rc6_residency@rc6-fence.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglb8/igt@i915_pm_rc6_residency@rc6-fence.html - {shard-tglu}: [WARN][121] ([i915#2681]) -> [PASS][122] [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-fence.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglu-3/igt@i915_pm_rc6_residency@rc6-fence.html * igt@kms_big_fb@linear-16bpp-rotate-180: - {shard-tglu}: [DMESG-WARN][123] ([i915#402]) -> [PASS][124] [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-1/igt@kms_big_fb@linear-16bpp-rotate-180.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-tglu-2/igt@kms_big_fb@linear-16bpp-rotate-180.html * igt@kms_big_fb@linear-32bpp-rotate-0: - shard-glk: [DMESG-WARN][125] ([i915#118]) -> [PASS][126] +3 similar issues [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk9/igt@kms_big_fb@linear-32bpp-rotate-0.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-glk5/igt@kms_big_fb@linear-32bpp-rotate-0.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-iclb: [FAIL][127] ([i915#2346]) -> [PASS][128] +1 similar issue [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb4/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1: - shard-apl: [FAIL][129] ([i915#79]) -> [PASS][130] [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling: - shard-iclb: [SKIP][131] ([i915#3701]) -> [PASS][132] +1 similar issue [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][133] ([i915#180]) -> [PASS][134] +1 similar issue [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][135] ([fdo#109441]) -> [PASS][136] [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][137] ([i915#180] / [i915#295]) -> [PASS][138] [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html - shard-apl: [DMESG-WARN][139] ([i915#180] / [i915#295]) -> [PASS][140] [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@prime_busy@hang-wait@bcs0: - {shard-tglu}: [DMESG-WARN][141] -> [PASS][142] [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shar == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6537/index.html [-- Attachment #2: Type: text/html, Size: 33612 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection @ 2022-01-06 10:00 Zbigniew Kempczyński 0 siblings, 0 replies; 16+ messages in thread From: Zbigniew Kempczyński @ 2022-01-06 10:00 UTC (permalink / raw) To: igt-dev Add some universal code which tries to detect kernel offset capabilities. v2: unify cache, fix start offset iteration run gem_softpin@safe-alignment also on integrated v3: move cache entry out of mutex v4: avoid assert and skip adding to cache if there's no memory rename to safe-start verify safe start offset on each engine v5: fix function doc (Ashutosh) v6: remove unnecessary initialization + rename to safe-alignment (Ashutosh) add 48b flag for softpin (Zbigniew) Zbigniew Kempczyński (3): lib/intel_memory_region: Add start offset and alignment detection tests/i915/gem_softpin: Add safe-alignment test tests/fast-feedback.testlist: Add gem_softpin@safe-alignment subtest lib/i915/intel_memory_region.c | 373 ++++++++++++++++++++++++++ lib/i915/intel_memory_region.h | 5 + tests/i915/gem_softpin.c | 87 ++++++ tests/intel-ci/fast-feedback.testlist | 1 + 4 files changed, 466 insertions(+) -- 2.32.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection @ 2021-12-30 18:26 Zbigniew Kempczyński 0 siblings, 0 replies; 16+ messages in thread From: Zbigniew Kempczyński @ 2021-12-30 18:26 UTC (permalink / raw) To: igt-dev Add some universal code which tries to detect kernel offset capabilities. v2: unify cache, fix start offset iteration run gem_softpin@safe-alignment also on integrated v3: move cache entry out of mutex v4: avoid assert and skip adding to cache if there's no memory rename to safe-start verify safe start offset on each engine Zbigniew Kempczyński (3): lib/intel_memory_region: Add start offset and alignment detection tests/i915/gem_softpin: Add safe-start test tests/fast-feedback.testlist: Add gem_softpin@safe-start subtest lib/i915/intel_memory_region.c | 371 ++++++++++++++++++++++++++ lib/i915/intel_memory_region.h | 5 + tests/i915/gem_softpin.c | 87 ++++++ tests/intel-ci/fast-feedback.testlist | 1 + 4 files changed, 464 insertions(+) -- 2.32.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection @ 2021-12-30 8:14 Zbigniew Kempczyński 0 siblings, 0 replies; 16+ messages in thread From: Zbigniew Kempczyński @ 2021-12-30 8:14 UTC (permalink / raw) To: igt-dev Add some universal code which tries to detect kernel offset capabilities. v2: unify cache, fix start offset iteration run gem_softpin@safe-alignment also on integrated v3: move cache entry out of mutex Zbigniew Kempczyński (3): lib/intel_memory_region: Add start offset and alignment detection tests/i915/gem_softpin: Add safe-alignment test tests/fast-feedback.testlist: Add gem_softpin@safe-alignment subtest lib/i915/intel_memory_region.c | 375 ++++++++++++++++++++++++++ lib/i915/intel_memory_region.h | 5 + tests/i915/gem_softpin.c | 66 +++++ tests/intel-ci/fast-feedback.testlist | 1 + 4 files changed, 447 insertions(+) -- 2.32.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection @ 2021-12-29 19:37 Zbigniew Kempczyński 0 siblings, 0 replies; 16+ messages in thread From: Zbigniew Kempczyński @ 2021-12-29 19:37 UTC (permalink / raw) To: igt-dev Add some universal code which tries to detect kernel offset capabilities. v2: unify cache, fix start offset iteration run gem_softpin@safe-alignment also on integrated Zbigniew Kempczyński (3): lib/intel_memory_region: Add start offset and alignment detection tests/i915/gem_softpin: Add safe-alignment test tests/fast-feedback.testlist: Add gem_softpin@safe-alignment subtest lib/i915/intel_memory_region.c | 367 ++++++++++++++++++++++++++ lib/i915/intel_memory_region.h | 5 + tests/i915/gem_softpin.c | 66 +++++ tests/intel-ci/fast-feedback.testlist | 1 + 4 files changed, 439 insertions(+) -- 2.32.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection @ 2021-12-29 13:57 Zbigniew Kempczyński 0 siblings, 0 replies; 16+ messages in thread From: Zbigniew Kempczyński @ 2021-12-29 13:57 UTC (permalink / raw) To: igt-dev Add some universal code which tries to detect kernel offset capabilites. Zbigniew Kempczyński (3): lib/intel_memory_region: Add start offset and alignment detection tests/i915/gem_softpin: Add safe-alignment test tests/fast-feedback.testlist: Add gem_softpin@safe-alignment subtest lib/i915/intel_memory_region.c | 269 ++++++++++++++++++++++++++ lib/i915/intel_memory_region.h | 5 + tests/i915/gem_softpin.c | 70 +++++++ tests/intel-ci/fast-feedback.testlist | 1 + 4 files changed, 345 insertions(+) -- 2.32.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-01-06 13:20 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-01-05 6:49 [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection Zbigniew Kempczyński 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 1/3] lib/intel_memory_region: " Zbigniew Kempczyński 2022-01-06 2:23 ` Dixit, Ashutosh 2022-01-06 9:45 ` Zbigniew Kempczyński 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 2/3] tests/i915/gem_softpin: Add safe-start test Zbigniew Kempczyński 2022-01-06 2:24 ` Dixit, Ashutosh 2022-01-06 9:55 ` Zbigniew Kempczyński 2022-01-06 13:20 ` Dixit, Ashutosh 2022-01-05 6:49 ` [igt-dev] [PATCH i-g-t 3/3] tests/fast-feedback.testlist: Add gem_softpin@safe-start subtest Zbigniew Kempczyński 2022-01-05 7:39 ` [igt-dev] ✓ Fi.CI.BAT: success for Add start offset and alignment detection (rev6) Patchwork 2022-01-05 8:47 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2022-01-06 10:00 [igt-dev] [PATCH i-g-t 0/3] Add start offset and alignment detection Zbigniew Kempczyński 2021-12-30 18:26 Zbigniew Kempczyński 2021-12-30 8:14 Zbigniew Kempczyński 2021-12-29 19:37 Zbigniew Kempczyński 2021-12-29 13:57 Zbigniew Kempczyński
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.