[PATCH] drm/amd/display: reset dcn31 SMU mailbox on failures

[PATCH] drm/amd/display: reset dcn31 SMU mailbox on failures

[Mario Limonciello]

Otherwise future commands may fail as well leading to downstream
problems that look like they stemmed from a timeout the first time
but really didn't.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index 8c2b77eb9459..162ae7186124 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -119,6 +119,12 @@ int dcn31_smu_send_msg_with_param(
 
 	result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
 
+	if (result == VBIOSSMC_Result_Failed) {
+		ASSERT(0);
+		REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
+		return -1;
+	}
+
 	if (IS_SMU_TIMEOUT(result)) {
 		ASSERT(0);
 		dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
-- 
2.25.1

Re: [PATCH] drm/amd/display: reset dcn31 SMU mailbox on failures

[Kazlauskas, Nicholas]

On 2022-01-07 4:40 p.m., Mario Limonciello wrote:
> Otherwise future commands may fail as well leading to downstream
> problems that look like they stemmed from a timeout the first time
> but really didn't.
> 
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>

I guess we used to do this but after we started adding the 
wait_for_response prior to sending the command this was ignored.

Should be fine.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Regards,
Nicholas Kazlauskas

> ---
>   drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
> index 8c2b77eb9459..162ae7186124 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
> @@ -119,6 +119,12 @@ int dcn31_smu_send_msg_with_param(
>   
>   	result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
>   
> +	if (result == VBIOSSMC_Result_Failed) {
> +		ASSERT(0);
> +		REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
> +		return -1;
> +	}
> +
>   	if (IS_SMU_TIMEOUT(result)) {
>   		ASSERT(0);
>   		dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);