* [PATCH] arm64: dts: imx8: add mu5/6 node
@ 2022-01-11 6:20 ` Peng Fan (OSS)
0 siblings, 0 replies; 4+ messages in thread
From: Peng Fan (OSS) @ 2022-01-11 6:20 UTC (permalink / raw)
To: robh+dt, shawnguo
Cc: s.hauer, kernel, festevam, linux-imx, aisheng.dong, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add mu5/6 for i.MX8QXP/QM, these two mu will be used for
communicating with general purpose Cortex-M4 cores.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 16 ++++++++++++++++
.../arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi | 8 ++++++++
.../boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 8 ++++++++
3 files changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index ee4e585a9c39..6446e6df7a9a 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -141,6 +141,22 @@ lsio_mu4: mailbox@5d1f0000 {
status = "disabled";
};
+ lsio_mu5: mailbox@5d200000 {
+ reg = <0x5d200000 0x10000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MU_5A>;
+ status = "disabled";
+ };
+
+ lsio_mu6: mailbox@5d210000 {
+ reg = <0x5d210000 0x10000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MU_6A>;
+ status = "disabled";
+ };
+
lsio_mu13: mailbox@5d280000 {
reg = <0x5d280000 0x10000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
index 30896610c654..669aa14ce9f7 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
@@ -56,6 +56,14 @@ &lsio_mu4 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
+&lsio_mu5 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu6 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
&lsio_mu13 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
index 11395479ffc0..8e2152c6eb88 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
@@ -56,6 +56,14 @@ &lsio_mu4 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
+&lsio_mu5 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu6 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
&lsio_mu13 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] arm64: dts: imx8: add mu5/6 node
@ 2022-01-11 6:20 ` Peng Fan (OSS)
0 siblings, 0 replies; 4+ messages in thread
From: Peng Fan (OSS) @ 2022-01-11 6:20 UTC (permalink / raw)
To: robh+dt, shawnguo
Cc: s.hauer, kernel, festevam, linux-imx, aisheng.dong, devicetree,
linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add mu5/6 for i.MX8QXP/QM, these two mu will be used for
communicating with general purpose Cortex-M4 cores.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 16 ++++++++++++++++
.../arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi | 8 ++++++++
.../boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 8 ++++++++
3 files changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index ee4e585a9c39..6446e6df7a9a 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -141,6 +141,22 @@ lsio_mu4: mailbox@5d1f0000 {
status = "disabled";
};
+ lsio_mu5: mailbox@5d200000 {
+ reg = <0x5d200000 0x10000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MU_5A>;
+ status = "disabled";
+ };
+
+ lsio_mu6: mailbox@5d210000 {
+ reg = <0x5d210000 0x10000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MU_6A>;
+ status = "disabled";
+ };
+
lsio_mu13: mailbox@5d280000 {
reg = <0x5d280000 0x10000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
index 30896610c654..669aa14ce9f7 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
@@ -56,6 +56,14 @@ &lsio_mu4 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
+&lsio_mu5 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu6 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
&lsio_mu13 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
index 11395479ffc0..8e2152c6eb88 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
@@ -56,6 +56,14 @@ &lsio_mu4 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
+&lsio_mu5 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu6 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
&lsio_mu13 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dts: imx8: add mu5/6 node
2022-01-11 6:20 ` Peng Fan (OSS)
@ 2022-01-28 8:59 ` Shawn Guo
-1 siblings, 0 replies; 4+ messages in thread
From: Shawn Guo @ 2022-01-28 8:59 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: robh+dt, s.hauer, kernel, festevam, linux-imx, aisheng.dong,
devicetree, linux-arm-kernel, linux-kernel, Peng Fan
On Tue, Jan 11, 2022 at 02:20:13PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add mu5/6 for i.MX8QXP/QM, these two mu will be used for
> communicating with general purpose Cortex-M4 cores.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied, thanks!
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dts: imx8: add mu5/6 node
@ 2022-01-28 8:59 ` Shawn Guo
0 siblings, 0 replies; 4+ messages in thread
From: Shawn Guo @ 2022-01-28 8:59 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: robh+dt, s.hauer, kernel, festevam, linux-imx, aisheng.dong,
devicetree, linux-arm-kernel, linux-kernel, Peng Fan
On Tue, Jan 11, 2022 at 02:20:13PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add mu5/6 for i.MX8QXP/QM, these two mu will be used for
> communicating with general purpose Cortex-M4 cores.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-01-28 9:01 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2022-01-11 6:20 [PATCH] arm64: dts: imx8: add mu5/6 node Peng Fan (OSS)
2022-01-11 6:20 ` Peng Fan (OSS)
2022-01-28 8:59 ` Shawn Guo
2022-01-28 8:59 ` Shawn Guo
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