From: Francisco Iglesias <francisco.iglesias@xilinx.com>
To: <qemu-devel@nongnu.org>
Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org,
frasse.iglesias@gmail.com, alistair@alistair23.me,
alistair23@gmail.com, philmd@redhat.com
Subject: [PATCH v6 02/12] hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models
Date: Fri, 14 Jan 2022 15:28:31 +0000 [thread overview]
Message-ID: <20220114152841.1740-3-francisco.iglesias@xilinx.com> (raw)
In-Reply-To: <20220114152841.1740-1-francisco.iglesias@xilinx.com>
Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/xlnx-versal-virt.c | 2 +-
hw/arm/xlnx-versal.c | 28 ++++++++++++++++++++++++++--
include/hw/arm/xlnx-versal.h | 5 +++--
3 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 0c5edc898e..8ea9979710 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -365,7 +365,7 @@ static void fdt_add_bbram_node(VersalVirt *s)
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
- GIC_FDT_IRQ_TYPE_SPI, VERSAL_BBRAM_APB_IRQ_0,
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_PMC_APB_IRQ,
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
qemu_fdt_setprop(s->fdt, name, "interrupt-names",
interrupt_names, sizeof(interrupt_names));
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index b2705b6925..fefd00b57c 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -25,6 +25,8 @@
#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
#define GEM_REVISION 0x40070106
+#define VERSAL_NUM_PMC_APB_IRQS 2
+
static void versal_create_apu_cpus(Versal *s)
{
int i;
@@ -260,6 +262,25 @@ static void versal_create_sds(Versal *s, qemu_irq *pic)
}
}
+static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic)
+{
+ DeviceState *orgate;
+
+ /*
+ * The VERSAL_PMC_APB_IRQ is an 'or' of the interrupts from the following
+ * models:
+ * - RTC
+ * - BBRAM
+ */
+ object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate",
+ &s->pmc.apb_irq_orgate, TYPE_OR_IRQ);
+ orgate = DEVICE(&s->pmc.apb_irq_orgate);
+ object_property_set_int(OBJECT(orgate),
+ "num-lines", VERSAL_NUM_PMC_APB_IRQS, &error_fatal);
+ qdev_realize(orgate, NULL, &error_fatal);
+ qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]);
+}
+
static void versal_create_rtc(Versal *s, qemu_irq *pic)
{
SysBusDevice *sbd;
@@ -277,7 +298,8 @@ static void versal_create_rtc(Versal *s, qemu_irq *pic)
* TODO: Connect the ALARM and SECONDS interrupts once our RTC model
* supports them.
*/
- sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
+ sysbus_connect_irq(sbd, 1,
+ qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0));
}
static void versal_create_xrams(Versal *s, qemu_irq *pic)
@@ -328,7 +350,8 @@ static void versal_create_bbram(Versal *s, qemu_irq *pic)
sysbus_realize(sbd, &error_fatal);
memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL,
sysbus_mmio_get_region(sbd, 0));
- sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
+ sysbus_connect_irq(sbd, 0,
+ qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1));
}
static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base)
@@ -455,6 +478,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_gems(s, pic);
versal_create_admas(s, pic);
versal_create_sds(s, pic);
+ versal_create_pmc_apb_irq_orgate(s, pic);
versal_create_rtc(s, pic);
versal_create_xrams(s, pic);
versal_create_bbram(s, pic);
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 895ba12c61..62fb6f0a68 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -85,6 +85,8 @@ struct Versal {
XlnxEFuse efuse;
XlnxVersalEFuseCtrl efuse_ctrl;
XlnxVersalEFuseCache efuse_cache;
+
+ qemu_or_irq apb_irq_orgate;
} pmc;
struct {
@@ -111,8 +113,7 @@ struct Versal {
#define VERSAL_GEM1_WAKE_IRQ_0 59
#define VERSAL_ADMA_IRQ_0 60
#define VERSAL_XRAM_IRQ_0 79
-#define VERSAL_BBRAM_APB_IRQ_0 121
-#define VERSAL_RTC_APB_ERR_IRQ 121
+#define VERSAL_PMC_APB_IRQ 121
#define VERSAL_SD0_IRQ_0 126
#define VERSAL_EFUSE_IRQ 139
#define VERSAL_RTC_ALARM_IRQ 142
--
2.11.0
next prev parent reply other threads:[~2022-01-14 15:31 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-14 15:28 [PATCH v6 00/12] Xilinx Versal's PMC SLCR and OSPI support Francisco Iglesias
2022-01-14 15:28 ` [PATCH v6 01/12] hw/misc: Add a model of Versal's PMC SLCR Francisco Iglesias
2022-01-18 21:58 ` Luc Michel
2022-01-14 15:28 ` Francisco Iglesias [this message]
2022-01-18 21:58 ` [PATCH v6 02/12] hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models Luc Michel
2022-01-14 15:28 ` [PATCH v6 03/12] hw/arm/xlnx-versal: Connect Versal's PMC SLCR Francisco Iglesias
2022-01-18 21:56 ` Luc Michel
2022-01-14 15:28 ` [PATCH v6 04/12] include/hw/dma/xlnx_csu_dma: Add in missing includes in the header Francisco Iglesias
2022-01-18 21:59 ` Luc Michel
2022-01-14 15:28 ` [PATCH v6 05/12] hw/dma: Add the DMA control interface Francisco Iglesias
2022-01-18 22:01 ` Luc Michel
2022-01-21 15:46 ` Francisco Iglesias
2022-01-14 15:28 ` [PATCH v6 06/12] hw/dma/xlnx_csu_dma: Implement " Francisco Iglesias
2022-01-14 15:28 ` [PATCH v6 07/12] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller Francisco Iglesias
2022-01-18 21:46 ` Luc Michel
2022-01-21 15:45 ` Francisco Iglesias
2022-01-14 15:28 ` [PATCH v6 08/12] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model Francisco Iglesias
2022-01-14 15:28 ` [PATCH v6 09/12] hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g Francisco Iglesias
2022-01-14 15:28 ` [PATCH v6 10/12] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI Francisco Iglesias
2022-01-14 15:28 ` [PATCH v6 11/12] MAINTAINERS: Add an entry for Xilinx Versal OSPI Francisco Iglesias
2022-01-14 15:28 ` [PATCH v6 12/12] docs/devel: Add documentation for the DMA control interface Francisco Iglesias
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